Display panel and driving method thereof

Abstract

The application provides a display panel and a driving method thereof. The gate driving unit comprises a stage transfer module and an output module which are electrically connected. A current path is formed between two adjacent stage transfer modules, and a current circuit is formed between two adjacent output modules. The output module is electrically connected to a plurality of sub-pixels. A first type of clock line is electrically connected to a plurality of stage transfer modules to provide a first type of clock signal. A second type of clock line is electrically connected to a plurality of output modules to provide a second type of clock signal. The number of the first type of clock line is less than the number of the second type of clock line. The display panel can be divided into different frequency zones. The first type of clock line has sufficient driving force, and the frame size of the display panel is reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a display panel and its driving method. Background Technology

[0002] Current display panels can use different frequencies to display in different areas of the screen, thus achieving the function of zone frequency division.

[0003] Currently, to achieve frequency division functionality, the prevailing approach is to separate the output module and the transmission module within the GOA (Gate driver on Array). Each module is controlled by two equal and independent sets of clock signals. Frequency division is achieved by adjusting the clock signal applied to the output module. However, this doubles the number of clock signals, resulting in an increase in the bezel size of the display product. Summary of the Invention

[0004] The purpose of this invention is to provide a display panel and its driving method to solve the problem of large bezels in existing GOA display products caused by the implementation of segmentation and frequency division.

[0005] This invention provides a display panel, including:

[0006] Multiple sub-pixels;

[0007] A gate driving circuit includes cascaded multi-stage gate driving units. Each gate driving unit includes an electrically connected transmission module and an output module. A current path is formed between two transmission modules in two adjacent gate driving units, and a current disconnect is formed between two output modules in two adjacent gate driving units. Each output module in a gate driving unit is electrically connected to a corresponding plurality of sub-pixels.

[0008] Multiple first-type clock lines are electrically connected to the corresponding multiple transmission modules to provide first-type clock signals;

[0009] Multiple second-type clock lines are electrically connected to corresponding multiple output modules to provide second-type clock signals;

[0010] The number of clock lines of the first type is less than the number of clock lines of the second type.

[0011] In some embodiments, the number of the cascading modules electrically connected to the same first type of clock line is greater than the number of the output modules electrically connected to the same second type of clock line.

[0012] In some embodiments, when the refresh rates of different areas within the display panel are the same, both the first type of clock signal and the second type of clock signal are periodic signals, and the period of the first type of clock signal is less than the period of the second type of clock signal.

[0013] In some embodiments, the first type of clock signal includes a plurality of first clock pulses, and the second type of clock signal includes a plurality of second clock pulses;

[0014] When the refresh rates of different areas of the display panel are the same, the time interval between two first clock pulses of two adjacent first-type clock signals in the same period, the time interval between two second clock pulses of two adjacent second-type clock signals in the same period, and the time interval between the first clock pulse of the last-level first-type clock signal in one period and the first clock pulse of the first-level first-type clock signal in the next period are equal.

[0015] In some embodiments, when the refresh rates of different areas within the display panel are the same, the product of the number of the first type of clock lines and the period of the second type of clock signal is equal to the product of the number of the second type of clock lines and the period of the first type of clock signal.

[0016] In some embodiments, the display panel includes a first region and a second region, the second type of clock signal includes a plurality of second clock pulses, and the multi-level gate driving unit includes:

[0017] A cascaded multi-stage first gate driving unit is electrically connected to a plurality of sub-pixels located in the first region;

[0018] A cascaded multi-stage second gate driving unit is electrically connected to a plurality of sub-pixels located in the second region;

[0019] When the refresh rate of the first region is less than the refresh rate of the second region, in the multi-frame display of the display panel, the total number of second clock pulses corresponding to the first region among the multiple second-type clock signals is less than the total number of second clock pulses corresponding to the second region among the multiple second-type clock signals.

[0020] In some embodiments, when the refresh rate of the first region is different from the refresh rate of the second region, the first type of clock signal is a periodic signal, and at least one of the second type of clock signals is an aperiodic signal.

[0021] In some embodiments, the gate driving unit of the nth stage includes:

[0022] The input module is electrically connected to the frame start line or the stage transmission line of the nith stage, where n is a positive integer and i is a positive integer less than n.

[0023] The cascading module is electrically connected to the input module via a first node and to the corresponding first type of clock line, and is used to output the cascading signal of the nth stage to the cascading line of the nth stage according to the signal of the first node and the corresponding first type of clock signal.

[0024] The output module is electrically connected to the input module through the first node and electrically connected to the corresponding second type of clock line, and is used to transmit the gate signal of the nth level to the corresponding plurality of sub-pixels through the gate line of the nth level according to the signal of the first node and the corresponding second type of clock signal.

[0025] This invention provides a driving method for a display panel. The display panel includes multiple sub-pixels, cascaded multi-level gate driving units, multiple first-type clock lines, and multiple second-type clock lines. Each gate driving unit includes a cascading module and an output module electrically connected. A current path is formed between two cascading modules in two adjacent gate driving units, and a current disconnect is formed between two output modules in two adjacent gate driving units. Each output module in a gate driving unit is electrically connected to a corresponding multiple sub-pixels. The first-type clock lines are electrically connected to the corresponding multiple cascading modules, and the second-type clock lines are electrically connected to the corresponding multiple output modules. The number of first-type clock lines is less than the number of second-type clock lines.

[0026] The driving method for the display panel includes:

[0027] Multiple first-type clock signals are transmitted to the multi-level transmission modules via multiple first-type clock lines to control the multi-level transmission modules to output corresponding multi-level transmission signals. Each level transmission signal includes a corresponding transmission pulse in each frame.

[0028] Multiple second-type clock signals are transmitted to the multi-level output modules via multiple second-type clock lines to control the output modules to output corresponding multi-level gate signals. Some of the gate signals include a corresponding scan pulse in each frame, while some of the gate signals do not include the corresponding scan pulse in at least one frame.

[0029] In some embodiments, the display panel includes a first region and a second region, the second type of clock signal includes a plurality of second clock pulses, and the multi-level gate driving unit includes a cascaded multi-level first gate driving unit electrically connected to a plurality of sub-pixels located in the first region and a cascaded multi-level second gate driving unit electrically connected to a plurality of sub-pixels located in the second region.

[0030] The step of transmitting multiple corresponding second-type clock signals to the multi-stage output modules via multiple second-type clock lines to control the output modules to output corresponding multi-stage gate signals includes:

[0031] When the refresh rate of the first region is less than the refresh rate of the second region, in the multi-frame display of the display panel, the total number of the second clock pulses corresponding to the first region in the multiple second-type clock signals is controlled to be less than the total number of the second clock pulses corresponding to the second region in the multiple second-type clock signals, so that in at least one frame of the display, the gate signal corresponding to the first region does not include the corresponding scan pulse, and the gate signal corresponding to the second region includes the corresponding scan pulse.

[0032] This invention provides a display panel and its driving method. The cascading module in the gate driving unit is controlled by a corresponding first type of clock signal to generate the cascading signal of the same level, and the output module of the same level is controlled by a corresponding second type of clock signal to generate the gate signal of the same level. By setting the first type of clock signal and the second type of clock signal separately, the waveform of the gate signal of the same level can be the same as or different from the waveform of the corresponding cascading signal. While realizing the cascading of the cascading signal, the display panel can also be divided into zones and frequencies. Furthermore, the number of first type of clock signal lines is set to be relatively small. While ensuring that the first type of clock signal lines have a sufficiently large driving force, the bezel size of the display panel is reduced by reducing the number of first type of clock signal lines. Attached Figure Description

[0033] Figure 1 This is a structural block diagram of a display panel and its associated display device provided in an embodiment of the present invention.

[0034] Figure 2 This is a schematic diagram showing the connection of multiple first-type clock signal lines, multiple second-type clock signal lines, multiple gate driving units, and multiple sub-pixels provided in an embodiment of the present invention.

[0035] Figure 3 This is a block diagram of a gate driving unit provided in an embodiment of the present invention.

[0036] Figure 4 The circuit diagram of the gate driving unit provided in the embodiment of the present invention.

[0037] Figure 5 Timing diagrams of multiple first-type clock signals and multiple second-type clock signals provided for embodiments of the present invention.

[0038] Figure 6 A flowchart of a display panel driving method provided in an embodiment of the present invention. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0040] In the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified; "electrical connection" indicates that the two are conductive, and is not limited to a direct or indirect connection.

[0041] Furthermore, it should be noted that the accompanying drawings only provide structures and steps closely related to the present invention, omitting some details less relevant to the invention. This is intended to simplify the drawings and make the inventive points immediately apparent, rather than indicating that the actual device is identical to the one shown in the drawings. Figure 1 It is identical, but this is not a limitation of the actual device.

[0042] The present invention provides a display panel, which may include, but is not limited to, the following embodiments and combinations thereof.

[0043] In some embodiments, combined with Figures 1 to 4As shown, the display panel 100 includes: a plurality of sub-pixels 301; a gate driving circuit 10, including cascaded multi-stage gate driving units 101, each gate driving unit 101 including a cascaded transmission module 501 and an output module 502 electrically connected, a current path being formed between two cascaded transmission modules 501 in two adjacent stages of the gate driving units 101, and a current disconnect being formed between two output modules 502 in two adjacent stages of the gate driving units 101, the output module 502 in the gate driving unit 101 being electrically connected to the corresponding plurality of sub-pixels 301; a plurality of first-type clock lines CK, the first-type clock lines CK being electrically connected to the corresponding plurality of cascaded transmission modules 501 to provide a first-type clock signal ck; a plurality of second-type clock lines XCK, the second-type clock lines XCK being electrically connected to the corresponding plurality of output modules 502 to provide a second-type clock signal xck; wherein, the number of first-type clock lines CK is less than the number of second-type clock lines XCK.

[0044] Among them, such as Figure 1 As shown, the display panel 100 may be included in the display device 200. The display device 200 may also include a timing controller 401 and at least one source driver 402. The timing controller 401 and the source driver 402 may be integrated into the same chip or set independently. The gate driving unit 101 in the gate driving circuit 10 may be electrically connected between the timing controller 401 and the corresponding plurality of sub-pixels 301, for outputting a gate signal Gate transmitted to the corresponding plurality of sub-pixels 301; each source driver 402 is electrically connected between the timing controller 401 and the corresponding plurality of sub-pixels 301, for outputting a data signal Data transmitted to the corresponding plurality of sub-pixels 301.

[0045] For ease of description, this example uses a 301 array of multiple subpixels arranged in N rows and M columns (n ​​and m are both positive integers).

[0046] like Figure 1 As shown, the gate driving circuit 10 may include at least N-level gate driving units 101. The gate driving circuit 10 (at least one gate driving unit 101) is controlled by the timing controller 401 so that each gate driving unit 101 generates a corresponding gate signal Gate. The N-level gate signals Gate are transmitted to the N rows of sub-pixels 301 through N gate lines (GL(1) to GL(N)). The N scan pulses in the N-level gate signals Gate used to turn on the N rows of sub-pixels 301 can be arranged sequentially on the time axis to turn on multiple rows of sub-pixels 301 sequentially.

[0047] The source driver 402 is controlled by the timing controller 401 to generate M data signals Data that are output to M columns of sub-pixels 301 through M data lines (DL1 to DLM). Each data signal Data can include N data voltages corresponding to N sub-pixels 301 in the same column. When each row of sub-pixels 301 is turned on, the M data lines (DL1 to DLM) receive multiple data voltages corresponding to multiple sub-pixels 301 in that row, so that multiple data voltages act on multiple sub-pixels 301 in that row to make multiple sub-pixels 301 in that row light up. In this way, the sub-pixels 301 in all rows can be controlled to light up in sequence to present a complete frame of the picture.

[0048] Specifically, combined Figures 1 to 4 As shown, in the N-level gate driving unit 101, two adjacent gate driving units 101 can be cascaded through the current path formed between the two-level transmission modules 501 respectively, thereby realizing the transmission of signals to drive the N-level gate driving unit 101 to work in sequence. At the same time, since the transmission signal of this level can be generated by the transmission module 501 according to the corresponding first type clock line CK, and the gate signal Gate of this level can be generated by the corresponding second type clock line XCK, the gate signal Gate does not need to have a corresponding transmission pulse in each frame to achieve transmission, as the transmission signal of the same level does. Instead, the waveform of the second type clock line XCK can be reasonably set according to the refresh rate requirements of the multiple areas of the display panel 100, so that the N-level output module 502 outputs the corresponding N-level gate signal Gate respectively, so that the sub-pixels 301 of some areas are turned off in some frames to maintain the picture of the previous frame, thereby realizing the segmentation and frequency division function of the display panel 100.

[0049] It should be noted that the multiple Type II clock lines XCK added to achieve the frequency division function are distributed in the bezel area of ​​the display panel 100, which will increase the size of the bezel area and is not conducive to the development of narrow bezels of the display panel 100.

[0050] Understandably, in this embodiment, the output module 502 in the gate driving unit 101 is connected to multiple sub-pixels 301 via corresponding gate lines (one of GL(1) to GL(N)) compared to the stage transmission module 501. Furthermore, the output module 502 and the stage transmission module 501 are controlled by corresponding second-type clock lines XCK and corresponding first-type clock lines CK, respectively. This results in the first-type clock line CK requiring additional electrical connections to multiple sub-pixels 301 compared to the corresponding second-type clock lines XCK, leading to a significantly larger load. In other words, multiple second-type clock lines XCK require more electrical connections than multiple first-type clock lines XCK. For the first type of clock line CK, the corresponding load is much larger, requiring each second type of clock line XCK to have a sufficiently large driving force. In comparison, each first type of clock line CK has a lower driving force requirement. Therefore, in this embodiment, the number of first type of clock lines CK is set to be less than the number of second type of clock lines XCK. While reducing the number of first type of clock lines CK to reduce the bezel size of the display panel 100, it is still possible to meet the low driving force requirement of the multi-level gate driving unit 101 for the first type of clock lines CK and the high driving force requirement of multiple sub-pixels 301 for the second type of clock lines XCK.

[0051] Among them, combined Figures 1 to 4 As shown, the number of cascading modules 501 electrically connected to the same first type clock line CK is greater than the number of output modules 502 electrically connected to the same second type clock line XCK. As discussed above, since each gate driving unit 101 includes electrically connected cascading modules 501 and output modules 502 (i.e., the number of cascading modules 501 and output modules 502 in the gate driving circuit 10 is equal), and based on the principle that one first type clock line CK is electrically connected to multiple corresponding cascading modules 501 and one second type clock line XCK is electrically connected to multiple corresponding output modules 502, the relatively small number of first type clock lines CK in this invention results in a smaller number of first type clock lines CK used to drive the gate driving circuit 10. This means that each first type clock line CK requires more gate driving units 101 electrically connected compared to the second type clock line XCK to achieve the overall driving of the gate driving circuit 10 by multiple first type clock lines CK.

[0052] As discussed above, the number of first-type clock lines CK is relatively small, while the number of cascade modules 501 connected to each first-type clock line CK is relatively large. Although each second-type clock line XCK is connected to the corresponding output module 502, and the output module 502 further connects to multiple corresponding sub-pixels 301, resulting in a large load on each second-type clock line XCK, the small number of second-type clock lines XCK results in a small number of output modules 502 connected to each second-type clock line XCK, thus reducing the load on each second-type clock line XCK. Ultimately, this can meet the driving force requirements of the gate drive circuit 10 and multiple sub-pixels 301 for multiple second-type clock lines XCK.

[0053] In some embodiments, combined with Figures 1 to 5 As shown, when the refresh rates of different areas within the display panel 100 are the same, both the first type of clock signal ck and the second type of clock signal xck are periodic signals, and the period T1 of the first type of clock signal ck is less than the period T2 of the second type of clock signal xck. Specifically, the first type of clock signal ck may include multiple first clock pulses p1, and the second type of clock signal xck may include multiple second clock pulses p2. Furthermore, the multiple transmission pulses in the transmission signal can be formed by multiple first clock pulses p1, and the multiple scan pulses in the gate signal can be formed by multiple second clock pulses p2.

[0054] Assuming that the refresh rate is the same in all areas of the display panel 100, such as Figure 5 As shown, each frame has multiple scan pulses and multiple stage transmission pulses in a one-to-one correspondence, meaning the number of scan pulses and the number of stage transmission pulses are equal within each frame. However, since the number of stage transmission modules 501 driven by the first type of clock signal ck is greater than the number of output modules 502 driven by the second type of clock signal xck, the first type of clock signal ck can have more first clock pulses p1 to drive a larger number of stage transmission modules 501 to form a larger number of stage transmission pulses. Conversely, the second type of clock signal xck can have fewer second clock pulses p2 to drive a smaller number of output modules 502 to form a smaller number of scan pulses.

[0055] In some embodiments, combined with Figures 1 to 5As shown, the first type of clock signal ck includes multiple first clock pulses p1 as described above, and the second type of clock signal xck includes multiple second clock pulses p2 as described above. When the refresh rates of different areas of the display panel 100 are the same, the time interval between two first clock pulses p1 of two adjacent first type of clock signals ck in the same period T, the time interval between two second clock pulses p2 of two adjacent second type of clock signals xck in the same period T, and the time interval between the first clock pulse p1 of the last type of clock signal ck in one period T and the first clock pulse p1 of the first type of clock signal ck in the next period T are equal.

[0056] As discussed above, when the refresh rate of each area of ​​the display panel 100 is the same, in each frame, the sum of the number of second clock pulses p2 in multiple second-type clock signals xck is equal to the sum of the number of first clock pulses p1 in multiple first-type clock signals ck. Furthermore, the time interval between two adjacent first clock pulses p1 in the first-type clock signal ck and the time interval between the second clock pulses p2 in the second-type clock signal xck are equal. However, since the number of first-type clock lines CK is relatively small, the time interval between the first clock pulse p1 of the first stage in the next cycle T and the first clock pulse p1 of the last stage in the current cycle T also needs to be set to be equal to the aforementioned "time interval" in order to achieve the same time interval between the two adjacent stages in the multiple scan pulses formed within a frame.

[0057] When the refresh rate is the same in different areas of the display panel 100, the sum of the number of second clock pulses p2 in each frame is equal to the sum of the number of first clock pulses p1. Since the number of first-type clock lines CK is relatively small, the number of first clock pulses p1 within the same first-type clock signal ck is relatively large, meaning the period T1 of the first-type clock signal ck is relatively small. Conversely, the number of second clock pulses p2 within the same second-type clock signal xck is relatively large, meaning the period T2 of the second-type clock signal xck is relatively large. Therefore, the product of the number of first-type clock lines CK and the period T2 of the second-type clock signal xck is equal to the product of the number of second-type clock lines xCK and the period T1 of the first-type clock signal ck.

[0058] For example Figure 2 and Figure 5As shown, taking an example where the number of first-type clock lines CK is 4 and the number of second-type clock lines XCK is 6, that is, multiple first-type clock lines CK include 4 first-type clock lines CK1 to CK4, and multiple second-type clock lines XCK include 6 second-type clock lines XCK1 to XCK6. The second-type clock signal xck transmitted by each of the more numerous second-type clock lines XCK (one of XCK1 to XCK6) has a larger period T2, while the first-type clock signal ck transmitted by each of the fewer numerous first-type clock lines CK (one of CK1 to CK4) has a smaller period T1, that is, 4×T2=6×T1. Furthermore, when the number of first-type clock lines CK is n1 and the number of second-type clock lines XCK is n2, the same condition is met: n1×T2=n2×T1.

[0059] In some embodiments, such as Figure 1 As shown, the display panel 100 includes a first region A1 and a second region A2. The second type of clock signal xck includes a plurality of second clock pulses p2. The multi-level gate driving unit 101 includes: a cascaded multi-level first gate driving unit electrically connected to a plurality of sub-pixels 301 located in the first region A1; and a cascaded multi-level second gate driving unit electrically connected to a plurality of sub-pixels 301 located in the second region A2. When the refresh rate of the first region A1 is less than the refresh rate of the second region A2, in the multi-frame display of the display panel 100, the total number of second clock pulses p2 corresponding to the first region A1 in the plurality of second type of clock signals xck is less than the total number of second clock pulses p2 corresponding to the second region A2 in the plurality of second type of clock signals xck.

[0060] Understandably, in this embodiment, within a multi-frame display, the multiple scan pulses output by the multi-level first gate driving unit only exist in some frames, while the multiple scan pulses output by the multi-level second gate driving unit can exist in all display frames. This allows the second region A2 to achieve screen refresh in more frames compared to the first region A1, thus achieving a higher refresh rate for the second region A2. Since the multiple scan pulses are generated by multiple second clock pulses p2 from multiple second-type clock signals xck, a higher refresh rate for the second region A2 can be achieved by setting a larger total number of second clock pulses p2 corresponding to the second region A2.

[0061] In some embodiments, combined with Figures 1 to 5As shown, when the refresh rate of the first region A1 is different from the refresh rate of the second region A2, the first type of clock signal ck is a periodic signal, and at least one of the second type of clock signals xck is a non-periodic signal. Based on the above discussion, since the transmission pulses in the transmission signal are used to drive the gate driving unit 101 of the next stage, the first type of clock signal xck includes a corresponding first clock pulse p1 in each period T, so that a corresponding transmission signal can be generated in each period T. The scan pulses in the gate signal are used to drive the sub-pixel 301 of the corresponding row to turn on. For the segmented frequency, i.e., when the refresh rate of the first region A1 is different from the refresh rate of the second region A2, the number of second clock pulses p2 corresponding to the first region A1 is not equal to the number of second clock pulses p2 corresponding to the second region A2. Therefore, at least one of the second type of clock signals xck does not include a second clock pulse p2 in at least one frame, and thus the second type of clock signal xck is not a periodic signal.

[0062] In some embodiments, combined with Figures 1 to 5 As shown, the gate driving unit 101 of the nth stage includes: an input module 503, electrically connected to the frame start line STV or the stage transmission line Carry(ni) of the nith stage, where n is a positive integer and i is a positive integer less than n; the stage transmission module 501 is electrically connected to the input module 503 through a first node Q and electrically connected to the corresponding first type clock line CK(n), and is used to output the stage transmission signal carry(n) of the nth stage to the stage transmission line Carry(n) of the nth stage according to the signal of the first node Q and the corresponding first type clock signal ck(n); the output module 502 is electrically connected to the input module 503 through the first node Q and electrically connected to the corresponding second type clock line XCK(n), and is used to transmit the gate signal Gate(n) of the nth stage to the corresponding plurality of sub-pixels 301 through the gate line GL(n) of the nth stage according to the signal of the first node Q and the corresponding second type clock signal xck(n).

[0063] Combination Figure 3 and Figure 4As shown, the input module 503 controls the signal of the first node Q based on the frame start signal stv transmitted by the frame start line STV or the ni-th stage transmission signal carry(ni) transmitted by the stage transmission line Carry(ni) of the ni-th stage, and the first type clock signal ck(n+1) corresponding to the n+1-th stage. The pull-down module 504 in the gate drive unit 101 also controls the signal of the second section P based on the first type clock signal ck(n-1) corresponding to the n-1-th stage. Further, the stage transmission module 501 generates the corresponding stage transmission signal carry(n) of the n-th stage based on the signal of the first node Q, the signal of the second section P, and the first type clock signal ck(n) corresponding to the n-th stage. The output module 502 generates the corresponding gate signal Gate(n) of the n-th stage based on the signal of the first node Q, the signal of the second section P, and the second type clock signal xck(n) corresponding to the n-th stage.

[0064] Among them, a first-type clock line CK is connected to the corresponding plurality of gate driving units 101, and a second-type clock line XCK is connected to the corresponding plurality of gate driving units 101, for example... Figure 2 One first-type clock line CK is connected to the gate driver unit 101 of the (n+4k)th stage, and one second-type clock line XCK is connected to the gate driver unit 101 of the (n+6k)th stage, where k is 0 or a positive integer. The first-type clock line CK connected to the gate driver unit 101 of the nth stage is referred to as the first-type clock line CK(n) of the nth stage. For example... Figure 2 The first type of clock line CK1 in the diagram refers to the second type of clock line XCK connected to the gate drive unit 101 of the nth stage as the second type of clock line XCK(n) of the nth stage. For example... Figure 2 The second type of clock line, XCK1.

[0065] Specifically, in combination Figure 3 and Figure 4 As shown, input module 503 may include first transistor NT1, third transistor NT3, seventh transistor NT7, fifth transistor NT5 and first capacitor C1; pull-down module 504 may include fourth transistor NT4, second transistor NT2, eighth transistor NT8, fourteenth transistor NT14, sixth transistor NT6, twelfth transistor NT12 and third capacitor C3; cascade module 501 includes ninth transistor NT9, tenth transistor NT10, eleventh transistor NT11 and second capacitor C2; and output module 502 may include fifteenth transistor NT15, sixteenth transistor NT16 and eighteenth transistor NT18.

[0066] The connection relationships between the forward scan line U2D, the reverse scan line D2U, the gate line GL(n+2) of the (n+2)th stage, the first voltage line VGH, the second voltage line VGL, the first control line GAS1, the third node Qa, and the aforementioned transistors can be referenced but are not limited to. Figure 4 .

[0067] The present invention also provides a driving method for a display panel, applicable to display panels including but not limited to those described above, and may include but not limited to the following embodiments and combinations thereof.

[0068] In some embodiments, such as Figure 6 As shown, the driving method for the display panel includes, but is not limited to, the following steps and combinations thereof:

[0069] S1, transmit multiple first-type clock signals to the multi-level transmission module through multiple first-type clock lines to control the multi-level transmission module to output corresponding multi-level transmission signals. Each level transmission signal includes a corresponding transmission pulse in each frame.

[0070] S2, multiple second-type clock signals are transmitted to the multi-level output modules via multiple second-type clock lines to control the multi-level output modules to output corresponding multi-level gate signals. Some of the gate signals include a corresponding scan pulse in each frame, while some of the gate signals do not include the corresponding scan pulse in at least one frame.

[0071] As discussed above, in this embodiment, the cascading module 501 in the gate driving unit 101 is controlled by the corresponding first type clock signal ck to generate the cascading signal of the same level, and the output module 502 of the same level is controlled by the corresponding second type clock signal xck to generate the gate signal Gate of the same level. By setting the first type clock signal ck and the second type clock signal xck separately, the waveform of the gate signal Gate of the same level can be the same as or different from the waveform of the corresponding cascading signal. While realizing the cascading of the cascading signal, the display panel 100 can also be divided into zones and frequencies.

[0072] Meanwhile, by setting the number of first-type clock signal lines CK to be smaller, the bezel size of the display panel 100 can be reduced while ensuring that the first-type clock signal lines CK have sufficient driving force.

[0073] Furthermore, based on the display panel 100 including the first region A1 and the second region A2 described above, the second type of clock signal xck including multiple second clock pulses p2, and the multi-level gate driving unit 101 including the multi-level first gate driving unit and the multi-level second gate driving unit described above, the above step S2 may include, but is not limited to, the following steps:

[0074] S21, when the refresh rate of the first region is less than the refresh rate of the second region, in the multi-frame display of the display panel, the total number of the second clock pulses corresponding to the first region in the multiple second-type clock signals is controlled to be less than the total number of the second clock pulses corresponding to the second region in the multiple second-type clock signals, so that in at least one frame of the display, the gate signal corresponding to the first region does not include the corresponding scan pulse, and the gate signal corresponding to the second region includes the corresponding scan pulse.

[0075] As discussed above, since the second type of clock signal xck is used to generate the gate signal Gate at this level, when the refresh rate requirement of the first region A1 is relatively small, by setting the total number of the second clock pulses p2 corresponding to the first region A1 in the second type of clock signal xck to be small, it is possible to achieve that the gate signal Gate corresponding to the first region A1 does not include the corresponding scan pulse in at least one frame of display so that the display of the first region A1 remains unchanged, while the gate signal Gate corresponding to the second region includes the corresponding scan pulse in the same frame of display so that the display of the second region A2 is refreshed.

[0076] The structure of the display panel and its driving method provided in the embodiments of the present invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: Multiple sub-pixels; A gate driving circuit includes cascaded multi-stage gate driving units. Each gate driving unit includes an electrically connected transmission module and an output module. A current path is formed between two transmission modules in two adjacent gate driving units, and a current disconnect is formed between two output modules in two adjacent gate driving units. Each output module in a gate driving unit is electrically connected to a corresponding plurality of sub-pixels. Multiple first-type clock lines are electrically connected to the corresponding multiple transmission modules to provide first-type clock signals; Multiple second-type clock lines are electrically connected to corresponding multiple output modules to provide second-type clock signals; The number of clock lines of the first type is less than the number of clock lines of the second type.

2. The display panel as described in claim 1, characterized in that, The number of the cascade modules electrically connected to the same first type of clock line is greater than the number of the output modules electrically connected to the same second type of clock line.

3. The display panel as described in claim 1, characterized in that, When the refresh rates of different areas within the display panel are the same, both the first type of clock signal and the second type of clock signal are periodic signals, with the period of the first type of clock signal being shorter than the period of the second type of clock signal.

4. The display panel as described in claim 3, characterized in that, The first type of clock signal includes multiple first clock pulses, and the second type of clock signal includes multiple second clock pulses; When the refresh rates of different areas of the display panel are the same, the time interval between two first clock pulses of two adjacent first-type clock signals in the same period, the time interval between two second clock pulses of two adjacent second-type clock signals in the same period, and the time interval between the first clock pulse of the last-level first-type clock signal in one period and the first clock pulse of the first-level first-type clock signal in the next period are equal.

5. The display panel as described in claim 4, characterized in that, When the refresh rate is the same in different areas of the display panel, the product of the number of the first type of clock lines and the period of the second type of clock signal is equal to the product of the number of the second type of clock lines and the period of the first type of clock signal.

6. The display panel as described in any one of claims 1 to 5, characterized in that, The display panel includes a first region and a second region, the second type of clock signal includes multiple second clock pulses, and the multi-level gate driving unit includes: A cascaded multi-stage first gate driving unit is electrically connected to a plurality of sub-pixels located in the first region; A cascaded multi-stage second gate driving unit is electrically connected to a plurality of sub-pixels located in the second region; When the refresh rate of the first region is less than the refresh rate of the second region, in the multi-frame display of the display panel, the total number of second clock pulses corresponding to the first region among the multiple second-type clock signals is less than the total number of second clock pulses corresponding to the second region among the multiple second-type clock signals.

7. The display panel as described in claim 6, characterized in that, When the refresh rate of the first region is different from the refresh rate of the second region, the first type of clock signal is a periodic signal, and at least one of the second type of clock signals is an aperiodic signal.

8. The display panel as described in any one of claims 1 to 5, characterized in that, The gate driving unit of the nth stage includes: The input module is electrically connected to the frame start line or the stage transmission line of the nith stage, where n is a positive integer and i is a positive integer less than n. The cascading module is electrically connected to the input module via a first node and electrically connected to the corresponding first type of clock line, and is used to output the cascading signal of the nth stage to the cascading line of the nth stage according to the signal of the first node and the corresponding first type of clock signal. The output module is electrically connected to the input module through the first node and electrically connected to the corresponding second type of clock line, and is used to transmit the gate signal of the nth level to the corresponding plurality of sub-pixels through the gate line of the nth level according to the signal of the first node and the corresponding second type of clock signal.

9. A driving method for a display panel, characterized in that, The display panel includes multiple sub-pixels, cascaded multi-level gate driving units, multiple first-type clock lines, and multiple second-type clock lines. Each gate driving unit includes an electrically connected transmission module and an output module. A current path is formed between two transmission modules in two adjacent gate driving units, and a current disconnect is formed between two output modules in two adjacent gate driving units. Each output module in a gate driving unit is electrically connected to a corresponding multiple sub-pixels. The first-type clock lines are electrically connected to the corresponding multiple transmission modules, and the second-type clock lines are electrically connected to the corresponding multiple output modules. The number of first-type clock lines is less than the number of second-type clock lines. The driving method for the display panel includes: Multiple first-type clock signals are transmitted to the multi-level transmission modules via multiple first-type clock lines to control the multi-level transmission modules to output corresponding multi-level transmission signals. Each level transmission signal includes a corresponding transmission pulse in each frame. Multiple second-type clock signals are transmitted to the multi-level output modules via multiple second-type clock lines to control the output modules to output corresponding multi-level gate signals. Some of the gate signals include a corresponding scan pulse in each frame, while some of the gate signals do not include the corresponding scan pulse in at least one frame.

10. The driving method for a display panel as described in claim 9, characterized in that, The display panel includes a first region and a second region. The second type of clock signal includes a plurality of second clock pulses. The multi-level gate driving unit includes a cascaded multi-level first gate driving unit electrically connected to a plurality of sub-pixels located in the first region and a cascaded multi-level second gate driving unit electrically connected to a plurality of sub-pixels located in the second region. The step of transmitting multiple corresponding second-type clock signals to the multi-stage output modules via multiple second-type clock lines to control the output modules to output corresponding multi-stage gate signals includes: When the refresh rate of the first region is less than the refresh rate of the second region, in the multi-frame display of the display panel, the total number of the second clock pulses corresponding to the first region in the multiple second-type clock signals is controlled to be less than the total number of the second clock pulses corresponding to the second region in the multiple second-type clock signals, so that in at least one frame of the display, the gate signal corresponding to the first region does not include the corresponding scan pulse, and the gate signal corresponding to the second region includes the corresponding scan pulse.

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