Gate driving circuit and display panel

Abstract

The application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a plurality of gate driving units connected in cascade. Each gate driving unit comprises a stage transmission sub-circuit and at least two output sub-circuits. The stage transmission sub-circuit is configured to output a first stage transmission signal of the gate driving unit. The output sub-circuit is configured to output a gate driving signal according to the first stage transmission signal and a corresponding frequency control signal. Each gate driving unit in the gate driving circuit can output a plurality of independent gate driving signals. The independent gate driving signals can have the same or different frequencies. The purpose of different display areas having different refresh frequencies can be achieved, so that the power consumption of the display panel can be reduced without affecting the user experience.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a gate driving circuit and a display panel. Background Technology

[0002] The gate drive circuit, also known as the array substrate row drive (GOA) circuit, uses the existing thin-film transistor display array substrate process to fabricate the gate row scan drive signal circuit on the array substrate to achieve a row-by-row scanning drive method for the gate.

[0003] Currently, with the development of the display industry and the increasing demands of users for display experience, display devices are experiencing ever-increasing refresh rates. However, increasing the refresh rate leads to increased panel power consumption. Summary of the Invention

[0004] The embodiments of the present invention provide a gate driving circuit and a display panel, which can achieve different refresh frequencies for different display areas, thereby reducing the power consumption of the display panel without affecting the user experience.

[0005] This invention provides a gate driving circuit, which includes a plurality of cascaded gate driving units. Each gate driving unit includes a stage transmission sub-circuit and at least two output sub-circuits, wherein the stage transmission sub-circuit is configured to output a first stage transmission signal of the gate driving unit at that stage, and the output sub-circuit is configured to output a gate driving signal according to the first stage transmission signal and a corresponding frequency control signal.

[0006] In some embodiments, the output sub-circuit includes an output control branch and an output pull-down branch, which are connected to form a gate control output node. The output control branch includes a first control terminal for receiving the first stage transmission signal, a first terminal for receiving the corresponding frequency control signal, and a second terminal connected to the gate control output node. The output pull-down branch includes a second control terminal connected to the pull-down node in the stage transmission sub-circuit, a first terminal connected to the gate control output node, and a second terminal for receiving a first voltage signal. The first voltage signal includes a voltage signal with a constant first voltage value. When the output control branch receives the first stage transmission signal and the corresponding frequency control signal, the gate control output node outputs the gate drive signal.

[0007] In some embodiments, the gate driving unit further includes an input sub-circuit, the input sub-circuit including a first terminal for receiving a second voltage signal, a third control terminal for receiving a second stage transmission signal from the previous stage gate driving unit, and a second terminal connected to a pull-up node in the stage transmission sub-circuit; wherein, the input sub-circuit is configured to provide a corresponding pull-up voltage signal to the stage transmission sub-circuit through the pull-up node under the control of the received second stage transmission signal; the second voltage signal includes a voltage signal having a constant second voltage value.

[0008] In some embodiments, the stage transmission sub-circuit includes a stage transmission pull-up branch and a stage transmission pull-down branch, which are connected to form a stage transmission output node. The stage transmission pull-up branch includes a first terminal connected to the pull-up node, a second terminal for receiving a first clock signal, a third terminal for receiving a second voltage signal, and a fourth terminal connected to the stage transmission output node. The stage transmission pull-down branch includes a fourth control terminal connected to the pull-down node, a first terminal for receiving the first voltage signal, and a second terminal connected to the stage transmission output node. When the stage transmission sub-circuit receives the pull-up voltage signal, the pull-down node receives the pull-down voltage signal, and the stage transmission pull-up branch receives the first clock signal, the stage transmission output node outputs the first stage transmission signal. The first voltage signal includes a voltage signal with a constant first voltage value.

[0009] In some embodiments, the gate driving unit further includes a pull-down control sub-circuit, the pull-down control sub-circuit including a first pull-down control branch; wherein the first pull-down control branch includes a fifth control terminal for accessing the second voltage signal, a first terminal for accessing the second clock signal, a second terminal for accessing the third clock signal, a sixth control terminal for accessing the first voltage signal, a third terminal for accessing the second voltage signal, and a fourth terminal connected to the pull-down node; wherein, when the first pull-down control branch accesses the first voltage signal, the second voltage signal, the second clock signal, and the third clock signal, the first pull-down control branch provides the pull-down voltage signal to the pull-down node.

[0010] In some embodiments, the pull-down control sub-circuit includes a second pull-down control branch; the second pull-down control branch includes a first terminal for connecting the first voltage signal, a seventh control terminal for connecting the third-level transmission signal corresponding to the next-stage gate drive unit, and a second terminal connected to the pull-up node; wherein, under the control of the second pull-down control branch connecting the third-level transmission signal, the second pull-down control branch resets the pull-up node.

[0011] In some embodiments, the stage transmission sub-circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; the output sub-circuit includes a fifth transistor and a sixth transistor; wherein, the first terminal of the first transistor is connected to a pull-up node, its control terminal is used to receive a second voltage signal, and its second terminal is connected to a first node; the first terminal of the second transistor is used to receive a first clock signal, its second terminal is connected to a stage transmission output node, and its control terminal is connected to the first node; the stage transmission output node is used to output the first stage transmission signal; the first terminal of the third transistor is used to receive the first voltage signal, its second terminal is connected to the pull-down node, and its control terminal is connected to the pull-up node; the first terminal of the fourth transistor is used to receive the first voltage signal, its second terminal is used to receive the stage transmission output node, and its control terminal is connected to the pull-down node; the first terminal of the fifth transistor is used to receive a corresponding frequency control signal, its second terminal is connected to the gate control output node, and its control terminal is connected to the stage transmission output node; the first terminal of the sixth transistor is connected to the gate control output node, its second terminal is used to receive the first voltage signal, and its control terminal is connected to the pull-down node; wherein, the second voltage signal includes a voltage signal with a constant second voltage value.

[0012] In some embodiments, the gate driving unit further includes an input sub-circuit and a pull-down control sub-circuit; the input sub-circuit includes a seventh transistor; the pull-down control sub-circuit includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; wherein, the first terminal of the seventh transistor is used to receive the second voltage signal, the second terminal is connected to the pull-up node, and the control terminal is used to receive the second-stage transmission signal of the preceding gate driving unit; the first terminal of the eighth transistor is used to receive the second clock signal, the second terminal is connected to the second node, and the control terminal is used to receive the second voltage signal; the first terminal of the ninth transistor is used to receive the third clock signal, the second terminal is connected to the second node, and the control terminal is used to receive the first voltage signal; the first terminal of the tenth transistor is used to receive the second voltage signal, the second terminal is connected to the pull-down node, and the control terminal is connected to the second node; the first terminal of the eleventh transistor is used to receive the first voltage signal, the second terminal is connected to the pull-up node, and the control terminal is used to receive the third-stage transmission signal provided by the following gate driving unit.

[0013] In some embodiments, the gate driving unit further includes: a twelfth transistor, a first terminal of which is connected to the pull-up node, a second terminal of which is used to receive the first voltage signal, and a control terminal of which is connected to the pull-down node; a first capacitor, one end of which is connected to the pull-up node, and the other end of which is used to receive the first voltage signal; and a second capacitor, one end of which is connected to the pull-down node, and the other end of which is used to receive the first voltage signal.

[0014] This invention also provides a display panel, comprising: the gate driving circuit described in any of the preceding claims; and multiple rows of sub-pixels, wherein each row of sub-pixels is connected to one or two gate driving units of the gate driving circuit, and the gate driving signals output by the one or two gate driving units are configured to drive some of the sub-pixels in the row of sub-pixels, wherein different gate driving signals drive different sub-pixels; wherein the display panel comprises multiple independently refreshed sub-display areas, each sub-display area comprising multiple sub-pixels, and the refresh frequency of each sub-display area is determined by a corresponding frequency control signal.

[0015] In some embodiments, the plurality of sub-display areas includes a plurality of first sub-display areas along a first direction; the number of the plurality of first sub-display areas is equal to the number of the gate drive signals; the first direction is the direction in which the sub-pixels in a row of sub-pixels are arranged.

[0016] In some embodiments, the portion of sub-pixels driven by the gate drive signal are multiple sub-pixels arranged consecutively in a row of sub-pixels.

[0017] In summary, the gate driving circuit provided in this embodiment of the invention, by setting at least two output sub-circuits to output at least two independent gate driving signals, and each gate driving signal can have the same or different frequencies according to its corresponding frequency control signal, thereby achieving the purpose of different display areas having different refresh frequencies when using the gate driving circuit to drive multiple rows of sub-pixels contained in the display panel. Thus, when the user is using the circuit, a higher refresh frequency can be used for the display area corresponding to the visual gaze area, while a lower refresh frequency can be used for the display area corresponding to the non-gaze area, thereby reducing the power consumption of the display panel without affecting the user experience. Attached Figure Description

[0018] The present invention will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for illustrating some embodiments of the present invention. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0019] Figure 1 This is a schematic diagram of the gate drive circuit provided in an embodiment of the present invention.

[0020] Figure 2 A schematic diagram of the gate driving unit provided in an embodiment of the present invention. Figure 1 .

[0021] Figure 3 A schematic diagram of the gate driving unit provided in an embodiment of the present invention. Figure 2 .

[0022] Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention.

[0023] Figure 5 Use provided for embodiments of the present invention Figure 3 A schematic diagram of the grid layout design of the gate drive circuit constructed by the provided gate drive unit.

[0024] Figure 6 The embodiments of the present invention provide a basis for... Figure 5 The diagram shows the driving principle structure of the gate drive circuit under the design.

[0025] Figure 7 The embodiments of the present invention provide a basis for... Figure 5 The diagram shows the distribution structure of each sub-display area under the design shown.

[0026] Figure 8 A schematic diagram of the gate driving unit provided in an embodiment of the present invention. Figure 3 .

[0027] Figure 9 Use provided for embodiments of the present invention Figure 8 A schematic diagram of the grid layout design of the gate drive circuit constructed by the provided gate drive unit.

[0028] Figure 10 The embodiments of the present invention provide a basis for... Figure 9 The diagram shows the driving principle structure of the gate drive circuit under the design.

[0029] Figure 11 The embodiments of the present invention provide a basis for... Figure 9 The diagram shows the distribution structure of each sub-display area under the design shown.

[0030] Figure 12 A method for providing an embodiment of the present invention to Figure 9 The diagram illustrates an exemplary timing sequence for refreshing each sub-display area under the design shown. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0032] The terms "first," "second," etc., used in this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to these processes, methods, products, or apparatuses.

[0033] In this article, "first terminal," "second terminal," "third terminal," "fourth terminal," etc., are used to describe the ports where a circuit (or a sub-circuit or a circuit branch) connects to other circuits (or sub-circuits or circuit branches), or to describe the ports where electrical signals are received by a circuit (or a sub-circuit or a circuit branch). Different circuits (or sub-circuits or circuit branches) may have ports for external connection. Here, for each circuit (or sub-circuit or circuit branch), the ports used to control whether the circuit (or sub-circuit or circuit branch) operates are named using terms such as "control terminal," and other included ports are distinguished by the naming convention of first terminal, second terminal, etc. In the following descriptions, when referring to the first, second, or third terminal of a circuit (or sub-circuit or circuit branch), the above description can be used as a reference, and further elaboration will not be repeated.

[0034] In this specification, the transistors mentioned can be implemented as n-type or p-type transistors. For example, a transistor can be implemented as a transistor with a metal-oxide-semiconductor field-effect transistor (MOSFET) structure. A transistor is a three-electrode device comprising a gate electrode, a source electrode, and a drain electrode. The source electrode supplies charge carriers to the transistor. In a transistor, charge carriers move from the source electrode. The drain electrode is the electrode through which charge carriers leave the transistor. The source and drain electrodes of a transistor are not fixed and can change depending on the applied voltage. Therefore, in this specification, when describing transistors, the source and drain are not distinguished, but rather described as "first terminal" and "second terminal." In a specific implementation, if the first terminal is the source electrode, then the second terminal is the drain electrode; if the first terminal is the drain electrode, then the second terminal is the source electrode. Therefore, in the following description, when referring to the first or second terminal of a transistor, it can be understood as described above, and will not be repeated here. The term "control terminal" refers to the gate electrode.

[0035] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0036] The present invention provides a gate driving circuit and a display panel, wherein the gate driving circuit includes, but is not limited to, the following embodiments and combinations thereof.

[0037] Specifically, the gate driving circuit and display panel provided in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] like Figure 1 The above is a schematic diagram of the gate drive circuit provided in the embodiment of the present invention. Figure 1 Specifically, the gate drive circuit 10 may include a plurality of cascaded gate drive units 100; such as Figure 2 As shown, the gate drive unit 100 may include a stage sub-circuit 101 and at least two output sub-circuits 102.

[0039] The stage transmission sub-circuit 101 is configured to output the first stage transmission signal Carry(n) of the gate drive unit of this stage. The output sub-circuit 102 is configured to output a gate drive signal based on the first stage transmission signal and the corresponding frequency control signal, for example... Figure 2 In G(n)~G(n)_m, G(n)~G(n)_m can be the nth level scan signal of the display panel, where n is greater than or equal to 1.

[0040] It is understood that the gate driving circuit provided in this embodiment, by setting at least two output sub-circuits to output at least two independent gate driving signals, and each gate driving signal can have the same or different frequencies depending on the control of its corresponding frequency control signal, thereby achieving different refresh rates for different display areas when using the aforementioned gate driving circuit 10 to drive multiple rows of sub-pixels included in the display panel. Thus, during user operation, a higher refresh rate can be used for the display area corresponding to the visual gaze area, while a lower refresh rate can be used for the display area corresponding to the non-gaze area, thereby reducing the power consumption of the display panel without affecting the user experience. It should be noted that the visual gaze area can refer to the core range focused by the human eye when observing a scene, which is approximately 2° of the visual field of the center of the eye (corresponding to the fovea region of the retina); the non-gaze area can refer to the visual field outside the fovea (approximately 180°). In this invention, the visual gaze area can refer to the display area that the user is gazing at; and the non-gaze area can refer to the display area that the user is not gazing at.

[0041] In some embodiments, the output sub-circuit 102 may include an output control branch 1021 and an output pull-down branch 1022, wherein the output control branch 1021 and the output pull-down branch 1022 are connected to form a gate-controlled output node O. The output control branch 1021 may include a first control terminal for accessing the first stage transmission signal Carry(n), and a terminal for accessing the corresponding frequency control signal SWn (including, for example, ...). Figure 2 The output control branch 1021 may include a first terminal of SW1, SW2, etc., and a second terminal connected to the gate control output node O. The output pull-down branch 1022 may include a second control terminal connected to the pull-down node P in the stage transmission circuit 101, a first terminal connected to the gate control output node O, and a second terminal for receiving a first voltage signal VGL. The first voltage signal VGL includes a voltage signal with a constant first voltage value (such as 0 volts (V)). When the first stage transmission signal Carry(n) and the corresponding frequency control signal SW are received in the output control branch 1021, the gate control output node O outputs one of the gate drive signals G(n) to G(n)_m.

[0042] It should be noted that, in this embodiment, the first-stage transmission signal Carry(n) can be the transmission signal provided by the nth-stage gate driving unit in the aforementioned gate driving circuit, where n is greater than or equal to 1. In this gate driving circuit, the first-stage transmission signal Carry(n) can be used to control the output sub-circuit 102 to output at least two independent gate driving signals, and can also be used as the start signal for starting the scanning of the next row of sub-pixels. Specifically, since the gate driving unit corresponding to the first row of sub-pixels does not have a corresponding upper-stage gate driving unit, the start signal for starting the scanning of the first row of sub-pixels can be provided by other circuits. The start signal of the gate driving unit corresponding to the first row of sub-pixels can be called STV. Here, the frequency control signal can be a pulse signal with a certain frequency, for example, an electrical signal that periodically switches between two different levels.

[0043] In some embodiments, such as Figure 2 As shown, the gate driving unit 100 may further include an input sub-circuit 103. The input sub-circuit 103 may include a first terminal for connecting to a second voltage signal VGH, a third control terminal for connecting to a second stage transmission signal Carry(n-1) of the previous stage gate driving unit, and a second terminal connected to a pull-up node Q in the stage transmission sub-circuit 101. The input sub-circuit 103 is configured to provide a corresponding pull-up voltage signal to the stage transmission sub-circuit 101 through the pull-up node Q under the control of the connected second stage transmission signal Carry(n-1); the second voltage signal includes a voltage signal with a constant second voltage value.

[0044] Here, the second voltage signal VGH includes a voltage signal with a constant second voltage value (such as VDD, for example, 3.3V). The second stage transmission signal Carry(n-1) is the stage transmission signal provided by the stage transmission sub-circuit of the gate driving unit preceding the gate driving unit corresponding to the first stage transmission signal Carry(n). In this embodiment, the second stage transmission signal Carry(n-1) can be used to control the output sub-circuit 102 included in the preceding stage gate driving unit (i.e., the (n-1)th stage) to output at least two independent gate driving signals, and can also be used as a control signal to start the operation of the gate driving unit corresponding to the nth stage, or in other words, as a start signal to start scanning for the next row of sub-pixels. It should be noted that the second stage transmission signal Carry(n-1) in the first stage gate driving unit of the gate driving circuit 10 corresponds to STV, that is, the signal connected to the third control terminal of the input sub-circuit in the gate driving unit corresponding to the first row of sub-pixels is STV.

[0045] In some embodiments, such as Figure 2As shown, the stage transmission sub-circuit 101 may include a stage transmission pull-up branch 1011 and a stage transmission pull-down branch 1012, which are connected to form a stage transmission output node H. The stage transmission pull-up branch 1011 may include a first terminal connected to the pull-up node Q, a second terminal for receiving a first clock signal CK(n), a third terminal for receiving a second voltage signal VGH, and a fourth terminal connected to the stage transmission output node H. The stage transmission pull-down branch 1012 may include a fourth control terminal connected to the pull-down node P, a first terminal for receiving a first voltage signal, and a second terminal connected to the stage transmission output node H. When the stage transmission sub-circuit 101 receives the pull-up voltage signal, the pull-down node P receives the pull-down voltage signal, and the stage transmission pull-up branch 1011 receives the first clock signal CK(n), the stage transmission output node H outputs the first stage transmission signal Carry(n); the first voltage signal includes a voltage signal with a constant first voltage value.

[0046] The first clock signal CK(n) can be a periodically changing electrical signal, typically a square wave, and its function is to coordinate the operating timing of different modules in the digital system. In this embodiment, the first clock signal CK(n) can be the nth clock signal, where n can be a positive integer.

[0047] In some embodiments, such as Figure 2 As shown, the gate driving unit 100 may further include a pull-down control sub-circuit 104, which may include a first pull-down control branch 1041. The first pull-down control branch 1041 includes a fifth control terminal for accessing the second voltage signal, a first terminal for accessing the second clock signal CK(n-1), a second terminal for accessing the third clock signal CK(n+1), a sixth control terminal for accessing the first voltage signal, a third terminal for accessing the second voltage signal, and a fourth terminal connected to the pull-down node P. When the first pull-down control branch 1041 accesses the first voltage signal, the second voltage signal, the second clock signal CK(n-1), and the third clock signal CK(n+1), the first pull-down control branch 1041 provides the pull-down voltage signal to the pull-down node P.

[0048] It is understandable that the second clock signal CK(n-1) can be the (n-1)th clock signal. The third clock signal CK(n+1) can be the (n+1)th clock signal.

[0049] In some embodiments, such as Figure 2As shown, the pull-down control sub-circuit 104 may include a second pull-down control branch 1042. The second pull-down control branch 1042 may include a first terminal for connecting the first voltage signal, a seventh control terminal for connecting the third-level transmission signal Carry(n+1) corresponding to the next-stage gate drive unit, and a second terminal connected to the pull-up node Q; wherein, under the control of the second pull-down control branch 1042 connecting the third-level transmission signal Carry(n+1), the second pull-down control branch 1042 resets the pull-up node Q.

[0050] It is understandable that the third-level transmission signal Carry(n+1) is the transmission signal provided by the transmission sub-circuit of the gate driving unit following the gate driving unit corresponding to the first-level transmission signal Carry(n). The function of the second pull-down control branch 1042 is to reset the pull-up node of the corresponding previous-level gate driving unit (e.g., level n) when the next-level gate driving unit (e.g., level n+1) starts driving the sub-pixels of the corresponding row, so that the corresponding previous-level gate driving unit (e.g., level n) stops outputting the gate driving signal, thereby stopping the driving of the corresponding sub-pixels.

[0051] In some embodiments, such as Figure 3 As shown, the stage transmission sub-circuit 101 may include a first transistor NT7, a second transistor NT9, a third transistor NT6, and a fourth transistor NT10; the output sub-circuit 102 may include a fifth transistor (one of NT12, NT14, ..., NT(V+1)) and a sixth transistor (one of NT11, NT13, ..., NTV).

[0052] In this configuration, the first transistor NT7 has its first terminal connected to the pull-up node Q, its second terminal connected to the first node N1, and its control terminal connected to the second voltage signal VGH. The second transistor NT9 has its first terminal connected to the first clock signal CK(n), its second terminal connected to the stage output node H, and its control terminal connected to the first node N1; the stage output node H outputs the first stage transmission signal Carry(n). The third transistor NT6 has its first terminal connected to the first voltage signal VGL, its second terminal connected to the pull-down node P, and its control terminal connected to the pull-up node Q. The fourth transistor NT10 has its first terminal connected to the first voltage signal VGL, its second terminal connected to the stage output node H, and its control terminal connected to the pull-down node P.

[0053] The fifth transistor (one of NT12, NT14, ..., NT(V+1)) has its first terminal connected to the corresponding frequency control signal SW, its second terminal connected to the gate control output node O, and its control terminal connected to the stage output node H. The sixth transistor (one of NT11, NT13, ..., NTV) has its first terminal connected to the gate control output node O, its second terminal connected to the first voltage signal VGL, and its control terminal connected to the pull-down node P; wherein the second voltage signal includes a voltage signal with a constant second voltage value.

[0054] The first transistor NT7 and the second transistor NT9 are composed of, as follows: Figure 2 The cascade pull-up branch 1011 is shown. The third transistor NT6 and the fourth transistor NT10 are configured as follows: Figure 2 The staged pull-down branch 1012 is shown. The fifth transistor (one of NT12, NT14, ..., NT(V+1)) is configured as follows. Figure 2 The output control branch 1021 is shown. The sixth transistor (one of NT11, NT13, ..., NTV) is configured as follows. Figure 2 The output drop-down branch shown is 1022.

[0055] In some embodiments, such as Figure 3 As shown, the gate driving unit 100 may further include an input sub-circuit 103 and a pull-down control sub-circuit 104. The input sub-circuit 103 may include a seventh transistor NT1; the pull-down control sub-circuit 104 may include an eighth transistor NT3, a ninth transistor NT4, a tenth transistor NT8, and an eleventh transistor NT2.

[0056] Specifically, the seventh transistor NT1 has its first terminal connected to the second voltage signal VGH, its second terminal connected to the pull-up node Q, and its control terminal connected to the second-stage transmission signal Carry(n-1) provided by the previous stage gate drive unit. The eighth transistor NT3 has its first terminal connected to the second clock signal CK(n-1), its second terminal connected to the second node N2, and its control terminal connected to the second voltage signal VGH. The ninth transistor NT4 has its first terminal connected to the third clock signal CK(n+1), its second terminal connected to the second node N2, and its control terminal connected to the first voltage signal VGL. The tenth transistor NT8 has its first terminal connected to the second voltage signal VGH, its second terminal connected to the pull-down node P, and its control terminal connected to the second node N2. The eleventh transistor NT2 has its first terminal connected to the first voltage signal, its second terminal connected to the pull-up node Q, and its control terminal connected to the third-stage transmission signal Carry(n+1) provided by the next stage gate drive unit.

[0057] The eighth transistor NT3, the ninth transistor NT4, and the tenth transistor NT8 are configured as follows: Figure 2 The first pull-down control branch 1041 is shown. The eleventh transistor NT2 is configured as follows: Figure 2 The second drop-down control branch 1042 is shown.

[0058] In some embodiments, such as Figure 3 As shown, the gate driving unit 100 may further include a twelfth transistor NT5, a first capacitor C1, and a second capacitor C2. The first terminal of the twelfth transistor NT5 is connected to the pull-up node Q, the second terminal is used to connect to the first voltage signal VGL, and the control terminal is connected to the pull-down node P. One end of the first capacitor is connected to the pull-up node Q, and the other end is used to connect to the first voltage signal VGL. One end of the second capacitor is connected to the pull-down node P, and the other end is used to connect to the first voltage signal VGL.

[0059] Understandably, the twelfth transistor NT5 can be used to provide feedback on the pull-up voltage signal of the pull-up node Q, thereby reducing gain fluctuations caused by changes in transistor parameters. The first capacitor C1 can be used as a voltage regulator to ensure a stable pull-up voltage signal for the pull-up node Q. The second capacitor C2 can also be used as a voltage regulator to ensure a stable pull-down voltage signal for the pull-down node P.

[0060] In some embodiments, at least one of the first transistor NT7 to the twelfth transistor NT5 may be, but is not limited to, a thin film transistor (TFT), such as an N-channel TFT or a P-channel TFT.

[0061] Based on the gate drive circuit described above, such as Figure 4 As shown, this embodiment of the invention also provides a display panel 20 that may include the aforementioned gate driving circuit 10 and multiple rows of sub-pixels 200. Each row of sub-pixels is connected to one or two gate driving units 100 of the gate driving circuit 10, and the gate driving signals output by the one or two gate driving units 100 are configured to drive a portion of the sub-pixels in the row. Different gate driving signals drive different sub-pixels. The display panel 20 includes multiple independently refreshed sub-display areas, each sub-display area including multiple sub-pixels, and the refresh frequency of each sub-display area is determined by a corresponding frequency control signal.

[0062] In some embodiments, the plurality of sub-display areas may include those along a first direction (e.g., Figure 5 Multiple first sub-display areas (as shown in the X direction) Figure 5The partitions shown are partition 1, partition 2, ..., partition m; the number of the plurality of first sub-display areas is equal to the number of the gate drive signals; the first direction is the direction in which the sub-pixels in a row of sub-pixels are arranged (e.g., ...). Figure 5 (shown in the X direction). As an example, the portion of sub-pixels driven by the gate drive signal can be multiple sub-pixels arranged consecutively in a row of sub-pixels.

[0063] It should be noted that Gate Adapter (GOA) technology is a technique that integrates gate driver circuits directly onto the display panel array substrate. In GOA technology, the gate driver circuit is mainly used for progressive scanning driving of multiple rows of sub-pixels 200. In some embodiments, GOA can employ single-sided or double-sided driving for the multiple rows of sub-pixels 200. Single-sided driving may involve arranging gate driver units on only one side (e.g., the left or right side) and driving the multiple rows of sub-pixels 200 progressively through cascading. Double-sided driving may involve arranging driving units on both the left and right sides of the multiple rows of sub-pixels 200, driving the multiple rows of sub-pixels 200 progressively through collaborative operation on both sides. In this embodiment, the connection of each row of sub-pixels to one or two gate driver units in the gate driver circuit can be understood as follows: when each row of sub-pixels is connected to one gate driver unit in the gate driver circuit, the driving method is single-sided driving; when each row of sub-pixels is connected to two gate driver units in the gate driver circuit, the driving method is double-sided driving.

[0064] In this embodiment, to achieve frequency division of 200 sub-pixels across multiple rows (i.e., different display areas can have different refresh frequencies), regardless of whether single-sided or double-sided driving is used, each gate driving signal output by one or two gate driving units is configured to drive a portion of the sub-pixels in the row. The portion of sub-pixels driven by the gate driving signal consists of multiple sub-pixels arranged consecutively in a row. In this way, the multiple rows of sub-pixels can be divided into multiple independently refreshed sub-display areas. By controlling the frequency of the frequency control signal corresponding to each sub-display area, different sub-display areas can have different refresh frequencies.

[0065] To understand how the gate driving circuit provided in this embodiment of the invention drives multiple rows of sub-pixels to achieve different refresh rates for different sub-display areas, please refer to [link to relevant documentation]. Figures 5 to 7 The diagram shown is shown in the image.

[0066] See Figure 5 This is the usage provided by the embodiments of the present invention. Figure 3 A schematic diagram of the grid layout design of the gate drive circuit constructed from the provided gate drive unit. Figure 5In this design, the display panel uses a dual-side driving method. The GOA includes a first sub-gate driving circuit (GOA1) and a second sub-gate driving circuit (GOA2). Each gate driving unit in the GOA can output m independent gate driving signals.

[0067] In this layout, the connection between each sub-pixel in the multi-row sub-pixels and the gate driving units in GOA1 and GOA2 is explained only by taking the connection between each sub-pixel in the first row and the gate driving units in GOA1 and GOA2 as an example. Specifically, as Figure 5 As shown, in the X direction, the first-stage gate driving unit in GOA1 includes a gate driving signal G(1) connected to each sub-pixel in the first row of sub-pixels in partition 1 (also called sub-display area 1), used to drive each sub-pixel in the first row of sub-pixels in partition 1. The first-stage gate driving unit in GOA2 includes gate driving signals G(1)_2 to G(1)_m connected to each sub-pixel in the first row of sub-pixels in partition 2 (also called sub-display area 2) to partition m (also called sub-display area m), used to drive each sub-pixel in the first row of sub-pixels in partition 2 to partition m. The connection between each sub-pixel in other rows of sub-pixels and the corresponding gate driving unit in GOA1 and GOA2 can be understood with reference to the previous description, and will not be elaborated here. The partition mentioned here is the sub-display area described above. Obviously, this connection method can realize the partitioning of the display area of ​​the display panel in the X direction. Figure 5 As shown, in the X direction, the number of sub-display areas into which the display area contained in the display panel can be divided is less than or equal to the number of gate drive signals contained in the gate drive units in GOA1 and GOA2.

[0068] It should be noted that, Figure 5 This is merely an example of how each row of sub-pixels is connected to the gate drive signals in the corresponding gate drive units in GOA1 and GOA2. In practical applications, the connection methods may also include, but are not limited to: the first-level gate drive unit in GOA1 includes gate drive signals G(1) to G(1)_x connected to each sub-pixel in the first row of sub-pixels in partitions 1 to x, respectively; the first-level gate drive unit in GOA2 includes gate drive signals G(1)_x+1 to G(1)_m connected to each sub-pixel in the first row of sub-pixels in partitions x+1 to m, respectively, where x is greater than or equal to 2 and less than or equal to m-1. Furthermore, partitions 1 to X may also be discontinuous partitions. In summary, within the framework of the aforementioned bilateral drive, the number of gate drive signals used in the gate drive unit corresponding to each row of sub-pixels and the number of sub-pixels in the corresponding row are determined by the specific design.

[0069] In the Y direction, G(1) to G(k-1) of the first-level gate driving unit to the (k-1)th gate driving unit included in GOA1 are respectively connected to each row of sub-pixels in partition 1 to drive each row of sub-pixels in partition 1. G(k)... of the multiple cascaded gate driving units after the k-th level gate driving unit included in GOA1 are respectively connected to each row of sub-pixels in partition 2 to drive each row of sub-pixels in partition 2. Similarly, G(n-1)... of the multiple cascaded gate driving units after the (n-1)-th level gate driving unit included in GOA1 are respectively connected to each row of sub-pixels in partition p to drive each row of sub-pixels in partition p, thereby achieving partitioning in the Y direction. It should be noted that the frequency control signal SW corresponding to each gate driving signal G(*) in the same partition has the same frequency to ensure that the refresh frequency of each row of sub-pixels in the same partition is the same. The frequencies of the frequency control signals SW corresponding to the gate driving signals G(*) in different partitions can be different or the same to flexibly set the refresh frequency of each partition. In addition, it should be noted that the number of sub-display areas controlled by GOA1 and GOA2 in the Y direction can be different or the same.

[0070] See Figure 6 This is provided by the embodiments of the present invention for the purpose of... Figure 5 The diagram shows the driving principle structure of the gate drive circuit under the design. Figure 6 In this diagram, STV is the start signal for the first-stage gate drive unit, which is connected to the control terminal of NT1 corresponding to the first-stage gate drive unit to enable the first-stage gate drive unit to operate. The first-stage gate drive unit can output m gate drive signals from G(1) to G(1)_m, and can also output a stage transfer signal Carry(1). This stage transfer signal Carry(1) is input to the control terminal of NT1 corresponding to the second-stage gate drive unit to enable the second-stage gate drive unit to operate. The second-stage gate drive unit can output m gate drive signals from G(2) to G(2)_m, and can also output a stage transfer signal Carry(2). This stage transfer signal Carry(2) is input to the control terminal of NT1 corresponding to the third-stage gate drive unit to enable the third-stage gate drive unit to operate. And so on, the (n-1)th stage gate drive unit is enabled by the stage transfer signal Carry(n-2), outputs m gate drive signals from G(n) to G(n)_m, and can also output a stage transfer signal Carry(n), and so on. In this invention, the gate drive signals are designed and distributed to drive each sub-pixel in order to achieve the division and frequency division of the display area (AA) in the display panel.

[0071] See Figure 7 The embodiments of the present invention provide for Figure 5 The diagram shows the distribution structure of each sub-display area under the design shown. Figure 7 In this design, the display area (AA) of the display panel is divided into P*m sub-display areas, and each sub-display area can be refreshed independently to achieve different refresh rates for different partitions.

[0072] To understand how to achieve different refresh rates for each sub-display area by setting the frequency control signal SW corresponding to each sub-display area, please refer to [link to documentation]. Figures 8 to 12 The diagram shown is shown in the image.

[0073] See Figure 8 This is a schematic diagram of the gate driving unit provided in an embodiment of the present invention. Figure 3 .in, Figure 8 The gate driving unit shown is Figure 3 This is a specific embodiment of the gate drive unit shown. Figure 8 In this configuration, the gate driving unit 100 may include two output sub-circuits 102. These two output sub-circuits 102 can output two gate driving signals G(n) and G(n)_2. Due to other structural differences... Figure 3 The gate drive unit shown is the same as that shown, and can be referenced in Figure 3 The descriptions of the connection methods and functions of each structure are explained in the text, and will not be repeated here.

[0074] See Figure 9 This is the usage provided by the embodiments of the present invention. Figure 8 A schematic diagram of the grid layout design of the gate drive circuit constructed from the provided gate drive unit. Figure 9 In this design, the display panel uses a dual-side driving method. The GOA can include GOA1 and GOA2, where each gate driving unit in the gate driving circuit can output two independent gate driving signals.

[0075] Similarly, in such Figure 9 In the layout shown, the connection between each sub-pixel in the multi-row sub-pixels and the gate driving units in GOA1 and GOA2 is explained only by taking the connection between each sub-pixel in the first row and the gate driving units in GOA1 and GOA2 as an example. Specifically, as Figure 9As shown, in the X direction, the first-stage gate driving unit in GOA1 includes a gate driving signal G(1) connected to each sub-pixel in the first row of sub-pixels in sub-display area 1, used to drive each sub-pixel in the first row of sub-pixels in sub-display area 1. The first-stage gate driving unit in GOA2 includes a gate driving signal G(1)_2 connected to each sub-pixel in the first row of sub-pixels in sub-display area 3, used to drive each sub-pixel in the first row of sub-pixels in sub-display area 3. The connections between each sub-pixel in other rows of sub-pixels and the corresponding gate driving units in GOA1 and GOA2 can be understood by referring to the previous description, and will not be elaborated here. Obviously, this connection method can realize the partitioning of the display area of ​​the display panel in the X direction. Similarly, with Figure 5 As shown, Figure 9 This is also an exemplary connection diagram. The number of sub-pixels connected to G(1) and G(1)_2 in the first row of sub-pixels can be designed according to the actual situation. Therefore, in this invention, the number of sub-pixels connected to G(1) in the first row of sub-pixels is not limited.

[0076] In the Y direction, G(1) to G(k-1) of the first-stage gate driving unit to the (k-1)th gate driving unit included in GOA1 are respectively connected to each row of sub-pixels in sub-display area 1, and are used to drive each row of sub-pixels in sub-display area 1 respectively; G(k)... of the gate driving units after the k-th stage gate driving unit included in GOA1 are connected to each row of sub-pixels in sub-display area 2, and are used to drive each row of sub-pixels in sub-display area 2 respectively. Similarly, GOA2 also controls two sub-display areas in the Y direction, namely sub-display area 3 and sub-display area 4. Similarly, in the case of Figure 9 In the design layout shown, the frequency control signal SW corresponding to each gate drive signal G(n) in each sub-display area has the same frequency. For example, in Figure 9 In sub-display area 1, the frequency control signals (e.g., SW1) corresponding to G(1) to G(k-1) have the same frequency. In specific implementation, the frequency control signals corresponding to G(1) to G(k-1) can be generated by the same signal generator. The frequencies of the frequency control signals (e.g., SW1 or SW2) corresponding to the gate drive signal G(n) in different sub-display areas can be different or the same. Similarly, it should be noted that the number of sub-display areas controlled by GOA1 and GOA2 in the Y direction can be different or the same.

[0077] See Figure 10 This is provided by the embodiments of the present invention for the purpose of... Figure 9 The diagram shows the driving principle structure of the gate drive circuit under the design. Figure 10In this diagram, STV is the start signal for the first-stage gate drive unit, which is used to connect to the control terminal of NT1 corresponding to the first-stage gate drive unit to start the first-stage gate drive unit. The first-stage gate drive unit can output two gate drive signals, G(1) and G(1)_2, and can also output a stage transfer signal Carry(1). This stage transfer signal Carry(1) is input to the control terminal of NT1 corresponding to the second-stage gate drive unit to start the second-stage gate drive unit. The second-stage gate drive unit can output two gate drive signals, G(2) and G(2)_2, and can also output a stage transfer signal Carry(2). This stage transfer signal Carry(2) is input to the control terminal of NT1 corresponding to the third-stage gate drive unit to start the third-stage gate drive unit. And so on, the (n-1)th stage gate drive unit is started by the stage transfer signal Carry(n-2) and outputs two gate drive signals, G(n) and G(n)_2, and can also output the stage transfer signal Carry(n), and so on. In this invention, the gate drive signals are designed and distributed to drive each sub-pixel in order to achieve the division and frequency division of the display area (AA) in the display panel.

[0078] See Figure 11 The embodiments of the present invention provide for Figure 9 The diagram shows the distribution structure of each sub-display area under the design shown. Figure 11 In this design, the display area (AA) of the display panel is divided into 4 sub-display areas, each of which can be refreshed independently to achieve different refresh rates for different partitions.

[0079] Specifically, see Figure 12 This is a method provided by an embodiment of the present invention for... Figure 9 The diagram illustrates an exemplary timing sequence for refreshing each sub-display area under the design shown.

[0080] according to Figure 12 As shown, it is assumed that the GOA operates at 120 Hz. Figure 9 Taking the frequency division refresh of the four partitions shown as an example, the specific refresh process is as follows.

[0081] During the first to 60 frames, SW1 is VGH, and the gate drive signal G(n) output in each frame is a valid signal that can drive the corresponding sub-pixel, that is, it can refresh; SW2 is VGH, and the gate drive signal G(n)_2 output in each frame is also a valid signal. At this time, sub-display area 1, sub-display area 2, sub-display area 3 and sub-display area 4 are all refreshed normally.

[0082] During frames 61-90, in rows 1 to k of each frame, if SW1 is VGL, then the gate drive signals G(1) to G(k) corresponding to each row of sub-pixels in sub-display area 1 are also VGL. At this time, the gate drive signals G(1) to G(k) are invalid signals, and sub-display area 1 is not refreshed. If SW2 is VGH, then the gate drive signals G(1)_2 to G(k)_2 corresponding to each row of sub-pixels in sub-display area 3 are also VGH. At this time, the gate drive signals G(1)_2 to G(k)_2 are valid signals, and sub-display area 1 is refreshed. Domain 3 is refreshed; in each frame, for rows k+1 to n, if SW1 is VGH, then the gate drive signals G(k+1) to G(n) corresponding to the sub-pixels in each row of sub-display area 2 are VGH. At this time, the gate drive signals G(k+1) to G(n) are valid signals, and sub-display area 2 is refreshed; if SW2 is VGH, then the gate drive signals G(k+1) to G(n) corresponding to the sub-pixels in each row of sub-display area 4 are VGH. At this time, the gate drive signals G(k+1) to G(n) are valid signals, and sub-display area 4 is refreshed. That is, during frames 61-90, sub-display area 1 is not refreshed, while sub-display areas 2, 3, and 4 are refreshed.

[0083] Similarly, during frames 91-120, in rows 1 to k of each frame, if SW1 is VGL, then the gate drive signals G(1) to G(k) corresponding to the sub-pixels in each row of sub-display area 1 are VGL. At this time, the gate drive signals G(1) to G(k) are invalid signals, and sub-display area 1 is not refreshed. If SW2 is VGL, then the gate drive signals G(1)_2 to G(k)_2 corresponding to the sub-pixels in each row of sub-display area 3 are VGL, and the gate drive signals G(1)_2 to G(k) are invalid signals, and sub-display area 3 is not refreshed. In each frame, for rows k+1 to n, if SW1 is VGL, then the gate drive signals G(k+1) to G(n) corresponding to the sub-pixels in each row of sub-display area 2 are VGL. At this time, the gate drive signals G(k+1) to G(n) are invalid signals, and sub-display area 2 is not refreshed. If SW2 is VGH, then the gate drive signals G(k+1)_2 to G(n)_2 corresponding to the sub-pixels in each row of sub-display area 4 are VGH. At this time, the gate drive signals G(k+1)_2 to G(n)_2 are valid signals, and sub-display area 4 is refreshed. That is, during frames 91-120, sub-display areas 1, 2, and 3 are not refreshed, while sub-display area 4 refreshes normally.

[0084] It should be noted that during frames 1 to 120, the transmission signals Carry(1) to Carry(n) are all valid signals capable of driving the corresponding transistors to turn on. Furthermore, as mentioned above... Figure 12In the timing diagram shown, CK(1), CK(2), CK(3), and CK(4) are four clock signals. Specifically, when CK(n) is CK(1), CK(n+1) is CK(2) and CK(n-1) is CK(4); when CK(n) is CK(2), CK(n+1) is CK(3) and CK(n-1) is CK(1); when CK(n) is CK(3), CK(n+1) is CK(4) and CK(n-1) is CK(2); and when CK(n) is CK(4), CK(n+1) is CK(1) and CK(n-1) is CK(3). In summary, the gate drive circuit provided in this embodiment can operate normally using only four clock signals, reducing the number of clock signal lines used and facilitating the achievement of a narrow bezel. Of course, the gate drive circuit provided in this embodiment can also use other numbers of clock signal lines, such as six or eight, depending on the specific requirements.

[0085] In summary, taking a four-zone display as an example, by controlling the frequency control signals SW1 and SW2, the sub-display area 1 refreshes 60 frames, the sub-display area 2 refreshes 90 frames, the sub-display area 3 refreshes 90 frames, and the sub-display area 4 refreshes 120 frames within 1 second (s), thereby achieving different refresh frequencies for different grid display areas.

[0086] The gate driving circuit and display panel provided in the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes multiple cascaded gate driving units; each gate driving unit includes a cascaded sub-circuit and at least two output sub-circuits, wherein; The stage transmission circuit is configured to output the first stage transmission signal of the gate drive unit of this stage. The output sub-circuit is configured to output a gate drive signal based on the first stage transmission signal and the corresponding frequency control signal.

2. The gate driving circuit according to claim 1, characterized in that, The output sub-circuit includes an output control branch and an output pull-down branch, which are connected to form a gate-controlled output node. The output control branch includes a first control terminal for receiving the first stage transmission signal, a first terminal for receiving the corresponding frequency control signal, and a second terminal connected to the gate control output node. The output pull-down branch includes a second control terminal connected to the pull-down node in the stage pass circuit, a first terminal connected to the gate control output node, and a second terminal for receiving a first voltage signal. Wherein, the first voltage signal includes a voltage signal with a constant first voltage value; when the first stage transmission signal and the corresponding frequency control signal are connected to the output control branch, the gate control output node outputs the gate drive signal.

3. The gate driving circuit according to claim 1, characterized in that, The gate driving unit further includes an input sub-circuit, which includes a first terminal for receiving a second voltage signal, a third control terminal for receiving a second-stage transmission signal from the previous gate driving unit, and a second terminal connected to a pull-up node in the transmission sub-circuit. The input sub-circuit is configured to provide a corresponding pull-up voltage signal to the stage transmission sub-circuit through the pull-up node under the control of the second stage transmission signal; the second voltage signal includes a voltage signal with a constant second voltage value.

4. The gate driving circuit according to claim 3, characterized in that, The stage transmission sub-circuit includes a stage transmission pull-up branch and a stage transmission pull-down branch, and the stage transmission pull-up branch and the stage transmission pull-down branch are connected to form a stage transmission output node; The cascade pull-up branch includes a first terminal connected to the pull-up node, a second terminal for receiving a first clock signal, a third terminal for receiving a second voltage signal, and a fourth terminal connected to the cascade output node. The cascade pull-down branch includes a fourth control terminal connected to the pull-down node, a first terminal for receiving a first voltage signal, and a second terminal connected to the cascade output node. Specifically, when the stage transmission sub-circuit is connected to the pull-up voltage signal, the pull-down node is connected to the pull-down voltage signal, and the stage transmission pull-up branch is connected to the first clock signal, the stage transmission output node outputs the first stage transmission signal; the first voltage signal includes a voltage signal with a constant first voltage value.

5. The gate driving circuit according to claim 4, characterized in that, The gate driving unit further includes a pull-down control sub-circuit, and the pull-down control sub-circuit includes a first pull-down control branch; The first pull-down control branch includes a fifth control terminal for connecting to the second voltage signal, a first terminal for connecting to the second clock signal, a second terminal for connecting to the third clock signal, a sixth control terminal for connecting to the first voltage signal, and a third terminal for connecting to the second voltage signal. 、 And the fourth end connected to the drop-down node; Specifically, when the first pull-down control branch is connected to the first voltage signal, the second voltage signal, the second clock signal, and the third clock signal, the first pull-down control branch provides the pull-down voltage signal to the pull-down node.

6. The gate driving circuit according to claim 5, characterized in that, The pull-down control sub-circuit includes a second pull-down control branch; The second pull-down control branch includes a first terminal for receiving the first voltage signal, a seventh control terminal for receiving the third-level transmission signal corresponding to the next-stage gate drive unit, and a second terminal connected to the pull-up node; wherein, under the control of the second pull-down control branch receiving the third-level transmission signal, the second pull-down control branch resets the pull-up node.

7. The gate driving circuit according to claim 2, characterized in that, The staged sub-circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; the output sub-circuit includes a fifth transistor and a sixth transistor; wherein, The first terminal of the first transistor is connected to the pull-up node, the control terminal is used to receive the second voltage signal, and the second terminal is connected to the first node. The first terminal of the second transistor is used to receive the first clock signal, the second terminal is connected to the stage transmission output node, and the control terminal is connected to the first node; the stage transmission output node is used to output the first stage transmission signal. The first terminal of the third transistor is used to receive the first voltage signal, the second terminal is connected to the pull-down node, and the control terminal is connected to the pull-up node; The first terminal of the fourth transistor is used to connect to the first voltage signal, the second terminal is used to connect to the stage transmission output node, and its control terminal is connected to the pull-down node. The first terminal of the fifth transistor is used to receive the corresponding frequency control signal, the second terminal is connected to the gate control output node, and the control terminal is connected to the stage transmission output node. The first terminal of the sixth transistor is connected to the gate control output node, the second terminal is used to receive the first voltage signal, and the control terminal is connected to the pull-down node. The second voltage signal includes a voltage signal with a constant second voltage value.

8. The gate driving circuit according to claim 7, characterized in that, The gate driving unit further includes an input sub-circuit and a pull-down control sub-circuit; the input sub-circuit includes a seventh transistor; the pull-down control sub-circuit includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; wherein, The first terminal of the seventh transistor is used to receive the second voltage signal, the second terminal is connected to the pull-up node, and the control terminal is used to receive the second-stage transmission signal of the previous stage gate drive unit. The first terminal of the eighth transistor is used to receive the second clock signal, the second terminal is connected to the second node, and the control terminal is used to receive the second voltage signal. The first terminal of the ninth transistor is used to receive the third clock signal, the second terminal is connected to the second node, and the control terminal is used to receive the first voltage signal. The first terminal of the tenth transistor is used to receive the second voltage signal, the second terminal is connected to the pull-down node, and the control terminal is connected to the second node. The first terminal of the eleventh transistor is used to receive the first voltage signal, the second terminal is connected to the pull-up node, and the control terminal is used to receive the third-stage transmission signal provided by the next stage gate drive unit.

9. The gate driving circuit according to claim 8, characterized in that, The gate driving unit further includes: The twelfth transistor has a first terminal connected to the pull-up node, a second terminal for receiving the first voltage signal, and a control terminal connected to the pull-down node. A first capacitor, one end of which is connected to the pull-up node, and the other end of which is used to connect to the first voltage signal; The second capacitor has one end connected to the pull-down node and the other end used to connect to the first voltage signal.

10. A display panel, characterized in that, include: The gate driving circuit as described in any one of claims 1 to 9; as well as Multiple rows of sub-pixels, wherein each row of sub-pixels is connected to one or two gate driving units of the gate driving circuit, and the gate driving signals output by the one or two gate driving units are configured to drive some sub-pixels in the row of sub-pixels, wherein different gate driving signals drive different sub-pixels; The display panel includes multiple independently refreshed sub-display areas, each sub-display area includes multiple sub-pixels, and the refresh frequency of each sub-display area is determined by a corresponding frequency control signal.

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