Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display panels, and specifically discloses a display panel and a display device, which comprises a display area and a frame area, wherein the frame area comprises a frame circuit and a plurality of peripheral signal lines, at least part of the peripheral signal lines are electrically connected with the frame circuit, the plurality of peripheral signal lines comprise a first signal line and a second signal line, both of which are electrically connected with the frame circuit, the first signal line is used for transmitting a first voltage signal, the second signal line is used for transmitting a second voltage signal, there is a voltage difference between the first voltage signal and the second voltage signal, and the absolute value of the voltage difference is greater than a preset voltage difference value; the absolute value of the voltage difference between the signal transmitted by the peripheral signal line which is less than a first preset distance from the first signal line and the first voltage signal is less than the preset voltage difference value; and the absolute value of the voltage difference between the signal transmitted by the peripheral signal line which is less than the first preset distance from the second signal line and the second voltage signal is less than the preset voltage difference value. The technical scheme provided by the application reduces the electrochemical corrosion risk of the peripheral signal lines.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, display panels have been increasingly applied to smaller wearable products, such as smartwatches. However, this can lead to problems due to limited design space, such as electrochemical corrosion of signal lines around the display panel. Summary of the Invention

[0003] This invention provides a display panel and a display device to reduce the risk of electrochemical corrosion of peripheral signal lines in the display panel.

[0004] According to one aspect of the present invention, a display panel is provided, comprising: a display area and a border area; the border area comprising:

[0005] Border circuitry;

[0006] Multiple peripheral signal lines are arranged at intervals in the bezel area of ​​the display panel, and at least a portion of the peripheral signal lines are electrically connected to the bezel circuit.

[0007] The plurality of peripheral signal lines include a first signal line and a second signal line, both electrically connected to the frame circuit. The first signal line is used to transmit a first voltage signal, and the second signal line is used to transmit a second voltage signal. There is a voltage difference between the first voltage signal and the second voltage signal, and the absolute value of the voltage difference between the first voltage signal and the second voltage signal is greater than a preset voltage difference value. The absolute value of the voltage difference between the signal transmitted by the peripheral signal line at a distance less than a first preset distance from the first signal line and the first voltage signal is less than the preset voltage difference value. The absolute value of the voltage difference between the signal transmitted by the peripheral signal line at a distance less than the first preset distance from the second signal line and the second voltage signal is less than the preset voltage difference value.

[0008] Optionally, the first signal line and the second signal line are arranged on the same layer, and the distance between the first signal line and the second signal line is greater than or equal to 30um;

[0009] Alternatively, the first signal line and the second signal line are disposed in different layers, and the distance between the first signal line and the second signal line is greater than or equal to 30um;

[0010] Preferably, the first preset distance is equal to 30 μm.

[0011] Optionally, the border area includes a straight-edge border area and / or a curved-edge border area;

[0012] The multiple peripheral signal lines are located in the straight edge border area and / or the curved edge border area;

[0013] Preferably, the frame circuit includes at least two of the following: a light-emitting control circuit, a scan-driving circuit, a multiplexer circuit, and an image quality inspection circuit; the first signal line is electrically connected to at least one of the following: the light-emitting control circuit, the scan-driving circuit, the multiplexer circuit, and the image quality inspection circuit.

[0014] Optionally, the extension direction of the peripheral signal line that is less than a first preset distance from the first signal line is parallel to the extension direction of the first signal line; the extension direction of the peripheral signal line that is less than a first preset distance from the second signal line is parallel to the second signal line.

[0015] Preferably, the extension direction of the first signal line is the same as the extension direction of the second signal line.

[0016] Optionally, the display panel further includes:

[0017] The substrate, multiple metal layers stacked sequentially on the same side of the substrate, and an insulating layer located between adjacent metal layers provide isolation; the multiple peripheral signal lines are located in at least one metal layer;

[0018] Preferably, the multilayer metal layers include a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer, which are sequentially located away from the substrate;

[0019] Preferably, at least one of the fourth and fifth metal layers has the same metal material as the third metal layer; the plurality of peripheral signal lines are located in at least one of the third, fourth, and fifth metal layers.

[0020] Optionally, the display panel further includes a pixel circuit unit located in the display area and a light-emitting device electrically connected to the pixel circuit unit;

[0021] The frame circuit includes a light-emitting control circuit for providing light-emitting control signals to the pixel circuit unit; both the first signal line and the second signal line are electrically connected to the light-emitting control circuit.

[0022] The first signal line includes a light-emitting control circuit enable signal line, which is used to transmit an enable signal to the light-emitting control circuit to activate the light-emitting control circuit.

[0023] The second signal line includes a clock signal line for the light-emitting control circuit. The clock signal line for the light-emitting control circuit is used to transmit a clock signal to the light-emitting control circuit to control the timing of the light-emitting control circuit outputting the light-emitting control signal.

[0024] Preferably, the clock signal line of the light-emitting control circuit includes a first clock signal line and a second clock signal line of the light-emitting control circuit; the number of the second signal lines is 2, namely the first clock signal line and the second clock signal line of the light-emitting control circuit.

[0025] Optionally, when the first signal line and the second signal line are disposed in the same layer, the first signal line and the second signal line are located in the third metal layer;

[0026] When the first signal line and the second signal line are disposed in different layers, the first signal line is located in the third metal layer, and the second signal line is located in the fourth metal layer or the fifth metal layer; or, the second signal line is located in the third metal layer, and the first signal line is located in the fourth metal layer or the fifth metal layer.

[0027] Optionally, the plurality of peripheral signal lines further include:

[0028] A first initialization signal line is used to transmit a first initialization signal to the driving transistor in the pixel circuit unit;

[0029] The second initialization signal line is used to transmit a second initialization signal to the first electrode of the light-emitting device;

[0030] The first level signal line is used to provide a first level signal to the light-emitting control circuit;

[0031] Wherein, the second initialization signal line, the first initialization signal line and the first level signal line are all located in the third metal layer, and the absolute value of the voltage difference between them and the first signal line is less than the preset voltage difference value;

[0032] Preferably, when the first signal line is located in the third metal layer, the first signal line is adjacent to at least one of the first initialization signal line, the second initialization signal line, and the first level signal line.

[0033] Optionally, the second initialization signal line, the first initialization signal line, and the first level signal line are arranged sequentially at intervals in the border area; the plurality of peripheral signal lines further include:

[0034] The second level signal line is used to provide a second level signal to the light emission control circuit; the second level signal line is located on the side of the second initialization signal line away from the first initialization signal line, and the distance between the second level signal line and the second initialization signal line is greater than or equal to 30um;

[0035] Preferably, the frame circuit further includes a scan driving circuit; the multiple peripheral signal lines further include a scan driving circuit enable signal line, a scan driving circuit first clock signal line, and a scan driving circuit second clock signal line electrically connected to the scan driving circuit; the absolute values ​​of the voltage differences between the scan driving circuit enable signal line, the scan driving circuit first clock signal line, and the scan driving circuit second clock signal line and the first signal line are all greater than the preset voltage difference value;

[0036] Preferably, the scan drive circuit enable signal line, the scan drive circuit first clock signal line, and the scan drive circuit second clock signal line are located on the third metal layer, and are all located on the side of the first level signal line away from the first initialization signal line; the distances of the scan drive circuit enable signal line, the scan drive circuit first clock signal line, and the scan drive circuit second clock signal line to the first level signal line are all greater than 30µm;

[0037] Preferably, when the second signal line is located in the third metal layer, the second signal line is adjacent to at least one of the scan drive circuit enable signal line, the scan drive circuit first clock signal line, and the scan drive circuit second clock signal line;

[0038] Preferably, the frame circuit further includes a multiplexer circuit, and the multiple peripheral signal lines further include at least two first control signal lines connected to the multiplexer circuit. The first control signal lines are used to control the conduction and disconnection of the transistors in the multiplexer circuit. The first control signal lines are located in the third metal layer and are located on the side of the second clock signal line of the scan drive circuit away from the first level signal line.

[0039] And / or, the bezel circuit further includes an image quality inspection circuit, and the plurality of peripheral signal lines further include at least two second control signal lines connected to the image quality inspection circuit. The second control signal lines are used to control the conduction and disconnection of the transistors in the image quality inspection circuit. The second control signal lines are located in the third metal layer and are located on the side of the second clock signal line of the scan drive circuit away from the first level signal line.

[0040] According to another aspect of the present invention, a display device is provided, comprising: a display panel as described in any embodiment of the present invention.

[0041] The technical solution provided by this invention sets the absolute value of the voltage difference between the signal transmitted by the peripheral signal line that is less than a first preset distance from the first signal line and the first voltage signal to be less than a preset voltage difference value, and sets the absolute value of the voltage difference between the signal transmitted by the peripheral signal line that is less than a first preset distance from the second signal line and the second voltage signal to be less than a preset voltage difference value. Wherein, the absolute value of the voltage difference between the first signal line and the second signal line is greater than the preset difference value, which can be understood as the first signal line and the second signal line transmitting a high-voltage signal and a low-voltage signal, respectively. In other words, the technical means provided by this invention improves the problem of electrochemical corrosion of the peripheral signal lines located in the bezel area of ​​the display panel by grouping peripheral signal lines that transmit at least a portion of high-voltage signals together and peripheral signal lines that transmit at least a portion of low-voltage signals together, and by setting the distance between the peripheral signal lines used for transmitting high-voltage signals and the peripheral signal lines used for transmitting low-voltage signals to be greater than a first preset distance. This prevents the formation of an electrolytic cell between the high and low signal lines due to their close proximity.

[0042] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the arrangement of peripheral signal lines located in a partial bezel area of ​​a display panel, as provided in the prior art.

[0045] Figure 2 This is a top view of a display panel provided in an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of the arrangement of peripheral signal lines located in a partial bezel area of ​​a display panel, provided by an embodiment of the present invention.

[0048] Figure 5 This is a schematic diagram of another arrangement of peripheral signal lines located in a partial bezel area of ​​a display panel, provided by an embodiment of the present invention.

[0049] Figure 6 yes Figure 5 Schematic diagram of the cross-sectional structure along AA1;

[0050] Figure 7 This is a schematic diagram of another arrangement of peripheral signal lines located in a partial bezel area of ​​a display panel, provided by an embodiment of the present invention.

[0051] Figure 8 yes Figure 7 Schematic diagram of the cross-sectional structure along BB1;

[0052] Figure 9 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0053] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0054] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0055] As the background technology suggests, display panels are increasingly being used in smaller products, such as wearable devices like smartwatches. Due to the reduction in display panel size, the design space for peripheral signal lines located in the display panel bezel area, such as GIP (Gate Driver in Panel) signal lines, is limited, resulting in a smaller spacing between these peripheral signal lines. Among the peripheral signal lines in the display panel bezel area are those used to transmit high-voltage signals and those used to transmit low-voltage signals. Because the voltage difference between the high-voltage and low-voltage signal lines is significant, the reduced spacing between the peripheral signal lines easily leads to the formation of an electrolytic cell between them, causing electrochemical corrosion. For example, Figure 1 This is a schematic diagram of the arrangement of peripheral signal lines located in a partial bezel area of ​​a display panel, provided in the prior art. (Refer to...) Figure 1 The enable signal line of the light-emitting control circuit is used to transmit the enable signal EIN to activate the light-emitting control circuit. The clock signal line of the light-emitting control circuit is used to transmit clock signals ECK1 and ECK2 to control the timing of the output light-emitting control signals. The enable signal EIN transmitted to the light-emitting control circuit is a low-voltage signal, for example, -7V, while the clock signals ECK1 and ECK2 are always high-voltage signals, for example, 7V. The small spacing between the enable signal line and the clock signal line of the light-emitting control circuit makes it easy for an electrolytic cell to form between them, resulting in electrochemical corrosion.

[0056] In view of this, embodiments of the present invention provide a display panel, including: a display area and a border area; the border area includes:

[0057] Border circuitry;

[0058] Multiple peripheral signal lines are arranged at intervals in the frame area, and at least some of the peripheral signal lines are electrically connected to the frame circuit.

[0059] The system includes multiple peripheral signal lines, including a first signal line and a second signal line, both electrically connected to the frame circuit. The first signal line transmits a first voltage signal, and the second signal line transmits a second voltage signal. A voltage difference exists between the first and second voltage signals, and the absolute value of this voltage difference is greater than a preset voltage difference value. The absolute value of the voltage difference between the signal transmitted by a peripheral signal line that is less than a first preset distance from the first signal line and the first voltage signal is less than the preset voltage difference value. Similarly, the absolute value of the voltage difference between the signal transmitted by a peripheral signal line that is less than a first preset distance from the second signal line and the second voltage signal is less than the preset voltage difference value.

[0060] Specifically, the absolute value of the voltage difference between the first voltage signal transmitted by the first signal line and the second voltage signal transmitted by the second signal line is greater than a preset difference value. Here, the first voltage signal is a low-voltage signal relative to the second voltage signal, and the second voltage signal is a high-voltage signal relative to the first voltage signal; or, the first voltage signal is a high-voltage signal relative to the second voltage signal, and the second voltage signal is a low-voltage signal relative to the first voltage signal. The preset difference value can be set according to actual conditions, for example, it can be 5V, 6V, 7V, 7.5V, 9V, 12V, or 14V. Further, the first voltage signal transmitted by the first signal line is a voltage signal within the low-voltage range, and the second voltage signal transmitted by the second signal line is a voltage signal within the high-voltage range, or, the first voltage signal transmitted by the first signal line is a voltage signal within the high-voltage range, and the second voltage signal transmitted by the second signal line is a voltage signal within the low-voltage range. The high-voltage range and low-voltage range can be set according to actual conditions; this embodiment of the invention does not set them. The absolute value of the voltage difference between the first voltage signal transmitted by the first signal line and the second voltage signal transmitted by the second signal line is greater than a preset difference. To reduce the risk of electrochemical corrosion between the first and second signal lines, the distance between them must be greater than or equal to a first preset distance. This first preset distance can be 28µm, 30µm, 31µm, 32µm, or 35µm, set according to actual conditions. Preferably, the first preset distance is 30µm.

[0061] When there are peripheral signal lines around the first signal line that are less than a first preset distance from the first signal line, the absolute value of the voltage difference between the voltage signal transmitted by the peripheral signal line that is less than the first preset distance from the first signal line and the first voltage signal is less than the preset voltage difference value. This can be understood as setting the first signal line around the peripheral signal lines that are close to the first voltage signal transmitted by the first signal line, thereby avoiding electrochemical corrosion between the first signal line and the peripheral signal lines around the first signal line.

[0062] When there are peripheral signal lines around the second signal line that are less than a first preset distance from the second signal line, the peripheral signal lines around the second signal line are set to be voltage signals for transmitting the second voltage signal transmitted by the second signal line with a voltage difference less than a preset voltage difference value. In other words, the second signal line is set between the peripheral signal lines that are close to the second voltage signal transmitted by the second signal line, thereby avoiding electrochemical corrosion between the second signal line and the peripheral signal lines around the second signal line.

[0063] Among them, the peripheral signal lines that are less than a first preset distance from the first signal line can be set on the same layer as the first signal line or on a different layer; the peripheral signal lines that are less than a first preset distance from the second signal line can be set on the same layer as the second signal line or on a different layer.

[0064] The technical solution provided by this invention sets the absolute value of the voltage difference between the signal transmitted by the peripheral signal line at a distance less than a first preset distance from the first signal line and the first voltage signal to be less than a preset voltage difference value, and sets the absolute value of the voltage difference between the signal transmitted by the peripheral signal line at a distance less than the first preset distance from the second signal line and the second voltage signal to be less than a preset voltage difference value; wherein, the absolute value of the voltage difference between the first signal line and the second signal line is greater than a preset difference value, and the first signal line and the second signal line respectively transmit high voltage signal and low voltage signal, that is, by setting at least a portion of the peripheral signal lines transmitting high voltage signal in the display panel together, setting at least a portion of the peripheral signal lines transmitting low voltage signal together, and setting the distance between the peripheral signal lines used to transmit high voltage signal and the peripheral signal lines used to transmit low voltage signal to be greater than a first preset distance, the formation of an electrolytic cell between the high and low signal lines due to their close proximity is prevented, thereby improving the problem of electrochemical corrosion of the peripheral signal lines located in the bezel area of ​​the display panel.

[0065] The above are the core inventive points of this invention. The structure of the display panel will be described in detail below with reference to the accompanying drawings.

[0066] Figure 2 This is a top view of a display panel provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 2 and Figure 3 The display panel includes a display area AA and a border area BK. The display area AA is used to display the image, while the border area BK is used to house the border circuitry and peripheral signal lines; it is a non-display area.

[0067] The display panel includes a substrate and at least one active layer and multiple metal layers stacked on one side of the substrate. The substrate provides protection and support for the display panel. The substrate can be a flexible substrate made of materials such as polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or a rigid substrate made of materials such as glass. At least one active layer and multiple metal layers are disposed on one side of the substrate, and the multiple metal layers are isolated from each other by insulating layers.

[0068] At least one active layer and multiple metal layers constitute a pixel circuit layer in the display area AA of the display panel. The pixel circuit layer includes multiple pixel circuit units electrically connected to light-emitting devices, and the pixel circuit units are used to drive the light-emitting devices. At least one active layer and multiple metal layers constitute a bezel circuit in the bezel area BK of the display panel. The bezel circuit may include at least one of a light-emitting control circuit 200, a scan drive circuit 100, a multiplexer circuit, and an image quality inspection circuit. Multiple peripheral signal lines are located in at least one metal layer. The first signal line is electrically connected to at least one of the light-emitting control circuit, the scan drive circuit, the multiplexer circuit, and the image quality inspection circuit. The second signal line is electrically connected to at least one of the light-emitting control circuit, the scan drive circuit, the multiplexer circuit, and the image quality inspection circuit.

[0069] Specifically, the display area AA includes a pixel circuit layer located on one side of the substrate and a light-emitting device layer located on the side of the pixel circuit layer away from the substrate. The pixel circuit layer includes multiple pixel circuit units, multiple data lines (D1 to Dn), multiple scan signal lines (S1 to Sq), multiple light-emitting control signal lines (E1 to Eo), and multiple first power lines. The border area BK includes border circuitry and peripheral signal lines, with at least some of the peripheral signal lines electrically connected to the border circuitry. The border circuitry in the border area BK includes a scan drive circuit 100 and a light-emitting control circuit 200. Multiple scan signal lines (S1 to Sm) are electrically connected to the scan drive circuit 100, and multiple light-emitting control signal lines (E1 to Eq) are electrically connected to the light-emitting control circuit 200. Multiple data lines D (D1 to Dr) are electrically connected to the data driver 300 of the display panel. A pixel circuit unit and a light-emitting device connected to the pixel circuit unit constitute a sub-pixel. The display area AA may include multiple sub-pixels Pxij, where i and j can be natural numbers. The pixel circuit unit is connected to the scan signal line, the light emission control signal line, and the data line, respectively. The data line is configured to provide data voltage to the pixel circuit unit, the scan signal line is configured to provide scan signal to the pixel circuit unit, and the light emission control signal line is configured to provide light emission control signal to the pixel circuit unit, thereby realizing the light emission control of the light-emitting device. Figure 3 In the illustrated display panel, the scan driving circuit 100 and the light emission control circuit 200 are located on one side of the display area AA, and on the same side of the display area AA. In some other embodiments, the scan driving circuit 100 is located on opposite sides of the display area AA, and the light emission control circuits 200 are all located on opposite sides of the display area AA, and the scan driving circuit 100 and the light emission control circuit 200 are located on the same side of the display area AA. The pixel circuit unit can adopt a "7T1C" circuit, an "8T1C" circuit, or a "10T1C" circuit, and this embodiment of the invention does not limit this.

[0070] Figure 4This is a schematic diagram of the arrangement of peripheral signal lines located in a partial bezel area of ​​a display panel, provided by an embodiment of the present invention. (Refer to...) Figure 4 The peripheral signal lines connected to the light-emitting control circuit 200 may include a light-emitting control circuit enable signal line for transmitting an enable signal EIN to the light-emitting control circuit 200, a light-emitting control circuit first clock signal line for transmitting a first clock signal ECK1 to the light-emitting control circuit 200, a light-emitting control circuit second clock signal line for transmitting a second clock signal ECK2 to the light-emitting control circuit 200, a first level signal line for transmitting a first level signal PVGL_P to the light-emitting control circuit 200, and a second level signal line PVGH_P for transmitting a second level signal to the light-emitting control circuit 200.

[0071] The peripheral signal lines connected to the scan drive circuit 100 may include a scan drive circuit enable signal line for transmitting an enable signal SINP to the scan drive circuit 100, a scan drive circuit first clock signal line for transmitting a first clock signal SCKP1 to the scan drive circuit 100, a scan drive circuit second clock signal line for transmitting a second clock signal SCKP2 to the scan drive circuit 100, a first level signal line, and a second level signal line. The first signal line 11 may be one of the light emission control circuit clock signal line, the light emission control circuit enable signal line, the first level signal line, and the second level signal line. The second signal line 12 may be one of the light emission control circuit clock signal line, the light emission control circuit enable signal line, the first level signal line, and the second level signal line. That is, the first signal line 11 and the second signal line 12 are used to transmit GIP signals to the GIP circuit, thereby improving the electrochemical corrosion of the peripheral GIP signal lines. Figure 4 An exemplary diagram shows that the first signal line 11 is an enable signal line for transmitting an enable signal EIN to the light-emitting control circuit 200, and the second signal line 12 is a first clock signal line for transmitting a first clock signal ECK1 to the light-emitting control circuit 200 and a second clock signal line for transmitting a second clock signal ECK2 to the light-emitting control circuit 200.

[0072] Furthermore, the bezel circuit may also include at least one of a demux circuit and a picture quality inspection circuit (CT circuit). The demux circuit is used to reduce the number of channels in the integrated circuit (IC) by distributing a single signal to multiple data lines through time-division multiplexing. After the display panel leaves the factory and before the driver chip is bonded, visual testing is generally performed to ensure product quality. This involves inputting a detection voltage to the display panel through the picture quality inspection circuit, causing the panel to display a solid color image or a checkerboard pattern for picture quality inspection.

[0073] The peripheral signal lines connected to the multiplexer circuit may include at least two first control signal lines (e.g., three first control signal lines transmitting control signals D_Mux1, D_Mux2, and D_Mux3 respectively) for transmitting control signals to the multiplexer circuit to control the on and off states of transistors in the multiplexer circuit; the peripheral signal lines connected to the image quality inspection circuit may include at least two second control signal lines (e.g., two second control signal lines transmitting control signals D_SW1 and D_SW2 respectively) for controlling the on and off states of transistors in the image quality inspection circuit. The first signal line 11 may also be a first control signal line or a second control signal line; the second signal line 12 may also be a first control signal line and a second control signal line, thereby improving the electrochemical corrosion of the peripheral signal lines connected to the multiplexer circuit or the image quality inspection circuit.

[0074] Based on the above embodiments, optionally, the bezel area BK of the display panel includes a straight bezel area and / or a curved bezel area, and multiple peripheral signal lines are located in the straight bezel area and / or the curved bezel area. The routing of the peripheral signal lines can be set according to the shape of the bezel area BK where the peripheral signal lines are located.

[0075] Based on the above embodiments, optionally, the extension direction of the peripheral signal line that is less than the first preset distance from the first signal line 11 is parallel to the extension direction of the first signal line 11; the extension direction of the peripheral signal line that is less than the first preset distance from the second signal line 12 is parallel to the second signal line 12.

[0076] Specifically, parallel routing avoids redundant space occupation caused by cross-layouts. The extension direction of peripheral signal lines that are less than a first preset distance from the first signal line 11 is parallel to the extension direction of the first signal line 11, and the extension direction of peripheral signal lines that are less than a first preset distance from the second signal line 12 is parallel to the second signal line 12. This facilitates a reduction in trace spacing (within the limits of the process), enabling a higher density of peripheral signal lines. It is suitable for narrow bezel designs, freeing up more area for the pixel region and increasing the screen-to-body ratio. Furthermore, parallel routing makes it easier to control the consistency of line width and spacing during photolithography and etching processes, reducing manufacturing defect rates (such as open circuits and short circuits), improving the yield and reliability of the display panel, and also reducing the difficulty of fabricating peripheral signal lines.

[0077] Preferably, the extension direction of the first signal line 11 is the same as the extension direction of the second signal line 12, so that the extension direction of the first signal line 11, the extension direction of the peripheral signal lines that are less than a first preset distance from the first signal line 11, the extension direction of the second signal line 12 and the extension direction of the peripheral signal lines that are less than a first preset distance from the second signal line 12 are parallel to each other, thereby further improving the screen ratio and reliability of the display panel, and reducing the manufacturing difficulty of the peripheral signal lines.

[0078] Based on the above embodiments, alternative options are available; please continue to refer to them. Figure 4 The first signal line 11 and the second signal line 12 are disposed in the same layer, and the distance between the first signal line 11 and the second signal line 12 is greater than or equal to 30 μm. By setting the distance between the first signal line 11 and the second signal line 12 to be greater than or equal to 30 μm, electrochemical corrosion can be prevented from occurring due to the first signal line 11 and the second signal line 12 being located in the same metal layer being too close.

[0079] Based on the above embodiments, optionally, refer to Figures 5-8 The first signal line 11 and the second signal line 12 are disposed in different layers. By disposing the first signal line 11 and the second signal line 12 in different layers, the distance between the first signal line 11 and the second signal line 12 can be increased in the vertical direction, which can prevent electrochemical corrosion caused by the first signal line 11 and the second signal line 12 being too close. In addition, an insulating layer is provided between adjacent metal layers in the display panel to isolate the two adjacent metal layers. Disposing the first signal line 11 and the second signal line 12 in different layers can also isolate the first signal line 11 and the second signal line 12 through the insulating layer between the metal layers, thereby preventing electrochemical corrosion of the first signal line 11 and the second signal line 12. Furthermore, when the first signal line 11 and the second signal line 12 are disposed in different layers, the distance between the first signal line 11 and the second signal line 12 is greater than or equal to 30 μm; the orthographic projection of the first signal line 11 on the substrate and the orthographic projection of the second signal line 12 on the substrate can overlap, partially overlap, or not overlap.

[0080] Based on the above embodiments, optionally, the multilayer metal layers in the display panel include a first metal layer M1 (not shown), a second metal layer M2 (not shown), a third metal layer M3, a fourth metal layer M4, and a fifth metal layer M5, which are sequentially located away from the substrate 10, and adjacent metal layers are isolated by an insulating layer. Multiple peripheral signal lines are located in at least one of the third metal layer M3, the fourth metal layer M4, and the fifth metal layer M5.

[0081] Optional, see reference Figure 4When the first signal line 11 and the second signal line 12 are arranged in the same layer, the first signal line 11 and the second signal line 12 are located in the third metal layer M3. When the first signal line 11 and the second signal line 12 are arranged in different layers, the first signal line 11 is located in the third metal layer M3, and the second signal line 12 is located in the fourth metal layer M4 or the fifth metal layer M5, wherein... Figure 6 An example is shown where the first signal line 11 is located in the third metal layer M3, and the second signal line 12 is located in the fourth metal layer M4. Figure 8 An example is shown where the first signal line 11 is located in the third metal layer M3 and the second signal line 12 is located in the fifth metal layer M5. In the case where the first signal line 11 and the second signal line 12 are disposed in different layers, the second signal line 12 may also be located in the third metal layer M3, and the first signal line 11 may be located in the fourth metal layer M4 or the fifth metal layer M5.

[0082] Optionally, at least one of the fourth metal layer M4 and the fifth metal layer M5 may be made of the same metal material as the third metal layer M3. By making at least one of the fourth metal layer M4 and the fifth metal layer M5 the same as the third metal layer M3, the peripheral signal lines originally located in the third metal layer M3 can be moved to the fourth metal layer M4 or the fifth metal layer M5, thus preventing changes in the resistance of the peripheral signal lines.

[0083] For example, the material of the first metal layer M1 includes Mo; the material of the insulating layer 11 located between the first metal layer M1 and the second metal layer M2 includes silicon oxide and silicon nitride; the material of the third metal layer M3 includes Ti and Al, forming a Ti / Al / Ti stacked structure; the material of the insulating layer 13 located between the third metal layer M3 and the fourth metal layer M4 includes organic adhesive; the material of the fourth metal layer M4 includes Ti and Al, forming a Ti / Al / Ti stacked structure; the material of the insulating layer 14 located between the fourth metal layer M4 and the fifth metal layer M5 includes organic adhesive; and the material of the fifth metal layer M5 includes Ti and Al, forming a Ti / Al / Ti stacked structure.

[0084] In some embodiments of the present invention, all peripheral signal lines used for transmitting high-voltage signals can be arranged on the same layer, all peripheral signal lines used for transmitting low-voltage signals can be arranged on the same layer, and the peripheral signal lines used for transmitting high-voltage signals and the peripheral signal lines used for transmitting low-voltage signals can be arranged on different layers.

[0085] Based on the above embodiments, in one embodiment of the present invention, reference is made to... Figure 4 , Figure 5 and Figure 7Both the first signal line 11 and the second signal line 12 are electrically connected to the light-emitting control circuit 200. The first signal line 11 is the light-emitting control circuit enable signal line, used to transmit an enable signal EIN to the light-emitting control circuit 200 to activate it. The second signal line 12 is the light-emitting control circuit clock signal line, used to transmit a clock signal to the light-emitting control circuit 200 to control the timing of the light-emitting control circuit 200's output light-emitting control signals. The light-emitting control circuit clock signal line includes a first clock signal line and a second clock signal line. There are two second signal lines 12, one transmitting the first clock signal ECK1 to the light-emitting control circuit 200 and the other transmitting the second clock signal ECK2.

[0086] Specifically, the clock signals (first clock signal ECK1 and second clock signal ECK2) transmitted from the clock signal line of the light-emitting control circuit to the light-emitting control circuit are long-term high-voltage signals; the enable signal EIN transmitted from the enable signal line of the light-emitting control circuit to the light-emitting control circuit is a low-voltage signal. For example, if the clock signal transmitted to the light-emitting control circuit 200 is a 7V high-voltage signal and the enable signal EIN transmitted to the light-emitting control circuit 200 is a -7V low-voltage signal, the voltage difference between the enable signal line and the clock signal line of the light-emitting control circuit is relatively large. Therefore, it is necessary to increase the distance between the enable signal line and the clock signal line of the light-emitting control circuit, for example, setting the distance between the enable signal line and the clock signal line of the light-emitting control circuit to be greater than or equal to 30um, to ensure the normal operation of the light-emitting control circuit.

[0087] The enable signal line and the clock signal line of the light-emitting control circuit can be set on the same layer (e.g., Figure 4 It can also be set in different layers (e.g.) Figures 5-8When the enable signal line and clock signal line of the light-emitting control circuit are arranged on the same layer, the enable signal line can be placed near other peripheral signal lines used for transmitting low-voltage signals, and the clock signal line can be placed near other peripheral signal lines used for transmitting high-voltage signals to prevent electrochemical corrosion of both. When the enable signal line and clock signal line are arranged on different layers, the position of the enable signal line in the third metal layer can be kept unchanged, and the clock signal line can be moved from the third metal layer M3 to the fourth metal layer M4 or the fifth metal layer M5; alternatively, the position of the clock signal line in the third metal layer M3 can be kept unchanged, and the enable signal line can be moved from the third metal layer M3 to the fourth metal layer M4 or the fifth metal layer M5.

[0088] The specific structure of the light-emitting control circuit can adopt a conventional structure, and the embodiments of the present invention do not limit it in this regard.

[0089] Based on the above embodiments, optionally, the multiple peripheral signal lines also include:

[0090] The first initialization signal line is used to transmit the first initialization signal VREFN1 to the drive transistor in the drive circuit.

[0091] The second initialization signal line is used to transmit the second initialization signal VREFN2 to the first electrode of the light-emitting device.

[0092] The first level signal line is used to provide a first level signal PVGL_P to the light emission control circuit 200 and the scan drive circuit 100.

[0093] The second-level signal line is used to provide the second-level signal PVGH_P to the light-emitting control circuit 200 and the scanning drive current 100.

[0094] Among them, the second initialization signal line, the first initialization signal line, and the first level signal line are all located in the third metal layer M3, and the absolute value of the voltage difference between each of them and the first signal line 11 is less than a preset voltage difference value. Therefore, when the first signal line 11 (the light-emitting control circuit enable signal line) is located in the third metal layer M3, the reference... Figure 4 The first signal line 11 is adjacent to at least one of the first initialization signal line, the second initialization signal line, and the first level signal line. This prevents electrochemical corrosion of the light-emitting control circuit enable signal line and the second initialization signal line, first initialization signal line, and first level signal line located around the light-emitting control circuit enable signal line. Figure 4 An example is shown where the first signal line 11 is adjacent to the first level signal line (used to provide the first level signal PVGL_P to the light emission control circuit 200 and the scan drive circuit 100).

[0095] Further reference Figure 4 , Figure 5 and Figure 7 The second initialization signal line, the first initialization signal line, and the first level signal line can be arranged sequentially and alternately in the border area BK; the multiple peripheral signal lines also include a second level signal line, which is used to provide a second level signal PVGH_P to the light-emitting control circuit; the second level signal line is located on the side of the second initialization signal line away from the first initialization signal line, and the distance between the second level signal line and the second initialization signal line is greater than or equal to 30um, thereby preventing the formation of an electrolytic cell between the second level signal line and the second initialization signal line and causing electrochemical corrosion.

[0096] Based on the above embodiments, optionally, the frame circuit further includes a scan driving circuit 100; the multiple peripheral signal lines also include a scan driving circuit enable signal line, a scan driving circuit first clock signal line, and a scan driving circuit second clock signal line electrically connected to the scan driving circuit 100; the absolute values ​​of the voltage differences between the scan driving circuit enable signal line, the scan driving circuit first clock signal line, and the scan driving circuit second clock signal line and the first signal line 11 are all greater than a preset voltage difference value.

[0097] Specifically, the enable signal SINP transmitted on the scan drive circuit enable signal line is a high-voltage signal, the clock signal SCK1 transmitted on the first clock signal line of the scan drive circuit is also set to a high-voltage signal, and the clock signal SCK2 transmitted on the second clock signal line of the scan drive circuit is also set to a high-voltage signal. The first signal line 11 is the enable signal line for the light emission control circuit, and the transmitted enable signal EIN is a low-voltage signal. This ensures that the absolute values ​​of the voltage differences between the scan drive circuit enable signal line, the first clock signal line, and the second clock signal line and the first signal line 11 are all greater than a preset voltage difference value. Therefore, the distances from the scan drive circuit enable signal line, the first clock signal line, and the second clock signal line to the first signal line 11 (the light emission control circuit enable signal line) must all be greater than 30µm to prevent electrochemical corrosion of these lines, thereby ensuring the normal operation of the scan drive circuit.

[0098] In addition, since the enable signal transmitted on the enable signal line of the scan drive circuit is a high-voltage signal SINP, the clock signal SCK1 transmitted on the first clock signal line of the scan drive circuit is set to a high-voltage signal and the clock signal SCK2 transmitted on the second clock signal line of the scan drive circuit is set to a high-voltage signal, the enable signal line of the scan drive circuit, the first clock signal line of the scan drive circuit, and the second clock signal line of the scan drive circuit can be arranged together.

[0099] Optionally, the scan drive circuit enable signal line, the scan drive circuit first clock signal line, and the scan drive circuit second clock signal line are located in the third metal layer M3, and are all located on the side of the first level signal line away from the first initialization signal line. The distance between the scan drive circuit enable signal line, the scan drive circuit first clock signal line, and the scan drive circuit second clock signal line and the first level signal line is greater than 30um, so as to prevent electrochemical corrosion of the scan drive circuit enable signal line, the scan drive circuit first clock signal line, and the scan drive circuit second clock signal line, thereby ensuring the normal operation of the scan drive circuit.

[0100] The specific structure of the scanning drive circuit can adopt a conventional structure, and the embodiments of the present invention do not limit it in this regard.

[0101] Optionally, when the second signal line 12 (the clock signal line of the light-emitting control circuit) is located in the third metal layer M3, since the scan drive circuit enable signal line, the scan drive circuit first clock signal line, and the scan drive circuit second clock signal line all transmit high-voltage signals, the second signal line 12 can be configured to be adjacent to at least one of the scan drive circuit enable signal line, the scan drive circuit first clock signal line, and the scan drive circuit second clock signal line located in the third metal layer M3; alternatively, it can be configured as follows: Figure 4 As shown, an external signal line for transmitting the test signal EM340 is provided between the second signal line 12 and the second clock signal line of the scan drive circuit.

[0102] Based on the above embodiments, refer to Figure 4 , Figure 5 and Figure 7 Optionally, the bezel circuit may further include a multiplexer circuit, and / or the bezel circuit may further include an image quality check circuit. The multiple peripheral signal lines also include at least two first control signal lines connected to the multiplexer circuit, the first control signal lines being located on the third metal layer M3 and on the side of the second clock signal line of the scan drive circuit away from the first level signal line; the multiple peripheral signal lines also include at least two second control signal lines connected to the image quality check circuit, the second control signal lines being located on the third metal layer M3 and on the side of the second clock signal line of the scan drive circuit away from the first level signal line.

[0103] Furthermore, the multiple peripheral signal lines also include a first test signal line for transmitting test signal S340P, a second test signal line for transmitting test signal EM340, a border data line for transmitting data signal D_R to the red sub-pixel, and a border data line for transmitting data signal D_G to the green sub-pixel. Among them, test signal S340P, test signal EM340, data signals D_R and D_G are all high-voltage signals. The first control signal line for transmitting control signal D_Mux1, the first control signal line for transmitting control signal D_Mux2, the first control signal line for transmitting control signal D_Mux3, the border data line for transmitting data signal D_R, the border data line for transmitting data signal D_G, the second control signal line for transmitting control signal D_SW1, and the second control signal line for transmitting control signal D_SW2 can be arranged together in sequence.

[0104] Figure 9 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, for reference. Figure 9 This invention also provides a display device, including the display panel 1 described in any embodiment of the invention. For example, the display device can be a smartwatch or other display devices.

[0105] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, Includes a display area and a border area: the border area includes: Border circuitry; Multiple peripheral signal lines are arranged at intervals in the bezel area of ​​the display panel, and at least a portion of the peripheral signal lines are electrically connected to the bezel circuit. The plurality of peripheral signal lines include a first signal line and a second signal line, both electrically connected to the frame circuit. The first signal line is used to transmit a first voltage signal, and the second signal line is used to transmit a second voltage signal. There is a voltage difference between the first voltage signal and the second voltage signal, and the absolute value of the voltage difference between the first voltage signal and the second voltage signal is greater than a preset voltage difference value. The absolute value of the voltage difference between the signal transmitted by the peripheral signal line at a distance less than a first preset distance from the first signal line and the first voltage signal is less than the preset voltage difference value. The absolute value of the voltage difference between the signal transmitted by the peripheral signal line at a distance less than the first preset distance from the second signal line and the second voltage signal is less than the preset voltage difference value.

2. The display panel according to claim 1, characterized in that, The first signal line and the second signal line are arranged on the same layer, and the distance between the first signal line and the second signal line is greater than or equal to 30um; Alternatively, the first signal line and the second signal line are disposed in different layers, and the distance between the first signal line and the second signal line is greater than or equal to 30um; Preferably, the first preset distance is equal to 30 μm.

3. The display panel according to claim 1, characterized in that, The border area includes a straight-edge border area and / or a curved-edge border area; The multiple peripheral signal lines are located in the straight edge border area and / or the curved edge border area; Preferably, the frame circuit includes at least two of the following: a light-emitting control circuit, a scan-driving circuit, a multiplexer circuit, and an image quality inspection circuit; the first signal line is electrically connected to at least one of the following: the light-emitting control circuit, the scan-driving circuit, the multiplexer circuit, and the image quality inspection circuit.

4. The display panel according to claim 1, characterized in that, The extension direction of the peripheral signal line that is less than a first preset distance from the first signal line is parallel to the extension direction of the first signal line; the extension direction of the peripheral signal line that is less than a first preset distance from the second signal line is parallel to the second signal line. Preferably, the extension direction of the first signal line is the same as the extension direction of the second signal line.

5. The display panel according to claim 1, characterized in that, Also includes: The substrate, multiple metal layers stacked sequentially on the same side of the substrate, and an insulating layer located between adjacent metal layers are isolated. The plurality of peripheral signal lines are located in at least one metal layer; Preferably, the multilayer metal layers include a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer, which are sequentially located away from the substrate; Preferably, at least one of the fourth and fifth metal layers has the same metal material as the third metal layer; the plurality of peripheral signal lines are located in at least one of the third, fourth, and fifth metal layers.

6. The display panel according to claim 5, characterized in that, It also includes a pixel circuit unit located in the display area of ​​the display panel and a light-emitting device electrically connected to the pixel circuit unit; The frame circuit includes a light-emitting control circuit for providing light-emitting control signals to the pixel circuit unit; both the first signal line and the second signal line are electrically connected to the light-emitting control circuit. The first signal line includes a light-emitting control circuit enable signal line, which is used to transmit an enable signal to the light-emitting control circuit to activate the light-emitting control circuit. The second signal line includes a clock signal line for the light-emitting control circuit. The clock signal line for the light-emitting control circuit is used to transmit a clock signal to the light-emitting control circuit to control the timing of the light-emitting control circuit outputting the light-emitting control signal. Preferably, the clock signal line of the light-emitting control circuit includes a first clock signal line and a second clock signal line of the light-emitting control circuit; the number of the second signal lines is 2, namely the first clock signal line and the second clock signal line of the light-emitting control circuit.

7. The display panel according to claim 6, characterized in that, When the first signal line and the second signal line are disposed in the same layer, the first signal line and the second signal line are located in the third metal layer; When the first signal line and the second signal line are disposed in different layers, the first signal line is located in the third metal layer, and the second signal line is located in the fourth metal layer or the fifth metal layer; or, the second signal line is located in the third metal layer, and the first signal line is located in the fourth metal layer or the fifth metal layer.

8. The display panel according to claim 6, characterized in that, The multiple peripheral signal lines also include: A first initialization signal line is used to transmit a first initialization signal to the driving transistor in the pixel circuit unit; The second initialization signal line is used to transmit a second initialization signal to the first electrode of the light-emitting device; The first level signal line is used to provide a first level signal to the light-emitting control circuit; Wherein, the second initialization signal line, the first initialization signal line and the first level signal line are all located in the third metal layer, and the absolute value of the voltage difference between them and the first signal line is less than the preset voltage difference value; Preferably, when the first signal line is located in the third metal layer, the first signal line is adjacent to at least one of the first initialization signal line, the second initialization signal line, and the first level signal line.

9. The display panel according to claim 8, characterized in that, The second initialization signal line, the first initialization signal line, and the first level signal line are arranged sequentially at intervals in the border area; The multiple peripheral signal lines also include: The second level signal line is used to provide a second level signal to the light-emitting control circuit; The second level signal line is located on the side of the second initialization signal line away from the first initialization signal line, and the distance between the second level signal line and the second initialization signal line is greater than or equal to 30um; Preferably, the frame circuit further includes a scan driving circuit; the multiple peripheral signal lines further include a scan driving circuit enable signal line, a scan driving circuit first clock signal line, and a scan driving circuit second clock signal line electrically connected to the scan driving circuit; the absolute values ​​of the voltage differences between the scan driving circuit enable signal line, the scan driving circuit first clock signal line, and the scan driving circuit second clock signal line and the first signal line are all greater than the preset voltage difference value; Preferably, the scan drive circuit enable signal line, the scan drive circuit first clock signal line, and the scan drive circuit second clock signal line are located on the third metal layer, and are all located on the side of the first level signal line away from the first initialization signal line; the distances of the scan drive circuit enable signal line, the scan drive circuit first clock signal line, and the scan drive circuit second clock signal line to the first level signal line are all greater than 30µm; Preferably, when the second signal line is located in the third metal layer, the second signal line is adjacent to at least one of the scan drive circuit enable signal line, the scan drive circuit first clock signal line, and the scan drive circuit second clock signal line; Preferably, the frame circuit further includes a multiplexer circuit, and the multiple peripheral signal lines further include at least two first control signal lines connected to the multiplexer circuit. The first control signal lines are used to control the conduction and disconnection of the transistors in the multiplexer circuit. The first control signal lines are located in the third metal layer and are located on the side of the second clock signal line of the scan drive circuit away from the first level signal line. And / or, the bezel circuit further includes an image quality inspection circuit, and the plurality of peripheral signal lines further include at least two second control signal lines connected to the image quality inspection circuit. The second control signal lines are used to control the conduction and disconnection of the transistors in the image quality inspection circuit. The second control signal lines are located in the third metal layer and are located on the side of the second clock signal line of the scan drive circuit away from the first level signal line.

10. A display device, characterized in that, include: The display panel according to any one of claims 1 to 9.

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