Display device, display driving circuit, and low dropout regulator circuit

Abstract

A display device includes a display panel of pixels each including a light emitting element, a power generation circuit including a low-dropout regulator circuit that changes a magnitude of an initialization voltage applied to an anode electrode of the light emitting element, and a timing controller that receives voltage variation information regarding a magnitude variation of a first power supply voltage applied to a cathode electrode of the light emitting element and generates a control signal for controlling the low-dropout regulator circuit based on the voltage variation information.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0046375, filed with the Korean Intellectual Property Office on April 9, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices, display driver circuits, and low dropout voltage regulator circuits. Background Technology

[0004] A display device that displays a video signal during an active period and stabilizes the signal during a blanking period. The blanking period includes a porch interval in which an initialization voltage applied to the display device is set. During the porch interval, a slew operation with gradually changing voltage occurs, and the slew rate affects the signal quality.

[0005] As resolution increases, the number of scan lines increases, which reduces the horizontal time slot allocated to each line at the same refresh rate. With a shorter horizontal time slot, the blanking time decreases, and the duration of the edge interval within the blanking time also decreases. As the edge interval duration shortens, less time is available to set the initial voltage, necessitating slew rate adjustments. Failure to properly adjust the slew rate can lead to image quality degradation or signal distortion. Summary of the Invention

[0006] On the one hand, it provides display devices, display driver circuits, and low-dropout regulator circuits with improved slew rate performance.

[0007] According to one or more embodiments, a display device is provided, including a display panel comprising a plurality of pixels, each of the plurality of pixels including a light-emitting element, a power generation circuit including a low-dropout regulator circuit configured to change the magnitude of an initialization voltage applied to the anode electrode of the light-emitting element, and a timing controller configured to receive voltage change information relating to a magnitude change of a first power supply voltage applied to the cathode electrode of the light-emitting element, and to generate a control signal for controlling the low-dropout regulator circuit based on the voltage change information.

[0008] According to another aspect of one or more embodiments, a display driving circuit is provided, including a power generation circuit comprising a low-dropout regulator circuit configured to change the amplitude of an initialization voltage applied to a display panel, a timing controller configured to: receive voltage change information indicating a change in the amplitude of a first power supply voltage applied to the display panel during a first blanking period of a first frame period between a first active period of a first frame period and a second active period of a second frame period consecutive to the first frame period; generate a control signal based on the voltage change information for controlling the low-dropout regulator circuit; and a data driver configured to transmit a data signal to the display panel during the first and second active periods.

[0009] According to another aspect of one or more embodiments, a low-dropout regulator circuit is provided, comprising a voltage distribution circuit configured to receive a first input voltage through a first input node and select a voltage having a level between the first input voltage and a first power supply voltage applied to the cathode electrode of a light-emitting element based on a control signal to generate an output voltage; a multiplexer configured to output one of the output voltage and the first input voltage based on a control signal; a feedback circuit configured to generate a feedback voltage by feeding back an initialization voltage applied to the anode electrode of the light-emitting element based on a control signal; and an output circuit configured to receive one of the output voltage and the first input voltage from the multiplexer, receive the feedback voltage from the feedback circuit, and change the magnitude of the initialization voltage based on the feedback voltage and one of the output voltage and the first input voltage. Attached Figure Description

[0010] Figure 1 This is a block diagram of a display device according to an embodiment.

[0011] Figure 2 This is a circuit diagram of the pixel according to an embodiment.

[0012] Figure 3 This is a timing diagram illustrating the driving operation of the display panel according to an embodiment.

[0013] Figure 4 This is a circuit diagram of a low-dropout regulator circuit according to an embodiment.

[0014] Figure 5 This is a circuit diagram of the voltage distribution circuit according to an embodiment.

[0015] Figure 6 This is a circuit diagram of the feedback circuit according to an embodiment.

[0016] Figure 7 This is a timing diagram of the first power supply voltage and control signal according to an embodiment.

[0017] Figure 8 This is a timing diagram of the first power supply voltage according to an embodiment.

[0018] Figure 9 This is a timing diagram of the initialization voltage according to the embodiment.

[0019] Figure 10 This is a timing diagram showing the difference between the first power supply voltage and the initialization voltage according to an embodiment.

[0020] Figure 11 This is a timing diagram of the first power supply voltage and control signal according to an embodiment.

[0021] Figure 12 This is a diagram illustrating bit information, delay value, pulse width, and fluctuation value of a first power supply voltage included in a memory according to an embodiment.

[0022] Figure 13 This is a timing diagram of the first power supply voltage and control signal according to an embodiment.

[0023] Figure 14 It is a timing diagram based on the first power supply voltage and control signal of the comparison example.

[0024] Figure 15 This is a block diagram of an electronic device according to an embodiment. Detailed Implementation

[0025] Various embodiments will now be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily practice the embodiments. However, these embodiments may be implemented in various different forms and are not limited to those described herein.

[0026] To clearly explain the various embodiments in the accompanying drawings, parts irrelevant to the explanation have been omitted, and similar parts are given similar reference numerals throughout the specification. In the flowcharts described with reference to the accompanying drawings, the order of operations can be changed, several operations can be combined, some operations can be split, and / or some operations can be omitted.

[0027] Furthermore, expressions written in the singular can be interpreted as either singular or plural unless explicitly expressed as "a" or "singular." Ordinal terms, such as first, second, etc., can be used to describe various components, but the component is not limited by these terms. These terms can be used to distinguish one component from another.

[0028] The present disclosure will be described in more detail below by way of examples. These examples are intended to illustrate the present disclosure only, and the scope of protection of the present disclosure is not limited by these examples.

[0029] Figure 1 This is a block diagram of a display device according to an embodiment.

[0030] refer to Figure 1 The display device 100 may include a timing controller 110, a scan driver 120, a data driver 130, a transmit driver 140, a display panel 150, a power management integrated circuit (PMIC) 160, and a voltage generator 170.

[0031] The timing controller 110 can acquire timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable level DE. The timing controller 110 can generate a scan control signal SCS based on one or more of the timing signals to control the operation timing of the scan driver 120. The timing controller 110 can generate a data control signal DCS based on one or more of the timing signals to control the operation timing of the data driver 130. The timing controller 110 can generate an emission control signal ECS based on one or more of the timing signals to control the operation timing of the transmit driver 140. The timing controller 110 can generate a voltage control signal PDS based on one or more of the timing signals to control the operation timing of the PMIC 160.

[0032] The timing controller 110 can obtain voltage change information TRAN from the processor. The voltage change information TRAN may include information about the magnitude of the voltage applied to the display panel 150. The timing controller 110 can generate a control signal CTRL based on the voltage change information TRAN to control the timing of the operation of the voltage generator 170.

[0033] In some embodiments, the timing controller 110 may include a memory 111. In an embodiment, the memory 111 may be random access memory (RAM). The memory 111 may include bit information indicating the delay value and pulse width value of the control signal CTRL. The delay value and pulse width value of the control signal CTRL may be determined based on the fluctuation value of the voltage applied to the display panel 150 included in the voltage change information TRAN. The timing controller 110 may generate the control signal CTRL for controlling the operating timing of the voltage generator 170 based on the delay value and / or the pulse width value of the control signal CTRL.

[0034] The scan driver 120 can receive a scan control signal SCS from the timing controller 110. The scan driver 120 can scan multiple scan lines S1 to SN based on the scan control signal SCS. The time for the scan driver 120 to scan each of the multiple scan lines S1 to SN can be defined as a horizontal cycle.

[0035] Data driver 130 can receive data control signal DCS from timing controller 110. Data driver 130 can output data signals to multiple data lines D1 to DN based on data control signal DCS. Data driver 130 can output data signals to multiple data lines D1 to DN within an active section.

[0036] The transmitter driver 140 can receive the light emission control signal ECS from the timing controller 110. The transmitter driver 140 can output the light emission signal to multiple light emission lines E1 to EN based on the light emission control signal ECS.

[0037] The display panel 150 may include a plurality of pixels PXL. Each of the plurality of pixels PXL can be connected to one of a plurality of scan lines S1 to SN. A pixel PXL connected to any one of the plurality of scan lines S1 to SN can receive a scan signal. Each of the plurality of pixels PXL can be connected to one of a plurality of data lines D1 to DN to receive a data signal. A pixel PXL connected to any one of the plurality of data lines D1 to DN can receive a data signal.

[0038] PMIC 160 can receive a voltage control signal PDS from timing controller 110. PMIC 160 can generate a first voltage V1, a second voltage V2, a first power supply voltage ELVSS, a second power supply voltage ELVDD, and a drive voltage AVDD based on the voltage control signal PDS. PMIC 160 can transmit the first voltage V1, the second voltage V2, the first power supply voltage ELVSS, the second power supply voltage ELVDD, and the drive voltage AVDD to voltage generator 170.

[0039] Voltage generator 170 can receive a control signal CTRL from timing controller 110. The control signal CTRL can include voltage change information TRAN as information about the magnitude of the voltage applied to display panel 150. Voltage generator 170 can receive a first voltage V1, a second voltage V2, a first power supply voltage ELVSS, a second power supply voltage ELVDD, and a drive voltage AVDD from PMIC 160.

[0040] Voltage generator 170 may include multiple low-dropout regulator circuits 171_1 to 171_N (hereinafter referred to as "LDO circuits"). The multiple LDO circuits 171_1 to 171_N can be driven based on a control signal CTRL. The multiple LDO circuits 171_1 to 171_N can change the initialization voltage VAINT based on a first voltage V1, a second voltage V2, a first supply voltage ELVSS, a second supply voltage ELVDD, and a drive voltage AVDD. The magnitude of the initialization voltage VAINT can be determined based on the control signal CTRL.

[0041] For example, when the voltage change information TRAN of the control signal CTRL includes information for increasing the first power supply voltage ELVSS applied to the display panel 150, the multiple LDO circuits 171_1 to 171_N can increase the initialization voltage VAINT based on the increase in the first power supply voltage ELVSS. When the voltage change information TRAN of the control signal CTRL includes information for decreasing the first power supply voltage ELVSS applied to the display panel 150, the multiple LDO circuits 171_1 to 171_N can decrease the initialization voltage VAINT based on the decrease in the first power supply voltage ELVSS. When the voltage change information TRAN of the control signal CTRL includes information for maintaining the first power supply voltage ELVSS applied to the display panel 150, the multiple LDO circuits 171_1 to 171_N can maintain the initialization voltage VAINT.

[0042] Voltage generator 170 can transmit the initialization voltage VAINT to display panel 150. In an embodiment, timing controller 110, data driver 130, and power generation unit 170 may be included in display driving circuitry. Display driving circuitry may be an organic light-emitting diode (OLED) display driving circuit, a liquid crystal display (LCD) display driving circuit, an LED-backlit LCD display driving circuit, or an active matrix OLED (AMOLED) display driving circuit.

[0043] Figure 2 This is a circuit diagram of the pixel according to an embodiment.

[0044] refer to Figure 2 The illustration shows the arrangement of the items. Figure 1 The pixel PXL in the i-th row (i is a positive integer) and j-th column (j is a positive integer) of the display panel 150.

[0045] Pixel PXL may include pixel circuit PXC, first voltage line VSSL, second voltage line VDDL, initialization voltage line VINL, reference voltage line VREL, and data line DL. Pixel circuit PXC may include a first transistor T1 receiving a first gate signal GW, a second transistor T2 receiving a second gate signal GB, a third transistor T3 receiving a third gate signal GR, a fourth transistor T4 receiving a fourth gate signal EB, a fifth transistor T5 receiving a transmit signal ET, a driving transistor T6, and a storage capacitor C1.

[0046] For ease of illustration, an embodiment including multiple transistors T1 to T6 for driving pixel PXL and a storage capacitor C1 is described. Each of the six transistors T1 to T6 may be a P-type oxide thin-film transistor. The oxide thin-film transistor may be a low-temperature polycrystalline oxide (LTPO) thin-film transistor in which the semiconductor layer comprises an oxide layer.

[0047] The first transistor T1 may include a gate for receiving a first gate signal GW, a source connected to a data line DL for receiving a data signal, and a drain connected to a first node N11. The first transistor T1 can transmit a data signal to the first node N11 based on the first gate signal GW having an enable level.

[0048] The second transistor T2 may include a gate for receiving the second gate signal GB, a source connected to the second node N12, and a drain connected to the anode ANODE of the light-emitting element LD.

[0049] The third transistor T3 may include a gate for receiving a third gate signal GR, a source connected to a reference voltage line VREL, and a drain connected to a first node N11. The third transistor T3 may transmit a reference voltage VREF to the first node N11 based on the third gate signal GR having an enable level.

[0050] The fourth transistor T4 may include a gate for receiving a fourth gate signal EB, a source connected to the initialization voltage line VINL, and a drain connected to the anode electrode ANODE of the light-emitting element LD. The fourth transistor T4 can transmit the initialization voltage VAINT to the anode electrode ANODE of the light-emitting element LD based on the fourth gate signal EB having an enable level.

[0051] The fifth transistor T5 may include a gate for receiving the transmit signal ET, a source connected to the second voltage line VDDL, and a drain connected to the third node N13. The fifth transistor T5 can transmit the second supply voltage ELVDD to the third node N13 based on the enable level transmit signal ET.

[0052] Storage capacitor C1 can be connected between the first node N11 and the third node N13. The light-emitting element LD can be connected to the first voltage line VSSL via the cathode electrode CATHODE. The light-emitting element LD can receive the first power supply voltage ELVSS from the first voltage line VSSL.

[0053] In the active segment, the fifth transistor T5 can be turned on based on the emit signal ET with an enable level. The gate of the sixth transistor T6 can be turned on based on the low-level voltage of the first node N11. The second transistor T2 can be turned on based on the second gate signal GB with an enable level. The second power supply voltage ELVDD can be applied to the anode electrode ANODE of the light-emitting element LD through the second voltage line VDDL, the fifth transistor T5, the sixth transistor T6, and the second transistor T2. The light-emitting element LD can be driven based on the difference between the second power supply voltage ELVDD applied to the anode electrode ANODE and the first power supply voltage ELVSS applied to the cathode electrode CATHODE. When the first power supply voltage ELVSS increases, the difference between the second power supply voltage ELVDD of the anode electrode ANODE and the first power supply voltage ELVSS applied to the cathode electrode CATHODE decreases, allowing the light-emitting element LD to be driven with lower power.

[0054] During the blanking period, the fifth transistor T5 can be turned off based on the emitter signal ET with a disable level. The gate of the sixth transistor T6 can be turned off based on the high-level voltage of the first node N11. The second transistor T2 can be turned off based on the second gate signal GB with a disable level. The fourth transistor T4 can be turned on based on the fourth gate signal EB with an enable level. The initialization voltage VAINT can be applied to the anode electrode ANODE of the light-emitting element LD through the initialization voltage line VINL and the fourth transistor T4. During the blanking period, the light-emitting element LD can have a brightness based on the difference between the initialization voltage VAINT of the anode electrode ANODE and the first power supply voltage ELVSS applied to the cathode electrode CATHODE. When the initialization voltage VAINT applied to the anode electrode ANODE of the light-emitting element LD increases based on the increase of the first power supply voltage ELVSS applied to the cathode electrode CATHODE of the light-emitting element LD, the light-emitting element LD can have a constant brightness during the blanking period.

[0055] Figure 3 This is a timing diagram illustrating the driving operation of the display panel according to an embodiment.

[0056] refer to Figure 3 , Figure 1 The timing controller 110 can operate in active mode and blanking mode based on the data enable level DE. Figure 1 Data drive 130 and Figure 1 The display panel is 150.

[0057] The timing controller 110 can operate the data driver 130 and the display panel 150 in ACTIVE mode based on a high level of the data enable level DE. The timing controller 110 can also operate the data driver 130 and the display panel 150 in BLANK mode based on a low level of the data enable level DE.

[0058] In ACTIVE mode, the data driver 130 can be based on Figure 1 The data control signal in the DCS outputs data signals to multiple data lines. Figure 1 (D1 to DN in the blanking mode). In blanking mode, the vertical synchronization signal Vsync can be activated. In blanking mode, voltage generator 170 can generate the initialization voltage VAINT based on the control signal CTRL. In blanking mode, data driver 130 can choose not to output data signals to multiple data lines D1 to DN.

[0059] A frame period FR1 or FR2 may include an active period AT1 or AT2 and a blanking period BT1 or BT2. For example, the first frame period FR1 may include a first active period AT1 and a first blanking period BT1. The second frame period FR2 following the first frame period FR1 may include a second active period AT2 and a second blanking period BT2. The active periods AT1 and AT2 may refer to the periods during which the timing controller 110, data driver 130, and display panel 150 operate in active mode ACTIVE. The blanking periods BT1 and BT2 may refer to the periods during which the timing controller 110, data driver 130, and display panel 150 operate in blanking mode BLANK.

[0060] The data driver 130 can transmit data signals to the display panel 150 during the first active period AT1 of the first frame time period FR1. The timing controller 110 can receive voltage change information TRAN as information about the amplitude change of the first power supply voltage ELVSS applied to the display panel 150 during the first blanking period BT1 of the first frame time period FR1. The timing controller 110 can generate control LDO circuitry based on the voltage change information TRAN. Figure 1 The control signal CTRL of any one of the multiple LDO circuits 171_1 to 171_N. LDO circuit ( Figure 1 Any one of the multiple LDO circuits 171_1 to 171_N in the display panel 150 can change the magnitude of the initialization voltage VAINT applied to the display panel 150 based on the control signal CTRL.

[0061] The data driver 130 can transmit data signals to the display panel 150 during the second active period AT2 of the second frame period FR2, which is continuous with the first frame period. The timing controller 110 can receive voltage change information TRAN as information about the amplitude change of the first power supply voltage ELVSS applied to the display panel 150 during the second blanking period BT2 of the second frame period FR2. The timing controller 110 can generate control LDO circuitry based on the voltage change information TRAN. Figure 1 The control signal CTRL of any one of the multiple LDO circuits 171_1 to 171_N. LDO circuit ( Figure 1 Any one of the multiple LDO circuits 171_1 to 171_N in the display panel 150 can change the magnitude of the initialization voltage VAINT applied to the display panel 150 based on the control signal CTRL.

[0062] Figure 4 This is a circuit diagram of an LDO circuit according to an embodiment.

[0063] refer to Figure 4 , Figure 1 The LDO circuit 171_1 may include an input circuit 405, a voltage distribution circuit 410, a multiplexer 430, a feedback circuit 420, an offset compensation circuit 460, and an output circuit 470.

[0064] Input circuit 405 may include a first amplifier AMP1 and input resistor circuit 440. Input resistor circuit 440 may include multiple resistors connected in series. One end of input resistor circuit 440 may be connected to the output node N1 of first amplifier AMP1. The other end of input resistor circuit 440 may be grounded.

[0065] exist Figure 1 The first voltage V1 generated in PMIC 160 can be input to the non-inverting terminal of the first amplifier AMP1 via input node N0. The inverting terminal of the first amplifier AMP1 can be connected to the input resistor circuit 440. The inverting terminal of the first amplifier AMP1 can be connected to node 1-4 N14 between two resistors connected in series among the multiple resistors included in the input resistor circuit 440. The voltage at node 1-4 N14 can be input to the inverting terminal of the first amplifier AMP1.

[0066] The voltage distribution circuit 410 can receive a first input voltage VI from the first input node N2. The first input node N2 can be connected to the output node N1 of the first amplifier AMP1. The voltage VI of the first input node N2 can be equal to the voltage of the output node N1 of the first amplifier AMP1.

[0067] Voltage distribution circuit 410 can be from Figure 1 The timing controller 110 in the middle receives Figure 1 The control signal CTRL is used in the voltage distribution circuit 410 to distribute the voltage VI of the first input node N2 based on the control signal CTRL. The voltage distribution circuit 410 can distribute the voltage VI of the first input node N2 to generate the output voltage VD.

[0068] For example, if Figure 1 The voltage change information of the control signal CTRL (TRAN) includes information for increasing the voltage applied to the signal. Figure 1 If the voltage distribution circuit 410 receives information about the first power supply voltage ELVSS of the display panel 150, it can distribute voltage VI to generate a first output voltage. When the voltage change information TRAN of the control signal CTRL includes information for reducing the first power supply voltage ELVSS applied to the display panel 150, the voltage distribution circuit 410 can distribute voltage VI to generate a second output voltage. Figure 1 The information of the first power supply voltage ELVSS of the display panel 150 is included in the control signal CTRL. Figure 1 When the voltage change information TRAN is received, the voltage distribution circuit 410 can distribute voltage VI to generate a third output voltage. The first output voltage can be greater than the third output voltage, and the third output voltage can be greater than the second output voltage.

[0069] The voltage distribution circuit 410 can transmit the output voltage VD to the multiplexer 430 through the third node N3.

[0070] Multiplexer 430 can receive output voltage VD from voltage distribution circuit 410. Multiplexer 430 can receive first voltage V1 from input circuit 405. Multiplexer 430 can receive... Figure 1 The timing controller 110 receives a control signal CTRL. The control signal CTRL may include a selection signal SEL for selecting the output voltage VD.

[0071] Multiplexer 430 can output one of an output voltage VD and a first input voltage VI based on a selection signal SEL. For example, multiple multiplexers 430 can transmit the output voltage VD to output circuit 470 based on a selection signal SEL with an enable level. Multiplexer 430 can transmit a first voltage V1 to output circuit 470 based on a selection signal SEL with a disable level.

[0072] The offset compensation circuit 460 may include a second amplifier AMP2 and an offset resistor 450. The offset resistor 450 may include multiple resistors connected in series. One end of the offset resistor 450 may be connected to the output node N6 of the second amplifier AMP2. The other end of the offset resistor 450 may be grounded.

[0073] The second voltage V2 generated in PMIC 160 can be input to the non-inverting terminal of the second amplifier AMP2. The second voltage V2 can be a preset voltage. The second voltage V2 can be applied to the offset compensation circuit 460 to compensate for the offset voltage caused by process variations and stress effects of the LDO circuit.

[0074] The inverting terminal of the second amplifier AMP2 can be connected to the offset resistor 450. The inverting terminal of the second amplifier AMP2 can also be connected to node 1-5 N15 between two resistors connected in series among the multiple resistors included in the offset resistor 450. The voltage at node 1-5 N15 can be input to the inverting terminal of the second amplifier AMP2.

[0075] Offset compensation circuit 460 can transmit offset compensation current IOS to feedback circuit 420 through output node N6. Feedback circuit 420 can receive offset compensation current IOS from offset compensation circuit 460. Feedback circuit 420 can receive initialization voltage VAINT from initialization node NA of output circuit 470. Feedback circuit 420 can receive control signal CTRL from timing controller 110. Control signal CTRL may include selection signal SEL for selecting output voltage VD. Feedback circuit 420 can generate feedback voltage VFD based on selection signal SEL by allocating initialization voltage VAINT.

[0076] Feedback circuit 420 can generate a first feedback voltage based on a selection signal SEL with a disable level. Feedback circuit 420 can generate a second feedback voltage based on a selection signal SEL with an enable level. The difference between the second feedback voltage and the initialization voltage VAINT can be less than the difference between the first feedback voltage and the initialization voltage VAINT. Feedback circuit 420 can transmit either the first or second feedback voltage as the feedback voltage VFD to output circuit 470.

[0077] The output circuit 470 may include a third amplifier AMP3, a PMOS transistor TP, and an NMOS transistor TN. The non-inverting terminal of the third amplifier AMP3 can receive one of the output voltage VD and the first voltage V1 from the multiplexer 430. The inverting terminal of the third amplifier AMP3 can receive the feedback voltage VFD from the feedback circuit 420.

[0078] The source of the PMOS transistor TP can be supplied with a drive voltage AVDD. The gate of the PMOS transistor TP can receive the output voltage of the third amplifier AMP3. The drain of the PMOS transistor TP can be connected to the fourth node N4.

[0079] The drain of NMOS transistor TN can be connected to the fourth node N4. The gate of NMOS transistor TN can receive the output voltage of the third amplifier AMP3. The source of NMOS transistor TN can be grounded.

[0080] Output circuit 470 can generate an initialization voltage VAINT based on a feedback voltage VFD and one of an output voltage VD and a first voltage V1. When output circuit 470 receives the output voltage VD based on a selection signal SEL with an enable level, output circuit 470 can generate a first initialization voltage based on the output voltage VD and a second feedback voltage. When output circuit 470 receives the first voltage V1 based on a selection signal SEL with a disable level, output circuit 470 can generate a second initialization voltage based on the first voltage V1 and the first feedback voltage. The voltage difference between the first initialization voltage and the initialization voltage VAINT can be greater than the voltage difference between the second initialization voltage and the initialization voltage VAINT. The difference between the first initialization voltage and the initialization voltage VAINT can correspond to an increase or decrease in the first power supply voltage ELVSS. Output circuit 470 can transmit the initialization voltage VAINT to display panel 150 through initialization node NA.

[0081] When the LDO circuit 171_1 generates the initialization voltage VAINT using the output voltage VD, the conversion rate of the generation speed of the initialization voltage VAINT can be improved compared to when the initialization voltage VAINT is generated based on the first input voltage VI. The output voltage VD can be the voltage assigned to the first input voltage VI based on the voltage change information TRAN. The output voltage VD can be a voltage corresponding to an increase or decrease in the first power supply voltage ELVSS. For example, if the voltage change information TRAN includes information for increasing the first power supply voltage ELVSS, the LDO circuit 171_1 can use the first output voltage to generate the initialization voltage VAINT. When the voltage change information TRAN includes information for decreasing the first power supply voltage ELVSS, the LDO circuit 171_1 can use a second output voltage to generate the initialization voltage VAINT. If the voltage change information TRAN includes information for maintaining the first power supply voltage ELVSS, the LDO circuit 171_1 can use a third output voltage to generate the initialization voltage VAINT. The first output voltage can be greater than the third output voltage, and the third output voltage can be greater than the second output voltage.

[0082] The first input voltage VI may be a voltage that does not correspond to an increase or decrease in the first supply voltage ELVSS. If the LDO circuit 171_1 generates the initialization voltage VAINT uniformly based on the first input voltage VI, the conversion rate of the initialization voltage VAINT generation speed may be reduced.

[0083] Since the LDO circuit 171_1 outputs the initialization voltage VAINT based on the voltage change information of the first power supply voltage ELVSS, therefore Figure 2 The light-emitting element (LD) can have a constant brightness during the blanking period. For example, the LDO circuit 171_1 can increase the initialization voltage VAINT in response to an increase in the first supply voltage ELVSS. The LDO circuit 171_1 can decrease the initialization voltage VAINT in response to a decrease in the first supply voltage ELVSS.

[0084] LDO circuit 171_1 can be driven based on a selection signal SEL with an enable level. By driving LDO circuit 171_1 based on the selection signal SEL, LDO circuit 171_1 can be driven at low power based on a selection signal SEL with a disable level.

[0085] Figure 5 This is a circuit diagram of the voltage distribution circuit according to an embodiment.

[0086] refer to Figure 5 The voltage distribution circuit 410 may include a first resistor circuit 414, a first distribution circuit 411, a second distribution circuit 412, and a third distribution circuit 413.

[0087] The first resistor circuit 414 may include a first resistor group 414-1, a second resistor group 414-2, and a third resistor group 414-3. Each of the first resistor group 414-1, the second resistor group 414-2, and the third resistor group 414-3 may include multiple resistors. One end of the first resistor group 414-1 may be connected to a first input node N41. The first input node N41 may be connected to... Figure 1 The first input node N2 is the same. The other end of the first resistor group 414-1 can be connected to the second input node N42. One end of the third resistor group 414-3 can be connected to the third input node N43. The other end of the third resistor group 414-3 can be connected to the fourth input node N44. The first power supply voltage ELVSS can be applied to the third resistor group 414-3 through the fourth input node N44. The second resistor group 414-2 can be placed between the first resistor group 414-1 and the third resistor group 414-3. The first resistor group 414-1 and the second resistor group 414-2 can be connected through the second input node N42. The second resistor group 414-2 and the third resistor group 414-3 can be connected through the third input node N43.

[0088] The first distribution circuit 411 may include a first multiplexer MUX#1, a first CMOS pass gate 4111, and a second CMOS pass gate 4112.

[0089] The first multiplexer MUX#1 can be connected to the first resistor group 414-1 and multiple voltage lines. The first multiplexer MUX#1 can receive multiple voltages having levels between the first input voltage VI and the first supply voltage ELVSS via the multiple voltage lines. For example, the first multiplexer MUX#1 can be connected to the first resistor group 414-1 and voltage lines P11 and P12. The first multiplexer MUX#1 can receive the 1-1 input voltage V11 through node N51 of voltage line P11. The first multiplexer MUX#1 can receive the first-second input voltage V12 through node N52 of voltage line P12.

[0090] The first multiplexer MUX#1 can receive a first selection signal SEL1. The first selection signal SEL1 can be a signal used to select one of a plurality of voltages input to the first multiplexer MUX#1. The first selection signal SEL1 can be included in... Figure 1 The control signal CTRL is used in the system.

[0091] The first multiplexer MUX#1 can output any one of the multiple input voltages as the first pass voltage VP1 to node 1-3 N53. For example, the first multiplexer MUX#1 can output the 1-1 input voltage V11 input through node 1-1 N51 as the first pass voltage VP1 to node 1-3 N53.

[0092] The first CMOS pass gate 4111 may include a 1-1 PMOS transistor T11 and a 1-1 NMOS transistor T12. The 1-1 PMOS transistor T11 and the 1-1 NMOS transistor T12 may be connected in parallel. The source of the 1-1 PMOS transistor T11 may be connected to node 1-3 N53. The drain of the 1-1 PMOS transistor T11 may be connected to node 1-4 N54. The gate of the 1-1 PMOS transistor T11 may receive an overdrive disable control signal ODB. The drain of the 1-1 NMOS transistor T12 may be connected to node 1-3 N53. The source of the 1-1 NMOS transistor T12 may be connected to node 1-4 N54. The gate of the 1-1 NMOS transistor T12 may receive an overdrive enable signal OD. The overdrive enable signal OD and the overdrive disable control signal ODB may be included in the control signal CTRL.

[0093] When used to change Figure 2 The magnitude of the first power supply voltage ELVSS is included in the information received from the processor. Figure 1 When the voltage change information is in TRAN Figure 1The timing controller 110 can generate a control signal CTRL that includes an overdrive enable signal OD with an enable level and an overdrive disable control signal ODB with a disable level.

[0094] The first CMOS pass gate 4111 can transmit the first pass voltage VP1 as the second pass voltage VP2 to node N54 of 1-4 based on the overdrive disable control signal ODB with a disable level and the overdrive enable control signal OB with an enable level.

[0095] The second CMOS pass gate 4112 may include 1-2 PMOS transistors T13 and 1-2 NMOS transistors T14. The 1-2 PMOS transistors T13 and T14 may be connected in parallel. The source of the 1-2 PMOS transistors T13 may be connected to node N54 (1-4). The drain of the 1-2 PMOS transistors T13 may be connected to node N55 (1-5). The gate of the 1-2 PMOS transistors T13 may receive a first transition disable signal LHB. The drain of the 1-2 NMOS transistors T14 may be connected to node N54 (1-4). The source of the 1-2 NMOS transistors T14 may be connected to node N55 (1-5). The gate of the 1-2 NMOS transistors T14 may receive a first transition enable signal LH. The first transition enable signal LH and the first transition disable signal LHB may be included in the control signal CTRL.

[0096] If the voltage change information TRAN received from the processor includes information for increasing the first power supply voltage ELVSS, then the timing controller 110 can generate a control signal CTRL that includes a first transition enable signal LH with an enable level and a first transition disable signal LHB with a disable level.

[0097] The second CMOS pass gate 4112 can transmit the second pass voltage VP2 as the first output voltage VO1 to node N55 of 1-5 based on the first transition disable signal LHB with a disable level and the first transition enable signal LH with an enable level.

[0098] The second distribution circuit 412 may include a third CMOS pass gate 4121.

[0099] The third CMOS pass gate 4121 may include a 2-1 PMOS transistor T21 and a 2-1 NMOS transistor T22. The 2-1 PMOS transistor T21 and the 2-1 NMOS transistor T22 may be connected in parallel. The source of the 2-1 PMOS transistor T21 may be connected to node N61 (2-1). The source of the 2-1 PMOS transistor T21 may receive the 2-1 input voltage V21 from node N61 (2-1). The 2-1 input voltage V21 may be less than the 1-1 input voltage V11 and the 1-2 input voltage V12. The drain of the 2-1 PMOS transistor T21 may be connected to node N62 (2-2). The gate of the 2-1 PMOS transistor T21 may receive the overdrive enable signal OD.

[0100] The drain of NMOS transistor T22 (2-1) can be connected to node N61 (2-1). The drain of NMOS transistor T22 (2-1) can receive the input voltage V21 (2-1) from node N61 (2-1). The source of NMOS transistor T22 (2-1) can be connected to node N62 (2-2). The gate of NMOS transistor T22 (2-1) can receive the overdrive disable signal ODB. The overdrive enable signal OD and the overdrive disable control signal ODB can be included in the control signal CTRL.

[0101] If the voltage change information TRAN received from the processor includes information for maintaining the magnitude of the first power supply voltage ELVSS, then the timing controller 110 can generate a control signal CTRL that includes an overdrive enable signal OD with a disable level and an overdrive disable control signal ODB with an enable level.

[0102] The third CMOS pass gate 4121 can transmit the second output voltage VO2 to node N62 based on the overdrive enable signal OD with a disable level and the overdrive disable control signal ODB with an enable level.

[0103] The third distribution circuit 413 may include a second multiplexer MUX#2, a fourth CMOS pass gate 4131, and a fifth CMOS pass gate 4132.

[0104] The second multiplexer MUX#2 can be connected to the third resistor group 414-3 and multiple voltage lines. The second multiplexer MUX#2 can receive multiple voltages with levels between the first input voltage VI and the first supply voltage ELVSS via the multiple voltage lines. For example, the second multiplexer MUX#2 can be connected to the third resistor group 414-3 and voltage lines 3-1 P31 and 3-2 P32. The second multiplexer MUX#2 can receive the 3-1 input voltage V31 via node N71 of voltage line 3-1 P31. The second multiplexer MUX#2 can receive the 3-2 input voltage V32 via node N72 of voltage line 3-2 P32. The 3-1 input voltage V31 and the 3-2 input voltage V32 can be less than the 2-1 input voltage V21.

[0105] The second multiplexer MUX#2 can receive a second selection signal SEL2. The second selection signal SEL2 can be a signal used to select one of multiple voltages input to the second multiplexer MUX#2. The second selection signal SEL2 can be included in the control signal CTRL.

[0106] The second multiplexer MUX#2 can output any one of the multiple input voltages as the third pass voltage VP3 to node 3-3 N73. For example, the second multiplexer MUX#2 can output the 3-1 input voltage V31, which is input through node 3-1 N71, as the third pass voltage VP3 to node 3-3 N73.

[0107] The fourth CMOS pass gate 4131 may include a 3-1 PMOS transistor T31 and a 3-1 NMOS transistor T32. The 3-1 PMOS transistor T31 and the 3-1 NMOS transistor T32 may be connected in parallel. The source of the 3-1 PMOS transistor T31 may be connected to node 3-3 N73. The drain of the 3-1 PMOS transistor T31 may be connected to node 3-4 N74. The gate of the 3-1 PMOS transistor T31 may receive an overdrive disable control signal ODB. The drain of the 3-1 NMOS transistor T32 may be connected to node 3-3 N73. The source of the 3-1 NMOS transistor T32 may be connected to node 3-4 N74. The gate of the 3-1 NMOS transistor T32 may receive an overdrive enable signal OD. The overdrive enable signal OD and the overdrive disable control signal ODB may be included in the control signal CTRL.

[0108] When the voltage change information TRAN received from the processor includes information for changing the magnitude of the first power supply voltage ELVSS, the timing controller 110 can generate a control signal CTRL that includes an overdrive enable signal OD with an enable level and an overdrive disable control signal ODB with a disable level.

[0109] The fourth CMOS pass gate 4131 can transmit the third pass voltage VP3 as the fourth pass voltage VP4 to the third-fourth node N74 based on the overdrive disable control signal ODB with a disable level and the overdrive enable control signal OB with an enable level.

[0110] The fifth CMOS pass gate 4132 may include a third-second PMOS transistor T33 and a third-second NMOS transistor T34. The 3-2 PMOS transistor T33 and the 3-2 NMOS transistor T34 may be connected in parallel. The source of the 3-2 PMOS transistor T33 may be connected to node 3-4 N74. The drain of the 3-2 PMOS transistor T33 may be connected to node 3-5 N75. The gate of the 3-2 PMOS transistor T33 may receive a second transition disable signal HLB. The drain of the 3-2 NMOS transistor T34 may be connected to node 3-4 N74. The source of the 3-2 NMOS transistor T34 may be connected to node 3-5 N75. The gate of the 3-2 NMOS transistor T34 may receive a second transition enable signal HL. The second transition enable signal HL and the second transition disable signal HLB may be included in the control signal CTRL.

[0111] When the voltage change information TRAN includes information for reducing the first power supply voltage ELVSS, the timing controller 110 can generate a control signal CTRL that includes a second transition enable signal HL with an enable level and a second transition disable signal HLB with a disable level.

[0112] The fifth CMOS pass gate 4132 can transmit the fourth pass voltage VP4 as the third output voltage VO3 to the 3-5 node N75 based on the second transition disable signal HLB with a disable level and the second transition enable signal HL with an enable level.

[0113] Figure 6 This is a circuit diagram of the feedback circuit according to an embodiment.

[0114] Feedback circuit 420 may include a second resistor circuit 423, a non-tracking circuit 421, and a tracking circuit 422. The second resistor circuit 423 may include a first initialization resistor group 4231 and a second initialization resistor group 4232. One end of the first initialization resistor group 4231 can receive an initialization voltage from initialization node NA through a first initialization resistor node N94. The other end of the first initialization resistor group 4231 can be connected to one end of the second initialization resistor group 4232 through a second initialization resistor node N96. The other end of the second initialization resistor group can receive an offset compensation current IOS through a third initialization resistor node N98.

[0115] The first initialization resistor group 4231 and the second initialization resistor group 4232 may each include multiple resistors. For example, the first resistor R1 in the first initialization resistor group 4231 may be connected between the first initialization resistor node N94 and the 9-5 node N95. The second resistor R2 in the first initialization resistor group 4231 may be connected between the 9-5 node N95 and the second initialization resistor node N96. The third resistor R3 in the second initialization resistor group 4232 may be connected between the second initialization resistor node N96 and the 9-7 node N97. The fourth resistor R4 in the second initialization resistor group 4232 may be connected between the 9-7 node N97 and the third initialization resistor node N98.

[0116] The non-tracking circuit 421 may include a 4-1 PMOS transistor T41 and a 4-1 NMOS transistor T42. The 4-1 PMOS transistor T41 and the 4-1 NMOS transistor T42 may be connected in parallel. The source of the 4-1 PMOS transistor T41 can be connected to node N95 at node 9-5 via a first initialization voltage line P95. The source of the 4-1 PMOS transistor T41 can receive a first intermediate voltage V95 from node N95 at node 9-5 via the first initialization voltage line P95. The drain of the 4-1 PMOS transistor T41 can be connected to node N91 at node 4-1. The gate of the 4-1 PMOS transistor T41 can receive a selection signal SEL. The selection signal SEL can be compared with the signal applied to... Figure 4 The signals of the multiplexer 430 in the middle are the same.

[0117] The source of NMOS transistor T42 (4-1) can be connected to node N91 (4-1). The drain of NMOS transistor T42 (4-1) can be connected to node N95 (9-5) via the first initialization voltage line P95. The drain of NMOS transistor T42 (4-1) can receive the first intermediate voltage V95 of node N95 (9-5) via the first initialization voltage line P95. The gate of NMOS transistor T42 (4-1) can receive the select disable signal SELB. The select disable signal SELB can be the opposite of the select signal SEL. The enable level of the select disable signal SELB can be the same voltage level as the disable level of the select signal SEL. The disable level of the select disable signal SELB can be the same voltage level as the enable level of the select signal SEL.

[0118] The tracking circuit 422 may include a 5-1 PMOS transistor T51 and a 5-1 NMOS transistor T52. The 5-1 PMOS transistor T51 and the 5-1 NMOS transistor T52 may be connected in parallel. The source of the 5-1 PMOS transistor T51 can be connected to node N97 (9-7) via a second initialization voltage line P97. The source of the 5-1 PMOS transistor T51 can receive a second intermediate voltage V97 from node N97 (9-7) via the second initialization voltage line P97. The second intermediate voltage V97 may be less than a first intermediate voltage V95. The drain of the 5-1 PMOS transistor T51 can be connected to node N92 (4-2). The gate of the 5-1 PMOS transistor T51 can receive a select disable signal SELB.

[0119] The source of NMOS transistor T52 (5-1) can be connected to node N92 (4-2). The drain of NMOS transistor T52 (5-1) can be connected to node N97 (9-7) via the second initialization voltage line P97. The drain of NMOS transistor T52 (5-1) can receive the second intermediate voltage V97 of node N97 (9-7) via the second initialization voltage line P97. The gate of NMOS transistor T52 (5-1) can receive the selection signal SEL.

[0120] Feedback circuit 420 can transmit the first feedback voltage VF1 or the second feedback voltage VF2 to the 4-3 node N93. Figure 4 The third amplifier AMP3 in the output circuit 470. When the enable level of the selection signal SEL is applied to the tracking circuit 422 and the non-tracking circuit 421, the feedback circuit 420 can transmit the second intermediate voltage V97 as the second feedback voltage VF2 to the third amplifier AMP3. The selection disable signal SELB can have a disable level.

[0121] When a selection signal SEL with a disable level is applied to the tracking circuit 422 and the non-tracking circuit 421, the feedback circuit 420 can transmit the first intermediate voltage V95 as the first feedback voltage VF1 to the third amplifier AMP3. The selection disable signal SELB can have an enable level.

[0122] When the selection signal SEL with an enable level is applied to the tracking circuit 422 and the non-tracking circuit 421, the feedback circuit 420 can transmit the second intermediate voltage V97 as the second feedback voltage VF2 to the third amplifier AMP3. The selection disable signal SELB can have a disable level.

[0123] Figure 7 This is a timing diagram of the first power supply voltage and control signal according to an embodiment.

[0124] refer to Figure 7 In the first segment S1, the first power supply voltage ELVSS can be at a low level L. At this time, the first transition enable signal LH, the second transition enable signal HL, and the overdrive enable signal OD can be at a disabled level.

[0125] In the second segment S2, the first power supply voltage ELVSS can transition from a low level L to a high level H. During this time, the first transition enable signal LH and the overdrive enable signal OD can be at the enabled level during time periods t1 to t12 of the second segment S2. During time periods t12 to t2 of the second segment S2, the first transition enable signal LH and the overdrive enable signal OD can be at the disabled level.

[0126] In the third segment S3, the first power supply voltage ELVSS can be at a high level H. At this time, the first transition enable signal LH, the second transition enable signal HL, and the overdrive enable signal OD can be at a disabled level.

[0127] In the fourth segment S4, the first power supply voltage ELVSS can transition from a high level H to a low level L. During this time, the second transition enable signal HL and the overdrive enable signal OD can be at the enabled level during time periods t3 to t34 of the fourth segment S4. During time periods t34 to t4 of the fourth segment S4, the second transition enable signal HL and the overdrive enable signal OD can be at the disabled level.

[0128] In the fifth segment S5, the first power supply voltage ELVSS can be at a low level L. At this time, the first transition enable signal LH, the second transition enable signal HL, and the overdrive enable signal OD can be at a disabled level.

[0129] Figure 8 This is a timing diagram of the first power supply voltage according to an embodiment. Figure 9It is a timing diagram of the initialization voltage according to the embodiment, and Figure 10 This is a timing diagram illustrating the difference between the first power supply voltage and the initialization voltage according to an embodiment.

[0130] refer to Figure 8 In the first segment S1, the first power supply voltage ELVSS can be a low-level voltage Vb. In the second segment S2, the first power supply voltage ELVSS can change from a low-level voltage Vb to a high-level voltage Va. In the third segment S3, the first power supply voltage ELVSS can be a high-level voltage Va.

[0131] refer to Figure 9 According to the embodiment, the initialization voltage Fa can represent the use of Figure 1 The initialization voltage is generated by the LDO circuit 171_1, which includes the voltage distribution circuit 410 and the feedback circuit 420. The second initialization voltage Fb can represent the initialization voltage generated using the LDO circuit excluding the voltage distribution circuit 410 and the feedback circuit 420.

[0132] In the first segment S1, the first initialization voltage Fa and the second initialization voltage Fb can both be low-level voltages Vd. In the 2-1 segment SF2, the first initialization voltage Fa can transition from low-level voltage Vd to high-level voltage Vc. In the 2-2 segment SB2, the second initialization voltage Fb can transition from low-level voltage Vd to high-level voltage Vc.

[0133] The second-1 segment SF2 can be shorter than the second-2 segment SB2. For example, the first initialization voltage Fa can transition from a low-level voltage Vd to a high-level voltage Vc during the time period t1 to tf of the second-1 segment SF2. The second initialization voltage Fb can transition from a low-level voltage Vd to a high-level voltage Vc during the time period t1~tb (tb>tf) of the second-2 segment SB2. The voltage transition speed of the first initialization voltage Fa can be higher than that of the second initialization voltage Fb. Therefore, compared with the conversion rate performance of an LDO circuit excluding the voltage distribution circuit 410 and the feedback circuit 420, the conversion rate performance according to the embodiment is higher. Figure 1 The conversion rate performance of the LDO circuit 171_1, which includes voltage distribution circuit 410 and feedback circuit 420, can be improved.

[0134] In segment SF3 (3-1), the first initialization voltage Fa can be a high-level voltage Vc. In segment SB3 (3-2), the second initialization voltage Fb can be a high-level voltage Vc.

[0135] refer to Figure 10The first differential voltage (delta) Da can represent the difference between the first initialization voltage Fa and the first power supply voltage ELVSS. The second differential voltage Db can represent the difference between the second initialization voltage Fb and the first power supply voltage ELVSS.

[0136] In the first segment S1, the first differential voltage Da and the second differential voltage Db can both be low-level voltages Vb-Vd. In the second segment S2, the first differential voltage Da at point tx can be the first maximum voltage Vf. The second differential voltage Db at point tx in the second segment S2 can be the second maximum voltage Ve. The second maximum voltage Ve can be greater than the first maximum voltage Vf. In the third segment S3, the first differential voltage Da and the second differential voltage Db can both be low-level voltages Vb-Vd.

[0137] refer to Figure 2 When applied to Figure 2 LED light-emitting element Figure 2 When the initial voltage VAINT of the anode electrode increases in response to the increase of the first power supply voltage ELVSS, Figure 2 The light-emitting element (LD) can have a constant brightness. The difference between the initialization voltage VAINT and the first power supply voltage ELVSS can be reduced. Therefore, the first difference voltage Da can provide a greater constant brightness to the LD than the second difference voltage Db.

[0138] Figure 11 This is a timing diagram of the first power supply voltage and control signal according to an embodiment.

[0139] refer to Figure 11 In the first segment S1, the first power supply voltage ELVSS can be at a low level L. At this time, the first transition enable signal LH, the second transition enable signal HL, and the overdrive enable signal OD can be at a disabled level.

[0140] In the second segment S2, the first power supply voltage ELVSS can transition from a low level L to a high level H. The first transition enable signal LH and the overdrive enable signal OD can be enabled based on a delay value Td and a pulse width W. For example, the delay value Td can be t12-t1 (seconds). The pulse width W can be t13-t12 (seconds). During the time period t1 to t12 of the second segment S2, the first transition enable signal LH and the overdrive enable signal OD can be at a disabled level. During the time period t12 to t13 of the second segment S2, the first transition enable signal LH and the overdrive enable signal OD can be at an enabled level. During the time period t13 to t2 of the second segment S2, the first transition enable signal LH and the overdrive enable signal OD can be at a disabled level.

[0141] In the third segment S3, the first power supply voltage ELVSS can be at a high level H. At this time, the first transition enable signal LH, the second transition enable signal HL, and the overdrive enable signal OD can be at a disabled level.

[0142] In the fourth segment S4, the first power supply voltage ELVSS can transition from a high level H to a low level L. The second transition enable signal HL and the overdrive enable signal OD can be enabled based on a delay value Td and a pulse width W. For example, the delay value Td can be t32-t3 (seconds), and the pulse width W can be t33-t32 (seconds). During the time period t3 to t32 of the fourth segment S4, the second transition enable signal HL and the overdrive enable signal OD can be at a disabled level. During the time period t32 to t33 of the fourth segment S4, the second transition enable signal HL and the overdrive enable signal OD can be at an enabled level. During the time period t33 to t4 of the fourth segment S4, the second transition enable signal HL and the overdrive enable signal OD can be at a disabled level.

[0143] In the fifth segment S5, the first power supply voltage ELVSS can be at a low level L. At this time, the first transition enable signal LH, the second transition enable signal HL, and the overdrive enable signal OD can be at a disabled level.

[0144] Figure 12 This is a diagram illustrating bit information, delay value, pulse width, and fluctuation value of a first power supply voltage included in a memory according to an embodiment.

[0145] refer to Figure 12 , Figure 1 The memory 111 may include an instruction Figure 1 The delay value DELAY and pulse width value PULSEWIDTH of the control signal CTRL are specified in bits. The delay value DELAY and pulse width value PULSEWIDTH can be based on information included in... Figure 1 Voltage change information in TRAN Figure 1 The fluctuation value ΔV of the first power supply voltage ELVSS is used to determine the voltage.

[0146] As the fluctuation value ΔV of the first power supply voltage ELVSS increases, Figure 1 The LDO circuit 171_1 can increase the fluctuation value of the first initialization voltage VAINT. Therefore, the delay value DELAY of the control signal CTRL used to control the LDO circuit 171_1 can be determined to decrease. The pulse width value PULSEWIDTH of the control signal CTRL used to control the LDO circuit 171_1 can be determined to increase.

[0147] For example, if the fluctuation value ΔV of the first power supply voltage ELVSS is Vd1, then the delay value DELAY can be the first delay Td1, and the pulse width value PULSEWIDTH can be the first pulse width W1. The fluctuation value ΔV (Vd1), the first delay Td1, and the first pulse width W1 of the first power supply voltage ELVSS can be stored as bit information as "00" in memory 111.

[0148] If the fluctuation value ΔV of the first power supply voltage ELVSS is Vd2 (Vd2>Vd1), then the delay value DELAY can be the second delay Td2, and the pulse width value PULSEWIDTH can be the second pulse width W2. The second delay Td2 can be less than the first delay Td1. The second pulse width W2 can be greater than the first pulse width W1. The fluctuation value ΔV (Vd2) of the first power supply voltage ELVSS, the second delay Td2, and the second pulse width W2 can be stored as bit information as "01" in memory 111.

[0149] If the fluctuation value ΔV of the first power supply voltage ELVSS is Vd3 (Vd3>Vd2), then the delay value DELAY can be the third delay Td3, and the pulse width value PULSEWIDTH can be the third pulse width W3. The third delay Td3 can be less than the second delay Td2. The third pulse width W3 can be greater than the second pulse width W2. The fluctuation value ΔV (Vd3) of the first power supply voltage ELVSS, the third delay Td3, and the third pulse width W3 can be stored as bit information as "10" in memory 111.

[0150] If the fluctuation value ΔV of the first power supply voltage ELVSS is Vd4 (Vd4>Vd3), then the delay value DELAY can be the fourth delay Td4, and the pulse width value PULSEWIDTH can be the fourth pulse width W4. The fourth delay Td4 can be less than the third delay Td3. The fourth pulse width W4 can be greater than the third pulse width W3. The fluctuation value ΔV (Vd4) of the first power supply voltage ELVSS, the fourth delay Td4, and the fourth pulse width W4 can be stored as bit information as "11" in memory 111.

[0151] Figure 13 It is a timing diagram of the first power supply voltage and control signal according to an embodiment, and Figure 14 It is a timing diagram based on the first power supply voltage and control signal of the comparison example.

[0152] refer to Figure 13 In the first segment S1, the first power supply voltage ELVSS can be at a low level L. At this time, the first transition enable signal LH, the second transition enable signal HL, and the overdrive enable signal OD can be at a disabled level.

[0153] In the second segment S2, the first power supply voltage ELVSS can transition from a low level L to a high level H.

[0154] The fluctuation value ΔV of the first power supply voltage ELVSS can be Figure 12 Vd1. The first transition enable signal LH and the overdrive enable signal OD can be based on Figure 12 The first delay Td1 and Figure 12 The first pulse width W1 is enabled. For example, the first delay Td1 can be t14-t1 (seconds) or t34-t3 (seconds). The pulse width W can be t15-t14 (seconds) or t35-t34 (seconds). During the time period t1 to t14 of the second segment S2, the first transition enable signal LH and the overdrive enable signal OD can be at the disabled level. During the time period t14 to t15 of the second segment S2, the first transition enable signal LH and the overdrive enable signal OD can be at the enabled level. During the time period t15 to t2 of the second segment S2, the first transition enable signal LH and the overdrive enable signal OD can be at the disabled level.

[0155] In the third segment S3, the first power supply voltage ELVSS can be at a high level H. At this time, the first transition enable signal LH, the second transition enable signal HL, and the overdrive enable signal OD can be at a disabled level.

[0156] In the fourth segment S4, the first power supply voltage ELVSS can transition from a high level H to a low level L. During time periods t3 to t34 of the fourth segment S4, the second transition enable signal HL and the overdrive enable signal OD can be at a disabled level. During time periods t34 to t35 of the fourth segment S4, the second transition enable signal HL and the overdrive enable signal OD can be at an enabled level. During time periods t35 to t4 of the fourth segment S4, the second transition enable signal HL and the overdrive enable signal OD can be at a disabled level.

[0157] In the fifth segment S5, the first power supply voltage ELVSS can be at a low level L. At this time, the first transition enable signal LH, the second transition enable signal HL, and the overdrive enable signal OD can be at a disabled level.

[0158] refer to Figure 14 In the first segment S1, the first power supply voltage ELVSS can be at a low level L. At this time, the first transition enable signal LH, the second transition enable signal HL, and the overdrive enable signal OD can be at a disabled level.

[0159] In the second segment S2, the first power supply voltage ELVSS can transition from low level L to high level H. The fluctuation value ΔV of the first power supply voltage ELVSS can be... Figure 12Vd4. The first transition enable signal LH and the overdrive enable signal OD can be based on Figure 12 The fourth delay Td4 and Figure 12 The fourth pulse width W4 is enabled. For example, the fourth delay Td4 can be t16-t1 (seconds) or t36-t3 (seconds). The pulse width W can be t17-t16 (seconds) or t37-t36 (seconds). During the time period t1 to t16 of the second segment S2, the first transition enable signal LH and the overdrive enable signal OD can be at the disabled level. During the time period t16 to t17 of the second segment S2, the first transition enable signal LH and the overdrive enable signal OD can be at the enabled level. During the time period t17 to t2 of the second segment S2, the first transition enable signal LH and the overdrive enable signal OD can be at the disabled level.

[0160] In the third segment S3, the first power supply voltage ELVSS can be at a high level H. At this time, the first transition enable signal LH, the second transition enable signal HL, and the overdrive enable signal OD can be at a disabled level.

[0161] In the fourth segment S4, the first power supply voltage ELVSS can transition from a high level H to a low level L. During time periods t3 to t36 of the fourth segment S4, the second transition enable signal HL and the overdrive enable signal OD can be at a disabled level. During time periods t36 to t37 of the fourth segment S4, the second transition enable signal HL and the overdrive enable signal OD can be at an enabled level. During time periods t37 to t4 of the fourth segment S4, the second transition enable signal HL and the overdrive enable signal OD can be at a disabled level.

[0162] In the fifth segment S5, the first power supply voltage ELVSS can be at a low level L. At this time, the first transition enable signal LH, the second transition enable signal HL, and the overdrive enable signal OD can be at a disabled level.

[0163] Figure 15 This is a block diagram of an electronic device according to an embodiment.

[0164] refer to Figure 15 The electronic device 1500 according to the embodiment may include a processor 1510, a power module 1520, a display module 1530, and a memory 1540.

[0165] The processor 1510 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), or a controller.

[0166] The memory 1540 can store data information required for the operation of the processor 1510 or the display module 1530. When the processor 1510 runs the application stored in the memory 1540, image data signals and / or input control signals are transmitted to the display module 1530, and the display module 1530 can process the received signals and output image information through the display screen.

[0167] Power module 1520 may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of electronic device 1500. Power module 1520 may supply power to display module and processor.

[0168] As mentioned above Figure 1 The display module 1530 may include multiple pixels containing light-emitting elements. (As mentioned above regarding...) Figures 1 to 13 As described above, the display module 1530 can change the magnitude of the initial voltage applied to the anode electrode of the light-emitting element. (As mentioned above regarding...) Figures 1 to 13 The display module 1530 can receive voltage change information as information about the amplitude of a first power supply voltage applied to the cathode electrode of the light-emitting element, and generate a control signal based on the voltage change information. (As for...) Figures 1 to 13 The display module 1530 can generate an initial voltage based on a control signal.

[0169] As described above, the display module 1530 can output an initialization voltage based on voltage change information of the first power supply voltage. If the voltage change information includes information for increasing the first power supply voltage, the display module 1530 can generate a first output voltage. If the voltage change information includes information for decreasing the first power supply voltage, the display module 1530 can generate a second output voltage lower than the first output voltage. If the voltage change information includes information for maintaining the first power supply voltage, the display module 1530 can generate a third output voltage lower than the first output voltage and higher than the second output voltage.

[0170] Because the display module 1530 outputs an initialization voltage based on voltage change information, the light-emitting element can maintain a constant brightness during the blanking period. For example, the display module 1530 can increase the magnitude of the initialization voltage in response to an increase in the first power supply voltage. The display module 1530 can decrease the magnitude of the initialization voltage in response to a decrease in the first power supply voltage.

[0171] The display module 1530 can be driven based on a selection signal with an enable level. By driving the display module 1530 based on the selection signal, the display module 1530 can be driven at low power when the selection signal is disabled.

[0172] At least one of the components of the above-described electronic device 1500 may be included in the display device according to the above embodiments.

[0173] In addition, some of the modules that are functionally included within the module can be included in the display device, while other modules can be provided separately from the display device.

[0174] For example, the display device may include a display module 1530, and the processor 1510, memory 1540, and power module 1520 may be provided as other devices within the electronic device 1500 besides the display device.

[0175] While various embodiments have been described above with reference to the accompanying drawings, various embodiments may be changed and modified within the context of this disclosure, and all such changes and modifications are included within the scope of the appended claims.

Claims

1. A display device comprising: The display panel includes a plurality of pixels, each of which includes a light-emitting element; A power generation circuit includes a low-dropout regulator circuit configured to change the magnitude of the initial voltage applied to the anode electrode of the light-emitting element. and A timing controller is configured to receive voltage change information regarding the amplitude of a first power supply voltage applied to the cathode electrode of the light-emitting element, and to generate a control signal for controlling the low-dropout regulator circuit based on the voltage change information.

2. The display device according to claim 1, wherein, The low-dropout regulator circuit includes: A voltage distribution circuit is configured to receive a first input voltage through a first input node and select a voltage having a level between the first input voltage and the first power supply voltage based on the control signal to generate an output voltage; A multiplexer configured to output one of the output voltage and the first input voltage based on the control signal; A feedback circuit, configured to generate a feedback voltage based on the control signal by feeding back the initialization voltage; and An output circuit is configured to receive one of the output voltage and the first input voltage from the multiplexer, receive the feedback voltage from the feedback circuit, and change the magnitude of the initialization voltage based on the feedback voltage and one of the output voltage and the first input voltage.

3. The display device according to claim 2, wherein, The voltage distribution circuit includes: The first resistor circuit includes: The first resistor group receives the first input voltage from the first input node. The second resistor group is connected to the first resistor group via the second input node, and The third resistor group is connected to the second resistor group via the third input node and receives the first power supply voltage from the fourth input node; A first distribution circuit is connected to the first resistor group and is configured to generate a first output voltage having a level between the first input voltage and the first power supply voltage as the output voltage through the first resistor group; A second distribution circuit, connected to the second resistor group, is configured to generate a second output voltage having a level between the first input voltage and the first power supply voltage as the output voltage via the second resistor group; and A third distribution circuit is connected to the third resistor group and is configured to generate a third output voltage having a level between the first input voltage and the first power supply voltage as the output voltage via the third resistor group.

4. The display device according to claim 3, wherein, The first allocation circuit includes: A first multiplexer is connected to the first resistor bank and multiple voltage lines. The first multiplexer is configured to receive multiple voltages having a level between the first input voltage and the first power supply voltage through the multiple voltage lines, and to output one of the multiple voltages as a first pass voltage. A first CMOS pass gate, connected to the first multiplexer, is configured to receive the first pass voltage and transmit the first pass voltage as a second pass voltage based on the control signal; and A second CMOS pass gate is connected to the first CMOS pass gate, and the second CMOS pass gate is configured to receive the second pass voltage and transmit the second pass voltage as the first output voltage based on the control signal.

5. The display device according to claim 4, wherein: The first CMOS pass gate and the second CMOS pass gate are also configured to receive the control signal generated based on information indicating an increase in the magnitude of the first power supply voltage according to the voltage change information. The first CMOS transfer gate is also configured to transfer the second transfer voltage, and The second CMOS pass gate is also configured to transmit the first output voltage.

6. The display device according to claim 3, wherein, The second distribution circuit includes: A third CMOS pass gate, which is connected via a voltage line to one of a plurality of resistors included in the second resistor group, is configured to receive a voltage having a level between the first input voltage and the first power supply voltage via the voltage line, and to transmit the second output voltage based on the control signal.

7. The display device according to claim 6, wherein: The third CMOS pass gate is also configured to receive the control signal generated based on information indicating that the voltage change information maintains the magnitude of the first power supply voltage, and to transmit the second output voltage.

8. The display device according to claim 3, wherein, The third distribution circuit includes: A second multiplexer is connected to the third resistor bank and multiple voltage lines. The second multiplexer is configured to receive multiple voltages having a level between the first input voltage and the first power supply voltage through the multiple voltage lines, and to output one of the multiple voltages as a third pass voltage. A fourth CMOS pass gate, connected to the second multiplexer, is configured to receive the third pass voltage and transmit the third pass voltage as a fourth pass voltage based on the control signal; and A fifth CMOS pass gate is connected to the fourth CMOS pass gate, the fifth CMOS pass gate being configured to receive the fourth pass voltage and transmit the fourth pass voltage as the third output voltage based on the control signal.

9. The display device according to claim 8, wherein: The fourth CMOS pass gate and the fifth CMOS pass gate are configured to receive the control signal generated based on information indicating a reduction in the first power supply voltage according to the voltage change information. The fourth CMOS transfer gate is also configured to transmit the fourth transfer voltage, and The fifth CMOS pass gate is also configured to transmit the third output voltage.

10. The display device according to claim 2, wherein, The control signal includes a selection signal for selecting the output voltage; The multiplexer is further configured to output the output voltage with an enable level based on the selection signal, and to output the first input voltage with a disable level based on the selection signal.

11. The display device according to claim 2, wherein, The feedback circuit includes: The second resistor circuit includes: The first initialization resistor group receives the initialization voltage from the first initialization node, and The second initialization resistor group is connected to the first initialization resistor group via the second initialization node; A non-tracking circuit, connected to the first initialization resistor group, is configured to output a first feedback voltage through the first initialization resistor group; and A tracking circuit, which is connected to the second initialization resistor group, is configured to output a second feedback voltage lower than the first feedback voltage through the second initialization resistor group.

12. The display device according to claim 11, wherein: The control signal includes a selection signal for selecting the output voltage. The tracking circuit is also configured to output the second feedback voltage based on the selection signal having an enable level, and The non-tracking circuit is also configured to output the first feedback voltage based on the selection signal having a disabled level.

13. The display device according to claim 1, wherein: The timing controller includes a memory, the memory including bit information indicating the delay value and the pulse width value of the control signal, and The delay value and the pulse width value of the control signal are based on the fluctuation value of the first power supply voltage included in the voltage change information.

14. The display device according to claim 13, wherein, When the fluctuation value of the first power supply voltage is a first value, the delay value of the control signal includes a first delay, and the pulse width value of the control signal includes a first pulse width. When the fluctuation value of the first power supply voltage is a second value that is less than the first value, the delay value of the control signal includes a second delay that is greater than the first delay, and the pulse width value of the control signal includes a second pulse width that is smaller than the first pulse width.

15. The display device according to claim 14, wherein: The timing controller is further configured to generate a first control signal having the first delay and the first pulse width when the fluctuation value of the first power supply voltage is the first value. The low-dropout regulator circuit is also configured to change the magnitude of the initialization voltage based on the first control signal.

16. The display device according to claim 14, wherein: The timing controller is further configured to generate a second control signal having the second delay and the second pulse width when the fluctuation value of the first power supply voltage is a second value less than the first value. The low-dropout regulator circuit is also configured to change the magnitude of the initialization voltage based on the second control signal.

17. A display driving circuit, comprising: A power generation circuit, comprising a low-dropout regulator circuit configured to change the amplitude of an initialization voltage applied to a display panel; The timing controller is configured as follows: Receive voltage change information indicating a change in the magnitude of the first power supply voltage applied to the display panel during a first blanking period of the first frame time interval, between a first active period of the first frame time interval and a second active period of the second frame time interval consecutive to the first frame time interval. Based on the voltage change information, a control signal is generated for controlling the low-dropout regulator circuit; and A data driver configured to transmit data signals to the display panel during the first and second active periods.

18. The display driving circuit according to claim 17, wherein, The low-dropout regulator circuit includes: A voltage distribution circuit is configured to receive a first input voltage through a first input node and select a voltage having a level between the first input voltage and a first power supply voltage based on the control signal to generate an output voltage; A multiplexer configured to output one of the output voltage and the first input voltage based on the control signal; A feedback circuit, configured to generate a feedback voltage based on the control signal by feeding back the initialization voltage; and An output circuit is configured to receive one of the output voltage and the first input voltage from the multiplexer, receive the feedback voltage from the feedback circuit, and change the magnitude of the initialization voltage based on the feedback voltage and one of the output voltage and the first input voltage.

19. The display driving circuit according to claim 18, wherein, The voltage distribution circuit includes: The first resistor circuit includes: The first resistor group receives the first input voltage from the first input node. The second resistor group is connected to the first resistor group via the second input node, and A third resistor group is connected to the second resistor group via a third input node and is configured to receive the first power supply voltage from a fourth input node; A first distribution circuit is connected to the first resistor group, and the first distribution circuit is configured to generate a first output voltage having a level between the first input voltage and the first power supply voltage as the output voltage through the first resistor group. A second distribution circuit, connected to the second resistor group, is configured to generate a second output voltage having a level between the first input voltage and the first power supply voltage as the output voltage via the second resistor group; and A third distribution circuit is connected to the third resistor group, and the third distribution circuit is configured to generate a third output voltage having a level between the first input voltage and the first power supply voltage as the output voltage through the third resistor group.

20. A low-dropout regulator circuit, comprising: A voltage distribution circuit is configured to receive a first input voltage through a first input node and select a voltage having a level between the first input voltage and a first power supply voltage applied to the cathode electrode of the light-emitting element based on a control signal to generate an output voltage. A multiplexer configured to output one of the output voltage and the first input voltage based on the control signal; A feedback circuit is configured to generate a feedback voltage based on the initial voltage applied to the anode electrode of the light-emitting element by the control signal via feedback. and An output circuit is configured to receive one of the output voltage and the first input voltage from the multiplexer, receive the feedback voltage from the feedback circuit, and change the magnitude of the initialization voltage based on the feedback voltage and one of the output voltage and the first input voltage.

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