Display panel control device and display device including the same

Abstract

The present invention relates to a display panel control device and a display device including the same. The display panel control device of one aspect of the present invention, which can prevent simultaneous access of an external device and a timing controller to a storage device, includes a timing controller that controls driving of a display panel including a plurality of pixels; a storage device that stores at least one of setting data of the timing controller and compensation data for compensating for characteristic values of the plurality of pixels; and a first routing wiring that connects the external device for recording or updating the setting data and the timing controller; the external device accesses the storage device through the timing controller and records or updates the setting data.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a display panel control device. Background Technology

[0002] With the development of information technology, various display devices capable of visualizing information are being developed. Display devices that have been developed or are under development include liquid crystal displays (LCDs), OLEDs (Organic Light Emitting Diodes), and PDPs (Plasma Display Panels). These display devices are being developed to be able to appropriately display high-resolution images.

[0003] The display device includes: a display panel including a plurality of pixels defined by a plurality of gate lines and a plurality of data lines; a gate driving circuit supplying gate signals to the gate lines; a data driving circuit supplying data voltages to the data lines; and a display panel device for controlling the operation of the gate driving circuit and the data driving circuit.

[0004] like Figure 1 As shown, a typical display panel control device 160 includes a printed circuit board (PCB) 20, a timing controller 30, a storage device 40, and a connector 60. The timing controller 30, the storage device 40, and the connector 60 are mounted on the printed circuit board 20.

[0005] During startup, the timing controller 30 reads firmware data, configuration data, icon data, or compensation value data for the action timing controller 30 from the storage device 40, or it may record new compensation value data generated by real-time sensing or the like in the storage device 40.

[0006] On the other hand, when it is necessary to update firmware data, configuration data, and icon data recorded in storage device 40, external device 50 is connected to storage device 40 through connector 60 to perform the corresponding data update.

[0007] As described above, since both the timing controller 30 and the external device 50 need to be able to connect to the storage device 40, therefore, Figure 1 The typical display control device 10 shown includes a T-shaped routing cable 70, and a timing controller 30 and an external device 50 can be connected to the storage device 40 via the T-shaped routing cable 70.

[0008] However, as Figure 1As shown, when the timing controller 30 and the external device 50 are connected to the storage device 40 through a T-shaped routing cable 70, the external device 50 and the timing controller 30 can be connected to the storage device 40 at the same time, which may lead to errors due to conflicts.

[0009] In addition, when using a T-shaped routing cable 70 to transmit and receive data, the data transmission and reception speed may be reduced, which may lead to a decrease in the performance of the display device. Summary of the Invention

[0010] The present invention addresses the aforementioned problems and aims to provide a display panel control device capable of preventing simultaneous access to a storage device by external devices and a timing controller, and a display device including the display panel control device.

[0011] In addition, another objective of the present invention is to provide a display panel control device and a display device including the display panel control device, wherein an external device can only be accessed by a storage device through a timing controller, the timing controller can control whether the external device is accessed by the storage device.

[0012] Another object of the present invention is to provide a display panel control device that can update setting data using an external device without errors even when performing display operations using a timing controller, and a display device including the display panel control device.

[0013] To address the aforementioned technical problems, a display panel control device according to one aspect of the present invention is characterized by comprising: a timing controller for controlling the driving of a display panel including a plurality of pixels; a storage device for storing at least one of setting data of the timing controller and compensation data for compensating characteristic values ​​of the plurality of pixels; and a first routing cable connecting an external device for recording or updating the setting data and the timing controller; wherein the external device accesses the storage device through the timing controller and records or updates the setting data.

[0014] To address the aforementioned technical problem, another aspect of the present invention provides a display device, characterized in that it comprises: a display panel including a plurality of pixels; a control printed circuit board connected to the display panel; a timing controller mounted on the control printed circuit board for controlling the driving of the display panel; a storage device mounted on the control printed circuit board for storing at least one of setting data of the timing controller and compensation data for compensating characteristic values ​​of the plurality of pixels; and an external device for recording or updating the setting data; wherein the external device is connected to the storage device through the timing controller and records or updates the setting data.

[0015] According to the present invention, external devices can only access the storage device through the timing controller. Therefore, it is possible to prevent the external device and the timing controller from accessing the storage device at the same time, thereby preventing errors caused by the simultaneous access of the external device and the timing controller to the storage device.

[0016] In addition, according to the present invention, the timing controller can receive an access enable signal from an external device and control only one of the external device and the timing controller to access the storage device according to the level of the access enable signal, thereby enabling easier and more accurate execution of access control of the storage device by the external device and the timing controller.

[0017] Furthermore, according to the present invention, external devices can only access the storage device through the timing controller. Therefore, external devices, timing controllers and storage devices can be connected using only a straight-line routing cable, without the need for a T-shaped routing cable, thereby preventing a reduction in data transmission speed.

[0018] Furthermore, according to the present invention, when performing display operations using a timing controller, if it is necessary to update the setting data, the timing controller can output predetermined icon data to the display panel, and then the external device can access the storage device through the timing controller. Thus, the setting data can be updated even during display operations without errors. Attached Figure Description

[0019] Figure 1 This is a schematic diagram illustrating the configuration of a typical display panel control device.

[0020] Figure 2 This is a diagram illustrating the configuration of a display device including a display panel control device according to an embodiment of the present invention.

[0021] Figure 3 This is a diagram illustrating an implementation example of a display device according to an embodiment of the present invention.

[0022] Figure 4 This is a block diagram illustrating the configuration of a display panel control device according to an embodiment of the present invention. Detailed Implementation

[0023] Throughout this specification, the same reference numerals denote substantially the same constituent elements. In the following description, detailed descriptions of structures and functions known in the technical field of this invention may be omitted unless they are relevant to the core structure of the invention.

[0024] The advantages and features of the present invention, as well as the methods for achieving these advantages and features, will become apparent from the detailed embodiments described below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various different ways. These embodiments are only intended to complete the disclosure of the invention and to fully inform those skilled in the art of the scope of the invention, which is defined solely by the scope of the claims.

[0025] The shapes, dimensions, ratios, angles, quantities, etc. disclosed in the accompanying drawings used to illustrate embodiments of the present invention are exemplary, and therefore the present invention is not limited to the matters illustrated.

[0026] When using terms such as "comprising," "having," or "consisting of" as mentioned in this specification, additional parts may be added unless "only" is used. Unless otherwise expressly stated, the use of the singular to express constituent elements includes the use of the plural.

[0027] When interpreting constituent elements, even without additional explicit documentation, it is interpreted as including a range of error.

[0028] When the positional relationship is described, for example, if the positional relationship between two parts is described as "on top of", "above", "below", "beside", etc., then unless "adjacent" or "direct" is used, there may be more than one other part between the two parts.

[0029] The terms "first," "second," etc., can be used to describe various constituent elements, but these constituent elements are not limited by these terms. These terms are only used to distinguish one constituent element from another. Therefore, the "first constituent element" mentioned below can also be a "second constituent element" within the technical concept of this invention.

[0030] The term "at least one" should be understood to include all combinations that can be derived from more than one related item. For example, "at least one of the first item, the second item, and the third item" can mean not only each of the first item, the second item, and the third item, but also all combinations of two or more of the first item, the second item, and the third item.

[0031] Each feature of the various embodiments of the present invention may be combined or integrated with each other in part or in whole, and may be linked and driven in various technical ways. Each embodiment may be implemented independently of each other or together in an associated relationship.

[0032] Hereinafter, embodiments of this specification will be described in detail with reference to the accompanying drawings.

[0033] Figure 2This is a diagram illustrating the configuration of a display device including a display panel control device according to an embodiment of the present invention. Figure 3 This is a diagram illustrating an implementation example of a display device according to an embodiment of the present invention.

[0034] Figure 2 and Figure 3 The display device 100 shown is an electronic device that includes the display panel control device of the present invention. For example, it can be various display devices that use the voltage of a battery or external power source as the operating voltage. In one embodiment, the display device 100 can be a vehicle display device mounted in an automobile.

[0035] Reference Figure 2 The display device 100 of the present invention includes: a display panel 110 connected to a plurality of gate lines GL and a plurality of data lines DL, and a plurality of sub-pixels SP arranged in a matrix; a gate driving circuit 120 driving the plurality of gate lines GL; a data driving circuit 130 supplying data voltage through the plurality of data lines DL; and a display panel control device 160 controlling the gate driving circuit 120 and the data driving circuit 130.

[0036] In particular, such as Figure 3 As shown, the display panel control device 160 of the present invention may include a timing controller 140 and a storage device 150 mounted on a control printed circuit board (CPCB).

[0037] The display panel 110 displays images based on scan signals transmitted from the gate drive circuit 120 via a plurality of gate lines GL and data voltages transmitted from the data drive circuit 130 via a plurality of data lines DL.

[0038] In one embodiment, the display panel 110 may be a liquid crystal display panel. When the display panel 110 is a liquid crystal display panel, the display panel 110 may include a liquid crystal layer formed between two substrates, and may operate in any known mode such as twisted nematic (TN) mode, vertical alignment (VA) mode, inplane switching (IPS) mode, fringe field switching (FFS) mode, etc.

[0039] In another embodiment, the display panel 110 may be an organic light-emitting diode (OLED) display panel. When the display panel 110 is an organic light-emitting diode display panel, the display panel 110 may be implemented as a top emission type, a bottom emission type, or a dual emission type, etc.

[0040] For ease of explanation, the following description will assume that the display panel 110 is an organic light-emitting diode (OLED) display panel.

[0041] The display panel 110 may have a plurality of pixels arranged in a matrix, each pixel may be composed of sub-pixels SP of different colors (e.g., white sub-pixels, red sub-pixels, green sub-pixels and blue sub-pixels), and each sub-pixel SP may be defined by a plurality of data lines DL and a plurality of gate lines GL.

[0042] A sub-pixel SP may include a thin-film transistor (TFT), an organic light-emitting diode (OLED), and a storage capacitor electrically connected to the OLED and used to maintain voltage, all formed in the region where a data line DL intersects with a gate line GL. An image can be displayed by controlling the current flowing through the OLEDs configured in each sub-pixel SP.

[0043] The gate driving circuit 120 is controlled by the timing controller 140. The gate driving circuit 120 sequentially outputs scan signals to a plurality of gate lines GL disposed on the display panel 110, thereby controlling the driving timing of a plurality of sub-pixels SP.

[0044] like Figure 3 As shown, the gate driving circuit 120 may include at least one gate drive integrated circuit (GDIC), and may be located on only one side of the display panel 110 or on both sides, depending on the driving method. In another embodiment, the gate driving circuit 120 may also be embedded in the bezel area of ​​the display panel 110 and implemented as a gate in panel (GIP) configuration.

[0045] One or more gate driver integrated circuits (GDICs) included in the gate driver circuit 120 can be mounted on the gate film GF, and one side of the gate film GF can be electrically connected to the display panel 110. In addition, wiring for electrically connecting the gate driver integrated circuits (GDICs) and the display panel 110 can be arranged on the upper part of the gate film GF.

[0046] The data driving circuit 130 receives image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, according to the timing of the scan signal applied through the gate line GL, it outputs the data voltage to each data line DL, so that each sub-pixel SP connected to the data line DL displays a light emission signal with a brightness corresponding to the data voltage.

[0047] like Figure 3 As shown, the data driving circuit 130 may include at least one source driver integrated circuit (SDIC). The source driver integrated circuit (SDIC) may be connected to the bonding pad of the display panel 110 or directly disposed on the display panel 110 by means of tape-automated bonding (TAB) or chip-on-glass (COG).

[0048] In one embodiment, each source driver integrated circuit (SDIC) can also be integrated into the display panel 110. Alternatively, each source driver integrated circuit (SDIC) can be implemented as a chip on film (COF). In this embodiment, each source driver integrated circuit (SDIC) can be mounted on a circuit film and electrically connected to the data lines DL of the display panel 110 through the circuit film.

[0049] The data driving circuit 130 includes one or more source driver integrated circuits (SDICs), which can be mounted on the source film SF. One side of the source film SF can be electrically connected to the display panel 110. In addition, wiring for electrically connecting the source driver integrated circuits (SDICs) and the display panel 110 can be arranged on the upper part of the source film SF.

[0050] At this time, at least one source printed circuit board (SPCB) can be connected to the other side of the source film (SF) on which the active driver integrated circuit (SDIC) is mounted. That is, one side of the source film (SF) on which the active driver integrated circuit (SDIC) is mounted can be electrically connected to the display panel 110, and the other side can be electrically connected to the source printed circuit board (SPCB).

[0051] The timing controller 140 supplies control signals to the gate drive circuit 120 and the data drive circuit 130, controlling their operation. Specifically, the timing controller 140 controls the gate drive circuit 120 to output a scan signal according to the timing implemented in each frame, transmitting externally received image data DATA to the data drive circuit 130, thereby controlling the data drive circuit 130 to output the data voltage corresponding to the image data DATA to the data line DL.

[0052] At this time, the timing controller 140 can receive timing signals, including vertical synchronization signal Vsync, horizontal synchronization signal Hsync, data enable signal (DE), master clock MCLK, etc., from the external host system 200 along with the image data DATA.

[0053] The host system 200 can be one of the following: a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, or a wearable device.

[0054] Therefore, the timing controller 140 uses the timing signals received from the host system 200 to generate control signals and transmits them to the gate drive circuit 120 and the data drive circuit 130.

[0055] For example, the timing controller 140 outputs gate control signals, including Gate Start Pulse (GSP), Gate Clock (GCLK), Gate Output Enable (GOE), etc., to the gate drive circuit 120 to control the gate drive circuit 120.

[0056] Here, the gate start pulse GSP controls the timing of the start of operation of at least one gate driver integrated circuit (GDIC) constituting the gate drive circuit 120. Additionally, the gate clock GCLK, as a clock signal common to the at least one gate driver integrated circuit (GDIC), controls the shift timing of the scan signal. Furthermore, the gate output enable signal GOE specifies the timing information of the at least one gate driver integrated circuit (GDIC).

[0057] Additionally, the timing controller 140 outputs data control signals, including a source start pulse (SSP), a source sampling clock (SCLK), and a source output enable signal (SOE), to the data driver circuit 130 to control the data driver circuit 130. Here, the source start pulse (SSP) controls the timing of data sampling for at least one source driver integrated circuit (SDIC) constituting the data driver circuit 130. The source sampling clock (SCLK) is a clock signal that controls the timing of data sampling from at least one source driver integrated circuit (SDIC). The source output enable signal (SOE) controls the output timing of at least one source driver integrated circuit (SDIC).

[0058] Additionally, the timing controller 140 can generate compensation data to compensate for deviations in the characteristic values ​​of the driving transistors of the sub-pixels connected to the sensing circuit 600 by comparing the sensing data received from the sensing circuit 600 with pre-stored reference values. The timing controller 140 can compensate for the image data by reflecting the generated compensation data in the image data, and record the generated compensation data in the storage device 150.

[0059] As mentioned above, such as Figure 3 As shown, the timing controller 140 and the storage device 150 can be mounted on a control printed circuit board (CPCB). On the other hand, although in Figure 3 Although not shown in the figure, a power management integrated circuit (PMIC, not shown) can also be installed on the printed circuit board (PCB). The power management integrated circuit supplies various voltages or currents to the display panel 110, gate drive circuit 120, data drive circuit 130, etc., or controls the various voltages or currents to be supplied.

[0060] At this time, the control printed circuit board (CPCB) and at least one source printed circuit board (SPCB) can be electrically connected by at least one connecting member, which can be made of, for example, a flexible printed circuit (FPC) or a flexible flat cable (FFC). The connecting member connecting at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) can be varied depending on the size and type of the display device 100. Alternatively, at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) can also be integrated into a single printed circuit board.

[0061] As described above, the timing controller 140 can operate from the storage device 150 using the setting data recorded in the storage device 150. In one embodiment, the setting data recorded in the storage device 150 may include at least one of firmware files, configuration files, and icon data for driving the timing controller 140.

[0062] In one embodiment, the setting data recorded in the storage device 150 can be recorded or updated using an external device. In this embodiment, the timing controller 140 of the present invention can control the access of the external device to the storage device 150.

[0063] The following is for reference Figure 4 A more detailed description will be given of a display panel control device according to an embodiment of the present invention, which includes the timing controller described above.

[0064] Figure 4 This is a schematic diagram illustrating the configuration of a display panel control device according to an embodiment of the present invention.

[0065] like Figure 4 As shown, a display panel control device 160 according to an embodiment of the present invention includes a control printed circuit board (CPCB), a timing controller 140, a storage device 150, a connector 400, a first routing wiring 410, a second routing wiring 420, and a third routing wiring 430.

[0066] A timing controller 140, a storage device 150, a connector 400, a first routing cable 410, a second routing cable 420, and a third routing cable 430 are mounted on the control printed circuit board (CPCB). As described above, the control printed circuit board (CPCB) can be connected to at least one source printed circuit board (SPCB) circuit via connecting components such as flexible printed circuits or flexible flat cables.

[0067] The timing controller 140 is mounted on the control printed circuit board (CPCB) to enable circuit connection with the external device 460 and the storage device 150 to control the connection between the external device 460 and the storage device 150.

[0068] Specifically, the timing controller 140 is connected to the external device 460 via the first pin P1, the first routing cabling 410, and the connector 400, and receives an access enable signal from the external device 460 for accessing the storage device 150. The timing controller 140 determines whether to allow the external device 460 to access the storage device 150 based on the logic level state of the access enable signal.

[0069] Additionally, the timing controller 140 connects to the external device 460 via the second pin P2, the second routing cable 420, and the connector 400, and receives setting data from the external device 460. When the timing controller 140 determines to allow the external device 460 to access the storage device 150 based on the logic level state of the access enable signal, the setting data received from the external device 460 via the second pin P2, the second routing cable 420, and the connector 400 can be recorded into the storage device 150.

[0070] On the other hand, the timing controller 140 is connected to the storage device 150 via the third pin P3 and the third routing wiring 430. Thus, the timing controller 140 can record setting data transmitted from the external device 460 to the storage device 150, or can read setting data recorded in the storage device 150, or can record compensation data for compensating the characteristic values ​​of each pixel in the storage device 150.

[0071] In one embodiment, such as Figure 4 As shown, the timing controller 140 includes a data controller 440, a multiplexer 450, a first pin P1, a second pin P2, a third pin P3, a first connection wiring L1, a second connection wiring L2, a third connection wiring L3, a fourth connection wiring L4, and a fifth connection wiring L5.

[0072] The data controller 440 supplies control signals to the gate drive circuit 120 and the data drive circuit 130, and controls the operation of the gate drive circuit 120 and the data drive circuit 130. In addition, the data controller 440 generates compensation data for each pixel based on the sensing data of each pixel acquired through the sensing operation, and stores the generated compensation data in the storage device 150.

[0073] In particular, the data controller 440 of the present invention receives an access enable signal for accessing the storage device 150 from the external device 460, and determines whether to allow the external device 460 to access the storage device 150 based on the logic level state of the access enable signal.

[0074] More specifically, the data controller 440 receives an access enable signal from an external device 460 connected to the display panel control device 160 via a connector 400. The data controller 440 determines the logic level of the received access enable signal and, based on the determined logic level, enables the external device 460 to connect to the storage device 150 or deconnects the storage device 150 from the external device 460.

[0075] In one embodiment, the data controller 440 receives an access enable signal from a first connection wiring L1 connected to the first pin P1. If the logic level of the access enable signal is a first logic level, the data controller 440 determines to connect the external device 460 and the storage device 150. As an example, if the logic level of the access enable signal is high, the data controller 440 determines to connect the external device 460 and the storage device 150.

[0076] On the other hand, if the access enable signal's logic level is a second logic level, the data controller 440 determines to disconnect the external device 460 from the storage device 150. For example, if the access enable signal's logic level is low, the data controller 440 determines to disconnect the external device 460 from the storage device 150.

[0077] The data controller 440 generates a selection signal SEL for controlling the operation of the multiplexer 450 based on the determined logic level state of the access enable signal. In one embodiment, when the logic level of the access enable signal is a first logic level, the data controller 440 generates a first logic level selection signal SEL for connecting the external device 460 to the multiplexer 450 and outputs it to the multiplexer 450.

[0078] On the other hand, when the access enable signal's logic level is the second logic level, the data controller 440 generates a second logic level selection signal SEL for disconnecting the external device 460 from the multiplexer 450 and connecting the data controller 440 to the multiplexer 450, and outputs it to the multiplexer 450.

[0079] The data controller 440 can supply the generated selection signal SEL to the multiplexer 450 via the fifth connection wiring L5.

[0080] In one embodiment, if the data controller 440 receives a first logic level access enable signal from the external device 460 during the output of image data through the display panel 110, it can stop the output of image data and output predetermined icon data through the display panel 110. Thus, when a display operation is performed using the data controller 440, even if an update of the setting data is required, the data controller 440 can connect the external device 460 to the storage device 150 after outputting the predetermined icon data to the display panel 110, thereby achieving the effect of updating the setting data without errors even during display operations.

[0081] Multiplexer 450 connects external device 460 to storage device 150 or connects data controller 440 to storage device 150 based on selection signal SEL transmitted from data controller 440.

[0082] Specifically, if a first logic level selection signal SEL is received from the data controller 440, the multiplexer 450 connects the second connection wire L2, which is connected to the second pin P2, to the third connection wire L3, which is connected to the output of the multiplexer 450. Thus, the setting data received via the second routing wire 420 connected to the second pin P2 is recorded into the storage device 150 via the second connection wire L2, the multiplexer 450, the third connection wire L3, the third pin P3, and the third routing wire 430.

[0083] Additionally, if a second logic level selection signal SEL is received from the data controller 440, the multiplexer 450 connects the fourth connection wire L4 connected to the data controller 440 with the third connection wire L3 connected to the output of the multiplexer 450. Thus, the data controller 440 can access the storage device 150 via the fourth connection wire L4, the multiplexer 450, the third connection wire L3, the third pin P3, and the third routing wire 430, thereby recording compensation data in the storage device 150 or reading setting data from the storage device 150.

[0084] In one embodiment, the multiplexer 450 may consist of at least one switching device (not shown) for selectively connecting one of the second connection wiring L2 and the fourth connection wiring L4 to the third routing wiring 430.

[0085] Storage device 150 records at least one of setting data and compensation data. Storage device 150 is connected to timing controller 140 via third routing cabling 430. That is, storage device 150 is only connected to timing controller 140 and not directly connected to external device 460. Thus, it is possible to prevent timing controller 140 and external device 460 from being connected to storage device 150 simultaneously.

[0086] In one embodiment, the storage device 150 may be a flash memory.

[0087] Connector 400 is mounted on the control printed circuit board (CPCB) to enable external device 460 to access display panel control device 160. Connector 400 is connected to the first pin P1 of timing controller 140 via first routing wiring 410 and to the second pin P2 of timing controller 140 via second routing wiring 420.

[0088] External device 460 is connected to display panel control device 160 via connector 400, thereby recording setting data in storage device 150 of display panel control device 160 or updating setting data recorded in storage device 150.

[0089] In particular, the external device 460 of the present invention can generate an access enable signal and transmit it to the timing controller 140 to access the storage device 150. In one embodiment, when the external device 460 requests access from the timing controller 140, it can generate an access enable signal of a first logic level and transmit it to the timing controller 140; when it does not request access from the timing controller 140, it can generate an access enable signal of a second logic level and transmit it to the timing controller.

[0090] In one embodiment, the external device 460 may be a laptop computer or a system-on-chip (SoC) of an electronic device equipped with a display device 100. The external device 460 may transmit setting data to the timing controller 140 using the SPI protocol or the I2C protocol.

[0091] Those skilled in the art to which this invention pertains should understand that this invention can be implemented in other specific ways without changing the technical concept or essential features of this invention.

[0092] Therefore, the embodiments described above should be understood as exemplary in all respects and not as limiting. The scope of the invention is not defined by the detailed description provided herein, but by the claims that follow, and the meaning and scope of the claims, as well as all modifications or variations derived from their equivalents, should be interpreted as encompassing the scope of the invention.

Claims

1. A display panel control device, wherein, include: A timing controller that controls the driving of a display panel comprising a plurality of pixels; A storage device that stores at least one of the timing controller's setting data and compensation data for compensating the characteristic values ​​of the plurality of pixels; as well as The first route cabling connects the external device used to record or update the set data and the timing controller; The external device connects to the storage device through the timing controller and records or updates the set data.

2. The display panel control device according to claim 1, wherein, Also includes: The second routing is used to receive an access enable signal for accessing the storage device from the external device and transmit it to the timing controller. If the access enable signal is at a first logic level, the timing controller connects the external device to the storage device; if the access enable signal is at a second logic level, the timing controller disconnects the external device from the storage device.

3. The display panel control device according to claim 2, wherein, It also includes a third routing cabling that connects the timing controller to the storage device; The timing controller includes: The data controller determines the connection between the external device and the storage device based on the access enable signal; and A multiplexer, controlled by the data controller, selectively connects one of the data controller and the external device to the third routing cabling; The data controller generates a selection signal for controlling the operation of the multiplexer based on the access enable signal and inputs it into the multiplexer; If the selection signal is a first logic level, the multiplexer connects the external device to the third routing cabling; if the selection signal is a second logic level, the multiplexer connects the data controller to the third routing cabling.

4. The display panel control device according to claim 3, wherein, If the access enable signal is the second logic level, the data controller accesses the storage device and reads the set data or the compensation data from the storage device, or records new compensation data in the storage device.

5. The display panel control device according to claim 3, wherein, The timing controller further includes: The first pin is connected to the first routing wiring; The second pin is connected to the second routing wiring; and The third pin is connected to the third routing wiring.

6. The display panel control device according to claim 1, wherein, The configuration data includes at least one of the following: firmware file, configuration file, and icon data used to drive the timing controller.

7. The display panel control device according to claim 1, wherein, If a first logic level access enable signal is received from the external device during the output of image data through the display panel, the timing controller stops the output of the image data and outputs predetermined icon data through the display panel.

8. The display panel control device according to claim 1, wherein, The storage device is a flash memory.

9. The display panel control device according to claim 1, wherein, The external device transmits the setting data to the timing controller using the SPI or I2C protocol.

10. A display device, wherein, include: The display panel comprises a plurality of pixels; A control printed circuit board is connected to the display panel; A timing controller, mounted on the control printed circuit board, controls the driving of the display panel; A storage device, mounted on the control printed circuit board, stores at least one of the timing controller's setting data and compensation data for compensating the characteristic values ​​of the plurality of pixels; as well as External devices record or update the set data; The external device connects to the storage device through the timing controller and records or updates the set data.

Images