Data driving apparatus and display apparatus including the same

Abstract

The present application provides a data driving device, which includes a plurality of data driving circuits; each of the plurality of data driving circuits includes a clock recovery unit that recovers display data and an internal system clock from image data received from a timing controller, and generates a plurality of candidate reference clocks having a pre-set phase difference using the internal system clock; and a data processing unit that calculates a timing difference of a clock training symbol of the display data and the internal system clock, and generates an output clock synchronized with other data driving circuits based on the calculated timing difference of the clock training symbol and the internal system clock.

Description

Technical Field

[0001] This invention relates to a data driving device and a display device including the same. Background Technology

[0002] Typically, a display device is configured such that a timing controller transmits display data to a display driver circuit, the display driver circuit outputs a source signal corresponding to the display data, and the display panel displays the image corresponding to the source signal.

[0003] The display data transmitted from the timing controller to the display driver consists of data packets. The display data may include data corresponding to the information used for display and a clock used for driving the data.

[0004] The display driver device may include a plurality of display driver circuits (D-IC #1~#N). When powered on, each display driver circuit can recover the display data (data) and internal system clock (SCLK) from the image data (DATA), and use the recovered clock to perform data processing, outputting a source signal. At this time, the source signal can use the recovered clock to determine the output timing. When the recovered internal system clock (SCLK) is normal, the display driver circuits (D-IC #1~#3) can be defined as locked. When the clock is abnormal, the display driver circuits (D-IC #1~#3) can be defined as unlocked, and the display driver circuits (D-IC #1~#3) can generate and output a lock signal to display the state of this internal system clock (SCLK). Figure 1 As shown, each of the plurality of display driver circuits can generate an internal system clock SCLK (②) at different times by using an internal lock signal LOCK (①) that becomes a high-level signal H at different times. Consequently, the source output signal SOE becomes a high-level signal H at different times (③) and outputs a source signal SS (④) at different times, resulting in a difference in the voltage output on the display panel (⑤). Therefore, the quality of the image displayed on the display panel will decrease. Summary of the Invention

[0005] The problem that the invention aims to solve

[0006] The present invention is intended to solve the above-mentioned problems, and its purpose is to provide a data driving device and a display device including the same device that can output source signals at the same time in a display driving circuit.

[0007] Technical solutions to the problem

[0008] An embodiment of the present invention provides a data driving device comprising a plurality of data driving circuits; each of the plurality of data driving circuits comprises: a clock recovery unit, which recovers display data and an internal system clock from image data received from a timing controller, and uses the internal system clock to generate a plurality of candidate reference clocks having a preset phase difference; and a data processing unit, which calculates the timing difference between the clock training symbols of the display data and the internal system clock, and generates an output clock synchronized with other data driving circuits based on the calculated timing difference between the clock training symbols and the internal system clock.

[0009] A display device according to an embodiment of the present invention includes: a display panel for receiving source signals and displaying images; and a data driving device including a plurality of data driving circuits that simultaneously supply the source signals to the display panel; each of the plurality of data driving circuits includes: a clock recovery unit for recovering display data and an internal system clock from image data received from a timing controller, and using the internal system clock to generate a plurality of candidate reference clocks having a preset phase difference; and a data processing unit for calculating the timing difference between the clock training symbols of the display data and the internal system clock, and generating an output clock synchronized with other data driving circuits based on the calculated timing difference between the clock training symbols and the internal system clock.

[0010] Invention Effects

[0011] This invention can use the timing difference between the internal system clock and the display data to output the source signal at the same time as other data driving circuits in the display device, thereby improving the image quality of the display device.

[0012] This invention enables a data window of a pre-set size to move in the direction of displaying data and detect clock training symbols, thereby enabling the calculation of the timing difference between the starting point of the data window that detected the clock training symbols and the internal system clock.

[0013] The present invention can use a signal that delays the source output signal to generate an output clock, thereby ensuring the setup time and hold time of the data driving circuit, and thus stably driving the components contained in the data driving circuit. Attached Figure Description

[0014] Figure 1 It is a timing diagram of signals processed in existing data-driven circuits.

[0015] Figure 2 This is a simplified block diagram of a display device according to an embodiment of the present invention.

[0016] Figure 3 This is a simplified block diagram of a data driving circuit according to an embodiment of the present invention.

[0017] Figure 4 This is a timing diagram of the signal output from the clock recovery unit of the data driving circuit according to an embodiment of the present invention.

[0018] Figure 5 (a) and (b) are diagrams illustrating a clock selection signal determined based on data and an internal system clock in a data processing unit according to an embodiment of the present invention.

[0019] Figure 6 This is a diagram illustrating the process of generating a clock selection signal in the data processing unit of a data driving circuit according to an embodiment of the present invention.

[0020] Figure 7 This is a simplified block diagram of the source output signal synchronization section according to an embodiment of the present invention.

[0021] Figure 8 This is a timing diagram illustrating the steps of determining the reference clock of the source output signal synchronization section according to an embodiment of the present invention.

[0022] Figure 9 This is a timing diagram of the input and output signals of the source output signal synchronization unit according to an embodiment of the present invention.

[0023] Figure 10 This is a diagram comparing the input and output data of a conventional data driving circuit and a data driving circuit according to an embodiment of the present invention.

[0024] Explanation of reference numerals in the attached figures

[0025] 100: Image processing device; 200: Timing controller

[0026] 300: Gate driving device; 400: Data driving device

[0027] 500: Display panel Detailed Implementation

[0028] If refer to and append Figure 1 The advantages, features, and methods of implementing the present invention will become clear from the detailed description of the embodiments. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms that differ from each other. These embodiments are provided to complete the description of the invention and to fully inform those skilled in the art of the scope of the invention, which is defined only by the scope of the claims.

[0029] Throughout this specification, the same reference numerals denote the same constituent elements. In the following description, detailed descriptions may be omitted for matters unrelated to the core structure of the invention and for structures and functions well-known in the technical field of the invention.

[0030] When using terms such as "comprising," "having," or "constituting" in this specification, additional parts may be added unless "only" is used. When constituting elements are expressed in the singular, this includes cases where multiple elements are included, unless otherwise expressly stated.

[0031] When interpreting constituent elements, even if there is no separate explicit record, it should be interpreted as including the range of error.

[0032] The terms "first," "second," etc., are used to describe various constituent elements, but these constituent elements are not limited by these terms. These terms are used only to distinguish one constituent element from another. Therefore, the "first constituent element" mentioned below may also be a "second constituent element" within the scope of the technical concept of this invention.

[0033] The term "at least one" should be understood to include all combinations that can be derived from at least one related item. For example, "at least one of the first item, the second item, and the third item" can mean not only one of the first, second, and third items, but also all combinations of items that can be derived from at least two of the first, second, and third items.

[0034] The various features of the various embodiments of the present invention can be combined or integrated with each other in part or in whole, and various linkages and drives can be achieved technically. The embodiments can be implemented independently of each other, or they can be implemented together through association.

[0035] The following is for reference Figure 2 This section describes a display driving circuit and display device according to an embodiment of the present invention. Figure 2 This is a simplified block diagram of a display device according to an embodiment of the present invention.

[0036] Reference Figure 2 The display device 10 may include a plurality of panel driving devices 100, 200, 300, 400 and a display panel 500.

[0037] The display panel 500 can be configured with a plurality of data lines DL, a plurality of gate lines GL, and a plurality of pixels P. A pixel P can be composed of a plurality of sub-pixels. Furthermore, sub-pixels can be R (red), G (green), B (blue), W (white), etc. A pixel can be composed of RGB sub-pixels, or RGBG sub-pixels, or RGBW sub-pixels, etc. For ease of explanation, the following description will focus on the case where a pixel is composed of RGB sub-pixels.

[0038] Panel driving devices 100, 200, 300, and 400 are devices for generating signals for displaying images on display panel 500, and image processing device 100, timing controller 200, gate driving device 300, and data driving device 400 can correspond to the panel driving devices.

[0039] The image processing device 100 can generate image data DATA and transmit it to the timing controller 200. The image processing device 100 can be referred to as a host device that provides the image to be displayed on the display panel.

[0040] The timing controller 200 can supply control signals to the gate drive device 300 and the data drive device 400. For example, the timing controller 200 can transmit the gate control signal GCS to the gate drive device 300 to start scanning. Furthermore, the timing controller 200 can receive image data DATA and output it to the data drive device 400. In this case, the image data DATA may include display data corresponding to the image to be displayed and a clock for supplying to the display panel 500.

[0041] The gate driving device 300 can supply a gate driving signal with an on or off voltage to the gate line GL. If the gate driving signal with an on voltage is supplied to pixel P, pixel P will be connected to the data line DL. Conversely, if the gate driving signal with an off voltage is supplied to pixel P, the connection between pixel P and the data line DL will be released. The gate driving device 300 may be referred to as a gate driver.

[0042] The data driving device 400 supplies a data voltage Vp, which serves as a source signal, to the pixel P via the data line DL. The data driving device 400 may include a plurality of data driving circuits 410, 420, and 430. The data driving circuits 410, 420, and 430 supply the data voltage Vp, which serves as a source signal, to the pixel P according to a gate driving signal supplied via the data line DL. The data driving device 400 may be referred to as a source driver, or each of the data driving circuits 410, 420, and 430 may also be referred to as a source driver.

[0043] Reference Figure 3 The data driving circuits 410, 420, and 430 of an embodiment of the present invention are described in detail below. Figure 3 This is a simplified block diagram of a data driving circuit according to an embodiment of the present invention.

[0044] Reference Figure 3 The data driving circuits 410, 420, and 430 supply the data voltage Vp, which serves as the source signal, to the pixel P via the data line DL. In particular, according to one embodiment of the present invention, the different data driving circuits 410, 420, and 430 supply the data voltage Vp, which serves as the source signal, to their respective pixels.

[0045] Therefore, such as Figure 3 As shown, the data driving circuits 410, 420, and 430 respectively include a clock recovery unit 411, a data processing unit 412, and a channel 415.

[0046] The following is for reference Figure 4 The clock recovery section of a data driving circuit according to an embodiment of the present invention will be described in detail. Figure 4 This is a timing diagram of the signal output from the clock recovery unit of the data driving circuit according to an embodiment of the present invention.

[0047] The clock recovery unit 411 recovers the display data data and the internal system clock SCLK from the image data DATA, and latches the display data data based on the recovered internal system clock SCLK. For example, as... Figure 4 As shown, the clock recovery unit 411 recovers the internal system clock SCLK and display data from the image data DATA, and latches the display data data corresponding to the internal system clock SCLK. At this time, 1 byte can be 10 UI (Unit Interval), and the internal system clock SCLK can be a clock with a period of 20 UI (2 bytes).

[0048] For this purpose, the clock recovery unit 411 includes a phase-locked loop (PLL).

[0049] The clock recovery unit 411 can generate and output a plurality of candidate reference clocks with preset phase differences based on the internal system clock SCLK. For example, such as Figure 4 As shown, the clock recovery unit 411 can generate and output a first candidate reference clock SOE_CLK[0] to a tenth candidate reference clock SOE_CLK[9] with a phase difference of multiples of 2UI, based on the internal system clock SCLK. That is, the first candidate reference clock SOE_CLK[0] can be a clock with a phase difference of 2UI from the internal system clock SCLK, and the second candidate reference clock SOE_CLK[1] can be a clock with a phase difference of multiples of 2UI from the internal system clock SCLK. The clock with a phase difference of 2UI, the third candidate reference clock SOE_CLK[2] can be the clock with a phase difference of 3 with the internal system clock SCLK. A clock with a phase difference of 2UI. Thus, the clock recovery unit 411 can generate and output a plurality of candidate reference clocks SOE_CLK[0]~SOE_CLK[9] with a resolution of 2UI.

[0050] However, the phase difference and resolution of the plurality of candidate reference clocks generated in the clock recovery unit 411 are not limited to this. The clock recovery unit 411 can generate and output a plurality of candidate reference clocks with various phase differences. For example, it can also generate and output the first to the twentieth candidate reference clocks with a phase difference of multiples of 1 UI and a resolution of 1 UI.

[0051] The data processing unit 412 detects the preset clock training symbol Symbol in the display data, calculates the timing difference between the detected clock training symbol Symbol and the internal system clock SCLK, and outputs a synchronized output clock SYNC_SOE to output the data voltage Vp as the source signal at the same time point as other data drive circuits.

[0052] Therefore, the data processing unit 412 includes a clock training symbol detection unit 413 and a clock synchronization unit 414.

[0053] The following is for reference Figure 5 and Figure 6 The clock training symbol detection unit 413 of an embodiment of the present invention will be described in detail.

[0054] like Figure 5 As shown, the clock training symbol detection unit 413 detects the preset clock training symbol Symbol in the display data data, generates information about the timing difference between the starting point of the clock training symbol Symbol in the display data data and the rising edge of the internal system clock SCLK as a clock selection signal SOE_CLK_SEL, and transmits it to the clock synchronization unit 414.

[0055] For example, such as Figure 5 As shown, the clock training symbol detection unit 413 of the first data driving circuit 410 receives, as... Figure 5 The display data (a) and the internal system clock SCLK are received. A preset clock training symbol Symbol is detected from the received display data data. The timing difference (2UI) between the start point of the detected clock training symbol Symbol and the rising edge of the internal system clock SCLK is calculated and a clock selection signal SOE_CLK_SEL (10′b01_0000_0000) is generated and transmitted to the clock synchronization unit 414.

[0056] Specifically, the clock training symbol detection unit 413 moves the starting point of a data window data_wdw with a preset size (e.g., 20 UI) in one direction in units of 1 UI from the rising edge of the internal system clock SCLK and detects the clock training symbol Symbol within the display data data. It then uses the timing difference between the starting point of the data window data_wdw where the clock training symbol Symbol is detected and the rising edge of the internal system clock SCLK to generate a clock selection signal SOE_CLK_SEL, which is then transmitted to the clock synchronization unit 414.

[0057] That is, such as Figure 6 As shown, the clock training symbol detection unit 413 configures the starting point of the data window data_wdw, which has a preset size (e.g., 20 UI), to correspond to the rising edge of the internal system clock SCLK, thereby determining whether the first comparison data cmp_data1 filtered by the data window data_wdw in the displayed data is consistent with the clock training symbol Symbol (e.g., HHHHLLLLLLHHHHHHLLLL).

[0058] When the first comparison data cmp_data1 is consistent with the clock training symbol Symbol, the clock selection signal SOE_CLK_SEL (10′b10_0000_0000) is generated and output based on Table 1 below using the timing difference (0UI) between the start point of the data window data_wdw that filters the first comparison data cmp_data1 and the rising edge of the internal system clock SCLK.

[0059] On the other hand, if the first comparison data cmp_data1 is inconsistent with the clock training symbol Symbol, the starting point of the data window data_wdw is moved by 1 UI, and it is determined whether the second comparison data cmp_data2 filtered by the data window data_wdw is consistent with the clock training symbol Symbol.

[0060] When the second comparison data cmp_data2 is consistent with the clock training symbol, the timing difference (1UI) between the starting point of the data window data_wdw that filters the second comparison data cmp_data2 and the rising edge of the internal system clock SCLK is used to generate and output the clock selection signal SOE_CLK_SEL (10′b10_0000_0000) based on Table 1 below.

[0061] On the other hand, if the second comparison data cmp_data2 is inconsistent with the clock training symbol Symbol, the starting point of the data window data_wdw is moved by 1 UI, and it is determined whether the third comparison data cmp_data3 filtered by the data window data_wdw is consistent with the clock training symbol Symbol.

[0062] When the third comparison data cmp_data3 is consistent with the clock training symbol Symbol, the timing difference (2UI) between the starting point of the data window data_wdw (filtered from the third comparison data cmp_data3) and the rising edge of the internal system clock SCLK is used to generate and output the clock selection signal SOE_CLK_SEL (10′b01_0000_0000).

[0063] [Table 1]

[0064] Refer again Figure 3 The clock synchronization unit 414 uses the display data data, the internal system clock SCLK, the clock selection signal SOE_CLK_SEL, and a plurality of candidate reference clocks SOE_CLK[9:0] to transmit the multiplexer control signal M_Ctrl to the channel 415 so as to output the source signal simultaneously with other data drive circuits included in the display device 10.

[0065] Therefore, the clock synchronization unit 414 includes a source output signal generation unit 414a, a source output signal synchronization unit 414b, and an output control unit 414c.

[0066] The source output signal generation unit 414a uses display data and the internal system clock SCLK to generate the source output signal SOE and transmits it to the source output signal synchronization unit 414b. At this time, since the generated source output signal SOE is a signal generated in different data drive circuits based on the internal system clock SCLK generated at different times, the source output signal SOE can also be a signal generated in different data drive circuits at different times.

[0067] The following is for reference Figures 7 to 9 The source output signal synchronization unit of an embodiment of the present invention will be described in detail.

[0068] Figure 7 This is a simplified block diagram of the source output signal synchronization section according to an embodiment of the present invention. Figure 8 This is a timing diagram illustrating the steps of determining the reference clock of the source output signal synchronization section in an embodiment of the present invention. Figure 9This is a timing diagram of the input and output signals of the source output signal synchronization unit according to an embodiment of the present invention.

[0069] The source output signal synchronization unit 414b uses the source output signal SOE, the internal system clock SCLK, a plurality of candidate reference clocks SOE_CLK[0:9] and the clock selection signal SOE_CLK_SEL[9:0] to generate and output a reference clock SYNC_SOE that is synchronized with other data drive circuits.

[0070] Therefore, such as Figure 7 As shown, the source output signal synchronization unit 414b includes a first multiplexer M1, a first latch LAT1, a first flip-flop FF1, a second latch LAT2, a second multiplexer M2, and a second flip-flop FF2.

[0071] The first multiplexer M1 outputs any one of the candidate reference clocks SOE_CLK[0:9] received from the clock training symbol detection unit 413 as a synchronization clock SOE_SYNC_CLK based on the clock selection signal SOE_CLK_SEL received from the clock recovery unit 411.

[0072] For example, such as Figure 8 As shown, when the timing difference between the starting point of the clock training symbol Symbol of the display data received from the first data driving circuit 410 and the rising edge of the internal system clock SCLK is 2UI, the first multiplexer M1 of the first data driving circuit 410 outputs the ninth candidate reference clock SOE_CLK[8] as the synchronous clock SOE_SYNC_CLK according to the clock selection signal SOE_CLK_SEL (10′b01_0000_0000) generated corresponding to the timing difference. On the one hand, when the timing difference between the starting point of the clock training symbol Symbol of the display data received from the second data driving circuit 420 and the rising edge of the internal system clock SCLK is 6UI, the first multiplexer M1 of the second data driving circuit 420 outputs the seventh candidate reference clock SOE_CLK[6] as the synchronous clock SOE_SYNC_CLK according to the clock selection signal SOE_CLK_SEL (10′b00_0100_0000) generated in accordance with the timing difference.

[0073] like Figure 7 As shown, the first latch LAT1 stores the source output signal SOE received from the source output signal generation unit 414a, and is triggered by the internal system clock SCLK to generate the first selection signal SEL1 based on the stored source output signal SOE.

[0074] Specifically, such as Figure 9 As shown, the first latch LAT1 stores the high-level signal of the source output signal SOE and is triggered by the falling edge of the internal system clock SCLK. Based on the high-level signal of SOE, it generates the first selection signal SEL1. Since the first selection signal SEL1 is generated by the first latch LAT1 triggered by the falling edge of the internal system clock SCLK, it can be a signal that delays the source output signal SOE by 1 byte (10UI), that is, 0.5 cycles of the source output signal SOE.

[0075] like Figure 7 As shown, the first flip-flop FF1 stores the source output signal SOE received from the source output signal generation unit 414a, and is triggered by the internal system clock SCLK to generate the second selection signal SEL2 based on the source output signal SOE.

[0076] Specifically, such as Figure 9 As shown, the first flip-flop FF1 stores the high-level signal of the source output signal SOE and is triggered by the rising edge of the internal system clock SCLK. Based on the high-level signal of SOE, it generates the second selection signal SEL2. Since the second selection signal SEL2 is generated by the first flip-flop FF1 triggered by the rising edge of the internal system clock SCLK, it can be a signal that delays the source output signal SOE by 2 bytes (20UI), that is, 1.0 cycle of the source output signal SOE.

[0077] like Figure 7 As shown, the second latch LAT2 stores the second selection signal SEL2 received from the first flip-flop FF1, and is triggered by the internal system clock SCLK to generate the third selection signal SEL3 based on the second selection signal SEL2.

[0078] Specifically, such as Figure 9 As shown, the second latch LAT2 stores the high-level signal of the second selection signal SEL2 and is triggered by the falling edge of the internal system clock SCLK. Based on the high-level signal of the second selection signal SEL2, a third selection signal SEL3 is generated. Since the third selection signal SEL3 is generated by the second latch LAT2 triggered by the falling edge of the internal system clock SCLK, it can be a signal that delays the source output signal SOE by 3 bytes (30UI), that is, 1.5 cycles of the source output signal SOE.

[0079] The second multiplexer M2 outputs any one of the first selection signals SEL1 to the third selection signal SEL3 received from the first latch LAT1, the first flip-flop FF1, and the second latch LAT2, based on the clock selection signal SOE_CLK_SEL received from the clock training symbol detection unit 413.

[0080] Specifically, such as Figure 9 As shown, when the first and second rightmost bits of the clock selection signal SOE_CLK_SEL[1:0] are 1 (10′b00_0000_0001 and 10′b00_0000_0010), the second multiplexer M2 outputs the first selection signal SEL1. When the third to seventh rightmost bits (SOE_CLK_SEL[6:2]) of the clock selection signal SOE_CLK_SEL are 1 (10′b00_0000_0100, 10′b00_0000_1000, ...), the second multiplexer M2 outputs the first selection signal SEL1. 10′b00_0001_0000, 10′b00_0010_0000 and 10′b00_0100_0000), the second multiplexer M2 outputs the second selection signal SEL2. When the value of the eighth to tenth bits of the clock selection signal SOE_CLK_SEL[9:7] on the right is 1 (10′b00_1000_0000, 10′b01_0000_0000 and 10′b10_0000_0000), the second multiplexer M2 outputs the third selection signal SEL3.

[0081] For example, such as Figure 9 As shown, when the value of the ninth bit SOE_CLK_SEL[8] on the right side of the received clock selection signal SOE_CLK_SEL is 1, the second multiplexer M2 of the first data driving circuit 410 outputs the third selection signal SEL3. When the value of the seventh bit SOE_CLK_SEL[6] on the right side of the received clock selection signal SOE_CLK_SEL is 1, the second multiplexer M2 of the second data driving circuit 420 outputs the second selection signal SEL2.

[0082] like Figure 7 As shown, the second flip-flop FF2 stores any one of the first selection signals SEL1 to the third selection signal SEL3 received from the second multiplexer M2, and is triggered by the rising edge of the synchronization clock SOE_SYNC_CLK received from the first multiplexer M1, generating the output clock SYNC_SOE based on the stored selection signal.

[0083] Specifically, the second flip-flop FF2 stores the received selection signal and is triggered by the rising edge of the synchronous clock SOE_SYNC_CLK, generating the output clock SYNC_SO based on the selection signal. At this time, the high-level signal interval of the selection signal before the rising edge of the synchronous clock SOE_SYNC_CLK can be used as the setup time, which is the shortest time required to keep the data stored before the rising edge of the second flip-flop FF2 unchanged. The high-level signal interval of the selection signal after the rising edge of the synchronous clock SOE_SYNC_CLK can be used as the hold time, which is the shortest time required to keep the data after the rising edge of the second flip-flop FF2 unchanged. That is, according to an embodiment of the present invention, the setup time and hold time of the input value within a specified period before or after the effective edge of the hold clock can be ensured, so that the second flip-flop FF2 is triggered by the rising edge of the synchronous clock SOE_SYNC_CLK and normally generates the output clock SYNC_SOE based on the selection signal.

[0084] For example, such as Figure 9 As shown, the second flip-flop FF2 of the first data driving circuit 410 stores the high-level signal of the third selection signal SEL3 and is triggered by the rising edge of the synchronous clock SOE_SYNC_CLK. The output signal SYNC_SOE is generated based on the high-level signal of the third selection signal SEL3. The high-level signal interval before the rising edge of the synchronous clock SOE_SYNC_CLK in the high-level signal interval of the third selection signal SEL3 (setup time: 8UI) can be used as the setup time, which is the shortest time required to keep the data stored before the rising edge of the second flip-flop FF2 unchanged. The high-level signal interval after the rising edge of the synchronous clock SOE_SYNC_CLK in the high-level signal interval of the third selection signal SEL3 (hold time: 12UI) can be used as the hold time, which is the shortest time required to keep the data after the rising edge of the second flip-flop FF2 unchanged.

[0085] Additionally, the second flip-flop FF2 of the second data driving circuit 420 stores the high-level signal of the second selection signal SEL2 and is triggered by the rising edge of the synchronous clock SOE_SYNC_CLK, generating the output signal SYNC_SOE based on the high-level signal of the second selection signal SEL2. The high-level signal interval before the rising edge of the synchronous clock SOE_SYNC_CLK in the high-level signal interval of the second selection signal SEL2 (setup time: 14UI) can be used as the setup time, which is the shortest time required to keep the data stored before the rising edge of the second flip-flop FF2 unchanged. The high-level signal interval after the rising edge of the synchronous clock SOE_SYNC_CLK in the high-level signal interval of the second selection signal SEL2 (hold time: 6UI) can be used as the hold time, which is the shortest time required to keep the data after the rising edge of the second flip-flop FF2 unchanged.

[0086] The output control unit 414c generates a multiplexer control signal M_Ctrl based on the output clock SYNC_SOE output from the source output signal synchronization unit 414b to output the source signal SS and transmit it to channel 415.

[0087] Refer again Figure 3 Channel 415 receives the multiplexer control signal M_Ctrl from the output control unit 414c, and outputs display data data simultaneously through the multiplexer (not shown) and other data drive circuits according to the multiplexer control signal M_Ctrl.

[0088] The following is for reference Figure 10 This describes the data input and output of existing data driving devices and data driving devices according to an embodiment of the present invention. Figure 10 This is a diagram comparing the input and output data of a conventional data driving circuit and a data driving circuit according to an embodiment of the present invention.

[0089] Reference Figure 10 The existing first data driving circuit and the first data driving circuit of an embodiment of the present invention receive the same display data (data) and generate the same internal system clock (SCLK). The existing first to third data driving circuits respectively generate and output source output signals (SOE), and output images on the display panel 500 according to the source output signals (SOE). In contrast, the first to third data driving circuits of an embodiment of the present invention respectively generate and output an output clock (SYNC_CLK), and output images on the display panel 500 according to the output clock (SYNC_CLK).

[0090] In particular, the data driving circuit of one embodiment of the present invention can output an output clock SYNC_CLK with the same timing as other data driving circuits in the data driving device, that is, outputting the same signal, so as to be able to output source signals simultaneously with other data driving circuits in the data driving device, thereby improving the image quality of the display panel.

[0091] Those skilled in the art to which this invention pertains should understand that this invention can be implemented in other specific forms without altering its technical concept or essential features.

[0092] Therefore, the embodiments described above should be understood as exemplary in all respects and not as limiting. The scope of the invention is not defined by the detailed description provided herein, but by the scope of the claims described below, and the meaning and scope of the claims, as well as all modifications or variations derived from their equivalents, should be interpreted as being included within the scope of the invention.

Claims

1. A data-driven device, wherein, Includes multiple data drive circuits; Each of the plurality of said data driving circuits includes: The clock recovery unit recovers display data and internal system clock from image data received from the timing controller, and uses the internal system clock to generate a plurality of candidate reference clocks with a preset phase difference. as well as The data processing unit calculates the timing difference between the clock training symbols of the displayed data and the internal system clock, and generates an output clock synchronized with other data driving circuits based on the calculated timing difference between the clock training symbols and the internal system clock.

2. The data driving device according to claim 1, wherein, The data processing unit includes a clock training symbol detection unit. The clock training symbol detection unit moves the starting point of a data window that filters data according to a preset size in one direction from the rising edge of the internal system clock and detects clock training symbols in the displayed data. It then uses the timing difference between the starting point of the data window that detected the clock training symbols and the rising edge of the internal system clock to generate a clock selection signal.

3. The data driving device according to claim 2, wherein, The data processing unit further includes a clock synchronization unit, which uses the display data, the internal system clock, the clock selection signal, and a plurality of candidate reference clocks to output a multiplexer control signal so as to output source signals simultaneously with other data driving circuits of the display device.

4. The data driving device according to claim 3, wherein, The data processing unit also includes: The source output signal generation unit uses the displayed data and the internal system clock to generate a source output signal; and The source output signal synchronization unit uses the source output signal, the internal system clock, the clock selection signal, and a plurality of candidate reference clocks to generate a reference clock that is synchronized with other data driving circuits.

5. The data driving device according to claim 4, wherein, The source output signal synchronization unit includes: The first multiplexer, based on the clock selection signal, outputs any one of the plurality of candidate reference clocks as a synchronization clock; The first latch generates a first selection signal as a signal delayed by 0.5 cycles from the source output signal; The first trigger generates a second selection signal that is a signal delayed by one cycle as the source output signal; The second latch generates a third selection signal as a signal delayed by 1.5 cycles from the source output signal; and The second multiplexer outputs any one of the first selection signal to the third selection signal based on the clock selection signal.

6. The data driving device according to claim 5, wherein, The source output signal synchronization unit further includes a second flip-flop, which generates an output clock triggered by the synchronization clock received from the first multiplexer for any one of the first selection signals to the third selection signal received from the second multiplexer.

7. The data driving device according to claim 5, wherein, The first selection signal is a signal generated by the first latch based on the source output signal, triggered by the falling edge of the internal system clock. The second selection signal is a signal generated by the first flip-flop based on the source output signal, triggered by the rising edge of the internal system clock. The third selection signal is a signal generated by the second latch based on the falling edge of the internal system clock.

8. The data driving device according to claim 2, wherein, The data window and the clock training symbol are each 20 UI in size. The data window moves in one direction in units of 1 UI to filter the data in the displayed data.

9. A display device, wherein, include: The display panel receives the source signal and displays the image. as well as A data driving device includes a plurality of data driving circuits that simultaneously supply the source signal to the display panel; Each of the plurality of said data driving circuits includes: The clock recovery unit recovers display data and internal system clock from image data received from the timing controller, and uses the internal system clock to generate a plurality of candidate reference clocks with a preset phase difference. as well as The data processing unit calculates the timing difference between the clock training symbols of the displayed data and the internal system clock, and generates an output clock synchronized with other data driving circuits based on the calculated timing difference between the clock training symbols and the internal system clock.

10. The display device according to claim 9, wherein, The data processing unit includes: The clock training symbol detection unit moves the starting point of the data window that filters data according to a preset size in one direction from the rising edge of the internal system clock and detects the clock training symbols in the display data. It also generates a clock selection signal using the timing difference between the starting point of the data window that detects the clock training symbols and the rising edge of the internal system clock. The clock synchronization unit uses the display data, the internal system clock, the clock selection signal, and a plurality of candidate reference clocks to output a multiplexer control signal so as to output the source signal simultaneously with other data drive circuits of the display device. The source output signal generation unit uses the displayed data and the internal system clock to generate a source output signal; and The source output signal synchronization unit uses the source output signal, the internal system clock, the clock selection signal, and a plurality of candidate reference clocks to generate a reference clock that is synchronized with other data driving circuits.

11. The display device according to claim 10, wherein, The source output signal synchronization unit includes: The first multiplexer, based on the clock selection signal, outputs any one of the plurality of candidate reference clocks as a synchronization clock; The first latch generates a first selection signal as a signal delayed by 0.5 cycles from the source output signal; The first trigger generates a second selection signal that is a signal delayed by one cycle as the source output signal; The second latch generates a third selection signal that is a signal delayed by 1.5 cycles as the source output signal; The second multiplexer, based on the clock selection signal, outputs any one of the first selection signal to the third selection signal; and The second trigger generates an output clock triggered by the synchronization clock received from the first multiplexer, where any one of the selection signals from the first selection signal to the third selection signal received from the second multiplexer is selected.

12. The display device according to claim 11, wherein, The first selection signal is a signal generated by the first latch based on the source output signal, triggered by the falling edge of the internal system clock. The second selection signal is a signal generated by the first flip-flop based on the source output signal, triggered by the rising edge of the internal system clock. The third selection signal is a signal generated by the second latch based on the falling edge of the internal system clock.

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