Display control device, chip, and apparatus

Abstract

The application discloses a display control device, a chip and equipment, and belongs to the technical field of electronics. An input analysis module in the display control device receives a first enabling signal sent by a host computer, and statistically obtains input timing parameters based on a local clock in real time. A timing determination module determines output timing parameters based on the input timing parameters and touch parameters of a display panel. A synchronization generation module generates a second enabling signal based on the output timing parameters, and outputs an image frame to the display panel based on the second enabling signal, so that the image frame is displayed through the display panel, and touch scanning is performed in the process of displaying the image frame. The timing determination module automatically determines the timing of the output image frame based on the timing of the input image frame, adjusts the timing of the image frame, is applicable to hosts with various timings, and has high versatility.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a display control device, chip, and equipment. Background Technology

[0002] In the field of electronic technology, since the display panel needs to take into account both image display and touch operation functions, the timing of the image frames sent by the host is adjusted by the display control device, and the image frames are displayed on the display panel according to the adjusted timing to reserve the time for the display panel to perform touch scanning. Summary of the Invention

[0003] This application provides a display control device, chip, and apparatus that can be used to adjust the timing of image frames. The technical solution is as follows: In a first aspect, embodiments of this application provide a display control device, which includes an input analysis module, a timing determination module, and a synchronization generation module that are sequentially connected by signals. The input analysis module is used to receive a first enable signal sent by the host, and to statistically analyze the first enable signal in real time based on the local clock to obtain input timing parameters. The input timing parameters are used to describe the timing of the host inputting image frames to the display control device. The timing determination module has built-in timing calculation logic, which is used to obtain the touch parameters of the display panel performing touch scanning; and dynamically calculates and generates output timing parameters by combining the input timing parameters and the touch parameters. The output timing parameters are used to describe the timing of the display control device outputting the image frame to the display panel. The synchronization generation module is used to generate a second enable signal based on the output timing parameters, output the image frame to the display panel based on the second enable signal, display the image frame through the display panel, and perform touch scanning during the display of the image frame.

[0004] The timing determination module automatically determines the timing of the output image frame based on the input timing parameters, and generates a corresponding second enable signal based on the first enable signal to achieve timing adjustment. Furthermore, this application does not limit the first enable signal of the host input image frame, and can be applied to hosts with various input timings, thus exhibiting high versatility.

[0005] In one possible implementation, the display control device further includes a memory control module and memory; The memory control module is connected to the input analysis module, the memory, and the synchronization generation module, respectively, and is used to receive the first enable signal and the image frame sent by the host; and to cache the image frame in the memory according to the first enable signal. The memory control module is further configured to receive a second enable signal sent by the synchronization generation module, read the cached image frame from the memory according to the second enable signal, and send the read image frame to the display panel.

[0006] By caching and then reading, the timing of image frames is adjusted to provide a time period for the display panel to perform touch scanning during the output of image frames. Furthermore, the timing adjustment process is simple and has low operational complexity.

[0007] In one possible implementation, the display control device further includes an output buffer module; The memory control module is used to send the read image frames to the output buffer module; The output buffer module is connected to the memory and the display panel, and is used to receive the image frame read by the memory control module and send the image frame to the display panel based on the second enable signal.

[0008] Because of the transmission delay between the memory read path of the memory control module and the receive path of the display panel, the memory control module cannot guarantee that the timing of the image frames output to the display panel is exactly the same as the timing of the second enable signal. Therefore, the image frames are received and then sent by the output buffer module to ensure that the timing of the image frames output to the display panel is strictly aligned with the timing of the second enable signal, thereby eliminating screen timing misalignment.

[0009] In one possible implementation, the memory capacity is smaller than the data size of the image frame. This application does not impose strict limitations on memory capacity; even if the memory capacity is limited and cannot cache the entire image frame, touch operation and display output can still be supported.

[0010] In one possible implementation, the memory is used to cache any segment of the image frame. Since the display panel performs touch scanning segment by segment, adjusting the input timing to reserve time for touch scanning is also done at the segment level, ensuring consistency between storage and timing adjustment, and providing a basis for adjusting the timing of image frames.

[0011] In one possible timing configuration, the output buffer module is used to send the inserted image frame to the display panel based on the second enable signal by inserting a fixed pixel clock delay into the image frame. By inserting a fixed pixel clock delay into the image frame, the data output timing of the image frame is ensured to be strictly aligned with the second enable signal.

[0012] In one possible implementation, the timing determination module configures segmented touch logic to divide the image frame into multiple segments based on image rows. The number of segments is equal to the number of times the display panel performs touch scans within the image frame, and one segment corresponds to one touch scan. The input timing parameters include the input single-line cycle, which refers to the input cycle of one image line in the image frame input by the display control device; The touch parameters include the number of virtual rows, which refers to the number of virtual rows filled within the segment. The output time of the virtual rows is used to perform the touch scan. For cases where the display panel performs multiple touch scans within an image frame, the image frame is divided into multiple segments, and touch scans are performed segment by segment. This achieves uniform distribution of touch scans, avoiding problems such as touch interruptions, jitter, horizontal lines, and sudden increases in power consumption caused by concentrated touch scans.

[0013] In one possible implementation, the virtual row is used to continuously transmit clock signals to maintain the stability of the panel GOA clock, so as to avoid screen flickering and horizontal stripe defects caused by the GOA clock stopping during the touch scanning period.

[0014] In one possible implementation, the output timing parameters include single-line blanking duration, which refers to the duration of the line blanking region of the image frame output by the display control device; The timing determination module calculates the single-line blanking duration of the output according to the following method: The number of rows in a segment is determined based on the number of segments and the number of valid rows in the image frame. The number of valid rows refers to the total number of rows in the image frame, and the number of rows in a segment refers to the number of multiple image rows included in the segment. The segment period is determined based on the input single-line period and the number of segmented lines, wherein the segment period indicates the sum of the input single-line periods of the multiple image lines included in the segment; The single-line blanking duration is determined based on the segmentation period, the first effective area duration, the number of virtual rows, and the number of segmented rows. The first effective area duration refers to the duration of one image row of the image frame output by the display control device.

[0015] The segmented period is determined based on the single-line input period, indicating that the total input duration and total output duration of multiple image lines within a segment are the same. The timing synchronization of input and output is achieved at the segment level, avoiding screen tearing and other abnormalities on the display panel due to timing asynchrony between input and output.

[0016] In one possible implementation, the input timing parameters include the input single-line cycle, the touch parameters include touch duration, global virtual interval duration, initialization duration, and margin duration, and the output timing parameters include startup delay; The touch duration refers to the execution duration of the touch scan, the global virtual interval duration refers to the running duration of the GOA clock, the initialization duration refers to the initialization duration of the GOA clock, the margin duration is used to compensate for the frequency changes caused by the state changes of the display panel, and the startup delay refers to the delay of the second enable signal compared to the first enable signal.

[0017] By determining the startup delay, the start time of the second enable signal is clarified, thereby improving the accuracy of the second enable signal. Furthermore, the startup delay is delayed after the first enable signal before the output of image frames begins based on the second enable signal, so as to reserve the necessary time for the display panel to operate the GOA circuit to perform touch scanning.

[0018] In one possible implementation, the startup delay is determined based on the number of touch rows, the number of virtual interval rows, the number of initialization rows, and the number of margin rows; The number of touch rows is obtained by counting the touch duration based on the input single-row cycle; The number of rows in the virtual interval is obtained by counting the duration of the global virtual interval based on the output single-row cycle. The output single-row cycle is determined based on the duration of the first effective area and the single-row blanking duration. The output single-row cycle refers to the cycle of one image row in the image frame output by the display control device. The number of initialization rows is obtained by counting the initialization duration based on the output single-row cycle; The number of margin rows is obtained by counting the margin duration based on the output single-row period.

[0019] The number of touch rows is obtained by counting the touch duration based on the input single-line cycle of the first enable signal, so that the touch duration and the input timing of the image frame are matched. Since the display control device counts and works by using the output single-line cycle as the basic beat when controlling the display panel to display image frames, the parameters designed for display, such as virtual interval, initial number of lines, and margin number of lines, are converted into the number of output single-line cycles. The count is based on the input single-line cycle / output single-line cycle to ensure that the startup delay and the timing of the image frame are matched.

[0020] In one possible implementation, the display device updates the timing register uniformly after the arrival of the Vsync field synchronization signal for each frame, without adjusting the output timing during the output of a single frame image. Adjusting the output timing during the output of a single frame image would lead to timing mismatch within that frame, resulting in display abnormalities. By determining the timing of output timing adjustments based on the field synchronization information, and adjusting the timing as a whole for each single frame image, the internal timing of the image frame is ensured to be consistent, resulting in a strong interactive experience.

[0021] In one possible implementation, the timing operation logic of the timing determination module is implemented using any of the following hardware architectures: First, implementation using pure digital logic circuits; second, implementation using a built-in MCU microprocessor. The pure digital logic circuit implementation is compatible with low-cost LTDDI chips in the repair market, while the MCU microprocessor implementation is compatible with high-end chips with complex timing compensation for multiple parameters.

[0022] In one possible implementation, the display control device is an LTDDI (Large Touch and Display Driver Integration) chip. This LTDDI chip can be integrated into any device, making it suitable for various device scenarios and highly versatile.

[0023] Secondly, a display control chip is also provided, which integrates the display control device of the first aspect or any possible implementation thereof.

[0024] Thirdly, a display device is also provided, which is configured with a display panel and a display control chip as described in the second aspect.

[0025] For example, the display device includes a mobile phone, and the display control chip is a main control host configured on the mobile phone. The mobile phone can be a mobile phone used in a repair scenario or a mobile phone used in other scenarios, and this application is not limited to the brand of the mobile phone. Even if the input timing is different under different brands, the timing can be adjusted through the main control host to be compatible with all compatible models. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a host input signal provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a display control device provided in an embodiment of this application; Figure 3 This is a digital timing diagram of another signal provided in an embodiment of this application; Figure 4 This is a schematic diagram of the pixel distribution of an image provided in an embodiment of this application; Figure 5 This is a schematic diagram of another display control device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of another display control device provided in the embodiments of this application; Figure 7 This is a schematic diagram of another display control device provided in the embodiments of this application; Figure 8 This is a flowchart of an image frame output provided in an embodiment of this application; Figure 9 This is a schematic diagram of another display control device provided in an embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0029] In the field of electronics, a display system comprises a host computer and a display device. The host computer, also known as the main control device, is used to generate and process the image frames to be displayed, while the display device is used to display the image frames sent by the host computer. Taking a mobile phone as an example, the host computer refers to the chip on the phone that generates image frames based on the phone's operating status, including camera-captured images and application running status. The display device refers to the screen configured on the phone. Furthermore, the mobile phone can be used in a repair setting or in other scenarios; this is not limited here.

[0030] Optionally, the display device includes a display panel and a display control device. The display control device is used to control the display panel to display image frames. Continuing with the example of a mobile phone screen, the display control device refers to the driver chip inside the mobile phone screen.

[0031] In one possible implementation, the host computer, in addition to providing image frames to the display control device, also sends field synchronization signals and data enable signals. See also Figure 1 , Figure 1In this context, Vsync refers to the field synchronization signal. Two adjacent pulses within the field synchronization signal correspond to the transmission duration of an image frame. DE refers to the data enable signal. One pulse in the data enable signal corresponds to one image line within an image frame. The low level within the data enable signal refers to the Hsync Porch (horizontal blanking area) of the image frame, also known as the line blanking area. It is the blank time from the end of the transmission of one image line within an image frame to the start of the transmission of the next image line. Figure 1 The data enable signal also includes Vsync Porch (vertical blanking region), which refers to the blanking time from the end of image frame transmission to the start of the next image frame transmission.

[0032] Figure 1 This example illustrates a signal sent by a host to a display controller. This signal indicates the input timing of image frames sent by the host to the display controller, rather than defining the input timing. Different hosts may have different input timings for image frames. For instance, although all hosts may have a frame rate of 60 frames per second, some hosts may send a longer vertical blanking interval and a shorter horizontal blanking interval in their data enable signals, while other hosts may send a shorter vertical blanking interval and a longer horizontal blanking interval.

[0033] In some cases, the display control device adjusts the timing of image frames, using an output timing different from the input timing to output image frames to the display panel, so that the display panel can display the image frames. For example, when different hosts have different input timings, the display control device cannot directly process image frames sent by different hosts and needs to parse the signals input by the hosts and adjust its internal timing.

[0034] Alternatively, since the display panel combines image display and touch functions, and the display panel achieves touch function by performing touch scanning, touch scanning is used to scan the touch electrodes in the display panel, collect the level signals of the touch electrodes to achieve touch positioning, and then interact with touch interaction devices based on touch positioning.

[0035] Because touch scanning cannot be performed on the display panel while an image line is being displayed, it must be performed only after the image line has finished displaying. Therefore, the display panel performs touch scanning during the blank time between the end of one image line and the start of the next. If the blank time between two image lines in the input timing sequence, i.e., the line blanking area, is too short, the display panel may be unable to perform touch scanning. Based on this, the display control device will readjust the timing to reserve sufficient execution time for touch scanning.

[0036] This application provides a display control device, see [link]. Figure 2The display control device includes an input analysis module 11, a timing determination module 12, and a synchronization generation module 13. The input analysis module 11 is connected to the timing determination module 12, and the timing determination module 12 is also connected to the synchronization generation module 13. That is, the input analysis module 11, the timing determination module 12, and the synchronization generation module 13 are sequentially connected by signals.

[0037] The input analysis module 11 receives the first enable signal sent by the host and performs real-time statistics on the first enable signal based on the local clock to obtain input timing parameters. The input timing parameters are used to describe the timing of the host inputting image frames to the display control device.

[0038] In some cases, the host transmits image frames intermittently with invalid data. For example, an image frame may consist of multiple image lines. After transmitting one image line, the host inserts invalid data to maintain data channel stability. The invalid data may be a signal with a fixed value. Since the data transmitted on the host's data channel for sending image frames includes both image frames and invalid data, the host also sends a first enable signal to the display control device. This enable signal allows the display control device to determine whether the data currently received through the data channel is an image frame or invalid data. For instance, when the first enable signal is high, the data transmitted on the data channel is an image frame; when the first enable signal is low, the data transmitted on the data channel is invalid data. Figure 3 In this context, DE_in is the first enable signal.

[0039] For example, the display control device receives a first enable signal through the memory control module to acquire an image frame based on the first enable signal. The function of the memory control module is described in the following embodiments and will not be repeated here.

[0040] In some cases, the display control device also receives a first enable signal via the input analysis module 11 to determine input timing parameters based on the first enable signal. Exemplarily, the input timing parameters include an input single-line period, which is the input period pointing to an image line in an input image frame for the display control device. See also... Figure 3 , Figure 3 DE_in in the input single-line cycle of the image line indicates that the transition of DE_in within the input single-line cycle is from low level to high level. After the transition from high level to low level, it can be understood that the input single-line cycle refers to the duration of the high level in the first enable signal plus the duration of the low level.

[0041] The input analysis module 11 uses the local clock to count the duration of the high level and the duration of the low level in the first enable signal to obtain the input single-line period. The determination process can be expressed as Htotal = H_Size + H_Porch, where Htotal is the input single-line period of the image line, H_porch is the line blank corresponding to the image line, i.e., the duration of the low level, and H_Size is the duration of the high level.

[0042] In one possible implementation, the input analysis module 11 starts counting based on the local clock when the first enable signal transitions from low to high. When the first enable signal transitions from high to low, the counting ends to obtain H_Size, and the next round of counting begins. When the first enable signal transitions from low to high, the current round of counting ends to obtain H_porch. The input single-line cycle is obtained by adding H_Size and H_porch. For example, with H_size = 500 and H_porch = 200 based on the local clock, Htotal = 200 + 500 = 700.

[0043] Alternatively, the input analysis module 11 starts counting via the local clock when the first enable signal jumps from low to high, and ends the current round of counting when the first enable signal jumps from low to high for the second time, using the count value as the input single-line cycle.

[0044] In some cases, the input timing parameters determined based on the first enable signal also include the number of valid rows, which refers to the number of rows in the multiple image rows included in the image frame. The image frame is used to display a frame of images, and the image row is used to display a row in that frame of images. Figure 4 This shows an image frame, where one image row corresponds to one row in the image. Figure 4 One of the rows in the image is marked in black.

[0045] A high-level signal of the first enable signal corresponds to one image row. The input analysis module 11 counts the number of high-level signals within the input time period of the image frame based on the first enable signal, thereby obtaining the number of valid rows. Optionally, the input analysis module 11 also receives a field synchronization signal. Figure 3 Vsync_in corresponds to the field synchronization signal. The input analysis module 11 determines the input time period of the image frame based on the field synchronization signal and performs counting within that input time period. For example, in... Figure 3 When Vsync_in transitions for the first time, counting begins. Each time DE_in transitions from low to high, the count increments by 1, continuing until... Figure 3 The counting ends when Vsync_in transitions for the second time, and the number of valid rows is determined based on the count value after the count ends.

[0046] Optionally, the input analysis module 11 uses the count value as the number of valid rows. Alternatively, since interference may occur during signal transmission, causing level fluctuations in the received first enable signal or field synchronization signal, the input analysis module 11 can also perform multiple counts based on multiple image frames and use the average of the multiple count values ​​as the number of valid rows.

[0047] In some cases, since the resolution of the display panel is fixed, the number of pixels in a row and the number of pixels in a column of the display panel are also fixed. Therefore, the number of rows and columns of the image frame displayed on the display panel is also fixed. The input analysis module 11 uses the number of pixels in a column of the display panel as the effective number of rows of the image frame.

[0048] The input analysis module 11 sends the statistically obtained input timing parameters to the timing determination module 12. The timing determination module 12 determines the output timing parameters based on the input timing parameters. The output timing parameters describe the timing of the display control device outputting image frames to the display panel. In some cases, the timing determination module 12 may also acquire the touch parameters of the display panel. The touch parameters describe the strategy for the display panel to perform touch scanning, and the output timing parameters are determined based on the touch parameters and the input timing parameters.

[0049] The touch parameters correspond to the display panel and can be understood as parameters preset at the factory. The timing determination module 12 can acquire touch parameters through manual configuration or receive touch parameters sent by other modules, which can be modules configured on the display panel. Furthermore, after acquiring the touch parameters, the timing determination module 12 can cache the touch parameters in storage and read them from storage when determining the output timing parameters.

[0050] For example, the touch parameters include the number of segments, the number of virtual rows, the touch duration, the global virtual interval duration, the initialization duration, and the margin duration; and the output timing parameters determined based on different touch parameters are also different. The process of determining different output timing parameters based on different parameters will be described below.

[0051] Scenario 1: Single-line disappearance duration.

[0052] For example, the single-line blanking duration refers to the duration of the line blanking region in the output image frame of the display control device, which can be understood as the buffer duration of the display control device after one image line in the output image frame. The timing control module 12 determines the single-line blanking duration based on the virtual line number and the input single-line period.

[0053] In one possible implementation, since the display panel performs one or more touch scans during the display of an image frame, problems such as touch dropouts, jitter, horizontal lines, and a sudden increase in power consumption can occur if touch scans are concentrated in a cluster. Therefore, the display panel also performs multiple touch scans evenly during the output of an image frame, that is, one touch scan is performed every few image rows. Based on this, the image frame is divided into multiple segments based on image rows, with one segment corresponding to one touch scan. The number of segments is equal to the number of times the display panel performs touch scans within the image frame. In other words, the display panel performs touch scans in units of segments, each segment containing multiple image rows. After multiple image rows within a segment have been displayed, the display panel performs a touch scan and then continues to display the image rows within the next segment.

[0054] For example, the timing determination module 12 determines the number of image rows included in a segment based on the number of valid rows and the number of segments included in the touch parameters. The number of image rows included in a segment is also called the number of segments. The number of segments refers to the number of times the display panel performs touch scanning during the output of image frames, reflecting the frequency at which the display panel performs touch scanning.

[0055] Optionally, the timing control module 12 divides the number of valid rows and the number of segments, and determines the number of rows in each segment based on the division result. The determination process is described in Formula 1.

[0056] (Formula 1) In formula 1, This refers to the number of lines in a segment. This refers to the number of valid rows. This refers to the number of segments. Divide the number of valid rows by the number of segments; the quotient is the number of rows in each segment. If... Unable to be Integer division will use the integer result of the division as the row number of the segment. For the last segment, the row number of that segment is the sum of the integer and the remainder. For 1922, If it is 10, then the first nine It is 192, the last one. The value is 194.

[0057] Subsequently, the timing control module 12 can determine the single-line blanking duration based on the number of segments, the input single-line cycle, and the number of virtual lines in the touch parameters. The number of virtual lines refers to the number of virtual lines filled in the segment. The output period of the virtual lines is used to perform touch scanning. It can be understood that the virtual lines are empty lines filled in the segment. The empty lines and image lines have the same structure. For example, the empty lines and image lines have the same number system and the same amount of data. However, the virtual lines are not used to display images. The display panel can perform touch scanning during this period.

[0058] Touch scanning is performed within segments, and the display panel does not display image rows during touch scanning. However, if the transmission channel between the display controller and the display panel is not used to transmit any data, the GOA (Gate On Array Clock) clock on the display panel will stop. The GOA clock refers to the dedicated clock signal of the GOA circuit, which provides the gate drive signal for each row of pixels on the display panel. The gate drive signal is used to open the gate. By opening the gate, the column drive circuit writes the data voltage to the pixel capacitor, lighting up a row of pixels on the display panel. After writing, the gate is closed, and the pixel capacitor maintains the voltage to maintain brightness.

[0059] A GOA clock outage can affect the display of subsequent image lines, leading to screen freezes or flickering horizontal lines on the display panel. Therefore, the display control device inserts virtual lines within the segments, continuously transmitting clock signals based on these virtual lines to maintain the stability of the GOA clock on the display panel. This ensures that data is still transmitted normally on the transmission channel during touch scanning, guaranteeing the normal operation of the GOA clock and preventing flickering and horizontal line defects caused by a GOA clock outage during touch scanning.

[0060] In one possible implementation, the timing determination module 12 determines the segment period based on the input single-line period and the number of segments, where the segment period indicates the input single-line period after which multiple image lines included in the segment are processed; then, it determines the single-line blanking duration based on the segment period, the first effective area duration, the number of virtual lines, and the number of segmented lines. The first effective area duration refers to the duration of one image line in the image frame output by the display control device.

[0061] In some cases, because the display control device needs to synchronize the reading and writing of output and input image frames, otherwise screen tearing and other abnormalities will appear on the display panel. Therefore, the duration of the output segment is controlled to be the same as the duration of the input segment to achieve read and write synchronization at the segment level. The input single-line cycle indicates the cycle of inputting one image line, and the segment line number indicates the number of image lines included in the segment. Therefore, the product of the input single-line cycle and the segment line number equals the segment cycle, which is both the duration of the input segment and the duration of the output segment.

[0062] Optionally, the duration of the first effective area is determined based on the number of pixels in an image row. The number of pixels refers to the number of pixels in a row of the display panel, which is the number of columns in the display panel. See also... Figure 4 , Figure 4 The image shown has 24 pixels.

[0063] Since the display control device outputs one pixel's data sequentially according to the local clock signal in the output image line, the effective range duration of one pixel's data is equal to the clock cycle of the local clock signal. The duration of outputting one image line is the sum of the effective range durations of multiple pixels' data. If the duration is determined by counting the number of transitions in the clock signal, the timing control module 12 can directly use the column number of the display panel as the first effective range duration.

[0064] In some cases, the process of determining the single-line blanking duration based on the segment period, the number of virtual rows, the number of segmented rows, and the input single-line period is shown in Formula 2.

[0065] (Formula 2) In formula 2, This refers to the duration of single-line blanking. This refers to the segmented period. This refers to the number of lines in a segment. This refers to the number of virtual rows. This refers to the horizontal resolution, which reflects the number of clock cycles required to output one line of image data, also known as the duration of the first effective area. Figure 3 The duration of the high level in DE_out.

[0066] in, The sum indicates how many rows of data are included in the segment. This refers to the output cycle of each row of data. The output cycle will be referred to as the single-row output cycle in the following text. The single-row output cycle includes the duration of the first valid area and the single-row blanking duration of each row of data. Therefore, the duration of the first valid area will be subtracted to obtain the single-row blanking duration.

[0067] Optionally, the timing control module 12 may first determine the data output duration based on the number of virtual rows, the input single-row cycle, and the segment cycle; determine the output single-row cycle based on the data output duration and the number of segment rows; and then determine the single-row blanking duration based on the output single-row cycle and the first valid area duration. For example, the timing control module 12 may multiply the number of virtual rows and the input single-row cycle to obtain the touch duration, subtract the segment cycle from the touch duration to obtain the data output duration, divide the data output duration by the number of segment rows to obtain the output single-row cycle, and then subtract the output single-row cycle from the first valid area duration to obtain the single-row blanking duration.

[0068] Scenario 2: Startup delay.

[0069] Startup delay refers to the delay between the second enable signal and the first enable signal. It can be understood as the delay between the start of outputting an image frame and the start of receiving an image frame. The reason for this fixed delay is that the display panel needs time to operate the GOA circuit and perform touch scanning; this delay allows the display panel sufficient time.

[0070] Optionally, operating the GOA circuit includes operations such as initializing the GOA clock and running the GOA clock. Initializing the GOA clock includes resetting the GOA clock or starting the GOA circuit. Running the GOA clock is used to continuously output uninterrupted output pulses to simulate the normal line-by-line scanning process, so as to stabilize the state of the GOA clock.

[0071] Since performing the above operations requires a certain amount of time, a fixed delay is used to allow time for their execution. Furthermore, because these operations are performed on the display panel, the time required for each operation is the same for the same display panel; that is, even if image frames with different input timings are displayed on the same display panel, the fixed delay duration remains the same.

[0072] Optionally, the fixed delay duration includes touch duration, global virtual interval duration, and initialization duration. Touch duration refers to the execution duration of touch scanning, global virtual interval duration refers to the runtime of the GOA clock, and initialization duration refers to the initialization duration of the GOA clock.

[0073] In addition, since the display panel may experience frequency changes due to temperature or operating speed variations, in some cases, the fixed delay duration will also take into account the margin duration. The margin duration is used to compensate for frequency changes caused by changes in the display panel's state, such as temperature or speed variations.

[0074] Since the display control device counts and works by controlling the display panel to display image frames based on the output single-line cycle, the duration of the fixed delay will be converted into the number of cycles of the output single-line cycle. This number of cycles corresponds to the start delay in the above embodiment. That is, the unit of the start delay is not a time unit, but a number of lines.

[0075] In some cases, the startup delay is determined based on the number of virtual interval rows, the number of initial rows, and the number of margin rows. The number of virtual interval rows is determined based on the output single-line period and the global virtual interval duration. Since the output single-line period is already determined in Scenario 1, the clock signal can be controlled to transition according to the output single-line period, and the number of virtual interval rows can be obtained by counting based on the clock signal. Alternatively, the number of virtual interval rows can be obtained by directly dividing the global virtual interval duration by the output single-line period. The number of initial rows is determined based on the output single-line period and the initialization duration, while the number of margin rows is determined based on the margin duration and the output single-line period. The process of determining the number of initial rows and the number of margin rows based on the output single-line period is similar to the process of determining the number of virtual interval rows based on the output single-line period, and will not be described again here.

[0076] Optionally, the touch duration may also be measured in rows. However, since the touch duration needs to be matched with the input timing of the image frame, for example, the touch duration is the upper limit of the total time slots allocated to touch scanning within the entire input cycle of the segment. Therefore, the touch duration will be counted based on the single row cycle of the first enable signal to obtain the touch row number. For example, the touch duration will be counted based on the first enable signal to obtain the touch row number.

[0077] Then, the timing determination module 12 determines the startup delay based on the number of touch rows, the number of virtual interval rows, the number of initialization rows, and the number of margin rows. The process of determining the startup delay is shown in Formula 3.

[0078] (Formula 3) Start Delay refers to the startup delay, Touch Time refers to the number of touch rows, DE Dummy refers to the number of virtual interval rows, and VBP Dummy refers to the number of initialization rows. This refers to the margin row count. Among them, Touch Time, DE Dummy, and... The VBP Dummy operation is used to store image frames in memory for a period of time without outputting them, which will occupy the pre-buffer waiting time. The initialization operation corresponding to VBP Dummy is used to start outputting when VBP Dummy is used. It is located in the vertical blanking blank interval that comes with the input image frame based on the field synchronization signal Vsync. It will not occupy the buffer waiting time, but will automatically lengthen the total waiting interval. Therefore, the two operations will be subtracted to cancel each other out.

[0079] In some cases, when the timing determination module 12 calculates the startup delay based on Formula 3, it will also perform unit conversion to unify the number of touch rows, virtual interval rows, initialization rows, and margin rows. For example, it will convert all four parameters into the number of clock signal transitions. Optionally, in addition to determining the startup delay based on the four parameters, it will also refer to the size of the internal memory. Since the input image frames are buffered in the memory during the delayed output image frame period, and the size of the internal memory is limited, there is also an upper limit to the number of image frames buffered in the memory. Therefore, the duration of delay by buffering image frames is also limited.

[0080] After determining the output timing parameters, the timing determination module 12 sends them to the synchronization generation module 13. The synchronization generation module 13 then generates a second enable signal based on the output timing parameters. For example, after the first transition of DE_in and after reaching the start delay, a single-cycle periodic signal is generated using Output DE Blank and H_Vize. Output DE Blank represents the low-level period of the periodic signal, and H_Vize represents the high-level period. After the number of transitions in the periodic signal reaches the required number of segments, virtual lines are output until the number of output virtual lines reaches the required virtual line count. The corresponding duration period begins the next segment's periodic transition. Figure 3 In this context, DE_out corresponds to the second enable signal.

[0081] Touch scanning can be performed during the output of an image frame using a second enable signal. Figure 3 Touch_EN is the touch enable signal, used to stop the display and start touch scanning. A high level of Touch_EN indicates that touch scanning is being performed. See [link to relevant documentation]. Figure 3 The line blanking region of the second enable signal is shorter than that of the first enable signal. The output time period of the virtual line reserved in the segment matches the high level of Touch_EN, which can support touch scanning.

[0082] For example, the output timing of the display control device outputting image frames to the display panel is controlled by the second enable signal, see [link to relevant documentation]. Figure 5 The display control device also includes a memory control module 14 and a memory 15. The memory control module 14 is used to receive a first enable signal and an image frame sent by the host; cache the image frame in the memory 15 according to the first enable signal; receive a second enable signal sent by the synchronization generation module 13; read the cached image frame from the memory 15 according to the second enable signal; and send the read image frame to the display panel.

[0083] Optionally, the first enable signal and the image frame are transmitted through different channels. After receiving the first enable signal, the memory control module 14 reads the data transmitted on the data channel as an image line based on the first enable signal being high, and caches the image line in memory 15. If the first enable signal is low, it determines that the data transmitted on the data channel is invalid data and does not read it.

[0084] In one possible scenario, the memory control module 14 caches the image frame segment by segment in memory 15 according to the first enable signal; that is, memory 15 is used to cache any segment of the image frame. Since memory 15 does not require storing the entire image frame, the memory capacity of memory 15 can be smaller than the data size of the image frame. There is no limitation on the memory size of memory 15; even if the memory of memory 15 is limited, touch operation and display output can still be supported.

[0085] Regardless of the method by which the memory control module 14 caches image frames in memory 15, the memory control module 14 will receive a second enable signal sent by the synchronization generation module 13. When the second enable signal is high, it reads an image line from memory 15 and outputs the read image line to the display panel. If the second enable signal is low, the memory control module 14 will output a virtual line or fixed data to fill the line blanking area.

[0086] In some cases, the memory control module 14 and the display panel are indirectly connected, see [reference needed]. Figure 6 The display control device also includes an output buffer module 16, which is connected to the memory control module 14. The memory control module 14 sends the read image frame to the output buffer module 16, and the output buffer module 16 receives the image frame read by the memory control module 14 and sends the image frame to the display panel based on the second enable signal.

[0087] Although the memory control module 14 reads the image frame according to the first enable signal, due to the transmission delay between the memory read path of the memory control module 14 and the receiving path of the display panel, the memory control module 14 cannot guarantee that the timing of the image frame output to the display panel is exactly the timing of the second enable signal. Therefore, the output buffer module 16 receives the image frame and then sends it to ensure that the timing of the image frame output to the display panel is strictly aligned with the second enable signal. For example, the output buffer module 16 inserts a fixed pixel clock delay into the image frame based on the second enable signal. The fixed pixel clock delay is, for example, a fixed delay of at least one PCLK pixel clock, to ensure that the data output timing of the image frame is strictly aligned with the second enable signal. This is done to align the second enable signal output by the synchronization generation module 13, thereby resolving the phase misalignment of the memory read timing, the second enable signal, and the panel receiving timing, ensuring that the image frame is strictly aligned with the H_size and DE blank single-line period, and avoiding left-right misalignment of the image.

[0088] Furthermore, the above is intended to illustrate the process by which the display control device adjusts the timing to output image frames to the display panel, and is not intended to limit the individual modules included in the display control device. See [link to relevant documentation]. Figure 7 , Figure 7Input Sync Analysis corresponds to Input Analysis Module 11, Timing Calculate corresponds to Timing Determination Module 12, Output Sync Generate corresponds to Sync Generate Module 13, Memory control corresponds to Memory Control Module 14, Memory corresponds to Memory Module 15, and Output Buffer corresponds to Output Buffer Module 16. Figure 7 The document also shows the signal transmission between the various modules. Input Image refers to the image frame input according to the first enable signal, and Output Image refers to the image frame output according to the second enable signal.

[0089] Next, combine Figure 8 The flowchart shown illustrates the process from receiving an image frame to outputting an image frame by the display control device. After power-on, the display control device performs internal operations to initialize the register devices and stabilize the display. Then, the display control device waits for the host to send an image frame. If the host inputs an image frame, the input analysis module 11 performs input synchronization analysis on the first enable signal of the input image frame to obtain input timing parameters. The timing determination module 12 performs timing calculations to determine the output timing parameters based on the input timing parameters and sets the output timing parameters in the register.

[0090] Afterwards, wait for the field synchronization signal. Based on the field synchronization signal, start receiving the next image frame and begin applying the output timing parameters. For example, the synchronization generation module 13 generates a second enable signal based on the output timing parameters. Use the second enable signal to output the received image frame. By adjusting the output timing at the beginning of the next image frame, timing changes within a single image frame are avoided.

[0091] Figure 9 Another display control device is shown, displaying the positions of multiple modules within the control device and Figure 9 The multiple modules within the display control device shown are located in different positions. Figure 9 The MCU in the above embodiment corresponds to the timing determination module 12. This can be understood as the algorithm for calculating the output timing parameters being implemented by the MCU. In some cases, the calculation algorithm can also be implemented by logic circuits.

[0092] Furthermore, the above is intended to illustrate the process of outputting a second enable signal based on a first enable signal, rather than to limit the input timing parameters determined based on the first enable signal. For example, in addition to determining the input single-line period based on the first enable signal, the duration of the first effective area can also be determined based on the first enable signal, i.e., to realize the statistics of image frame resolution, or parameters such as Vsync gate timing. Moreover, when determining the output timing parameters, other parameters for improving display quality can also be considered, such as rescanning or virtual lines.

[0093] It can be understood that the timing operation logic within the timing determination module 12 is implemented using any of the following hardware architectures, including but not limited to: the first is a pure digital logic circuit to adapt to the low-cost LTDDI chip with long maintenance time; the second is to implement the operation using a built-in MCU microprocessor to adapt to high-end chips with complex timing compensation for multiple parameters.

[0094] In summary, the display control device provided in this application automatically determines the timing of the output image frame based on the input timing parameters through the timing determination module 12, and generates a corresponding second enable signal based on the first enable signal to achieve timing adjustment. Furthermore, this application does not limit the first enable signal when the host inputs the image frame, and can be applied to hosts with various timings, exhibiting high versatility and compatibility. For example, it can be applied to various mobile phones, thereby shortening the mobile phone development cycle, saving manpower and costs, and significantly improving customer response speed and operational efficiency. Moreover, this display control device eliminates the need for high-capacity memory 15, still supporting touch functionality and display output with limited storage resources. The timing determination module 12 can be implemented using an MCU or pure logic, offering high flexibility. Furthermore, the MCU-based solution is suitable for more complex calculations, while the pure logic-based method is suitable for calculations in ultra-low-cost products.

[0095] This application embodiment provides a display control chip, the display control chip being configured as follows: Figure 2 , Figures 5-7 or Figure 9 The display control device shown is, for example, an LTDDI chip.

[0096] This application provides a display device, which includes a display panel and a display control chip. Exemplarily, the display device includes smartphones, tablets, laptops with integrated touchscreens, touchpads, in-vehicle terminals, etc.

[0097] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the first enabling signals involved in this application were all obtained under fully authorized conditions.

[0098] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0099] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A display control device, characterized in that, The display control device includes an input analysis module, a timing determination module, and a synchronization generation module that are connected in sequence by signals. The input analysis module is used to receive a first enable signal sent by the host, and to statistically analyze the first enable signal in real time based on the local clock to obtain input timing parameters. The input timing parameters are used to describe the timing of the host inputting image frames to the display control device. The timing determination module has built-in timing operation logic, which is used to obtain the touch parameters of the display panel performing touch scanning; and to determine the output timing parameters based on the input timing parameters and the touch parameters. The output timing parameters are used to describe the timing of the display control device outputting the image frame to the display panel. The synchronization generation module is used to generate a second enable signal based on the output timing parameters, output the image frame to the display panel based on the second enable signal, display the image frame through the display panel, and perform touch scanning during the display of the image frame.

2. The apparatus according to claim 1, characterized in that, The display control device further includes a memory control module and memory; The memory control module is configured to receive a first enable signal and the image frame sent by the host; and cache the image frame in the memory according to the first enable signal. The memory control module is further configured to receive a second enable signal sent by the synchronization generation module, read the cached image frame from the memory according to the second enable signal, and send the read image frame to the display panel.

3. The apparatus according to claim 2, characterized in that, The display control device also includes an output buffer module; The memory control module is used to send the read image frames to the output buffer module; The output buffer module is used to receive the image frame read by the memory control module and send the image frame to the display panel based on the timing of the second enable signal.

4. The apparatus according to any one of claims 1-3, characterized in that, The timing determination module configures segmented touch logic to divide the image frame into multiple segments based on image rows. The number of segments is equal to the number of times the display panel performs touch scans within the image frame, and one segment corresponds to one touch scan. The input timing parameters include the input single-line cycle, which refers to the input cycle of one image line in the image frame input by the display control device; The touch parameters include the number of virtual rows, which refers to the number of virtual rows filled in the segment, and the output time of the virtual rows is used to perform the touch scan.

5. The apparatus according to claim 4, characterized in that, The output timing parameters include single-line blanking duration, which refers to the duration of the line blanking area of ​​the image frame output by the display control device; The timing determination module calculates the single-line blanking duration of the output according to the following method: The number of rows in a segment is determined based on the number of segments and the number of valid rows in the image frame. The number of valid rows refers to the total number of rows in the image frame, and the number of rows in a segment refers to the number of multiple image rows included in the segment. The segment period is determined based on the input single-line period and the number of segmented lines, wherein the segment period indicates the sum of the input single-line periods of the multiple image lines included in the segment; The single-line blanking duration is determined based on the segmentation period, the first effective area duration, the number of virtual rows, and the number of segmented rows. The first effective area duration refers to the duration of one image row of the image frame output by the display control device.

6. The apparatus according to any one of claims 1-3, characterized in that, The input timing parameters include the input single-line cycle; the touch parameters include touch duration, global virtual interval duration, initialization duration, and margin duration; and the output timing parameters include startup delay. The touch duration refers to the execution duration of the touch scan, the global virtual interval duration refers to the runtime of the integrated gate drive GOA clock, the initialization duration refers to the initialization duration of the GOA clock, the margin duration is used to compensate for the frequency changes caused by the state changes of the display panel, and the startup delay refers to the delay of the second enable signal compared to the first enable signal.

7. The apparatus according to claim 6, characterized in that, The startup delay is determined based on the number of touch rows, the number of virtual interval rows, the number of initialization rows, and the number of margin rows; The number of touch rows is obtained by counting the touch duration based on the input single-row cycle; The number of rows in the virtual interval is obtained by counting the duration of the global virtual interval based on the output single-row cycle. The output single-row cycle is determined based on the duration of the first effective area and the single-row blanking duration. The output single-row cycle refers to the cycle of one image row in the image frame output by the display control device. The number of initialization rows is obtained by counting the initialization duration based on the output single-row cycle; The number of margin rows is obtained by counting the margin duration based on the output single-row period.

8. The apparatus according to any one of claims 1-7, characterized in that, The timing determination module's timing operation logic is implemented using any of the following hardware architectures: pure digital logic circuit implementation; or, implementation using a built-in microprocessor (MCU).

9. A display control chip, characterized in that, The display control chip integrates the display control device as described in any one of claims 1-8.

10. A display device, characterized in that, The display device is equipped with a display panel and a display control chip as described in claim 9.

Images