A display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises: a plurality of pixel circuits, the pixel circuit comprising a driving module, an initialization module and a compensation module, a reset module, a light-emitting control module and a light-emitting element; a plurality of scanning lines, the scanning line comprising a first scanning line, a second scanning line and a light-emitting control line, the i-th first scanning line, the i-th second scanning line and the i-th light-emitting control line being connected with the initialization module, the compensation module, the light-emitting control module and the reset module in the i-th pixel circuit row respectively; and a scanning driving circuit comprising a plurality of shift register units in cascade. In part of the scanning driving circuit, the first-stage shift register unit provides a scanning driving signal to the n pixel circuit rows located in the display area, and the multi-stage shift register unit provides a scanning driving signal to the m pixel circuit rows located in the display area. The above technical scheme can reduce the brightness difference between different rows and improve the display uniformity.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display technology, users have increasingly higher requirements for display quality.

[0003] For high-frequency displays, in order to reduce the bezel size and the number of signal lines in the display area, the shift register unit in some scan drive circuits usually drives multiple pixel circuit rows. At the same time, some pixel circuit rows will reuse the drive signals of other pixel circuit rows. However, this will cause differences in the drive timing in different pixel circuit rows, resulting in brightness differences in sub-pixels of different rows and affecting display uniformity. Summary of the Invention

[0004] This application provides a display panel and display device that can reduce the brightness difference of light-emitting elements in different pixel circuit rows and improve display uniformity.

[0005] According to one aspect of this application, a display panel is provided, comprising: a plurality of pixel circuits located in a display area; a plurality of pixel circuits arranged along a first direction to form a pixel circuit row, the plurality of pixel circuit rows being arranged along a second direction, the first direction and the second direction intersecting; The pixel circuit includes a driving module, an initialization module, a compensation module, a reset module, a light emission control module, and a light emission element. The driving module includes a driving transistor. The initialization module and the compensation module are both electrically connected to the gate of the driving transistor, and the compensation module is also electrically connected to the light emission control module. The reset module and the light emission control module are both electrically connected to the light emission element. The display panel also includes multiple scan lines for transmitting scan drive signals; the scan lines include a first scan line, a second scan line, and a light emission control line located in the display area; along the second direction, the i-th first scan line is electrically connected to the control terminal of the initialization module in the i-th pixel circuit row, the i-th second scan line is electrically connected to the control terminal of the compensation module in the i-th pixel circuit row, the i-th light emission control line is electrically connected to the control terminal of the light emission control module in the i-th pixel circuit row, and the (i+j)-th first scan line is also electrically connected to the control terminal of the reset module in the i-th pixel circuit row, where i and j are both positive integers; The display panel also includes multiple scan driving circuits, which are electrically connected to the first scan line, the second scan line, and the light emission control line, respectively. The scan driving circuit includes multiple cascaded shift register units. In some scan driving circuits, the first-level shift register unit is configured to provide scan driving signals to n scan lines located in the display area, and the multi-level shift register unit is configured to provide scan driving signals to m scan lines located in the display area, where m > n and m and n are both positive integers.

[0006] According to another aspect of this application, a display device is provided, including the aforementioned display panel.

[0007] The technical solution of this application, by configuring a first-stage shift register unit to provide scan drive signals to n scan lines located in the display area in a partial scan drive circuit, and a multi-stage shift register unit to provide scan drive signals to m scan lines located in the display area, can reduce the number of scan lines connected to the output terminal of the first-stage shift register unit in this partial scan drive circuit. By changing the timing of the scan drive signals transmitted on the scan lines connected to this scan drive circuit, the working timing in the pixel circuit row can be effectively adjusted, so that at least a portion of the timing relationship of the multiple scan drive signals received in different pixel circuit rows remains consistent. This is beneficial to reduce the brightness difference of the light-emitting elements in different pixel circuit rows and improve the display uniformity of the display panel.

[0008] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a top view of a display panel provided in an embodiment of this application; Figure 2 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of this application; Figure 3 This is a timing diagram of a pixel circuit provided in an embodiment of this application; Figure 4 This is a top view of another display panel provided in an embodiment of this application; Figure 5 This is a timing diagram of a display panel provided in an embodiment of this application; Figure 6 This is a top view of another display panel provided in an embodiment of this application; Figure 7 This is a timing diagram of another display panel provided in an embodiment of this application; Figure 8 This is a top view of another display panel provided in an embodiment of this application; Figure 9 This is a timing diagram of another display panel provided in an embodiment of this application; Figure 10 This is a top view of another display panel provided in an embodiment of this application; Figure 11 This is a timing diagram of another display panel provided in an embodiment of this application; Figure 12 This is a top view of another display panel provided in an embodiment of this application; Figure 13 This is a timing diagram of another display panel provided in an embodiment of this application; Figure 14 This is a top view of another display panel provided in an embodiment of this application; Figure 15 This is a timing diagram of another display panel provided in an embodiment of this application; Figure 16 This is a top view of another display panel provided in an embodiment of this application; Figure 17 This is a timing diagram of another display panel provided in an embodiment of this application; Figure 18 This is a top view of another display panel provided in an embodiment of this application; Figure 19 This is a timing diagram of another display panel provided in an embodiment of this application; Figure 20 This is a top view of another display panel structure provided in the embodiments of this application; Figure 21 This is a timing diagram of another display panel provided in an embodiment of this application; Figure 22 This is a top view of another display panel provided in an embodiment of this application; Figure 23 This is a timing diagram of another display panel provided in an embodiment of this application; Figure 24 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application; Figure 25 This is a schematic diagram of the layout structure of a pixel circuit provided in an embodiment of this application; Figure 26 This is a top view of another display panel provided in an embodiment of this application; Figure 27 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0011] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.

[0012] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0013] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0014] It should be noted that the implementation methods provided in this application can be combined with each other without contradiction.

[0015] Figure 1 This is a top view structural diagram of a display panel provided in an embodiment of this application. Figure 2 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of this application, for reference. Figure 1 and Figure 2The display panel 001 includes multiple pixel circuits PC located in the display area AA; the multiple pixel circuits PC arranged along the first direction X constitute pixel circuit rows PCR, and the multiple pixel circuit rows PCR are arranged along the second direction Y, with the first direction X and the second direction Y intersecting. The pixel circuit PC includes a driving module 110, an initialization module 120, a compensation module 130, a reset module 140, a light emission control module 150, and a light emission element OLED. The driving module 110 includes a driving transistor M3; the initialization module 120 and the compensation module 130 are both electrically connected to the gate of the driving transistor M3, and the compensation module 130 is also electrically connected to the light emission control module 150 at a third node N3; the reset module 140 and the light emission control module 150 are both electrically connected to the light emission element OLED at a fourth node N4.

[0016] In this circuit, the driving module 110 in the pixel circuit PC provides a driving current to the OLED when it emits light. The magnitude of the driving current is related to the gate potential of the driving transistor M3. The initialization module 120 initializes the gate potential of the driving transistor M3 before the OLED emits light. The compensation module 130 compensates the threshold voltage of the driving transistor M3 before the OLED emits light. The reset module 140 resets the potential of the OLED before it emits light, which helps improve display uniformity. The light emission control module 150 is electrically connected to the driving module 110 at the third node N3. When the OLED is turned on, the light emission control module 150 controls the driving module 110 to provide a driving current to the OLED, thereby controlling the OLED's emission time. When both the driving module 110 and the light emission control module 150 are turned on, the two ends of the OLED can be connected to the first power supply terminal PVDD and the second power supply terminal PVEE, respectively. A voltage difference is formed between them, causing the OLED to conduct and emit light. The brightness of the OLED is related to the magnitude of the driving current.

[0017] In some embodiments, the pixel circuit PC further includes a writing module 160 and a coupling module 170. The writing module 160 is electrically connected to the gate of the driving transistor M3 through the coupling module 170. Specifically, the coupling module 170 and the gate of the driving transistor M3 are electrically connected to a first node N1, and the writing module 160 and the coupling module 170 are electrically connected to a second node N2. The writing module 160 is used to write the data signal on the data line DL to the second node N2 of the pixel circuit PC, and the coupling module 170 can couple the data signal from the second node N2 to the first node N1, thereby controlling the gate potential of the driving transistor M3.

[0018] In some embodiments, the pixel circuit PC further includes a storage module 180. One end of the storage module 180 can be electrically connected to the first power supply segment PVDD, and the other end can be electrically connected to the first node N1 or the second node N2. The storage module 180 is used to store the potential of the first node N1 or the second node N2, which helps maintain the stability of the gate potential of the driving transistor M3, thereby keeping the driving current stable and enabling the OLED to emit light stably.

[0019] It should be noted that, Figure 2 The diagram illustrates only one example of a pixel circuit PC; the pixel circuit PC is not limited to this example. Figure 2 The circuit structure shown is shown in the figure.

[0020] Continue to refer to Figure 1 and Figure 2 The display panel 001 also includes multiple scan lines SL for transmitting scan drive signals; the scan lines SL include a first scan line S1L, a second scan line S2L and a light emission control line EML located in the display area AA; along the second direction Y, the i-th first scan line S1L(i) is electrically connected to the control terminal of the initialization module 120 in the i-th pixel circuit row PCR(i), the i-th second scan line S2L(i) is electrically connected to the control terminal of the compensation module 130 in the i-th pixel circuit row PCR(i), the i-th light emission control line EML(i) is electrically connected to the control terminal of the light emission control module 150 in the i-th pixel circuit row PCR(i), and the (i+j)-th first scan line S1L(i+j) is also electrically connected to the control terminal of the reset module 140 in the i-th pixel circuit row PCR(i), where i and j are both positive integers.

[0021] The scan line SL is electrically connected to multiple pixel circuits PC in the pixel circuit row PCR, and is used to provide scan drive signals to the multiple pixel circuits PC in the pixel circuit row PCR to realize the scan refresh of the pixel circuit row PCR. The first scan line S1L can transmit a first scan signal to control the working timing of the initialization module 120 and the reset module 140; the second scan line S2L can transmit a second scan signal to control the working timing of the compensation module 130; and the light emission control line EML can transmit a light emission control signal to control the working timing of the light emission control module 150. Along the second direction Y, the reset module 140 in the i-th pixel circuit row PCR (i) and the initialization module 120 in the (i+j)-th pixel circuit row PCR (i+j) are both connected to the (i+j)-th first scan line S1L (i+j), which helps to reduce the number of scan lines SL in the display area AA.

[0022] In some embodiments, the scan line SL further includes a third scan line SPL located in the display area AA; along the second direction Y, the i-th third scan line SPL(i) is electrically connected to the control terminal of the writing module 160 in the i-th pixel circuit row PCR(i). The third scan line SPL can transmit a third scan signal to control the operating timing of the writing module 160.

[0023] In some implementations... Figure 3 This is a timing diagram of a pixel circuit provided in an embodiment of this application, with reference to... Figures 1 to 3 Along the second direction Y, the scan drive signals transmitted by the i-th second scan line S2L(i) and the i-th third scan line SPL(i) are different, meaning that the second scan signal and the third scan signal received by the same pixel circuit PC are different. Through the second and third scan signals, the pixel circuit PC can independently perform the data writing process and the threshold compensation process. The threshold compensation process is no longer affected by the data writing process, nor is it limited by the data writing duration. This is beneficial for increasing the threshold compensation duration, improving the charging rate during the threshold compensation process, achieving complete compensation of the threshold voltage, and improving the uniformity of the display image quality.

[0024] In some implementations, reference continues. Figures 1 to 3 Along the second direction Y, the enable periods of the scan drive signals transmitted by the i-th first scan line S1L(i) and the i-th second scan line S2L(i) do not overlap. That is, in the same pixel single-channel PC, the enable periods of the first scan signal received by the initialization module 120 and the second scan signal received by the compensation module 130 do not overlap. The enable period refers to the period when the scan drive signal is at the enable level. During the enable period of the first scan signal, the first scan signal is at the enable level, which can control the initialization module 120 to be turned on and transmit the first reset signal of the first reset terminal Vref1 to the first node N1 to initialize the gate of the drive transistor M3. During the enable period of the second scan signal, the second scan signal is at the enable level, which can control the compensation module 130 to be turned on, so that the first node N1 and the third node N3 are short-circuited. When the drive transistor M3 is turned on, the threshold voltage of the drive transistor M2 is compensated to the gate of the drive transistor M3. The initialization module 120 and the compensation module 130 of the same pixel single-channel PC are not turned on at the same time.

[0025] In some implementations, reference continues. Figures 1 to 3The enable periods of the scan drive signals transmitted by the (i+j)th first scan line S1L(i+j) and the ith first scan line S1L(i) can overlap, and / or the enable periods of the scan drive signals transmitted by the (i+j)th first scan line S1L(i+j) and the ith second scan line S2L(i) can overlap. That is, in the same pixel single-channel PC, the enable period of the first scan signal received by the reset module 140 can overlap with the enable period of the first scan signal received by the initialization module 120, and / or the enable period of the first scan signal received by the reset module 140 can overlap with the enable period of the second scan signal received by the compensation module 130. During the enable period of the first scan signal, the first scan signal is at the enable level, which can control the reset module 140 to be turned on, and transmit the second reset signal of the second reset terminal Vref2 to the fourth node N4, so as to reset the OLED with the potential of the light-emitting element. The reset module 140 of the same pixel single-channel PC can be turned on at the same time as the initialization module 120, and / or the reset module 140 of the same pixel single-channel PC can be turned on at the same time as the compensation module 130.

[0026] Figure 4 This is a top view schematic diagram of another display panel provided in an embodiment of this application, with reference to... Figure 4 The display panel 001 also includes multiple scan drive circuits SDC, which are electrically connected to the first scan line S1L, the second scan line S2L, and the light emission control line EML, respectively. The scan drive circuit SDC includes multiple cascaded shift register units SRU. In some scan drive circuits SDC, the first-level shift register unit SRU (1) is configured to provide scan drive signals to n scan lines SL located in the display area AA, and the multi-level shift register unit SRU is configured to provide scan drive signals to m scan lines SL located in the display area AA, where m > n, and m and n are both positive integers.

[0027] It should be noted that, for ease of understanding and explanation, Figure 4 Only a portion of the scan drive circuit SDC in the display panel 001 is shown as an example, and all scan drive circuits SDC in the display panel 001 are not shown. It should also be noted that... Figure 4 The example shown only illustrates the scanning drive circuit SDC and its shift register unit SRU located in the non-display areas NA on opposite sides of the display area AA. In other embodiments, the scanning drive circuit SDC and its shift register unit SRU may also be located in the non-display areas NA on other sides of the display area AA, or they may be located within the display area AA. This application does not limit the specific location of the scanning drive circuit SDC and its shift register unit SRU.

[0028] The scan drive circuit SDC provides a drive circuit to the scan line SL. The scan drive circuit SDC can provide scan drive signals to multiple pixel circuits PC in the pixel circuit row PCR through the scan line SL to control the scan refresh of the pixel circuit row PCR. The scan drive circuit SDC includes multiple cascaded shift register units SRU. The first-stage shift register unit SRU (1) can receive the start signal. The input terminal of the subsequent shift register unit SRU can be connected to the output terminal of the previous shift register unit SRU, so that the scan drive signals output by the multiple cascaded shift register units SRU are shifted sequentially, which can control the pixel circuit row PCR to scan refresh sequentially.

[0029] Specifically, at least some of the shift register units (SRUs) can be connected to multiple scan lines (SLs) at their outputs, which can reduce the number of shift register units (SRUs) and help to make the display panel (001) thinner and lighter. In some implementations, in the partial scan drive circuit SDC, the shift register unit SRU is configured to provide scan drive signals to the m scan lines SL located in the display area AA. That is, in the partial scan drive circuit SDC, the shift register unit SRU is electrically connected to the m scan lines SL located in the display area AA, and provides scan drive signals to the m pixel circuit rows PCR. At the same time, the reset module 140 in the i-th pixel circuit row PCR (i) and the initialization module 120 in the i+j-th pixel circuit row PCR (i+j) are both connected to the i+j-th first scan line S1L (i+j) and receive the same scan drive signal. When j and m are different, the timing relationship of the multiple scan drive signals received in different pixel circuit rows PCR will be different, resulting in changes in the working timing in different pixel circuit rows PCR. This causes differences in the brightness of the light-emitting elements OLED in different pixel circuit rows PCR, affecting the display uniformity of the display panel 001.

[0030] By configuring a first-stage shift register unit SRU (1) in the partial scan drive circuit SDC to provide scan drive signals to n scan lines SL located in the display area AA, and a multi-stage shift register unit SRU to provide scan drive signals to m scan lines SL located in the display area AA, that is, in the partial scan drive circuit SDC, the first-stage shift register unit SRU (1) is electrically connected to the n scan lines SL located in the display area AA and provides scan drive signals to n pixel circuit rows PCR, and the multi-stage shift register unit SRU (multiple shift register units SRU other than the first-stage shift register unit SRU (1)) is electrically connected to the m scan lines SL located in the display area AA and provides scan drive signals to m pixel circuit rows PCR, it is possible to keep at least part of the timing relationship of multiple scan drive signals received in different pixel circuit rows PCR consistent, which is beneficial to reduce the brightness difference of the light-emitting element OLED in different pixel circuit rows PCR and improve the display uniformity of the display panel 001.

[0031] For example, the display panel 001 includes a first scan driving circuit SDC1, a second scan driving circuit SDC2, and a third scan driving circuit SDC3. The first scan driving circuit SDC1 includes a plurality of cascaded first shift register units SRU1, which are electrically connected to a first scan line S1L and are used to provide a first scan signal to the first scan line S1L. The second scan driving circuit SDC2 includes a plurality of cascaded second shift register units SRU2, which are electrically connected to a second scan line S2L and are used to provide a second scan signal to the second scan line S2L. The third scan driving circuit SDC3 includes a plurality of cascaded third shift register units SRU3, which are electrically connected to a light emission control line EML and are used to provide a light emission control signal to the light emission control line EML.

[0032] Taking j=1, n=1, m=2, and the enable level of the scan drive signal as an example, Figure 5 This is a timing diagram of a display panel provided in an embodiment of this application, with reference to... Figure 4 and Figure 5In the first scan driving circuit SDC1, the first shift register unit SRU1 can be electrically connected to the two first scan lines S1L located in the display area AA; in the second scan driving circuit SDC2, the first-level second shift register unit SRU2 (1) can be electrically connected to a second scan line S2L located in the display area AA along the second direction Y, and the multi-level second shift register unit SRU2 can be electrically connected to the two adjacent second scan lines S2L located in the display area AA along the second direction Y; along the second direction Y, the control terminal of the reset module 140 in the i-th pixel circuit row PCR (i) is electrically connected to the i+1-th first scan line S1L (i+1).

[0033] It is understandable that j, n, m can also be other positive integers. In some implementations, j and n are both positive integers less than m.

[0034] It is also understood that the enable level of the scan drive signal can be entirely high, or partially high and partially low. The enable level of the scan drive signal is related to the channel type of the transistor in the module it controls. When the transistor in the module it controls is an N-type transistor, the enable level of the scan drive signal can be high; when the transistor in the module it controls is a P-type transistor, the enable level of the scan drive signal can be low. In this embodiment of the invention, the channel type of the transistor in the module can be set according to actual needs, and the enable level of the scan drive signal can be determined according to the channel type of the transistor. Here, high level and low level refer to the voltage used to control the module to turn on or off, but are not limited to a fixed voltage. For example, potentials from +15V to +30V that can control the transistors in the module to be in the same state can all be high, and potentials from -10V to -5V that can control the module to be in the same state can all be low.

[0035] To more intuitively illustrate the number of scan lines SL connected to the shift register unit SRU, that is, the correspondence between the shift register unit SRU and the pixel circuit row PCR, the embodiments of this application are based on the appendix. Figure 4 and attached Figure 5 The content is provided in Table 1.

[0036] Table 1. Correspondence between a bit register unit and a pixel circuit row In Table 1, the first column represents the PCR of each pixel circuit arranged along the second direction Y, the second column represents the first shift register unit SRU1 electrically connected to the control terminal of the initialization module 120 of the PCR of each pixel circuit arranged along the second direction Y, the third column represents the first shift register unit SRU1 electrically connected to the control terminal of the reset module 140 of the PCR of each pixel circuit arranged along the second direction Y, and the third column represents the second shift register unit SRU2 electrically connected to the control terminal of the compensation module 130 of the PCR of each pixel circuit arranged along the second direction Y.

[0037] refer to Figure 4 , Figure 5 According to Table 1, by configuring the first-level second shift register unit SRU2 (1) to provide a second scan signal to a second scan line S2L located in the display area AA, and the multi-level second shift register unit SRU2 to provide a second scan signal to two scan lines SL located in the display area AA, the timing relationship between the first scan signal received by the control terminal of the reset module 140 and the second scan signal received by the control terminal of the compensation module 130 in the PCR of different pixel circuits is consistent. That is, in the display cycle of one frame, the time interval between the termination time of the first shift register unit SRU1 driving the reset module 140 to reset the fourth node N4 and the termination time of the second shift register unit SRU2 driving the compensation module 130 to compensate the potential of the first node N1 is the first time interval Δt1. The first time interval Δt1 of the PCR of different pixel circuits is the same.

[0038] In some embodiments, within the same pixel circuit row PCR, the number of stages of the first shift register unit SRU1 connected to the control terminal of the reset module 140 and the number of stages of the second shift register unit SRU2 connected to the control terminal of the compensation module 130 are the same. In other embodiments, within the same pixel circuit row PCR, the number of stages of the first shift register unit SRU1 connected to the control terminal of the reset module 140 and the number of stages of the second shift register unit SRU2 connected to the control terminal of the compensation module 130 may also be different. In different pixel circuit rows PCR, when the difference between the number of stages of the first shift register unit SRU1 connected to the control terminal of the reset module 140 and the number of stages of the second shift register unit SRU2 connected to the control terminal of the compensation module 130 is the same, the first duration Δt1 of the different pixel circuit rows PCR can also be the same.

[0039] Taking j=1, m=2, and the enable level of the scan drive signal as an example, Figure 6 This is a top view schematic diagram of another display panel provided in the embodiments of this application. Figure 7 This is a timing diagram of another display panel provided in an embodiment of this application. Figure 6 and Figure 7This illustrates the case where the number of second scan lines S2L connected to the output of the second-stage shift register unit SRU2(1) is not reduced. To more intuitively illustrate the number of scan lines SL connected to the shift register unit SRU, that is, the correspondence between the shift register unit SRU and the pixel circuit row PCR, this embodiment is based on the appendix... Figure 6 and attached Figure 7 The content is provided in Table 2.

[0040] Table 2 shows another correspondence between bit register units and pixel circuit rows. In Table 2, the first column represents the PCR of each pixel circuit arranged along the second direction Y, the second column represents the first shift register unit SRU1 electrically connected to the control terminal of the initialization module 120 of the PCR of each pixel circuit arranged along the second direction Y, the third column represents the first shift register unit SRU1 electrically connected to the control terminal of the reset module 140 of the PCR of each pixel circuit arranged along the second direction Y, and the third column represents the second shift register unit SRU2 electrically connected to the control terminal of the compensation module 130 of the PCR of each pixel circuit arranged along the second direction Y.

[0041] refer to Figure 6 , Figure 7 According to Table 2, the first shift register unit SRU1 in the first scan drive circuit SDC1 is electrically connected to the two first scan lines S1L located in the display area AA. The second shift register unit SRU2 in the second scan drive circuit SDC2 is also electrically connected to the two first scan lines S1L located in the display area AA. At the same time, along the second direction Y, the control terminal of the reset module 140 in the i-th pixel circuit row PCR(i) is electrically connected to the (i+1)-th first scan line S1L(i+1), which will cause the odd-numbered pixel circuit row PCR and the even-numbered pixel circuit row PCR along the second direction Y to be connected to the two first scan lines S1L(i+1). In the PCR of several pixel circuits, the first scan signal received by the control terminal of the reset module 140 and the second scan signal received by the control terminal of the compensation module 130 have different timing relationships. That is, the first duration Δt1 of the PCR of the odd-numbered pixel circuits and the PCR of the even-numbered pixel circuits are different. At this time, in the PCR of the odd-numbered pixel circuits and the PCR of the even-numbered pixel circuits, the difference between the number of stages of the first shift register SRU1 connected to the control terminal of the reset module 140 and the number of stages of the second shift register SRU2 connected to the control terminal of the compensation module 130 are different.

[0042] refer to Figure 2 , Figure 6 and Figure 7If the number of second scan lines S2L connected to the output of the second-stage shift register unit SRU2 (1) is not reduced, the pixel circuit PC of the odd-numbered row pixel circuit PCR will have a longer threshold voltage compensation time after resetting the fourth node N4, and the pixel circuit PC of the even-numbered row pixel circuit PCR will have a shorter threshold voltage compensation time after resetting the fourth node N4. During the threshold voltage compensation process, the driving transistor M3 is turned on, and the electrical signal of the third node N3 will leak to the fourth node N4 through the light-emitting control module 150. The different first duration Δt1 will result in different leakage times after resetting the fourth node N4, and the potential deviation of the fourth node N4 will be inconsistent. The reset status of the light-emitting element OLED will be inconsistent, resulting in differences in the brightness of the light-emitting element OLED in different pixel circuit rows PCR, which will affect the display uniformity of the display panel 001.

[0043] In this embodiment of the application, by configuring a first-stage shift register unit to provide scan drive signals to n scan lines located in the display area and a multi-stage shift register unit to provide scan drive signals to m scan lines located in the display area in a partial scan drive circuit, the number of scan lines connected to the output terminal of the first-stage shift register unit in this partial scan drive circuit can be reduced. By changing the timing of the scan drive signals transmitted on the scan lines connected to the scan drive circuit, the working timing in the pixel circuit row can be effectively adjusted, so that at least a portion of the timing relationship of the multiple scan drive signals received in different pixel circuit rows remains consistent. This is beneficial to reduce the brightness difference of the light-emitting elements in different pixel circuit rows and improve the display uniformity of the display panel.

[0044] Optional, continue to refer to Figure 4 The partial scan drive circuit SDC includes z cascaded shift register units SRU; the first-level shift register unit SRU (1) is configured to provide scan drive signals to n scan lines SL located in the display area AA; the second-level to z-1-level shift register units SRU are all configured to provide scan drive signals to m scan lines SL located in the display area AA.

[0045] Specifically, when the number of scan lines SL connected to the output of the first-stage shift register unit SRU (1) in the configuration part of the scan drive circuit SDC is reduced, only the number of scan lines SL connected to the output of the first-stage shift register unit SRU (1) can be reduced. The outputs of the second-stage shift register unit SRU (2) to the previous stage shift register unit SRU (z-1) of the last stage can all be connected to m scan lines SL to provide scan drive signals to m pixel circuits for PCR. The number of scan lines SL connected to the output of the last stage shift register unit SRU (z) can be adjusted adaptively.

[0046] In some implementations, when the scan drive circuit SDC, which is configured to reduce the number of scan lines SL connected to the output of the first-stage shift register unit SRU (1), is not electrically connected to the first scan line S1L, the output of the last-stage shift register unit SRU (z) can be connected to mn scan lines SL.

[0047] Specifically, the number of pixel circuit rows PCR in the display area AA is an integer multiple of m. At the same time, the scan line SL connected to the scan drive circuit SDC can be connected to only one pixel circuit row PCR. The number of scan lines SL connected to the scan drive circuit SDC can also be an integer multiple of m. When n scan lines SL are connected to the output of the first stage shift register unit SRU (1), the output of the last stage shift register unit SRU (z) can be connected to mn scan lines SL.

[0048] For example, continuing with j=1, n=1, m=2, mn=1, refer to... Figure 4 In the second scan drive circuit SDC2, the output terminal of the first stage second shift register unit SRU2 (1) is electrically connected to a second scan line S2L. The output terminals of the second stage second shift register unit SRU2 (2) to the previous stage second shift register unit SRU2 (z-1) can all be connected to two scan lines S2L. The output terminal of the last stage second shift register unit SRU2 (z) can be connected to a second scan line S2L.

[0049] In other embodiments, when the scan drive circuit SDC, which is configured to reduce the number of scan lines SL connected to the output of the first-stage shift register unit SRU (1), is electrically connected to the first scan line S1L, the output of the last-stage shift register unit SRU (z) can be connected to m-n+j scan lines SL.

[0050] Specifically, the number of pixel circuit rows PCR in the display area AA is an integer multiple of m. At the same time, the first scan line S1L connected to the scan drive circuit SDC needs to be connected to the control terminal of the initialization module 120 of all pixel circuit rows PCR, and also needs to be connected to the control terminal of the reset module 140 of all pixel circuit rows PCR. The number of the first scan line S1L connected to the scan drive circuit SDC is an integer multiple of m plus j. When n scan lines SL are connected to the output terminal of the first stage shift register unit SRU (1), the output terminal of the last stage shift register unit SRU (z) can be connected to m-n+j scan lines SL.

[0051] Optionally, taking the example where the enable level of the scan drive signal is all low, refer to... Figures 2 to 5Along the second direction Y, in the refresh cycle of the i-th pixel circuit line PCR(i): along the second direction Y, the scan drive signal transmitted by the i-th second scan line S2L(i) includes a first voltage edge J1, the first voltage edge J1 jumps from the enable level of the compensation module 130 to the disable level; along the second direction Y, the scan drive signal transmitted by the i-th light emission control line EML(i) includes a second voltage edge J2, the second voltage edge J2 jumps from the enable level of the light emission control module 150 to the disable level; along the second direction Y, the scan drive signal transmitted by the (i+j)-th first scan line S1(i+j) includes a third voltage edge J3 and a fourth voltage edge J4; the third voltage edge J3 jumps from the disable level of the reset module 140 to the enable level, and the fourth voltage edge J4 jumps from the enable level of the reset module 140 to the disable level; the first voltage edge J1 and the fourth voltage edge J4 are spaced by a first duration Δt1, and the second voltage edge J2 and the third voltage edge J3 are spaced by a second duration Δt2. In the PCR of two adjacent pixel circuits, the first duration Δt1 is the same, and / or the second duration Δt2 is the same.

[0052] Wherein, the first duration △t1 is the interval between the time when the reset module 140 stops resetting and the time when the compensation module 130 stops compensating, and the second duration △t2 is the interval between the time when the light-emitting element OLED stops emitting light and the time when the reset module 140 starts resetting.

[0053] For example, refer to Figures 2 to 5 After the reset module 140 stops resetting, the potential of the fourth node N4 will float. When the compensation module 130 compensates the threshold voltage of the driving transistor M3, the driving transistor M3 is turned on, and the electrical signal of the first power supply terminal PVDD will be transmitted to the third node N3. The leakage current between the third node N3 and the fourth node N4 will affect the potential of the fourth node N4. The first duration Δt1 of the PCR of two adjacent pixel circuits is the same, which can make the leakage current time between the third node N3 and the fourth node N4 in the PCR of two adjacent pixel circuits the same. The potential of the fourth node N4 is more consistent, which is beneficial to reduce the brightness difference of the light-emitting element OLED in the PCR of different pixel circuits and improve the display uniformity of the display panel 001.

[0054] When the light-emitting control module 140 is turned off, the scan drive signal at the control terminal of the light-emitting control module 140 will be pulled high. Under the influence of parasitic capacitance, the potential of the fourth node N4 will also be pulled high. Before the reset module 140 resets the fourth node N4, the potential of the fourth node N4 will be floating. The potential of the fourth node N4 will always be in a state of being coupled high, causing the light-emitting element OLED to light up stealthily. The second duration Δt2 of the PCR of the two adjacent pixel circuits is the same, which can make the duration of the light-emitting element OLED to light up stealthily in the PCR of the two adjacent pixel circuits the same, which helps to improve the display uniformity of the display panel 001.

[0055] By configuring the first duration Δt1 and / or the second duration Δt2 to be the same in two adjacent pixel circuit rows PCR, the brightness difference of the light-emitting elements OLED in any adjacent pixel circuit row PCR can be reduced, thereby improving the display uniformity of the display panel 001.

[0056] Optionally, the scan driving signal includes a first scan signal, a second scan signal, and a light emission control signal; the scan driving circuit SDC includes a first scan driving circuit SDC1, a second scan driving circuit SDC2, and a third scan driving circuit SDC3; the first scan driving circuit SDC1 includes a plurality of cascaded first shift register units SRU1, the second scan driving circuit SDC2 includes a plurality of cascaded second shift register units SRU2, and the third scan driving circuit SDC3 includes a plurality of cascaded third shift register units SRU3. At least a portion of the first shift register units SRU1 provide first scan signals to multiple pixel circuits for PCR through multiple first scan lines S1L; at least a portion of the second scan driving circuits SRU2 provide second scan signals to multiple pixel circuits for PCR through multiple second scan lines S2L; and at least a portion of the third scan driving circuits SRU3 provide light emission control signals to multiple pixel circuits for PCR through multiple light emission control lines EML.

[0057] Specifically, at least a portion of the output terminals of the first shift register units SRU1 in the first scan drive circuit SDC1 are connected to multiple first scan lines S1L, at least a portion of the output terminals of the second shift register units SRU2 in the second scan drive circuit SDC2 are connected to multiple second scan lines S2L, and at least a portion of the output terminals of the third scan drive circuit SDC3 are connected to multiple light emission control lines EML. It can be configured that the number of scan lines SL connected to at least one of the first-stage first shift register units SRU1 (1) in the first scan drive circuit SDC1, the first-stage second shift register units SRU2 (1) in the second scan drive circuit SDC2, and the first-stage third shift register units SRU3 (1) in the third scan drive circuit SDC3 is less than the number of scan lines SL connected to the other at least a portion of the shift register units SRU.

[0058] In some embodiments, at least a portion of the output terminals of the first shift register units SRU1 in the first scan driving circuit SDC1 are connected to m first scan lines S1L; at least a portion of the output terminals of the second shift register units SRU2 in the second scan driving circuit SDC2 are connected to m second scan lines S2L; and at least a portion of the output terminals of the third scan driving circuit SDC3 are connected to m light emission control lines EML. For example, m=2, such as... Figure 4 As shown, in other embodiments, m can also be an integer greater than 1, such as 3, 4, 5, 6, etc.

[0059] In an optional embodiment, the first-stage second shift register unit SRU2 (1) is configured to provide second scan signals to n second scan lines S2L located in the display area AA, and the multi-stage second shift register unit SRU is configured to provide second scan signals to m second scan lines S1L located in the display area AA.

[0060] For details, please refer to Figure 4 , Figure 5 According to Table 1, by reducing the number of second scan lines S2L connected to the output terminal of the first-stage second shift register unit SRU2 (1) to n, the second scan signal received by the compensation module 130 of the pixel circuit row PCR can be adjusted, so that the first duration Δt1 of the adjacent two pixel circuit rows PCR is the same, the leakage time between the third node N3 and the fourth node N4 in the adjacent two pixel circuit rows PCR is the same, and the potential consistency of the fourth node N4 is better, which helps to improve the display uniformity of the display panel 001.

[0061] In an optional implementation, n = mj, j < M.

[0062] For example, taking the reduction of the number of second scan lines S2L connected to the output of the first-stage second shift register unit SRU2(1) to n as an example, and continuing to refer to Figure 4 , Figure 5 According to Table 1, when j=1, m=2, and n=1, in different pixel circuit rows PCR, the difference between the number of stages of the first shift register unit SRU1 connected to the control terminal of the reset module 140 and the number of stages of the second shift register unit SRU2 connected to the control terminal of the compensation module 130 is the same. This ensures that the timing relationship between the first scan signal received by the control terminal of the reset module 140 and the second scan signal received by the control terminal of the compensation module 130 remains consistent in different pixel circuit rows. The first duration Δt1 of the PCR in different pixel circuit rows can remain the same, which helps to improve the display uniformity of the display panel 001.

[0063] For example, taking the reduction of the number of second scan lines S2L connected to the output of the first-stage second shift register unit SRU2(1) to n, when j=1, m=4, n=3. Taking the enable level of the scan drive signal as low as an example, Figure 8 This is a top view schematic diagram of another display panel provided in the embodiments of this application. Figure 9 This is a timing diagram of another display panel provided in the embodiments of this application. To more intuitively show the number of scan lines SL connected to the shift register unit SRU, that is, the correspondence between the shift register unit SRU and the pixel circuit row PCR, the embodiments of this application are based on the appendix... Figure 8 and attached Figure 9 The content is provided in Table 3.

[0064] Table 3 shows another type of correspondence between bit register units and pixel circuit rows. refer to Figure 8 , Figure 9 According to Table 3, when j=1, m=4, and n=3, in the first scan driving circuit SDC1, the first shift register unit SRU1 can be electrically connected to all four first scan lines S1L located in the display area AA; in the second scan driving circuit SDC2, the first-stage second shift register unit SRU2 (1) can be electrically connected to the three second scan lines S2L located in the display area AA along the second direction Y, and the multi-stage second shift register unit SRU2 can be electrically connected to the four adjacent second scan lines S2L located in the display area AA along the second direction Y; in the third scan driving circuit SDC3, the third shift register unit SRU3 can be electrically connected to all four light emission control lines EML located in the display area AA. In this way, the timing relationship between the first scan signal received by the control terminal of the reset module 140 and the second scan signal received by the control terminal of the compensation module 130 in different pixel circuit rows can be kept consistent, and the first duration Δt1 of PCR in different pixel circuit rows can be kept the same, which helps to improve the display uniformity of the display panel 001.

[0065] It is understood that in other implementations, m can also be other positive integers greater than 1, and j can also be other positive integers less than m. Taking m=4 as an example, regardless of j=1, 2, or 3, along the second direction Y, the first scan signal received by the control terminal of the reset module 140 of the i-th pixel circuit row PCR(i) will be shifted backward by j units compared to the first scan signal received by the control terminal of the initialization module 120 of the i-th pixel circuit row PCR(i). By setting n=mj, the second scan signal received by the control terminal of the compensation module 130 of the i-th pixel circuit row PCR(i) can also be shifted backward by j units compared to the first scan signal received by the control terminal of the initialization module 120 of the i-th pixel circuit row PCR(i). This ensures that the timing relationship between the first scan signal received by the control terminal of the reset module 140 and the second scan signal received by the control terminal of the compensation module 130 remains consistent in different pixel circuit rows, and the first duration Δt1 of the PCR in different pixel circuit rows remains the same.

[0066] In another optional embodiment, taking the example that the enable levels of the scan drive signals are all low, Figure 10 This is a top view schematic diagram of another display panel provided in the embodiments of this application. Figure 11 This is a timing diagram of another display panel provided in an embodiment of this application, see reference. Figure 10 and Figure 11 The first-level third shift register unit SRU3 (1) is configured to provide light-emitting control signals to the n light-emitting control lines EML located in the display area AA; the multi-level third shift register unit SRU3 is configured to provide light-emitting control signals to the m light-emitting control lines EML located in the display area AA.

[0067] For details, please refer to Figure 10 and Figure 11 By reducing the number of light emission control lines EML connected to the output of the first-level third shift register unit SRU (3) to n, the light emission control signal received by the light emission control module 150 of the pixel circuit row PCR can be adjusted, so that the second duration Δt2 of the adjacent two pixel circuit rows PCR is the same, and the duration of the light emission element OLED in the adjacent two pixel circuit rows PCR is the same, which helps to improve the display uniformity of the display panel 001.

[0068] In an optional implementation, n = mj, j < M.

[0069] To more intuitively illustrate the number of scan lines SL connected to the shift register unit SRU, that is, the correspondence between the shift register unit SRU and the pixel circuit row PCR, the embodiments of this application are based on the appendix. Figure 10 and attached Figure 11 The content is provided in Table 4.

[0070] Table 4 shows another type of correspondence between bit register units and pixel circuit rows. refer to Figure 10 , Figure 11 According to Table 4, when j=1, m=2, and n=1, in different pixel circuit rows PCR, the difference between the stage of the third shift register SRU3 connected to the control terminal of the light emission control module 15 and the stage of the first shift register SRU1 connected to the control terminal of the reset module 140 is the same. This ensures that the timing relationship between the light emission control signal received by the control terminal of the light emission control module 15 and the first scan signal received by the control terminal of the reset module 140 remains consistent in different pixel circuit rows. The second duration Δt2 of the PCR in different pixel circuit rows can remain the same, which helps to improve the display uniformity of the display panel 001.

[0071] For example, taking the reduction of the number of light-emitting control lines EML connected to the output of the first-stage third shift register unit SRU3(1) to n, when j=1, m=4, n=3. Taking the enable level of the scan drive signal as low as an example, Figure 12 This is a top view schematic diagram of another display panel provided in the embodiments of this application. Figure 13 This is a timing diagram of another display panel provided in the embodiments of this application. To more intuitively show the number of scan lines SL connected to the shift register unit SRU, that is, the correspondence between the shift register unit SRU and the pixel circuit row PCR, the embodiments of this application are based on the appendix... Figure 12 and attached Figure 13 The content is provided in Table 5.

[0072] Table 5 shows another type of correspondence between bit register units and pixel circuit rows. refer to Figure 12 , Figure 13According to Table 5, when j=1, m=4, and n=3, in the first scan driving circuit SDC1, the first shift register unit SRU1 can be electrically connected to all four first scan lines S1L located in the display area AA; in the second scan driving circuit SDC2, the second shift register unit SRU2 can be electrically connected to all four first scan lines S1L located in the display area AA; in the third scan driving circuit SDC3, the first-stage third shift register unit SRU3(1) can be electrically connected to the three light emission control lines EML located in the display area AA along the second direction Y, and the multi-stage third shift register unit SRU3 can be connected to the four adjacent light emission control lines EML located in the display area AA along the second direction Y. In this way, the timing relationship between the light emission control signal received by the control terminal of the light emission control module 15 and the first scan signal received by the control terminal of the reset module 140 in different pixel circuit rows can be kept consistent, and the second duration Δt2 of PCR in different pixel circuit rows can be kept the same, which helps to improve the display uniformity of the display panel 001.

[0073] It is understood that in other implementations, m can also be other positive integers greater than 1, and j can also be other positive integers less than m. Taking m=4 as an example, regardless of j=1, 2, or 3, along the second direction Y, the first scan signal received by the control terminal of the reset module 140 of the i-th pixel circuit row PCR(i) will be shifted backward by j units compared to the first scan signal received by the control terminal of the initialization module 120 of the i-th pixel circuit row PCR(i). By setting n=mj, the light emission control signal received by the control terminal of the light emission control module 150 of the i-th pixel circuit row PCR(i) can also be shifted backward by j units compared to the first scan signal received by the control terminal of the initialization module 120 of the i-th pixel circuit row PCR(i). This ensures that the timing relationship between the light emission control signal received by the control terminal of the light emission control module 150 and the first scan signal received by the control terminal of the reset module 140 remains consistent in different pixel circuit rows, and the second duration Δt2 of PCR in different pixel circuit rows remains the same.

[0074] In another optional embodiment, taking the example that the enable levels of the scan drive signals are all low, Figure 14 This is a top view schematic diagram of another display panel provided in the embodiments of this application. Figure 15 This is a timing diagram of another display panel provided in an embodiment of this application, see reference. Figure 14 and Figure 15The first-stage second shift register unit SRU2 (1) is configured to provide second scan signals to n second scan lines S2L located in the display area AA, and the multi-stage second shift register unit SRU is configured to provide second scan signals to m second scan lines S1L located in the display area AA; the first-stage third shift register unit SRU3 (1) is configured to provide light emission control signals to n light emission control lines EML located in the display area AA; and the multi-stage third shift register unit SRU3 is configured to provide light emission control signals to m light emission control lines EML located in the display area AA.

[0075] For details, please refer to Figure 14 and Figure 15 By reducing the number of second scan lines S2L connected to the output of the first-stage second shift register unit SRU2 (1) to n, and reducing the number of light emission control lines EML connected to the output of the first-stage third shift register unit SRU (3) to n, the second scan signal received by the compensation module 130 of the pixel circuit row PCR and the light emission control signal received by the light emission control module 150 can be adjusted. This makes the first duration Δt1 of the row PCR of two adjacent pixel circuits the same, the second duration Δt2 of the row PCR of two adjacent pixel circuits the same, the potential consistency of the fourth node N4 is better, and the duration of the light emission element OLED in the row PCR of two adjacent pixel circuits is the same, which helps to improve the display uniformity of the display panel 001. In an optional implementation, n = mj, j < M.

[0076] To more intuitively illustrate the number of scan lines SL connected to the shift register unit SRU, that is, the correspondence between the shift register unit SRU and the pixel circuit row PCR, the embodiments of this application are based on the appendix. Figure 14 and attached Figure 15 The content is provided in Table 6.

[0077] Table 6 shows another type of correspondence between bit register units and pixel circuit rows. refer to Figure 14 , Figure 15According to Table 6, when j=1, m=2, and n=1, in different pixel circuit rows PCR, the difference between the number of stages of the first shift register unit SRU1 connected to the control terminal of the reset module 140 and the number of stages of the second shift register unit SRU2 connected to the control terminal of the compensation module 130 is the same, and the difference between the number of stages of the third shift register unit SRU3 connected to the control terminal of the light emission control module 15 and the number of stages of the first shift register unit SRU1 connected to the control terminal of the reset module 140 is the same. This ensures that the timing relationship between the first scan signal received by the control terminal of the reset module 140 and the second scan signal received by the control terminal of the compensation module 130 remains consistent in different pixel circuit rows, and the timing relationship between the light emission control signal received by the control terminal of the light emission control module 15 and the first scan signal received by the control terminal of the reset module 140 remains consistent. The first duration Δt1 and the second duration Δt2 of the PCR in different pixel circuit rows are the same, which helps to improve the display uniformity of the display panel 001.

[0078] For example, taking the reduction of the number of second scan lines S2L connected to the output of the first-stage second shift register unit SRU2(1) to n, and the reduction of the number of light emission control lines EML connected to the output of the first-stage third shift register unit SRU3(1) to n, when j=1, m=4, n=3. Taking the example that the enable level of the scan drive signal is low, Figure 16 This is a top view schematic diagram of another display panel provided in the embodiments of this application. Figure 17 This is a timing diagram of another display panel provided in the embodiments of this application. To more intuitively show the number of scan lines SL connected to the shift register unit SRU, that is, the correspondence between the shift register unit SRU and the pixel circuit row PCR, the embodiments of this application are based on the appendix... Figure 16 and attached Figure 17 The content is provided in Table 7.

[0079] Table 7 shows another type of correspondence between bit register units and pixel circuit rows. refer to Figure 16 , Figure 17According to Table 7, when j=1, m=4, and n=3, in the first scan driving circuit SDC1, the first shift register unit SRU1 can be electrically connected to the four first scan lines S1L located in the display area AA; in the second scan driving circuit SDC2, the first-stage second shift register unit SRU2(1) can be electrically connected to the three second scan lines S2L located in the display area AA along the second direction Y, and the multi-stage second shift register unit SRU2 can be electrically connected to the four adjacent second scan lines S2L located in the display area AA along the second direction Y; in the third scan driving circuit SDC3, the first-stage third shift register unit SRU3(1) can be electrically connected to the three light emission control lines EML located in the display area AA along the second direction Y, and the multi-stage third shift register unit SRU3 can be electrically connected to the four adjacent light emission control lines EML located in the display area AA along the second direction Y. In this way, the timing relationship between the first scan signal received by the control terminal of the reset module 140 and the second scan signal received by the control terminal of the compensation module 130 can be kept consistent in different pixel circuit rows. The timing relationship between the light emission control signal received by the control terminal of the light emission control module 15 and the first scan signal received by the control terminal of the reset module 140 can also be kept consistent. The first duration Δt1 and the second duration Δt2 of the PCR in different pixel circuit rows are the same, which helps to improve the display uniformity of the display panel 001.

[0080] It is understood that in other implementations, m can also be other positive integers greater than 1, and j can also be other positive integers less than m.

[0081] In another optional embodiment, taking the example that the enable levels of the scan drive signals are all low, Figure 18 This is a top view schematic diagram of another display panel provided in the embodiments of this application. Figure 19 This is a timing diagram of another display panel provided in an embodiment of this application, see reference. Figure 18 and Figure 19 The first-level first shift register unit SRU1 (1) is configured to provide first scan signals to n first scan lines S1L located in the display area AA, and the multi-level first shift register unit SRU1 is configured to provide first scan signals to m first scan lines S1L located in the display area AA.

[0082] For details, please refer to Figure 18 and Figure 19By reducing the number of first scan lines S1L connected to the output of the first shift register unit SRU1 (1) to n, the first scan signal received by the reset module 140 of the pixel circuit row PCR can be adjusted, so that the first duration Δt1 of the adjacent two pixel circuit rows PCR is the same, the second duration Δt2 of the adjacent two pixel circuit rows PCR is the same, the potential of the fourth node N4 is more consistent, and the duration of the light-emitting element OLED in the adjacent two pixel circuit rows PCR is the same, which helps to improve the display uniformity of the display panel 001.

[0083] Furthermore, by reducing the number of first scan lines S1L connected to the output of the first-stage first shift register unit SRU1(1) to n, it is not necessary to reduce the number of second scan lines S2L connected to the output of the first-stage second shift register unit SRU2(1), nor is it necessary to reduce the number of light emission control lines EML connected to the output of the first-stage third shift register unit SRU3(1), which is beneficial to reducing the total number of shift register units SRU; moreover, after reducing the number of first scan lines S1L connected to the output of the first-stage first shift register unit SRU1(1), the number of first scan lines S1L connected to the output of the last-stage first shift register unit SRU1(1) can be increased, compared to Figure 6 The display panel 001 shown is shown. Figure 18 The display panel 001 shown does not increase the total number of shift register units (SRUs), which is beneficial for improving the display uniformity of the display panel 001 while achieving a thinner and lighter display panel 001.

[0084] In an optional implementation, n=j, j<M.

[0085] To more intuitively illustrate the number of scan lines SL connected to the shift register unit SRU, that is, the correspondence between the shift register unit SRU and the pixel circuit row PCR, the embodiments of this application are based on the appendix. Figure 18 and attached Figure 19 The content is provided in Table 8.

[0086] Table 8 shows another type of correspondence between bit register units and pixel circuit rows. refer to Figure 18 , Figure 19According to Table 8, when j=1, m=2, and n=1, in different pixel circuit rows PCR, the difference between the number of stages of the first shift register unit SRU1 connected to the control terminal of the reset module 140 and the number of stages of the second shift register unit SRU2 connected to the control terminal of the compensation module 130 is the same, and the difference between the number of stages of the third shift register unit SRU3 connected to the control terminal of the light emission control module 15 and the number of stages of the first shift register unit SRU1 connected to the control terminal of the reset module 140 is the same. This ensures that the timing relationship between the first scan signal received by the control terminal of the reset module 140 and the second scan signal received by the control terminal of the compensation module 130 remains consistent in different pixel circuit rows, and the timing relationship between the light emission control signal received by the control terminal of the light emission control module 15 and the first scan signal received by the control terminal of the reset module 140 remains consistent. The first duration Δt1 and the second duration Δt2 of the PCR in different pixel circuit rows are the same, which helps to improve the display uniformity of the display panel 001.

[0087] For example, taking the reduction of the number of first scan lines S1L connected to the output of the first shift register unit SRU1(1) to n, when j=1, m=4, n=1. Taking the enable level of the scan drive signal as low as an example, Figure 20 This is a top view schematic diagram of another display panel provided in the embodiments of this application. Figure 21 This is a timing diagram of another display panel provided in the embodiments of this application. To more intuitively show the number of scan lines SL connected to the shift register unit SRU, that is, the correspondence between the shift register unit SRU and the pixel circuit row PCR, the embodiments of this application are based on the appendix... Figure 20 and attached Figure 21 The content provided in Table 9.

[0088] Table 9 shows another type of correspondence between bit register units and pixel circuit rows. refer to Figure 20 , Figure 21According to Table 9, when j=1, m=4, n=1, in the first scan driving circuit SDC1, the first-stage first shift register unit SRU1 (1) can be electrically connected to a first scan line S1L located in the display area AA along the second direction Y, and the multi-stage second shift register unit SRU2 can be electrically connected to four adjacent first scan lines S1L located in the display area AA along the second direction Y; in the second scan driving circuit SDC2, the second shift register unit SRU2 can be electrically connected to four second scan lines S2L located in the display area AA; in the third scan driving circuit SDC3, the third shift register unit SRU3 can be electrically connected to four light emission control lines EML located in the display area AA. In this way, the timing relationship between the first scan signal received by the control terminal of the reset module 140 and the second scan signal received by the control terminal of the compensation module 130 can be kept consistent in different pixel circuit rows. The timing relationship between the light emission control signal received by the control terminal of the light emission control module 15 and the first scan signal received by the control terminal of the reset module 140 can also be kept consistent. The first duration Δt1 and the second duration Δt2 of the PCR in different pixel circuit rows are the same, which helps to improve the display uniformity of the display panel 001.

[0089] It is understood that in other implementations, m can also be other positive integers greater than 1, and j can also be other positive integers less than m. Taking m=4 as an example, regardless of j=1, 2, or 3, along the second direction Y, the first scan signal received by the control terminal of the reset module 140 of the i-th pixel circuit row PCR(i) will be shifted backward by j units compared to the first scan signal received by the control terminal of the initialization module 120 of the i-th pixel circuit row PCR(i). By setting n=j, the first scan signal received by the control terminal of the initialization module 120 of the i-th pixel circuit row PCR(i) can be shifted backward by nj units compared to the second scan signal received by the control terminal of the compensation module 130 of the i-th pixel circuit row PCR(i) and the light emission control signal received by the control terminal of the light emission control module 150 of the i-th pixel circuit row PCR(i). Ultimately, this can make the i-th pixel... The first scan signal received by the control terminal of the reset module 140 of the PCR (i) circuit row is offset by m units compared to the second scan signal received by the control terminal of the compensation module 130. This ensures that the timing relationship between the first scan signal received by the control terminal of the reset module 140 and the second scan signal received by the control terminal of the compensation module 130 remains consistent in different pixel circuit rows. The timing relationship between the light emission control signal received by the control terminal of the light emission control module 15 and the first scan signal received by the control terminal of the reset module 140 remains consistent. The first duration Δt1 and the second duration Δt2 of the PCR in different pixel circuit rows are the same, which helps to improve the display uniformity of the display panel 001.

[0090] Based on the above embodiments, Figure 22 This is a top view schematic diagram of another display panel provided in the embodiments of this application. Figure 23 This is a timing diagram of another display panel provided in an embodiment of this application, see reference. Figure 2 , Figure 22 , Figure 23 The pixel circuit PC also includes a writing module 160, which is coupled to the gate of the driving transistor M3; the scan line SL also includes a third scan line SPL located in the display area; along the second direction Y, the i-th third scan line SPL(i) is electrically connected to the control terminal of the writing module 160 in the i-th pixel circuit row PCR(i); the scan drive signal also includes a third scan signal; the scan drive circuit SDC also includes a fourth scan drive circuit SDC4, which includes a plurality of cascaded fourth shift register units SRU4; the fourth shift register unit SRU4 provides a third scan signal to a pixel circuit row PCR through a third scan line SPL.

[0091] Specifically, the writing module 160 is used to write the data signal on the data line DL to the pixel circuit PC. By setting the fourth shift register unit SRU4 to provide a third scan signal to a pixel circuit row PCR through a third scan line SPL, the third scan signals received by multiple pixel circuit rows PCR arranged along the second direction Y can be shifted sequentially, and the multiple pixel circuit rows PCR can sequentially write the data signal on the data line DL.

[0092] Optional, Figure 24 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. Figure 25 This is a schematic diagram of the layout structure of a pixel circuit provided in an embodiment of this application, with reference to... Figure 24 and Figure 25 The initialization module 120 includes an initialization transistor M5, and the reset module 140 includes a reset transistor M7. In the pixel circuit PC, along the second direction Y, the initialization transistor M5 and the reset transistor M7 are located on opposite sides of the driving transistor M3. Along the second direction Y, the reset transistor M7 in the i-th pixel circuit row PCR(i) and the initialization transistor M5 in the (i+1)-th pixel circuit row PCR(i+1) are arranged along the first direction X.

[0093] For example, continue to refer to Figure 24 and Figure 25The initialization transistor M5 can be a dual-gate transistor (M5-1, M5-2). The first terminal of the initialization transistor M5 is connected to the first reset terminal Vref1. The second terminal of the initialization transistor M5 is connected to the gate of the driving transistor M3 at the first node N1. The gate of the initialization transistor M5 is connected to the first scan line S1L. The first terminal of the reset transistor M7 is connected to the second reset terminal Vref2. The second terminal of the reset transistor M7 is connected to the light-emitting element OLED at the fourth node N4. The gate of the reset transistor M7 is also connected to the first scan line S1L.

[0094] By arranging the reset transistor M7(i) in the i-th pixel circuit row PCR(i) and the initialization transistor M5(i+1) in the (i+1)-th pixel circuit row PCR(i+1) along the second direction Y, the active regions of the reset transistor M7(i) and the initialization transistor M5(i+1) can be arranged along the first direction X. This allows the gates of the reset transistor M7(i) and the initialization transistor M5(i+1) in adjacent pixel circuit rows PCR to reuse the first scan line S1(i) along the (i+1)-th pixel circuit row PCR. +1), that is, along the second direction Y, the first scan line S1 (i+1) can be reused as the gate of the reset transistor M7 (i) and the gate of the initialization transistor M5 (i+1). In this way, when the gate of the reset transistor M7 (i) is connected to the first scan line S1 (i+1) connected to the gate of the initialization transistor M5 (i+1) of the PCR line of other pixel circuits, there is no need to set up additional connecting wires, which helps to reduce the connecting wires of the display area AA and avoids too many connecting wires in the display area AA, which affects the performance and yield of the display panel 001.

[0095] In some embodiments, the compensation module 130 includes a compensation transistor M4, which can be a dual-gate transistor (M4-1, M4-2). The first terminal of the compensation transistor M4 is connected to the first node N1, the second terminal of the compensation transistor M4 is electrically connected to the third node N3, and the gate of the compensation transistor M4 is connected to the second scan line S2L. The light emission control module 150 includes a light emission control transistor M6, the first terminal of the light emission control transistor M6 is connected to the third node N3, the second terminal of the light emission control transistor M6 is connected to the light emission element OLED at the fourth node, and the gate of the light emission control transistor M6 is connected to the light emission control line EML.

[0096] In some embodiments, the pixel circuit PC further includes a writing module 160 and a coupling module 170. The writing module 160 may include a first writing transistor M1 and a second writing transistor M2. The first writing transistor M1 may be a dual-gate transistor (M1-1, M1-2), with its first terminal connected to the third reset terminal Vref3, its second terminal electrically connected to the second node N2, and its gate connected to the second scan line S2L. The gates of the first writing transistor M1 and the compensation transistor M4 in the same pixel circuit PC may be connected to the same second scan line S2L. The second writing transistor M2 may be a dual-gate transistor (M2-1, M2-2), with its first terminal connected to the data line DL, its second terminal electrically connected to the second node N2, and its gate connected to the third scan line SPL. The coupling module 170 includes a first capacitor C1, with its first plate electrically connected to the second node N2 and its second plate electrically connected to the first node N1.

[0097] In some embodiments, the pixel circuit PC further includes a storage module 180, which includes a second capacitor C2. The first plate of the second capacitor C2 is electrically connected to the first power supply terminal PVDD, and the second plate of the second capacitor C2 is electrically connected to the first node N1 or the second node N2.

[0098] It should be noted that, Figure 24 The illustration only shows that all transistors in the pixel circuit PC are P-type transistors. In other embodiments, all transistors in the pixel circuit PC may be N-type transistors, or some may be P-type transistors and some may be N-type transistors. The channel type of the transistors in the pixel circuit PC can be set according to actual needs.

[0099] Optional, Figure 26 This is a top view structural diagram of another display panel provided in an embodiment of this application, with reference to... Figure 25 and Figure 26 The display panel 001 also includes virtual lines FL, which extend along the first direction X; in the partial scan drive circuit SDC, the output of the first-level shift register unit SRU (1) is connected to n scan lines SL located in the display area AA, and the output of the first-level shift register unit SRU (1) is also connected to mn virtual lines FL, and the output of the multi-level shift register unit SRU is connected to m scan lines SL located in the display area.

[0100] The virtual line FL can be located in the display area AA or in the non-display area NA. The virtual line FL is a trace that is not directly electrically connected to the pixel circuit PCR located in the display area AA. In some embodiments, some virtual lines FL can be indirectly electrically connected to the pixel circuit PCR located in the display area AA through the scan line SL.

[0101] For example, taking m=2 and n=1 as an example, refer to... Figure 26 In the first scan drive circuit SDC1, the output terminal of the first-stage first shift register unit SRU1 (1) is connected to a first scan line S1L located in the display area AA, and the output terminal of the first-stage first shift register unit SRU1 (1) is also connected to a virtual line FL; the output terminals of the multi-stage first shift register units SRU1 are connected to two scan lines SL located in the display area AA, and the output terminals of these first shift register units SRU1 connected to the two scan lines SL are not connected to the virtual line FL.

[0102] When the number of scan lines SL connected to the output terminal of the first-stage shift register unit SRU (1) is less than m, the output terminal of the first-stage shift register unit SRU (1) is connected to a virtual line FL so that the sum of the number of scan lines SL connected to the output terminal of the first-stage shift register unit SRU (1) and the virtual line FL is m. This is beneficial to balance the load of the output terminal of the first-stage shift register unit SRU (1) and the output terminals of other-stage shift register units SRU, so that the scan drive signal output by the output terminal of the first-stage shift register unit SRU (1) is more consistent with the scan drive signal output by the output terminals of other-stage shift register units SRU.

[0103] In other embodiments, when the number of scan lines SL connected to the output of the last stage shift register unit SRU is less than m, the output of the last stage shift register unit SRU may also be connected to a virtual line FL, so that the sum of the number of scan lines SL connected to the output of the last stage shift register unit SRU and the virtual line FL is m.

[0104] In some implementations, when the virtual line FL is located in the non-display area NA, a virtual pixel circuit row can also be set in the non-display area NA, and the virtual line FL can be electrically connected to the virtual pixel circuit row. Figure 26 (not shown in the image) to further reduce the load difference at the output of different shift register units (SRUs).

[0105] In some implementations, when the virtual line FL is located in the display area AA, the virtual line FL can be set on a different layer from the scan line SL; in some implementations, when the virtual line FL is located in the display area AA, the virtual line FL can also be set on the same layer as the scan line SL. This application does not specifically limit this.

[0106] Based on the same inventive concept, embodiments of this application also provide a display device. Figure 27 This is a schematic diagram of the structure of a display device provided in an embodiment of this application, such as... Figure 27 The display device 002 includes the display panel 001 provided in any embodiment of this application. The display device 002 provided in the embodiments of this application can be... Figure 27 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, in-vehicle display, medical device, industrial control equipment, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0107] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: Multiple pixel circuits located in the display area; The plurality of pixel circuits arranged along a first direction constitute a pixel circuit row, and the plurality of pixel circuit rows are arranged along a second direction, wherein the first direction and the second direction intersect. The pixel circuit includes a driving module, an initialization module, a compensation module, a reset module, a light emission control module, and a light emission element. The driving module includes a driving transistor. The initialization module and the compensation module are both electrically connected to the gate of the driving transistor, and the compensation module is also electrically connected to the light emission control module. The reset module and the light emission control module are both electrically connected to the light emission element. The display panel further includes multiple scan lines for transmitting scan drive signals; the scan lines include a first scan line, a second scan line, and a light emission control line located in the display area; along the second direction, the i-th first scan line is electrically connected to the control terminal of the initialization module in the i-th pixel circuit row, the i-th second scan line is electrically connected to the control terminal of the compensation module in the i-th pixel circuit row, the i-th light emission control line is electrically connected to the control terminal of the light emission control module in the i-th pixel circuit row, and the (i+j)-th first scan line is also electrically connected to the control terminal of the reset module in the i-th pixel circuit row, where i and j are both positive integers; The display panel further includes multiple scan driving circuits, which are electrically connected to the first scan line, the second scan line, and the light emission control line, respectively. Each scan driving circuit includes multiple cascaded shift register units. In some of the scan driving circuits, the first-stage shift register unit is configured to provide the scan driving signal to n scan lines located in the display area, and the multi-stage shift register units are configured to provide the scan driving signal to m scan lines located in the display area, where m > n, and m and n are both positive integers.

2. The display panel according to claim 1, characterized in that, Part of the scan drive circuit includes z cascaded shift register units; The first-level shift register unit is configured to provide the scan drive signal to the n scan lines located in the display area; The shift register units from the second level to the z-1th level are all configured to provide the scan drive signal to the m scan lines located in the display area.

3. The display panel according to claim 1, characterized in that, Along the second direction, in the refresh cycle of the i-th pixel circuit row: Along the second direction, the scan drive signal transmitted by the i-th second scan line includes a first voltage edge, which is switched from the enable level of the compensation module to the disable level. Along the second direction, the scan drive signal transmitted by the i-th light-emitting control line includes a second voltage edge, which is switched from the enable level of the light-emitting control module to the disable level. Along the second direction, the scan drive signal transmitted by the (i+j)th first scan line includes a third voltage edge and a fourth voltage edge; the third voltage edge transitions from the disabled level of the reset module to the enabled level, and the fourth voltage edge transitions from the enabled level of the reset module to the disabled level. The first voltage edge and the fourth voltage edge are spaced apart for a first duration, and the second voltage edge and the third voltage edge are spaced apart for a second duration; In two adjacent pixel circuit rows, the first duration is the same, and / or the second duration is the same.

4. The display panel according to claim 1, characterized in that, The scanning drive signal includes a first scanning signal, a second scanning signal, and a light emission control signal; The scan driving circuit includes a first scan driving circuit, a second scan driving circuit, and a third scan driving circuit; the first scan driving circuit includes a plurality of cascaded first shift register units, the second scan driving circuit includes a plurality of cascaded second shift register units, and the third scan driving circuit includes a plurality of cascaded third shift register units. At least a portion of the first shift register units provide the first scan signal to the plurality of pixel circuit rows through multiple first scan lines; at least a portion of the second scan drive circuits provide the second scan signal to the plurality of pixel circuit rows through multiple second scan lines; and at least a portion of the third scan drive circuits provide the light emission control signal to the plurality of pixel circuit rows through multiple light emission control lines.

5. The display panel according to claim 4, characterized in that, The first-level second shift register unit is configured to provide the second scan signal to n second scan lines located in the display area, and the multi-level second shift register unit is configured to provide the second scan signal to m second scan lines located in the display area.

6. The display panel according to claim 5, characterized in that, n = mj, j < M.

7. The display panel according to claim 6, characterized in that, j=1, m=2, n=1.

8. The display panel according to claim 4, characterized in that, The first-level third shift register unit is configured to provide the light emission control signal to n light emission control lines located in the display area; the multi-level third shift register unit is configured to provide the light emission control signal to m light emission control lines located in the display area.

9. The display panel according to claim 8, characterized in that, n = mj, j < M.

10. The display panel according to claim 9, characterized in that, j=1, m=2, n=1.

11. The display panel according to claim 4, characterized in that, The first-stage second shift register unit is configured to provide the second scan signal to n second scan lines located in the display area, and the multi-stage second shift register unit is configured to provide the second scan signal to m second scan lines located in the display area; The first-level third shift register unit is configured to provide the light emission control signal to n light emission control lines located in the display area, and the multi-level third shift register unit is configured to provide the light emission control signal to m light emission control lines located in the display area.

12. The display panel according to claim 11, characterized in that, j=1, m=2, n=1.

13. The display panel according to claim 4, characterized in that, The first-level first shift register unit is configured to provide the first scan signal to n first scan lines located in the display area, and the multi-level first shift register unit is configured to provide the first scan signal to m first scan lines located in the display area.

14. The display panel according to claim 13, characterized in that, n=j, j<M.

15. The display panel according to claim 14, characterized in that, j=1, m=2, n=1.

16. The display panel according to claim 4, characterized in that, The pixel circuit further includes a writing module, which is coupled to the gate of the driving transistor. The scan line also includes a third scan line located in the display area; along the second direction, the i-th third scan line is electrically connected to the control terminal of the writing module in the i-th pixel circuit row; The scan drive signal also includes a third scan signal; The scan driving circuit further includes a fourth scan driving circuit, which includes a plurality of cascaded fourth shift register units; the fourth shift register units provide the third scan signal to a pixel circuit row through a third scan line.

17. The display panel according to claim 1, characterized in that, The initialization module includes an initialization transistor, and the reset module includes a reset transistor; In the pixel circuit, along the second direction, the initialization transistor and the reset transistor are located on opposite sides of the driving transistor; Along the second direction, the reset transistor in the i-th pixel circuit row and the initialization transistor in the (i+1)-th pixel circuit row are arranged along the first direction.

18. The display panel according to claim 1, characterized in that, The display panel further includes virtual lines; the virtual lines extend along the first direction; In some of the scanning drive circuits, the output terminal of the first-stage shift register unit is connected to n scan lines located in the display area, and the output terminal of the first-stage shift register unit is also connected to mn virtual lines. The output terminals of the multi-stage shift register units are connected to m scan lines located in the display area.

19. A display device, characterized in that, include: The display panel according to any one of claims 1-18.

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