Micro-led display circuit, display panel and display device

Abstract

The application provides a Micro-LED display circuit, a display panel and a display device. The control module in the display circuit is configured to adjust the driving current output by the digital-to-analog conversion module according to the brightness requirement in a single configuration period, so as to adapt to the target current requirement of different display contents. Before the target current requirement is adapted, the control module controls the timing of the driving current output by the digital-to-analog conversion module, so as to provide a dynamically adjustable overshoot current for the pixel unit, and the pixel unit is quickly stabilized to the target current, thereby ensuring the overall consistency of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a Micro-LED display circuit, display panel and display device. Background Technology

[0002] In some electronic device display panels, light-emitting devices such as micro light-emitting diodes (Micro-LEDs) are arranged in rows and columns to form a basic display structure. Each light-emitting device is connected to a corresponding pixel circuit, which is used to control the light-emitting device to emit light.

[0003] In existing technology, a drive current generating module in the pixel circuit provides drive current to the pixel unit, causing the light-emitting device in the pixel unit to emit light based on the drive current. However, because different pixel units respond to the drive current at different speeds, even in the same display panel, the power-on rate of the drive circuit at different positions of the light-emitting device will have certain differences at the moment of emission, thus affecting the power-on consistency of the light-emitting device and consequently affecting the display effect.

[0004] Therefore, how to improve the response speed of pixel units to driving current in order to ensure the consistency of light-emitting devices in display panels is a technical problem that needs to be solved in this field. Summary of the Invention

[0005] This application provides a Micro-LED display circuit, display panel, and display device. By providing overshoot current, the response speed of pixel units to driving current is improved, thereby ensuring the consistency of light-emitting devices in the display panel.

[0006] This application provides a Micro-LED display circuit, comprising: a pixel array including a plurality of pixel units arranged in rows and columns, each pixel unit including a driving transistor, a light-emitting device, and a switching transistor connected between the driving transistor and the light-emitting device, the switching transistor being used to receive a pulse width modulation signal to control the light emission duration; a driving current generation module disposed outside the pixel array and electrically connected to the pixel units, the driving current generation module including a reference current module and a digital-to-analog converter module, used to generate a multi-level adjustable driving current; and a control module disposed outside the pixel array and electrically connected to the driving current generation module, the control module being used to adjust the driving current output by the digital-to-analog converter module according to brightness requirements within a single configuration cycle to adapt to the target current requirements of different display content; and, before adapting to the target current requirements, controlling the driving current output by the digital-to-analog converter module through a control timing to provide a dynamically adjustable overshoot current to the pixel units, so that the pixel units quickly stabilize to the target current.

[0007] A second aspect of this application provides a display panel, including the display circuitry provided in the first aspect of this application.

[0008] A third aspect of this application provides a display device, including a display panel as provided in the second aspect of this application.

[0009] In summary, the Micro-LED display circuit, display panel, and display device provided in this application have a control module in the display circuit that adjusts the drive current output by the digital-to-analog converter module according to the brightness requirements within a single configuration cycle to adapt to the target current requirements of different display content. Before adapting to the target current requirements, the control module controls the drive current output by the digital-to-analog converter module through timing control to provide dynamically adjustable overshoot current to the pixel unit. This greatly improves the charging rate of the capacitor in the pixel unit, shortens the stabilization time of the pixel unit driving the light-emitting device to emit light, and improves the response speed of the pixel unit to the drive current. This significantly reduces the charging delay difference caused by load differences or switching timing, thereby ensuring the overall power-on rate and light emission consistency of the display panel in the full panel. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of the structure of an embodiment of the display circuit provided in this application;

[0012] Figure 2 A schematic diagram of the structure of an embodiment of the display circuit provided in this application;

[0013] Figure 3 A schematic diagram of the circuit structure of an embodiment of the display circuit provided in this application;

[0014] Figure 4 A schematic diagram of another embodiment of the display circuit provided in this application;

[0015] Figure 5 A schematic diagram of the circuit structure of an embodiment of the display circuit provided in this application;

[0016] Figure 6 A schematic diagram of the structure of an embodiment of the display panel provided in this application;

[0017] Figure 7This application provides a schematic diagram of the structure of a pixel unit;

[0018] Figure 8 A schematic diagram of the current values ​​for the drive current provided in this application;

[0019] Figure 9 A schematic diagram of the circuit structure of an embodiment of the display panel provided in this application;

[0020] Figure 10 A schematic diagram of the circuit structure of another embodiment of the display panel provided in this application;

[0021] Figure 11 A schematic diagram of the structure of an embodiment of the control module provided in this application;

[0022] Figure 12 This is a flowchart illustrating a method for calibrating the brightness of a display panel. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] Figure 1 A schematic diagram of the structure of an embodiment of the display circuit provided in this application is shown below. Figure 1 The display circuit shown can be applied to the display panel of electronic devices with relevant display requirements, such as mobile phones, tablets, desktop computers, or televisions. The display circuit includes multiple pixel units 12 arranged in rows and columns, each pixel unit 12 including a corresponding light-emitting device. Figure 1In the example described, the display circuit includes a total of 9 pixel units 12 arranged in 3 rows and 3 columns. These 3 rows and 3 columns of pixel units 12 constitute a pixel array.

[0026] like Figure 1 The display circuit shown also includes a control module 11 and at least one drive current generating module 13. The control module 11 can control at least one drive current generating module 13 to provide drive current to the pixel units 12 in the pixel array. Both the control module 11 and the drive current generating module 13 are located outside the pixel array. The control module 11 is electrically connected to the drive current generating module 132, and the drive current generating module 132 is electrically connected to the pixel units 12 in the pixel array.

[0027] In one embodiment, such as Figure 1 The display circuit shown can be equipped with multiple drive current generating modules 13, each of which corresponds to a pixel unit 12. The drive current generated by each drive current generating module 13 is sent to the corresponding pixel unit 12.

[0028] In another embodiment, a drive current generating module 13 can also provide drive current to multiple pixel units 12. For example, a drive current generating module 13 can send drive current to a row of pixel units 12, or a drive current generating module 13 can send drive current to all pixel units 12 in a column, or a drive current generating module 13 can provide drive current to all multiple pixel units 12 on the display panel 1, etc.

[0029] Specifically, Figure 2 A schematic diagram of the structure of an embodiment of the display circuit provided in this application is shown below. Figure 2 The display circuit shown includes a drive current generating module 13, and the control module 11 can be used to control the drive current generating module 13 to provide drive current to the pixel units 12 in the pixel array. More specifically, Figure 3 A schematic diagram of the circuit structure of an embodiment of the display circuit provided in this application is shown below. Figure 3 In the display panel shown, taking a pixel array consisting of 9 pixel units 12 arranged in 3 rows and 3 columns as an example, a drive current generating module 13 provides drive current to the 9 pixel units 12 in the pixel array.

[0030] Figure 4 A schematic diagram of another embodiment of the display circuit provided in this application is shown below. Figure 4 The display circuit shown includes multiple drive current generating modules 13. The control module 11 can be used to control the multiple drive current generating modules 13 to provide drive current to the corresponding pixel units 12 in the pixel array.

[0031] More specifically, Figure 5 A schematic diagram of the circuit structure of an embodiment of the display circuit provided in this application is shown below. Figure 3 In the display panel shown, taking a pixel array comprising nine pixel units 12 arranged in 3 rows and 3 columns as an example, the control module 11 can be used to control three drive current generating modules 13 respectively, so that each drive current generating module 13 provides drive current to one row of pixel units 12 in the pixel array. Alternatively, the control module 11 can be used to control three drive current generating modules 13 respectively, so that each drive current generating module 13 provides drive current to one column of pixel units 12 in the pixel array.

[0032] When the display panel adopts such Figure 4 or Figure 5 When the driving current generating module 13 and pixel unit 12 are arranged as shown, the display panel has the following technical effects: First, the driving current generating module 13 can be placed entirely outside the AA area where the light-emitting device 123 is located, without occupying the area of ​​the AA area. Second, by having multiple pixel units 12 share the driving current generating module 13, the number of devices generating driving current is simplified, thereby reducing the area of ​​the driving current generating module 13 and the area of ​​the display circuit in which it is located. Third, by having multiple pixel units 12 jointly realize the conversion of transistor gate potential based on the same driving current generating module 13, it is beneficial to the consistency of potential between different pixel units 12, thereby ensuring the overall display stability of the display panel.

[0033] Furthermore, Figure 6 A schematic diagram of the structure of an embodiment of the display panel provided in this application is shown below. Figure 6 The embodiments shown can be applied to, for example Figure 1 In the display panel shown, as Figure 6 The display panel shown includes: pixel unit 12, drive current generation module 13 and control module 11.

[0034] Specifically, in such Figure 6 In the example shown, taking any pixel unit 12 in the pixel array as an example, the pixel unit 12 includes a driving transistor 121, a light-emitting device 123, and a switching transistor 122 connected between the driving transistor 121 and the light-emitting device 123. The switching transistor 122 can be used to receive the pulse width modulation signal EM sent by the control module 11 to control the light emission duration of the light-emitting device 123.

[0035] In this application Figure 6 Based on the illustrated embodiment, Figure 7 A schematic diagram of a pixel unit structure provided in this application is shown below. Figure 7 The driving circuit shown can be applied to, for example Figure 1 or Figure 2 The display panel shown shows... Figure 6 This describes a specific circuit implementation of the pixel unit 12 provided in the document. For example... Figure 7 The pixel unit 12 shown includes a driving transistor T2, a switching transistor T3, and a capacitor Cst. The driving current generation module 13 includes an equivalent control transistor Tshare, which is connected to the driving transistor T2 and forms a current mirror, so that the driving transistor T2 can be used to replicate the driving current generated by the driving current generation module 13 to improve the current uniformity of the pixel circuit 12.

[0036] In some embodiments, the Tshare tube can be composed of a digital-to-analog conversion module and a proportional adjustment module, or it can be composed of only a proportional adjustment module. The specific design depends on actual needs and will not be elaborated here.

[0037] Specifically, the control terminal of the driving transistor T2 is connected to the second terminal of the capacitor Cst. Both the first terminal of the driving transistor T2 and the second terminal of the capacitor Cst are connected to the second voltage source ELVDD. The second terminal of the driving transistor T2 is connected to the corresponding light-emitting device 11 via the switching transistor T3. The switching transistor T3 can be used to receive the pulse width modulation signal EM sent by the control module 11 to control the light-emitting duration of the light-emitting device 123. Furthermore, it should be noted that... Figure 7 The structure of the pixel unit 12 shown is 2T1C as an example. The pixel unit 12 can also be implemented in other ways, such as including other numbers of capacitors and transistors.

[0038] like Figure 6 As shown, the drive current generation module 13 provided in this embodiment includes a reference current generation module 131 and a digital-to-analog conversion module 132. The reference current generation module 131 and the digital-to-analog conversion module 132 are connected in sequence. The reference current generation module 131 is used to generate a reference current Iin and send the reference current Iin to the digital-to-analog conversion module 132.

[0039] In one embodiment, the reference current generation module 131 provided in this application can be implemented through a bandgap reference current generation circuit or an external input current source, and is used to provide a stable reference current Iin for use by the digital-to-analog conversion module 132 and the proportional adjustment module 133, thereby ensuring that the generated reference current Iin has a more stable PVT characteristic, ensuring the stability of the drive current output to the pixel unit 12, and thus ensuring the stability of the drive voltage received by the pixel unit 12. In addition, to better take into account the PVT characteristics, the reference current generation module 131 can also be designed to ensure the output of the reference current Iin by adopting a stepped coverage method.

[0040] In one embodiment, a current level modulation mapping relationship is established between the digital-to-analog converter module 132 and the proportional adjustment module 133 based on brightness requirements. Specifically, the control module 11 can be used to adjust the information input to the digital-to-analog converter module 132 and the proportional adjustment module 133 according to the brightness requirements and the current level modulation mapping relationship, so as to generate a dynamically adjustable driving current based on the reference current Iin and output it to the pixel unit 12, thereby achieving brightness control of the light-emitting device 123. In one embodiment, the control module includes a one-time programmable (OTP) memory for storing the current level modulation mapping relationship.

[0041] The digital-to-analog converter module 132 and the reference current generation module 131 constitute a current mirror circuit. The control module 11 controls the number of bits output to the digital-to-analog converter module 132 based on brightness requirements and current level modulation mapping, thereby controlling the number of current branches in the digital-to-analog converter module 132 that are active. The control module 11 also dynamically adjusts the current based on the reference current generation range to meet the drive current margin. Furthermore, the control module 11 controls the drive current generation module 13 to adjust the drive current output by the digital-to-analog converter module 132 within a single configuration cycle according to brightness requirements, adapting to the target current requirements of different display content.

[0042] In one embodiment, the proportional adjustment module 133 is electrically connected to the digital-to-analog converter module 132 and is used to perform secondary modulation on the intermediate current output by the digital-to-analog converter module to form a multi-level adjustable drive current to adapt to different brightness requirements.

[0043] Furthermore, considering the different switching rates of the pixel units 12 and the presence of RC loading in the circuit, even in the same display panel 1, the power-on rate of the pixel units 12 will be different at the same light-emitting moment when the light-emitting devices 123 at different locations are emitting light.

[0044] Therefore, in order to address the problem that the pixel unit 12 has a slow response speed to the driving current, the control module in the pixel circuit 12 provided in this application can also improve the response speed of the pixel unit 12 to the driving current by controlling the driving current generation module 13 to provide the driving current to the pixel unit 12, so as to ensure the consistency of the light-emitting devices in the display panel 1.

[0045] In one embodiment, the current generated by the drive current generation module 13 is provided in a local current manner or in a global current manner, thereby enabling the light-emitting devices 123 of the pixel units 12 in the pixel array to light up row by row or globally, in order to optimize power consumption.

[0046] Specifically, the control module 11 provided in this embodiment is used to control the driving current output by the digital-to-analog converter module 132 by controlling the timing before adapting to the target current requirement, so as to provide the pixel unit 12 with a dynamically adjustable overshoot current. The overshoot current refers to the overdrive current that is instantaneously higher than the current setting value of the actual driving current required by the light-emitting device 123, so as to improve the response speed of the pixel unit 12 and make the pixel unit 12 stabilize to the target current more quickly.

[0047] In one embodiment, the dynamically adjustable overshoot current specifically includes: a first overshoot current in a first stage and a second overshoot current in a second stage, wherein the first overshoot current is greater than the second overshoot current. Alternatively, the dynamically adjustable overshoot current specifically includes: a third overshoot current maintained within the timing control range.

[0048] For example, Figure 8 The diagram illustrates the current value of the driving current provided in this application. When the control module 11 controls the driving current generating module 13 to provide the driving current Iref to the pixel unit 12 for a period of t1-t2, and the target current value of the driving current Iref is Itarget, then the control module 11 can control the driving current generating module 13 to provide a sustained third overshoot current to the pixel unit 12 within the timing control range t1-t3 of the power-on phase of the pixel unit 12 between t1-t2. The value of the third overshoot current is greater than the required target driving current value Itarget. Figure 8 In the example shown, the overcharge current values ​​are I1>I2>I3>I4>Itarget, and the timing control range of overcharge current I1 is t1-t31, the timing control range of overcharge current I2 is t1-t32, the timing control range of overcharge current I3 is t1-t33, and the timing control range of overcharge current I4 is t1-t34.

[0049] More specifically, based on the relationship between charge Q and current I, time T, voltage V, and capacitance C as Q=IT=CV, when Q is constant, T can be shortened by increasing the value of I. Therefore, when the driving current value Itarget is constant, the gate voltage Vg of the driving transistor T2 in the corresponding pixel unit 12 is V_target. Since the load corresponding to each light-emitting device 123 is constant after its position is determined, the control module 11 controls the driving current generation module 13 to generate overshoot currents I1 / I2 / I3 / I4 for charging. The settling times to reach Vg=V_target are t31, t32, t33, and t34, respectively. Since I1>I2>I3>I4>Itarget, when Itarget and V_target are constant, t31... <t32<t33<t34。

[0050] In addition, such as Figure 8 The overdrive current value and overdrive duration shown can be adjusted according to different voltage requirements to achieve more flexible applications. For example, the overdrive current can also be provided in a stepped manner, where the first overdrive current value is I1 in the first stage between t1 and t31, and the second overdrive current value is I2 in the second stage between t31 and t32, and the first overdrive current value I1 is greater than the second overdrive current value I2.

[0051] In summary, from Figure 8 It can be seen that when the control module 11 controls the drive current generation module 13 to provide a dynamically adjustable overshoot current to the pixel circuit 12, and then reduces the current value of the drive current to the target current after stabilization, the charging rate of the capacitor in the pixel unit 12 is greatly improved, the stabilization time of the pixel unit 12 driving the light-emitting device 123 to emit light is shortened, and the response speed of the pixel unit 12 to the drive current is improved. This greatly shortens the charging delay difference caused by load differences or switching timing, thereby ensuring the overall power-on rate and light emission consistency of the display panel 1 in the Full Panel.

[0052] In one specific implementation, the proportional adjustment module 133 and the digital-to-analog converter module 132 constitute a current mirror circuit. The control module 11 is then used to select combinations of different current branches in the proportional adjustment module 133 according to the brightness requirements and the current level modulation mapping relationship, so as to output a current with a corresponding proportion based on the current output by the digital-to-analog converter module 133. The specific implementation of the digital-to-analog converter module 132 and the proportional adjustment module 133 provided in this application will be described below with reference to the accompanying drawings.

[0053] Figure 9 A circuit structure diagram of an embodiment of the display panel provided in this application is shown below. Figure 9 As shown Figure 1 The above describes a specific circuit implementation of the digital-to-analog conversion module 132 and the proportional adjustment module 133 in the drive current generation module 13 of the display panel shown.

[0054] The digital-to-analog converter module 132 includes: a first transistor, at least two second transistors, and at least one first switch. (In the context of...) Figure 9 In the example shown, the first transistor, at least two second transistors, and the third switch are all NMOS transistors. Specifically, the drive current generation module 13 optimizes the output drive current through a P / N current mirror structure to improve the stability of the drive current modulation.

[0055] The first transistor is connected to the reference current generation module 131 and is used to receive the reference current Iin provided by the reference current generation module 131. At least two second transistors form current mirror structures with the first transistor to replicate the reference current Iin. The at least two second transistors include one normally open second transistor and at least one non-open second transistor, and at least one first switch is used to adjust the operating state of the at least one non-open second transistor.

[0056] Specifically, such as Figure 9 The first transistor N_lin is shown with its first terminal (drain) and control terminal (gate) connected to the reference current generation module 131. Both the drain and gate are used to receive the reference current Iin. The second terminal (source) of the first transistor N_lin is grounded. The first terminal (drain) of the normally open second transistor Nk is connected to the proportional adjustment module 133. The control terminal (gate) of the normally open second transistor Nk is connected to the reference current generation module 131 to receive the reference current Iin. The second terminal (source) of the normally open second transistor Nk is grounded. The non-open second transistors include N0, N1...N(k-1), where the first switches corresponding to the non-open second transistors are denoted as b0, b1...b(k-1). The first terminal (drain) of each non-open second transistor is connected to the proportional adjustment module 133 through a corresponding first switch. The control terminal (gate) of each non-open second transistor is connected to the reference current generation module 131 to receive the reference current Iin. The second terminal (source) of each non-open second transistor is grounded.

[0057] The control module 11 can be used to control the switching states of the first switches b0, b1...b(k-1) according to the current level modulation mapping relationship, so as to adjust the working state of the non-open second transistors N0, N1...N(k-1), thereby generating a multi-level adjustable drive current and providing dynamic current margin for the drive current.

[0058] In one embodiment, the aspect ratio of the normally open second transistor and the aspect ratio of the non-open second transistor are both multiples of a first preset value. Simultaneously, the aspect ratio of the k-th non-open second transistor to the first transistor is twice the first preset value. （k-1） Times. For example, in Figure 9 In the example shown, let the first preset value be y. Then the width-to-length ratio of the first transistor is a times y, i.e., ay; the width-to-length ratio of the normally open second transistor is b times y, i.e., by. The width-to-length ratios of the k normally open second transistors N0, N1...N(k-1) are respectively: 1y, 2y, ... 2y. （k-1） y.

[0059] In specific implementations, such as Figure 9The circuit structure of the digital-to-analog converter module 132 shown can also be referred to as a k-bit DAC current modulation circuit, which can generate and output an intermediate current Idac based on the reference current Iin. Furthermore, the current value of the intermediate current Idac generated by the digital-to-analog converter module 132 has a certain margin compared to the current setting value Itarget of the drive current required by the light-emitting device 123. For example, as... Figure 9 The digital-to-analog converter module 132 shown can output an intermediate current Idac with a current value between (b / a)*Iin and [(b+1+2+……+2(k-1)) / a]*Iin. This range of current values ​​is recorded as the preset current range.

[0060] In one embodiment, for the digital-to-analog converter module 132, the current value of the intermediate current Idac output by the digital-to-analog converter module 132 can be adjusted to different preset current ranges by adjusting the number of bits k and / or adjusting the width-to-length ratio of the transistor.

[0061] The proportional adjustment module 133 includes at least two third transistors and at least one second switch. Figure 9 In the example shown, at least two of the third transistors are PMOS transistors. These at least two third transistors are used to receive the intermediate current Idac provided by the digital-to-analog converter module 132 and output the intermediate current Idac to form a multi-level adjustable drive current Iref. The at least two third transistors include one normally open third transistor and at least one constantly open third transistor, and at least one second switch is used to adjust the operating state of the at least one constantly open third transistor. The at least two third transistors in the proportional adjustment module 133 can be equivalent to... Figure 7 The control transistor Tshare shown has at least two third transistors connected to the driving transistor T2 in the pixel unit 12 to form a current mirror, so that the driving transistor T2 in the pixel unit 12 replicates the multi-level adjustable driving current Iref generated by the driving current generation module 13.

[0062] Specifically, Figure 9The array contains at least two third transistors, designated P0, P1, P2...Pj (j+1 in total), and at least one second switch, designated s1, s2...sj, corresponding to at least one normally open third transistor P1, P2...Pj. The first terminal (source) of the normally open third transistor P0 is connected to a first voltage source, and its control terminal (gate) is connected to a pixel unit 12 in the pixel array, used to output a drive current Iref to the pixel unit 12, forming the drive voltage G received by the pixel unit 12. The second terminal (drain) of the normally open third transistor P0 is connected to a digital-to-analog converter module 132, used to receive an intermediate current Idac. The first terminal (source) of each normally open third transistor is connected to the first voltage source, the control terminal (gate) of each normally open third transistor is connected to a pixel unit 12 in the pixel array through a corresponding second switch, and the second terminal (drain) of each normally open third transistor is connected to the digital-to-analog converter module 132.

[0063] The control module 11 can be used to control the switching states of the second switches s1, s2...sj according to the current level modulation mapping relationship, so as to adjust the working state of the non-open third transistors P1, P2...Pj, so as to perform secondary modulation of the drive current proportionally.

[0064] In one embodiment, the aspect ratio of both the normally open third transistor and at least one non-open third transistor is a multiple of a second preset value. For example, in Figure 9 In the example shown, let the second preset value be x. Then the width-to-length ratio of the normally open third transistor P0 is x, and the width-to-length ratios of the j non-open third transistors are cx, dx, ..., ex, respectively.

[0065] In specific implementations, such as Figure 9 The proportional adjustment module 133 shown achieves different current distribution outputs by selecting different combinations of j branches, thereby adjusting the current value of the drive current Iref.

[0066] In one embodiment, for the proportional adjustment module 133, the ratio of the drive current Iref output by the proportional adjustment module 133 to the received intermediate current Idac can be adjusted to a different preset current adjustment ratio by adjusting the number of branches j and / or adjusting the width-to-length ratio of the switching transistor.

[0067] In the initial stage of light emission, the control module 11 is specifically used to control the switching state of the second switches s1, s2...sj by adjusting the bit number information input to the digital-to-analog converter module 133, so as to adjust the working state of the non-open third transistors P1, P2...Pj, thereby adjusting the overdrive current provided to the digital-to-analog converter module 133 at a moment higher than the target drive current setting value, so as to improve the response speed of the pixel circuit.

[0068] For example, Figure 10 A schematic diagram of the circuit structure of another embodiment of the display panel provided in this application is shown below. Figure 10 As shown Figure 9 The specific circuit implementation in the display panel 1 shown, where the parameters set in the digital-to-analog conversion module 132 and the proportional adjustment module 133 are k=4, j=2, a=50, b=45, c=2, and d=5, is as follows: The width-to-length ratio of the first transistor N_Iin to the normally open second transistor N0 (minimum bit) is 50:1, and the width-to-length ratio of the normally open second transistor N5 to the first transistor N_Iin is 45:50.

[0069] The reference current Iin generated by the reference current generation module 131 is 2uA. When all the first switches b0, b1, b2, and b3 in the digital-to-analog converter module 132 are in the off state, the adjustable drive current Idac obtained by the digital-to-analog converter module 132 based on the reference current Iin is Idac_min = (45 / 50)*2uA = 1.8uA. When all the first switches b0, b1, b2, and b3 in the digital-to-analog converter module 132 are in the on state, the intermediate current Idac obtained by the digital-to-analog converter module 132 based on the reference current Iin is Idac_max = [(45+1+2+4+8) / 50]*2uA = 2.4uA. Therefore, as... Figure 10 The preset range of the intermediate current Idac of the digital-to-analog converter module 132 after adjustment is between 1.8uA and 2.4uA.

[0070] For the proportional adjustment module 133, when both the second switches s1 and s2 are in the open state, the ratio of the intermediate current Idac input to the proportional adjustment module 133 to the current value of the multi-level adjustable drive current Iref is 1 (P0):1, and the current range of the multi-level adjustable drive current Iref is 1.8uA-2.4uA. When the second switch s1 is in the on state and the second switch s2 is in the open state, the ratio of the intermediate current Idac input to the proportional adjustment module 133 to the current value of the multi-level adjustable drive current Iref is 3 (P0+P1):1, and the current range of the multi-level adjustable drive current Iref is 0.6uA~0.8uA. When the second switch s1 is in the open state and the second switch s2 is in the closed state, the ratio of the intermediate current Idac input to the proportional adjustment module 133 to the current value of the multi-level adjustable drive current Iref is 6 (P2+P0):1, and the current range of the corresponding drive current Iref is 0.3uA~0.4uA. When both the first switches s1 and s2 are in the closed state, the ratio of the intermediate current Idac input to the proportional adjustment module 133 to the current value of the multi-level adjustable drive current Iref is 8 (P2+P1+P0):1, and the current range of the corresponding multi-level adjustable drive current Iref is 0.225uA~0.3uA.

[0071] Figure 11 A schematic diagram of the structure of an embodiment of the control module provided in this application is shown below. Figure 11 This illustrates a specific implementation of the control module 11.

[0072] In one embodiment, such as Figure 11 The control module 11 shown includes: a control unit 100 and an OTP memory 101.

[0073] The OTP memory 101 is used to store the current range modulation mapping relationship. Specifically, the OTP memory 101 can write and store the current setting value of the intermediate current Idac output by the digital-to-analog converter module 132 corresponding to each current range in the multi-range using Code form information. This allows the OPT circuit to subsequently look up the current range modulation mapping relationship in the form as needed and match the current setting value of the corresponding current range.

[0074] The control unit 100 is connected to the OTP memory 101. The control unit 100 can obtain the current level modulation mapping relationship through the OTP memory 101, and according to the current setting value corresponding to the target current level in the current level modulation mapping relationship, control the digital-to-analog conversion module 132 to adjust the current value of the multi-level adjustable drive current Iref within the preset current range, so as to obtain the current value of the multi-level adjustable drive current Iref as the current setting value, so as to realize the brightness compensation of the light-emitting device 11 through the multi-level adjustable drive current Iref.

[0075] Figure 12 This is a flowchart illustrating a method for calibrating the brightness of a display panel, as shown below. Figure 12 As shown, a DBV level is first set via SOC / DDIC, and the screen is made to emit light through timing control. After the screen emits light, the actual brightness of the light-emitting device is measured first using an optical detection device (such as CA310). Then, based on the detection result of the actual brightness, the setting values ​​of the digital-to-analog conversion module 132 and the proportional adjustment module 133 are adjusted, and the calibration data of the adjusted setting values ​​and the corresponding multi-level adjustable drive current values ​​are recorded. The above steps are repeated for all DBV levels to obtain the mapping relationship and store it in OTP. Subsequently, when the display device is running, the control module 11 can match the current value of the corresponding multi-level adjustable drive current Iref according to the stored calibration data.

[0076] In one embodiment, such as Figure 11 The control module 11 shown also includes a switch register 102. The control unit 100 is connected to the switch register 102. The control unit 100 can obtain the current value of the intermediate current Idac corresponding to the preset current range through the switch register 102, thereby controlling all the first switches in the digital-to-analog converter module 132 to be turned on or off, so that the digital-to-analog converter module 132 can obtain the intermediate current Idac.

[0077] In one embodiment, such as Figure 11 The control module 11 shown also includes a current DAC register 103. The control module 100 is connected to the DAC register 103. The control module 100 can obtain the relationship between the target current level in the multi-level range and the current value of the proportionally output drive current through the DAC register 103, thereby controlling all the second switches in the proportional adjustment module 133 to be turned on or off, so that the proportional adjustment module 133 can obtain the multi-level adjustable drive current Iref based on the intermediate current Idac.

[0078] In one embodiment, such as Figure 11The control module 100 shown also includes: a system-level or driver chip (SOC / DDIC) and an interface or register circuit (Interface Ctrl / Reg Ctrl). The SOC / DDIC sends Meta Data / Command Mode information to Interface Ctrl / RegCtrl through a MIPI / SPI / QSOI type interface. Interface Ctrl / Reg Ctrl can control or configure the value of Reg in the switch register 102 and DAC register 103, thereby configuring the switching information of the mapping relationship stored in the switch register 102 and DAC register 103.

[0079] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A Micro-LED display circuit, characterized in that, include: A pixel array, comprising multiple pixel units arranged in rows and columns, wherein each pixel unit includes a driving transistor, a light-emitting device, and a switching transistor connected between the driving transistor and the light-emitting device, the switching transistor being used to receive a pulse width modulation signal to control the light emission duration; A drive current generation module is disposed outside the pixel array and electrically connected to the pixel unit. The drive current generation module includes a reference current module and a digital-to-analog conversion module, which are used to generate a multi-level adjustable drive current. A control module, located outside the pixel array and electrically connected to the drive current generating module, is used to adjust the drive current output by the digital-to-analog converter module according to the brightness requirements within a single configuration cycle to adapt to the target current requirements of different display content; and, before adapting to the target current requirements, to control the drive current output by the digital-to-analog converter module through control timing to provide the pixel unit with a dynamically adjustable overshoot current, so that the pixel unit can quickly stabilize to the target current.

2. The circuit according to claim 1, characterized in that, The drive current generation module further includes a proportional adjustment module, which is electrically connected to the digital-to-analog conversion module and is used to perform secondary modulation on the intermediate current output by the digital-to-analog conversion module to form the multi-level adjustable drive current to adapt to different brightness requirements.

3. The circuit according to claim 1 or 2, characterized in that, The dynamically adjustable overshoot current includes: a first overshoot current in a first stage and a second overshoot current in a second stage, wherein the first overshoot current is greater than the second overshoot current. Alternatively, the dynamically adjustable process current includes a third overshoot current maintained within the timing control range.

4. The circuit according to claim 3, characterized in that, The control module is used to control the digital-to-analog conversion module and the proportional adjustment module according to the brightness requirements, so as to generate a multi-level adjustable driving current based on the reference current and output it to the pixel unit, so as to realize the brightness control of the light-emitting device.

5. The circuit according to claim 4, characterized in that, The digital-to-analog conversion module and the proportional adjustment module have a current level modulation mapping relationship based on the brightness requirements. The control circuit is specifically used to: adjust the information input to the digital-to-analog conversion module and the proportional adjustment module according to the brightness requirement and the current level modulation mapping relationship, so as to generate a dynamically adjustable driving current based on the reference current and output it to the pixel unit, so as to realize the brightness control of the light-emitting device.

6. The circuit according to claim 5, characterized in that, The digital-to-analog conversion module and the reference current generation module constitute a current mirror circuit; The control module is specifically used to: control the number of bits output to the digital-to-analog converter module according to the brightness requirement and the current level modulation mapping relationship, so as to control the number of current branches in the digital-to-analog converter module that are turned on, and dynamically adjust the current based on the reference current generation range and satisfy the driving current margin.

7. The circuit according to claim 6, characterized in that, The proportional adjustment module and the digital-to-analog conversion module constitute a current mirror circuit; The control circuit is specifically used to: select combinations of different current branches in the proportional adjustment module according to the brightness requirements and the current level modulation mapping relationship, so as to output a current with a corresponding proportion based on the current output by the digital-to-analog conversion module.

8. The circuit according to claim 6, characterized in that, The aspect ratio of the current mirror tube in the current branch of the digital-to-analog conversion module is adjustable.

9. The circuit according to claim 7, characterized in that, The aspect ratio of the current mirror tube in the current branch of the proportional adjustment module is adjustable.

10. The circuit according to claim 5 or 6, characterized in that, The control module includes a one-time programmable OTP memory for storing the current level modulation mapping relationship.

11. The circuit according to claim 1, characterized in that, The drive current generation module optimizes the output drive current through a P / N type current mirror structure to improve the stability of drive current modulation.

12. The circuit according to claim 1, characterized in that, The digital-to-analog conversion module includes: a first transistor, at least two second transistors, and at least one first switch; wherein, the first transistor is connected to the reference current generation module and is used to receive the reference current, the at least two second transistors respectively form a current mirror structure with the first transistor to replicate the reference current, the at least two second transistors include a normally open second transistor and at least one non-open second transistor, and the at least one first switch is used to adjust the operating state of the at least one non-open second transistor. The control module is specifically used to: control the switching state of the at least one first switch according to the current level modulation mapping relationship, so as to adjust the working state of the at least one non-open second transistor, thereby generating a multi-level adjustable drive current and providing dynamic current margin for the drive current.

13. The circuit according to claim 12, characterized in that, The aspect ratio of the first transistor and the aspect ratio of the normally open second transistor are both multiples of a first preset value; The width-to-length ratio of the kth non-open second transistor to the first transistor is 2(k-1) times the first preset value.

14. The circuit according to claim 2, characterized in that, The proportional adjustment module includes: at least two third transistors and at least one second switch; wherein, the at least two third transistors are respectively used to receive the drive current and output the drive current, the at least two third transistors include a normally open third transistor and at least one non-open third transistor, and the at least one second switch is respectively used to adjust the operating state of the at least one non-open third transistor; The control module is specifically used to: control the switching state of the at least one second switch according to the current level modulation mapping relationship, so as to adjust the working state of the at least one non-open third transistor, so as to perform secondary modulation of the drive current in proportion.

15. The circuit according to claim 14, characterized in that, The aspect ratio of each of the at least two third transistors is a multiple of the second preset value.

16. The circuit according to any one of claims 1-15, characterized in that, The reference current generation circuit includes a bandgap reference circuit.

17. The circuit according to any one of claims 1-16, characterized in that, The driving current generating module is located outside the AA region corresponding to the light-emitting device.

18. The circuit according to any one of claims 1-17, characterized in that, The current generated by the drive current generation module is provided in a local current manner or in a global current manner.

19. A display panel, characterized in that, include: The display circuit as described in any one of claims 1-18.

20. A display device, characterized in that, Includes the display panel as described in claim 19.

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