Display circuit, display panel, display device and method

Abstract

The application provides a display circuit, a display panel, a display device and a method. The display circuit comprises a pixel array, a driving current generation module and a control module. The control module can control a digital-to-analog conversion module and a proportional adjustment module in the driving current generation module according to brightness requirements, so as to generate a driving current with multiple gears based on a reference current and output to each pixel unit in the pixel array, thereby more effectively realizing brightness control of a light-emitting device by adjusting the current value of the driving current of the pixel unit.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display circuit, display panel, display device and method. Background Technology

[0002] In some light-emitting diode (LED) display devices, light-emitting devices such as micro-LEDs are arranged in rows and columns to form a basic display panel. Each light-emitting device is connected to a corresponding driving circuit, and the driving circuits of all light-emitting devices are also arranged in rows and columns.

[0003] In existing technologies, a voltage source circuit in the pixel circuit provides a voltage signal to the driving circuit, enabling the driving circuit to switch to an operating state based on the voltage signal and control the light-emitting device to emit light. However, voltage source circuits suffer from problems such as current fluctuations, slow response speed, and a large number of components, which not only increases the size of the pixel circuit but also reduces the stability of the light-emitting device. Therefore, how to more effectively set a current source circuit in the pixel circuit to control the driving circuit, and how to adjust the value of the driving current to achieve brightness control of the light-emitting device, is a technical problem that needs to be solved in this field. Summary of the Invention

[0004] This application provides a display circuit, display panel, display device, and method, which controls the driving circuit by setting a current source circuit in the pixel circuit, and achieves brightness control of the light-emitting device by adjusting the current value of the driving current.

[0005] This application provides a display circuit, comprising: a pixel array including a plurality of pixel units arranged in rows and columns, each pixel unit including a driving transistor, a light-emitting device, and a switching transistor connected between the driving transistor and the light-emitting device, the switching transistor being used to receive a pulse width modulation signal to control the light emission duration; a driving current generation module disposed outside the pixel array and electrically connected to each pixel unit, the driving current generation module including a reference current generation module, a digital-to-analog converter module connected to the reference current generation module, and a proportional adjustment module connected to the digital-to-analog converter module, the reference current generation module being used to generate a reference current; and a control module disposed outside the pixel array and electrically connected to the driving current generation module, the control module being used to control the digital-to-analog converter module and the proportional adjustment module according to brightness requirements, so as to generate a multi-level adjustable driving current based on the reference current and output it to each pixel unit, thereby realizing brightness control of the light-emitting device.

[0006] A second aspect of this application provides a display panel, including the display circuitry provided in the first aspect of this application.

[0007] A third aspect of this application provides a display device, including a display panel as provided in the second aspect of this application.

[0008] A fourth aspect of this application provides a method for calibrating the brightness of a display circuit, comprising: measuring the actual brightness of a light-emitting device using an optical detection device; adjusting the set values ​​of a digital-to-analog conversion module and a proportional adjustment module based on the detection result of the actual brightness; recording calibration data of the adjusted set values ​​and the corresponding current values ​​of a multi-level adjustable drive current, and storing them in a one-time programmable (OTP) memory; and matching the current values ​​of the corresponding multi-level adjustable drive current according to the stored calibration data during operation of the display device.

[0009] In summary, the display circuit, display panel, display device, and method provided in this application include a pixel array, a drive current generation module, and a control module. The control module can control the digital-to-analog conversion module and the proportional adjustment module in the drive current generation module according to the brightness requirements, so as to generate a multi-level adjustable drive current based on the reference current and output it to each pixel unit in the pixel array. In this way, by adjusting the current value of the drive current of the pixel unit, the brightness control of the light-emitting device is realized more effectively. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the structure of a pixel unit in the prior art;

[0012] Figure 2 A schematic diagram of the structure of an embodiment of the display circuit provided in this application;

[0013] Figure 3A A schematic diagram of the structure of an embodiment of the display circuit provided in this application;

[0014] Figure 3B A schematic diagram of another embodiment of the display circuit provided in this application;

[0015] Figure 4 A schematic diagram of the structure of an embodiment of the display panel provided in this application;

[0016] Figure 5 A schematic diagram of the circuit structure of an embodiment of the display panel provided in this application;

[0017] Figure 6 A schematic diagram of the circuit structure of a display circuit provided in this application;

[0018] Figure 7 A control timing diagram of the display circuit provided in this application;

[0019] Figure 8 Another control timing diagram of the display circuit provided in this application;

[0020] Figure 9 A schematic diagram of the circuit structure of another display circuit provided in this application;

[0021] Figure 10 Another control timing diagram for the display circuit provided in this application;

[0022] Figure 11 A timing diagram for controlling a display circuit is provided in this application;

[0023] Figure 12 A schematic diagram of the structure of a control module provided in this application;

[0024] Figure 13 This application provides a schematic diagram of the structure of a drive current generating module;

[0025] Figure 14 A flowchart illustrating a method for calibrating the brightness of a display circuit, as provided in this application;

[0026] Figure 15 This is a schematic diagram showing the setup of the grading circuit. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] Figure 1 This is a schematic diagram of the structure of a pixel unit in the prior art, such as... Figure 1 In the pixel unit shown, transistor T1 receives the voltage signal Scan sent by the voltage source, so that transistor T2 switches to the working state according to the voltage signal Scan, thereby controlling the light-emitting device to emit light.

[0030] However, in the existing technology, in order to enable the voltage source to provide voltage signals to the pixel unit, the voltage source circuit has problems such as current fluctuation, slow response speed and many components, which not only increases the size of the display circuit, but also reduces the stability of the light-emitting device.

[0031] Therefore, how to more effectively control the brightness of light-emitting devices by adjusting the value of the driving current in the display circuit, as well as how to reduce the size of the display circuit and improve the stability of the light-emitting devices, are technical problems that need to be solved in this field.

[0032] Based on this, this application provides a display circuit to provide driving current to the light-emitting device in the pixel unit through a current source circuit disposed in the display circuit.

[0033] Figure 2 A schematic diagram of the structure of an embodiment of the display circuit provided in this application is shown below. Figure 2 The display circuit shown can be applied to the display panel of electronic devices with relevant display requirements, such as mobile phones, tablets, desktop computers, or televisions. The display circuit includes multiple pixel units 12 arranged in rows and columns, each pixel unit including a corresponding light-emitting device. Figure 2 In the example described, the display circuit includes a total of 9 pixel units 12 arranged in 3 rows and 3 columns. These 3 rows and 3 columns of pixel units 12 constitute a pixel array.

[0034] In one embodiment, the display circuit can display an image through the light-emitting devices in each pixel unit, and the light-emitting devices in each pixel can be used to achieve different color display effects. The light-emitting devices can be light-emitting diodes (LEDs), micro light-emitting diodes (MicroLEDs), organic light-emitting diodes (OLEDs), etc. Taking the pixel display color based on the Red-Green-Blue (RGB) color model as an example, each pixel includes three light-emitting devices: red, blue, and green, and the arrangement of the three light-emitting devices in the pixel can be arranged in a preset order. With this arrangement, by adjusting the brightness of each light-emitting device, each pixel can display the corresponding color. For example, when the red and green sub-pixels are lit at the same brightness, the human eye sees yellow. This arrangement is widely used in common display technologies such as liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs). In addition, the colors displayed by pixels can also be based on other color models, such as the Red-Green-Blue-White (RGBW) color model. In this case, the arrangement of subpixels in the pixel is the same as that of the color model.

[0035] like Figure 2 The display circuit shown also includes a control module 11 and at least one drive current generating module 13. The control module 11 can control at least one drive current generating module 13 to provide drive current to the pixel units 12 in the pixel array. Both the control module 11 and the drive current generating module 13 are located outside the pixel array. The control module 11 is electrically connected to the drive current generating module 132, and the drive current generating module 132 is electrically connected to the pixel units 12 in the pixel array.

[0036] In one embodiment, Figure 3A The schematic diagram of an embodiment of the display circuit provided in this application is shown in FIG3. The display circuit includes a drive current generating module 13, and the control module 11 can be used to control the drive current generating module 13 to provide drive current to each pixel unit 12 in the pixel array.

[0037] In another embodiment, Figure 3B A schematic diagram of another embodiment of the display circuit provided in this application is shown below. Figure 3BThe display circuit shown includes multiple drive current generating modules 13. The control module 11 can be used to control the multiple drive current generating modules 13 to provide drive current to the corresponding pixel units 12 in the pixel array. For example, for such... Figure 2 The pixel array shown comprises nine pixel units 12 arranged in a 3x3 grid. The control module 11 can be used to control nine drive current generating modules 13 to provide drive current to each of the nine pixel units 12 in the pixel array. Alternatively, the control module 11 can be used to control three drive current generating modules 13 to provide drive current to each of the three rows of pixel units 12 in the pixel array. Or, for example, the control module 11 can be used to control three drive current generating modules 13 to provide drive current to each of the three columns of pixel units 12 in the pixel array.

[0038] Furthermore, Figure 4 A schematic diagram of the structure of an embodiment of the display panel provided in this application is shown below. Figure 4 The embodiments shown can be applied to, for example Figure 3A or Figure 3B The display circuit shown illustrates an example where the control module 11 controls a drive current generating module 13 to provide drive current to a pixel unit 12.

[0039] Specifically, in such Figure 4 In the example shown, taking any pixel unit 12 in the pixel array as an example, the pixel unit 12 includes a driving transistor 121, a light-emitting device 123, and a switching transistor 122 connected between the driving transistor 121 and the light-emitting device 123. The switching transistor 122 can be used to receive the pulse width modulation signal EM sent by the control module 11 to control the light emission duration of the light-emitting device 123.

[0040] like Figure 4 As shown, the driving current generation module 13 provided in this embodiment includes: a reference current generation module 131, a digital-to-analog conversion module 132, and a proportional adjustment module 133. The reference current generation module 131, the digital-to-analog conversion module 132, and the proportional adjustment module 133 are connected in sequence. The output terminal of the proportional adjustment module 133 is electrically connected to the pixel unit 12. The reference current generation module 131 is used to generate a reference current Iin and send the reference current Iin to the digital-to-analog conversion module 132.

[0041] The control module 11 is used to control the digital-to-analog conversion module 132 and the proportional adjustment module 133 in the drive current generation module 13 according to the brightness requirements, so that the digital-to-analog conversion module 132 and the proportional adjustment module 133 generate a multi-level adjustable drive current based on the reference current Iin and output it to the pixel unit 12, so as to realize the brightness control of the light-emitting device.

[0042] In this embodiment, a current source is set in the driving current generation module of the display circuit to generate a driving current. The current value of the driving current is adjusted by controlling the digital-to-analog conversion module and the proportional adjustment module in the driving current generation module through the control module, thereby realizing brightness control of the light-emitting device. Furthermore, the multi-level adjustable driving current generated based on the reference current also provides a dynamic current margin for the driving current, thus increasing the range of adjustment of the current value of the driving current and the range of adjustment of the brightness of the light-emitting device 123. This improves the accuracy of adjusting the brightness of the light-emitting device 123 and enables the display circuit and its associated display panel and display device to be applied in more scenarios, meeting the brightness adjustment needs of the light-emitting device 123 in more scenarios. This is more conducive to the use and promotion of the display circuit and its associated display panel and display device provided in this application.

[0043] In one embodiment, the reference current generation module 131 provided in this application can be implemented through a bandgap reference current generation circuit or an external input current source, and is used to provide a stable reference current Iin for use by the digital-to-analog conversion module 132 and the proportional adjustment module 133, thereby ensuring that the generated reference current Iin has a more stable PVT characteristic, ensuring the stability of the drive current output to the pixel unit 12, and thus ensuring the stability of the drive voltage received by the pixel unit 12. In addition, to better take into account the PVT characteristics, the reference current generation module 131 can also be designed to ensure the output of the reference current Iin by adopting a stepped coverage method.

[0044] In one embodiment, a current level modulation mapping relationship is established between the digital-to-analog converter module 132 and the proportional adjustment module 133 based on brightness requirements. Specifically, the control module 11 can be used to adjust the information input to the digital-to-analog converter module 132 and the proportional adjustment module 133 according to the brightness requirements and the current level modulation mapping relationship, so as to generate a dynamically adjustable driving current based on the reference current Iin and output it to each pixel unit 12, thereby achieving brightness control of the light-emitting device 123. In one embodiment, the control module includes an OTP memory for storing the current level modulation mapping relationship.

[0045] The digital-to-analog converter module 132 and the reference current generation module 131 constitute a current mirror circuit. The control module 11 is used to control the number of bits output to the digital-to-analog converter module 132 according to the brightness requirements and the current level modulation mapping relationship, so as to control the number of current branches in the digital-to-analog converter module 132 to conduct, and dynamically adjust the current based on the reference current generation range and meet the driving current margin.

[0046] The proportional adjustment module 133 and the digital-to-analog conversion module 132 constitute a current mirror circuit. The control module 11 is used to select the combination of different current branches in the proportional adjustment module 133 according to the brightness requirements and the current level modulation mapping relationship, so as to output a current with a corresponding proportion based on the current output by the digital-to-analog conversion module 133.

[0047] The specific implementation of the analog-to-digital conversion module 132 and the proportional adjustment module 133 provided in this application will be described below with reference to the accompanying drawings.

[0048] Figure 5 A circuit structure diagram of an embodiment of the display panel provided in this application is shown below. Figure 5 As shown Figure 4 The above describes a specific circuit implementation of the digital-to-analog conversion module 132 and the proportional adjustment module 133 in the display panel 1 shown.

[0049] The digital-to-analog converter module 132 includes: a first transistor, at least two second transistors, and at least one first switch. (In the context of...) Figure 5 In the example shown, the first transistor, at least two second transistors, and the third switch are all NMOS transistors.

[0050] The first transistor is connected to the reference current generation module 131 and is used to receive the reference current Iin provided by the reference current generation module 131. At least two second transistors form current mirror structures with the first transistor to replicate the reference current Iin. The at least two second transistors include one normally open second transistor and at least one non-open second transistor, and at least one first switch is used to adjust the operating state of the at least one non-open second transistor.

[0051] Specifically, such as Figure 5 The first transistor N_lin is shown with its first terminal (drain) and control terminal (gate) connected to the reference current generation module 131. Both the drain and gate are used to receive the reference current Iin. The second terminal (source) of the first transistor N_lin is grounded. The first terminal (drain) of the normally open second transistor Nk is connected to the proportional adjustment module 133. The control terminal (gate) of the normally open second transistor Nk is connected to the reference current generation module 131 to receive the reference current Iin. The second terminal (source) of the normally open second transistor Nk is grounded. The non-open second transistors include N0, N1...N(k-1), where the first switches corresponding to the non-open second transistors are denoted as b0, b1...b(k-1). The first terminal (drain) of each non-open second transistor is connected to the proportional adjustment module 133 through a corresponding first switch. The control terminal (gate) of each non-open second transistor is connected to the reference current generation module 131 to receive the reference current Iin. The second terminal (source) of each non-open second transistor is grounded.

[0052] In one embodiment, the aspect ratio of the current mirror tube in the current branch of the digital-to-analog converter module 132 is adjustable.

[0053] For example, such as Figure 5 The current mirror in the current branch of the digital-to-analog converter module 132 shown includes a normally open second transistor and a non-open second transistor. The aspect ratio of both the normally open and non-open second transistors can be adjusted to multiples of a first preset value. Simultaneously, the aspect ratio of the k-th non-open second transistor to the first transistor is 2(k-1) times the first preset value. For example, in... Figure 5 In the example shown, let the first preset value be y. Then the width-to-length ratio of the first transistor is a times y, i.e., ay; the width-to-length ratio of the normally open second transistor is b times y, i.e., by. The width-to-length ratios of the k normally open second transistors N0, N1, ..., N(k-1) are 1y, 2y, ..., 2(k-1)y, respectively.

[0054] In specific implementations, such as Figure 5 The circuit structure of the digital-to-analog converter module 132 shown can also be referred to as a k-bit DAC current modulation circuit. It can generate and output a dynamically adjustable drive current Idac based on a reference current Iin. Furthermore, the current value generated by the digital-to-analog converter module 132 has a certain margin compared to the current setting value Itarget required by the drive current of the light-emitting device 11. For example, as... Figure 5 The digital-to-analog converter module 132 shown can output an adjustable drive current Idac with a current value between (b / a)*Iin and [(b+1+2+……+2(k-1)) / a]*Iin. This range of current values ​​is recorded as the preset current range.

[0055] In one embodiment, for the digital-to-analog converter module 132, the current value of the adjustable drive current Idac output by the digital-to-analog converter module 132 can be adjusted to different preset current ranges by adjusting the number of bits k and / or adjusting the width-to-length ratio of the transistor.

[0056] The proportional adjustment module 133 includes at least two third transistors and at least one second switch. Figure 5 In the example shown, at least two of the third transistors are PMOS transistors. These at least two third transistors are used to receive an adjustable drive current Idac provided by the digital-to-analog converter module 132, and output the drive current Idac to form a drive current Iref corresponding to the target current level. The at least two third transistors include one normally open third transistor and at least one non-open third transistor, and at least one second switch is used to adjust the operating state of the at least one non-open third transistor.

[0057] Specifically, Figure 5 The array contains at least two third transistors, designated P0, P1, P2...Pj (j+1 in total), and at least one second switch, designated s1, s2...sj, corresponding to at least one normally open third transistor P1, P2...Pj. The first terminal (source) of the normally open third transistor P0 is connected to a first voltage source, and its control terminal (gate) is connected to a pixel unit 12 in the pixel array, used to output a drive current Iref to the pixel unit 12, forming the drive voltage G received by the pixel unit 12. The second terminal (drain) of the normally open third transistor P0 is connected to a digital-to-analog converter module 132, used to receive an adjustable drive current Idac. The first terminal (source) of each normally open third transistor is connected to the first voltage source, the control terminal (gate) of each normally open third transistor is connected to a pixel unit 12 in the pixel array through a corresponding second switch, and the second terminal (drain) of each normally open third transistor is connected to the digital-to-analog converter module 132.

[0058] In one embodiment, the aspect ratio of the current mirror tube in the current branch of the proportional adjustment module 133 is adjustable.

[0059] For example, such as Figure 5 The current mirror in the current branch of the proportional adjustment module 133 shown includes a normally open third transistor and at least one non-open third transistor. The aspect ratio of both the normally open third transistor and the at least one non-open third transistor can be adjusted to a multiple of a second preset value. For example, in... Figure 5 In the example shown, let the second preset value be x. Then the width-to-length ratio of the normally open third transistor P0 is x, and the width-to-length ratios of the j non-open third transistors are cx, dx, ..., ex, respectively.

[0060] In specific implementations, such as Figure 5 The proportional adjustment module 133 shown achieves different current distribution outputs by selecting different combinations of j branches, thereby adjusting the drive current Iref.

[0061] In one embodiment, for the proportional adjustment module 133, the ratio of the drive current Iref output by the proportional adjustment module 133 to the drive current Idac with adjustable receiving current can be adjusted to different preset current adjustment ratios by adjusting the number of branches j and / or adjusting the width-to-length ratio of the switching transistor.

[0062] Furthermore, in the display circuit provided in this application embodiment, when the display area corresponding to the pixel array of the display circuit is large, the characteristics of the light-emitting devices 123 of the pixel units 12 in different display areas may be uneven. In particular, when the threshold values ​​of the transistors in the pixel units 12 are different, since the light-emitting current of the light-emitting device 123 is a function of the threshold value, there will be brightness differences between different light-emitting devices 123, which will affect the overall uniformity of the display circuit.

[0063] Therefore, the scaling module 132 in the display circuit provided in this application is connected to the driving transistor 121 in the pixel unit 12 through the first control transistor, so that the driving transistor 121 and the first control transistor are mirrored to replicate the driving current generated by the driving current generation module 13, thereby improving the current uniformity of the pixel circuit 12.

[0064] More specifically, Figure 6 This is a schematic diagram of the circuit structure of a display circuit provided in this application, illustrating a specific circuit implementation of the display circuit provided in this application. For example... Figure 6 As shown, the proportional adjustment module of the driving current generation module 13 is connected to the driving transistor T2 in the pixel unit 12 through the first control transistor T1. The first control transistor T1 and the driving transistor T2 are set as a mirror image. The driving transistor T2 can be used to copy the driving current generated by the driving current generation module 13.

[0065] In one embodiment, the pixel unit 12 further includes a scan control module located between the drive current generation module 13 and the first control transistor T1, and used to control the direction of the current generated by the drive current generation module 13. The scan control module includes at least one drive current control transistor, such as... Figure 6 In the example shown, the scan control module includes a first scan control transistor T4 and a second scan control transistor T5. The drive current generation circuit 13 is used to generate a drive current Iref. At least one drive current control transistor in the scan control module is used to receive the scan signal Scan and turn on according to the scan signal Scan, so that the drive current Iref generated by the drive current generation circuit 13 flows through the first control transistor T1.

[0066] In one embodiment, the pixel unit 12 further includes a capacitor C1. The driving transistor T2 and the switching transistor T3 are connected in sequence, and the switching transistor T3 is also connected to the light-emitting device 123. The switching transistor T3 is used to receive a pulse modulation signal EM to control the light-emitting duration of the light-emitting device 123. The capacitor C1 is disposed between the first control transistor T1 and the driving transistor T2, and is used to receive the driving current provided by the calibration 13 of the driving current generation circuit 1 and store the charge provided by the driving current.

[0067] In one embodiment, such as Figure 6The first control transistor T1, the first scan control transistor T4, and the second scan control transistor T5 shown are all NMOS transistors. The first terminal of the drive current generation module 13 is connected to the second voltage source ELVSS, and the second terminal is connected to the drain of the first scan control transistor T4 and the second scan control transistor T5. The gates of both the first scan control transistor T4 and the second scan control transistor T5 are used to receive the scan signal Scan. The source of the first scan control transistor T4 is connected to the drain of the first control transistor T1, and the source of the second scan control transistor T5 is connected to the gate of the first control transistor T1. The source of the first control transistor T1 is connected to the first voltage source ELVDD.

[0068] In one embodiment, such as Figure 6 In the pixel unit 12 shown, both the driving transistor T2 and the switching transistor T3 are NMOS transistors. The source of the driving transistor T2 and the first terminal of the capacitor C1 are connected to the first voltage source ELVDD. The gate of the driving transistor T2 is connected to the second terminal of the capacitor C1 and the gate of the first control transistor T1. The drain of the driving transistor T2 is connected to the source of the switching transistor T3. The drain of the switching transistor T3 is connected to the positive terminal of the light-emitting device 123. The negative terminal of the light-emitting device 123 is connected to the second voltage source ELVSS.

[0069] In one embodiment, the transistors in pixel unit 12 operate in the voltage range of the low-voltage domain.

[0070] In one specific embodiment, the scan control transistor adopts a medium-voltage domain process, that is, the scan control transistor operates in the voltage range of the medium-voltage domain. In this case, the scan control transistor is a medium-voltage domain device.

[0071] The voltage range of the medium voltage domain can be less than or equal to 3.3V, such as a value between 0 and 3.3V, or less than or equal to 5V, such as a value between 0 and 5V. The voltage range of the low voltage domain can be less than or equal to 1V, such as a value between 0 and 1V.

[0072] For example, in this embodiment, the first control transistor T1 operates in the low-voltage range, and the first scan control transistor T4 and the second scan control transistor T5 operate in the medium-voltage range. The purpose of setting the first scan control transistor T4 and the second scan control transistor T5 as medium-voltage devices is to improve the stability of the devices and improve the accuracy of the driving current provided subsequently.

[0073] For example, the first control transistor T1, the first scan control transistor T4, and the second scan control transistor T5 provided in this embodiment all operate in the low-voltage range, which can further reduce power consumption.

[0074] In one embodiment, both the driving transistor T2 and the switching transistor T3 provided in this embodiment adopt a low-voltage domain process to reduce the power consumption and area of ​​the pixel unit 12 and increase the integration density of the pixel unit 12. That is, both the driving transistor T2 and the switching transistor T3 operate in the low-voltage domain voltage range, and at this time, both the driving transistor T2 and the switching transistor T3 are low-voltage domain devices.

[0075] To meet the voltage range requirements of the low-voltage domain devices, when the second voltage range is 1V, the voltage value of the first voltage source ELVDD can be set to a first preset value greater than 0V, wherein the first preset value is less than or equal to 1V. For example, the voltage value of the first voltage source ELVDD can be set to 1V. The voltage value of the second voltage source ELVSS can be set to a second preset value less than 0V, wherein the range of the second preset value can be -1.5V to -2.5V. By setting the voltage values ​​of the first voltage source ELVDD and the second voltage source ELVSS in this embodiment, the voltage difference between the first voltage source ELVDD and the second voltage source ELVSS is sufficiently large, thereby meeting the driving requirements of the transistors in the pixel unit 12. This ensures that the pixel unit 12 can more effectively provide driving current to the light-emitting device 123, enabling the light-emitting device 123 to emit light normally and stably. Simultaneously, during the process of the pixel unit 12 providing driving current to the light-emitting device 123, the voltage of all nodes in the pixel unit 12 does not exceed 1V, ensuring the normal operation of all low-voltage domain devices in the pixel unit 12 and improving the lifespan of the low-voltage domain devices in the pixel unit 12.

[0076] In a specific implementation, such as Figure 6 In the pixel unit 12 shown, the first control transistor T1 and at least one scan control transistor are both located outside the AA area corresponding to the light-emitting device 123, while the driving transistor T2 and the switching transistor T3 are located inside the AA area corresponding to the light-emitting device 123. Since the transistors such as the first control transistor T1 and at least one scan control transistor are low-voltage devices, the pixel unit 12 has a small size, which can reduce the area occupied by the AA area.

[0077] In summary, the pixel circuit provided in this embodiment has the first control transistor T1 in the pixel unit 12 operating in a low voltage range of less than or equal to 1V. This allows the driving current generated by the driving current generation module 13 to be achieved without requiring a high voltage. Combined with the use of the current mirror structure in the pixel unit 12, this reduces the power consumption of each light-emitting device 123 when it emits light, as well as the overall power consumption required for the light-emitting devices 123 to emit light in the entire display circuit. Furthermore, it can improve the uniformity of the display brightness of the light-emitting devices 123 in the display circuit.

[0078] Meanwhile, since the transistors in the low-voltage domain are smaller in size than those in the medium-voltage domain, the circuit area of ​​the pixel unit 12 can be reduced, allowing the pixel unit 12 to be placed in the AA area corresponding to the smaller light-emitting device 123. This reduces the effective area occupied by the AA area of ​​the display circuit, enabling the pixel unit 12 provided in this application embodiment to be implemented in more display circuits, enriching the application scenarios and making it more conducive to the application and promotion of this application embodiment.

[0079] Figure 7 A control timing diagram of the display circuit provided in this application shows the control timing of, for example, the control timing of ... Figure 6 The diagram shows the control of the display circuit. The control module 11 is connected to the first scan control transistor T4, the second scan control transistor T5, and the switch transistor T3. The control module 11 can send scan signals Scan to the first scan control transistor T4 and the second scan control transistor T5, and send light emission signals EM to the switch transistor T3 through the PWM_GEN module set in the pixel unit 12.

[0080] Specifically, such as Figure 7 As shown, in the first part p1 of the entire display time of a frame image n, between the first time t1 and the second time t2, the control module 11 sends a scan signal Scan to the gates of the first scan control transistor T4 and the second scan control transistor T5, so that the first scan control transistor T4 and the second scan control transistor T5 are turned on. The drive current generated by the drive current generation module 13 passes through the first scan control transistor T4 and the second scan control transistor T5 to the first control transistor T1. At the same time, since the width-to-length ratio of the first control transistor T1 and the drive transistor T2 is set to be the same, and the voltage of the gates of the two devices is the same, the drive transistor T2 replicates the current flowing through the first control transistor T1 based on the current mirror structure, and the capacitor C1 can store the charge provided by the drive current. Subsequently, in the second part p2, between the second time t2 and the third time t3, the control module 11 generates a light-emitting signal EM based on the PWM_GEN module and sends the light-emitting signal EM to the switching transistor T3, so that the switching transistor T3 turns on when it receives the light-emitting signal EM. The driving current provided by the driving transistor T2 is sent to the light-emitting device 123 through the switching transistor T3, thereby driving the light-emitting device 123 to emit light.

[0081] More specifically, the control module 11 can adjust the brightness of the light-emitting device 123 by adjusting the magnitude of the driving current generated by the driving current generation module 13 and adjusting the duration of the driving current provided by the pixel unit 12 to the light-emitting device 123 according to the light emission signal EM, thereby enabling more brightness adjustments and more precise brightness adjustments.

[0082] Figure 8Another control timing diagram of the display circuit provided in this application shows a timing diagram of the control module 11 controlling multiple rows of pixel units 12. During the first part p11 time period of the light-emitting device 123 of the first row of pixel units 12, between time t11 and t12, the control module 11 sends a scan signal Scan to the first row of pixel units 12. <1> At this time, the driving current generated by the driving current generation module 13 is I1. After time t12, the control module 11 sends the light emission signal EM to the first row pixel unit 12. <1> Simultaneously, during the first part p21 time period of the light-emitting device 123 in the second row pixel unit 12, between time t12 and t22, the control module sends a scan signal Scan to the second row pixel unit 12. <2> At this time, the driving current generated by the driving current generation module 13 is I2. After time t22, the control module 11 sends the light emission signal EM to the first row pixel unit 12. <2> This process continues until the light-emitting device 123 of the nth row of pixel units 12 is charged and emits light. After one frame is completed, the process is repeated. Figure 8 The light-emitting devices 123 of the first row of pixel units 12 shown begin to charge and emit light sequentially.

[0083] Furthermore, in Figure 7 and 8 The illustrated embodiment shows the timing of the control module 11 controlling the light-emitting devices of the multi-row pixel units 12. In the first part p1 of a frame, a scan signal Scan is sent to one row of pixel units 12, and in the second part p2, a light-emitting signal EM is sent to the pixel circuit 12 to drive the light-emitting device 123 to emit light. Subsequently, a scan signal is sent to the second row of pixel units 12, and a light-emitting signal is sent to the pixel units 12. This method can reduce instantaneous power consumption and is suitable for application scenarios with high power consumption requirements.

[0084] Figure 9 A schematic diagram of the circuit structure of another display circuit provided in this application is shown below. Figure 9 The pixel circuit shown is in Figure 6 Based on the display circuit shown, another specific circuit implementation of the display circuit provided in this application is illustrated. For example, Figure 9 The display circuit shown is in Figure 6 The circuit shown also includes a reset control transistor MN1 and a voltage control transistor MN2.

[0085] Among them, the reset control transistor MN1 is used to release residual charge when at least one scan control transistor is in the off state, to prevent overvoltage breakdown of the display circuit and improve device stability.

[0086] Specifically, the reset control transistor MN1 is used to receive the reset signal RE and turn on according to the reset signal RE, so that when the first scan control transistor T4 and the second scan control transistor T5 are turned off, the voltage at point N between the first control transistor T1 and the drive transistor T2 is reset.

[0087] In one embodiment, such as Figure 9 The reset control transistor MN1 shown is an NMOS transistor. The source of the reset control transistor MN1 is used to receive the reset voltage V0, which can be the ground voltage. The gate of the reset control transistor MN1 is used to receive the reset signal RE. The drain of the reset control transistor MN1 is connected to the drain of the first scan control transistor T4 and the second scan control transistor T5.

[0088] When the gate of the reset control transistor MN1 receives the reset signal RE, the reset control transistor MN1 is turned on, so that the reset voltage V0 resets point N and the drain and gate of the first control transistor T1 through the reset control transistor MN1 and the second scan control transistor T5.

[0089] The voltage control transistor MN2 is used to receive the voltage control signal RA and turn on according to the voltage control signal RA, thereby controlling the voltage Vgd between the gate and drain of at least one scan control transistor to a preset value.

[0090] In one embodiment, such as Figure 9 The voltage control transistor MN2 shown is an NMOS transistor. The source of the voltage control transistor MN2 is connected to the drain of the first scan control transistor T4 and the second scan control transistor T5. The gate of the voltage control transistor MN2 is used to receive the voltage control signal RA. The drain of the voltage control transistor MN2 is connected to the current source.

[0091] When the voltage control transistor MN2 receives the voltage control signal RA, the voltage control transistor MN2 is turned on, so that the second voltage source ELVSS passes through the voltage control transistor MN2 and the first scan control transistor T4, so that the voltage between the gate and drain of the first scan control transistor T4 and the second scan control transistor T5 is a preset value.

[0092] In specific implementation methods, such as Figure 9 In the display circuit shown, the driving transistor T2, the switching transistor T3, the first control transistor T1, and at least one scanning control transistor are all disposed within the AA region corresponding to the light-emitting device 11. The reset control transistor MN1 and the voltage control transistor MN2 can be disposed outside the AA region corresponding to the light-emitting device 12. Figure 9 At least one drive current control transistor shown also operates in the low voltage range. Since the transistors in the pixel circuit are all low voltage devices, they are smaller in size, which can reduce the area occupied by the AA region.

[0093] Figure 10Another control timing diagram of the display circuit provided in this application, wherein, is shown for, as Figure 9 The schematic diagram shown illustrates the control of the display circuit. The control module 11 of the display circuit is connected to the first scan control transistor T4, the second scan control transistor T5, the switch transistor T3, the reset control transistor MN1, and the voltage control transistor MN2. The control module can be used to send a scan signal Scan, an emission signal EM, a reset control signal RE to the reset control transistor MN1 to control the reset control transistor MN1, and a voltage control signal RA to the voltage control transistor MN2 to control the voltage control transistor MN2.

[0094] Specifically, such as Figure 10 During the display of one frame of an image, for a pixel unit 12, between the first and second moments within time S1, the control module 11 sends a reset signal RE to the reset control transistor MN1, and the scan control module sends a scan signal Scan. When the reset signal RE is at a high level and the scan signal Scan is at a low level, the reset voltage V0, together with the reset control transistor MN1 and the second scan control transistor T5, resets point N and the drain and gate of the first control transistor T1.

[0095] Between the second and third moments within time S2, control module 11 sends a voltage control signal RA to voltage control transistor MN2 and a scan signal Scan to current source circuit 13. At this time, the drive current provided by drive current generation module 13 charges capacitor C1 through voltage control transistor MN2 and second scan control transistor T5. Capacitor C1 stores the charge passed by the drive current and simultaneously raises the gate signal at point N to a preset value.

[0096] Between the third and fourth moments within time S3, control module 11 sends a reset signal RE to reset control transistor MN1. At this time, due to the voltage division effect of the MOSFET, the voltage at point N is pulled down to near ELVSS. In a specific embodiment, ELVSS = -2V, and the voltage at point N is -1.7V. When the gate signals of the first scan control transistor T4 and the second scan control transistor T5 are 1V, Vgd = 2.7V, which exceeds the withstand voltage range of the first scan control transistor T4 and the second scan control transistor T5, there is a risk of breakdown. Therefore, control module 11 sends a reset signal RE to reset control transistor MN1, causing reset control transistor MN1 to discharge the charge at point N, ensuring that the first scan control transistor T4 and the second scan control transistor T5 do not overvoltage.

[0097] After the fourth moment of time S4, the control module 11 sends a light emission signal EM to the switch transistor T3, so that the switch transistor T3 provides a drive current to the light emission device 123 according to the light emission signal EM.

[0098] In summary, the display circuit provided in this embodiment, by setting the reset control transistor MN1 and the voltage control transistor MN2, can prevent the display circuit devices from exceeding the voltage range, thus ensuring the stability of the display circuit and its associated display panel and display device, and extending their service life.

[0099] Figure 11 This application provides a timing diagram for controlling a display circuit, such as... Figure 11 Another control method is shown to scan all pixel units 12 on the display panel 1 line by line and control the light-emitting devices 123 of all pixel units 12 to emit light globally, so as to improve the synchronization and uniformity of the overall display of the display panel and to be used in application scenarios with high requirements for display effect consistency.

[0100] Specifically, the control module 11 controls the duty cycle of the first control transistor T1 and the driving transistor T2 to provide the current generated by the driving current generation module 13 in a local current manner or a global current manner, thereby enabling the light-emitting devices 123 of the pixel units 12 in the pixel array to light up row by row or globally, thus optimizing power consumption. For example, as Figure 11 As shown, the display time range of a frame image n is divided into a first part p11 and a second part p21. The control module 11 adjusts the duty cycle of the scan signal Scan, thereby sending the scan signal Scan to the pixel unit 12 line by line in the first part p11, and adjusting the duty cycle of the light emission signal EM in the second part p21, thereby starting to send the light emission signal EM to the switching transistor T3, so that the light emission device 123 of each row of pixel unit 12 can start to emit light simultaneously. The duration of the light emission signal EM in each row is related to the brightness required by the light emission device 123, and the change in duration can be used to adjust the brightness of the light emission device 123.

[0101] Figure 12 A schematic diagram of the structure of a control module provided in this application is shown below. Figure 12 A specific implementation of the control module 11 in a display circuit is provided. The control module 11 can be used to control the drive current generating module 13 in the display circuit.

[0102] Specifically, such as Figure 12 The control module 11 shown includes: a scan generator located on the left and right sides of the array formed by the pixel units 12 of the display panel 1, a bandgap circuit for generating a reference current, and a current source circuit, wherein the current source circuit is... Figure 12The Iref generation circuit (including DAC and Switch modules), OTP (One-Time Programmable Memory) module, interface and register control module (Interface Ctrl / Reg Ctrl), Switch Reg register module, and DAC Reg register module are included. Furthermore, it should be noted that in different application scenarios, the row scanning circuit can also be set in the column direction, while the Iref generation circuit is set in the row direction. For ease of description, as follows... Figure 12 The example shown uses a row scanning circuit for row scanning and an Iref generation circuit for column direction.

[0103] The row scanning circuit selects and scans each row of the Panel one by one. The transistors in the pixel units 12 of the selected row are turned on to write and store data signals, preparing for the next stage of light emission.

[0104] A bandgap circuit is a circuit that adds voltages with positive and negative temperature coefficients with specific weights to compensate for temperature changes, generating a reference current that does not change with the PVT. The bandgap circuit scheme used in this technical solution is not subject to specific limitations.

[0105] The Iref generation circuit uses the reference current generated by the bandgap to mirror the current in different proportions using current mirrors with different aspect ratios to meet the driving requirements of the pixel circuit. The Iref generation circuit can be set in one or more columns.

[0106] OTP can store the Iref DAC configuration corresponding to each DBV. The data bit width stored can be determined according to the brightness accuracy requirements, ensuring that the module can automatically load the optimal current setting according to the preset brightness level through the look-up table when in use, thereby improving the consistency and stability of the panel display performance.

[0107] The SOC (System-on-a-Chip) sends Meta Data via the MIPI interface or DAC and DBV information to the interface and register control module via SPI or QSPI interfaces. The interface and register control module can control the register values ​​of the Switch and Current DAC. Upon receiving the brightness level information, the register uses the OTP lookup table to precisely control the current value of the Iref generation circuit.

[0108] More specifically, Figure 13 This application provides a schematic diagram of the structure of a drive current generating module, as shown below. Figure 13 A specific circuit implementation of the drive current generation module 13 is shown.

[0109] like Figure 13 The current source shown includes a digital-to-analog converter (DBV) circuit 131 and a proportional control (DAC) circuit 132. The DBV circuit 131 receives the initial reference current Ibg generated by the Bandgap module and adjusts the value of the reference current Ibg within a preset current range to obtain an adjustable drive current Iref, providing a dynamic current margin for the drive current. Subsequently, the proportional control circuit 132 adjusts the output drive current Iref proportionally according to the target current level among the multiple levels.

[0110] Specifically, such as Figure 13 The digital-to-analog converter circuit 131 shown includes a first transistor Mn and at least two second transistors, wherein at least one second transistor includes a normally open second transistor Ma and at least one non-open second transistor, such as... Figure 13 The example shown uses eight non-open second transistors, denoted as M0-M8. Each non-open second transistor is also connected to two switches. For example, the gate of non-open second transistor M0 is connected to switches b0 and b0', the gate of non-open second transistor M1 is connected to switches b1 and b1', and so on. Switches b0-b8 correspond to the 8-bit digital control signals of non-open second transistors M0-M8. Switches b0-b8 are inversely related to the corresponding switches b0'-b8' to ensure that only one set of M0-M8 is in the on state according to the gate control signal.

[0111] Specifically, the control module 11 can control the digital-to-analog converter circuit 131 to adjust the current value of the reference current Ibg within a preset current range by controlling the on or off states of the control switches b0-b8, thereby obtaining the current range of the adjustable drive current Iref. When the current source generates the initial drive current Ibg, the normally open second transistor Ma is in the on state. At this time, the current flowing through the first mirror control transistor M13 consists of two parts: one part is the current Ia flowing through the normally open second transistor Ma, and the other part is the current Ib flowing through the non-open second transistors M0-M8, so I0 = Ia + Ib. When the aspect ratio of the first transistor Mn is n and the aspect ratio of the normally open second transistor Ma is a, the current value of the intermediate current I0 can be obtained by setting the aspect ratio. For example, when the initial drive current Ibg is 1.5uA, a=380, and n=300, the drive current Iref output by the digital-to-analog converter circuit 131 ranges from 1.4uA to 3.955uA.

[0112] Subsequently, the second mirror control transistor M14 provides a drive current Iref to the proportional adjustment circuit 132 based on the current mirror principle between it and the first mirror control transistor M13.

[0113] like Figure 13 The proportional adjustment circuit 132 shown includes at least two third transistors, including a normally open third transistor M12, in the case of... Figure 8 The example shown uses two unopened third transistors, denoted as M10 and M11. Each unopened third transistor is also connected to two switches. For example, unopened third transistor M10 is connected to switches b10 and b10', and unopened third transistor M11 is connected to switches b11 and b11'. Here, b10' and b11' are the inverse switches of b10 and b11. M15 is the current mirror transistor inside the pixel circuit. The aspect ratio of M12 is set to be the same as that of M15. The aspect ratio of M10 is set to be c times that of M12, and the aspect ratio of M11 is set to be d times that of M12.

[0114] Specifically, the control module 11 can control the proportional adjustment circuit 132 to adjust the current range of the output driving current Iref proportionally according to the target current level among the multiple levels by controlling the on or off state of the control switches b10-b11. This ultimately achieves a more precise and flexible adjustment of the current value of the driving current provided to the subsequent pixel unit 12.

[0115] When b10 and b11 are disconnected, Iref = I0.

[0116] When b10 is closed and b11 is open .

[0117] When b11 is closed and b10 is open .

[0118] When both b10 and b11 are closed .

[0119] In one embodiment, the control module 11 can determine the control of the switches in the digital-to-analog converter circuit 131 and the proportional adjustment circuit 132 according to the preset mapping relationship, so that the digital-to-analog converter circuit 131 and the proportional adjustment circuit 132 adjust the initial drive current Ibg to obtain the corresponding multi-level adjustable drive current Iref, and provide dynamic current margin for the drive current Iref.

[0120] Figure 14 A flowchart illustrating a method for calibrating the brightness of a display circuit provided in this application is shown below. Figure 14As shown, a DBV level is first set via SOC / DDIC, and the screen is made to emit light through timing control. After the screen emits light, the actual brightness of the light-emitting device is measured first using an optical detection device (such as CA310). Then, based on the detection result of the actual brightness, the set values ​​of the digital-to-analog conversion module 132 and the proportional adjustment module 133 are adjusted, and the calibration data of the adjusted set values ​​and the corresponding multi-level adjustable drive current values ​​are recorded. The above steps are repeated for all DBV levels to obtain the mapping relationship and store it in OTP. Subsequently, when the display device is running, the control module 11 can match the current value of the corresponding multi-level adjustable drive current according to the stored calibration data.

[0121] In one embodiment, to ensure that the Iref generation circuit can generate current values ​​within the required range under different PVT conditions, the current values ​​at different settings need to have a certain overlap. In this embodiment, the overlap value can be set to be greater than 30%, and the current value is adjusted by adjusting the width-to-length ratio of the transistor in the proportional adjustment circuit 132. See Table 1 below. Figure 15 The diagram illustrates the relationship between the width-to-length ratio of the transistors in the proportional control circuit 132 and the overlap when the drive current Iref ranges from 0.07µA to 7µA. Figure 15 This is a schematic diagram of the baffle circuit setup. The horizontal axis represents the current range of the drive current in μA, and the vertical axis represents the width-to-length ratio of the transistor in the proportional adjustment circuit 132.

[0122]

[0123] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display circuit, characterized in that, include: A pixel array, comprising multiple pixel units arranged in rows and columns, wherein each pixel unit includes a driving transistor, a light-emitting device, and a switching transistor connected between the driving transistor and the light-emitting device, the switching transistor being used to receive a pulse width modulation signal to control the light emission duration; A drive current generation module is disposed outside the pixel array and electrically connected to the pixel unit. The drive current generation module includes a reference current generation module, a digital-to-analog converter module connected to the reference current generation module, and a proportional adjustment module connected to the digital-to-analog converter module. The reference current generation module is used to generate a reference current. A control module is located outside the pixel array and electrically connected to the drive current generation module. The control module is used to control the digital-to-analog conversion module and the proportional adjustment module according to the brightness requirements, so as to generate a multi-level adjustable drive current based on the reference current and output it to the pixel unit, so as to realize the brightness control of the light-emitting device.

2. The circuit according to claim 1, characterized in that, The digital-to-analog conversion module and the proportional adjustment module have a current level modulation mapping relationship based on the brightness requirements. The control module is specifically used to: adjust the information input to the digital-to-analog conversion module and the proportional adjustment module according to the brightness requirement and the current level modulation mapping relationship, so as to generate a dynamically adjustable driving current based on the reference current and output it to each pixel unit, so as to realize the brightness control of the light-emitting device.

3. The circuit according to claim 2, characterized in that, The digital-to-analog conversion module and the reference current generation module constitute a current mirror circuit; The control module is specifically used to: control the number of bits output to the digital-to-analog converter module according to the brightness requirement and the current level modulation mapping relationship, so as to control the number of current branches in the digital-to-analog converter module that are turned on, and dynamically adjust the current based on the reference current generation range and satisfy the driving current margin.

4. The circuit according to claim 3, characterized in that, The proportional adjustment module and the digital-to-analog conversion module constitute a current mirror circuit; The control module is specifically used to: select combinations of different current branches in the proportional adjustment module according to the brightness requirements and the current level modulation mapping relationship, so as to output a current with a corresponding proportion based on the current output by the digital-to-analog conversion module.

5. The circuit according to claim 3, characterized in that, The aspect ratio of the current mirror tube in the current branch of the digital-to-analog conversion module is adjustable.

6. The circuit according to claim 4, characterized in that, The aspect ratio of the current mirror tube in the current branch of the proportional adjustment module is adjustable.

7. The circuit according to claim 2 or 3, characterized in that, The control module includes a one-time programmable OTP memory for storing the current level modulation mapping relationship.

8. The circuit according to any one of claims 1-7, characterized in that, The scaling module is connected to the driving transistor in the pixel unit through the first control transistor; The driving transistor is mirrored with the first control transistor to replicate the current generated by the driving current generation module, thereby improving the current uniformity of the pixel circuit.

9. The circuit according to claim 8, characterized in that, At least one of the driving transistor and the first control transistor employs a low-voltage domain process to reduce the power consumption and area of ​​the pixel circuit, and to increase the integration density of the pixel circuit.

10. The circuit according to claim 8 or 9, characterized in that, The pixel unit further includes a scan control module, which is located between the drive current generation module and the first control tube, and is used to control the direction of the current generated by the drive current generation module.

11. The circuit according to claim 10, characterized in that, The scanning control module includes at least one scanning control transistor connected to the drive current generation module and the first control transistor, for receiving scanning signals to control the current flow through the first control transistor.

12. The circuit according to claim 11, characterized in that, The scanning control tube uses a medium-voltage domain process.

13. The circuit according to any one of claims 1-12, characterized in that, The reference current generation module is a bandgap reference circuit or an external input current source, and is used to provide a stable reference current for use by the digital-to-analog conversion module and the proportional adjustment module.

14. The circuit according to any one of claims 1-13, characterized in that, The current generated by the drive current generation module is provided in a local current manner or in a global current manner.

15. The circuit according to claim 14, characterized in that, The pixel array is lit up row by row, or all pixels are lit up at once.

16. The pixel circuit according to any one of claims 8-12, characterized in that, The pixel unit further includes a capacitor disposed between the first control transistor and the driving transistor for storing the charge of the driving current.

17. The pixel circuit according to claim 16, characterized in that, The pixel unit further includes a reset control transistor, used to release residual charge when at least one scan control transistor is in the off state, to prevent the pixel circuit from overvoltage breakdown and improve device stability.

18. The pixel circuit according to claim 17, characterized in that, The reset control transistor is specifically used to: receive a reset signal and turn on according to the reset signal to reset the voltage between the first control transistor and the drive transistor.

19. The pixel circuit according to claim 18, characterized in that, The pixel unit further includes a voltage control transistor, used to receive a voltage control signal and turn on according to the voltage control signal to control the voltage between the gate and drain of the at least one scan control transistor to a preset value.

20. The pixel circuit according to any one of claims 8-12, characterized in that, The first control transistor and the at least one scanning control transistor are disposed outside the AA region corresponding to the light-emitting device, and the driving transistor and the switching transistor are disposed inside the AA region corresponding to the light-emitting device.

21. The pixel circuit according to claim 19, characterized in that, The driving transistor, the switching transistor, the first control transistor, and the at least one scanning control transistor are disposed within the AA region corresponding to the light-emitting device, while the reset control transistor and the voltage control transistor are disposed outside the AA region corresponding to the light-emitting device.

22. A display panel, characterized in that, include: The display circuit as described in any one of claims 1-21.

23. A display device, characterized in that, Includes the display panel as described in claim 22.

24. A method for calibrating the brightness of a display circuit, characterized in that, include: The actual brightness of the light-emitting device is measured using optical detection equipment; Adjust the settings of the digital-to-analog conversion module and the proportional adjustment module based on the actual brightness detection results; Record the calibration data of the adjusted set value and the corresponding current value of the multi-level adjustable drive current, and store them in a one-time programmable OTP memory; When the display device is running, the current value of the corresponding multi-level adjustable drive current is matched according to the stored calibration data.

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