Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises at least two pixel circuits; each pixel circuit comprises a driving module, a first light-emitting control module, a second light-emitting control module, a light-emitting module and a first reset module; the first light-emitting control module is connected between a first power supply line and a first end of the first light-emitting control module; the first reset module is connected between a first reset signal line and a second end of the driving module, and a control end of the first reset module is connected to a first scan line; the first reset module is used for transmitting a first reset voltage on the first reset signal line to the second end of the driving module in response to a first scan signal on the first scan line; wherein the first reset module comprises a first sub-transistor and a second sub-transistor, and each adjacent two pixel circuits share one first sub-transistor along an extension direction of the first scan line. The technical scheme of the application improves the use performance of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] This invention provides a display panel and a display device to improve the performance of the display panel.

[0005] According to one aspect of the present invention, a display panel is provided, the display panel comprising: at least two pixel circuits; the pixel circuits comprising:

[0006] A driving module and a first light-emitting control module, wherein the first light-emitting control module is connected between the first power line and the first end of the first light-emitting control module;

[0007] The second light-emitting control module and the light-emitting module are connected in series between the second end of the driving module and the second power supply.

[0008] A first reset module is connected between a first reset signal line and a second terminal of the drive module, and the control terminal of the first reset module is connected to a first scan line; the first reset module is used to respond to a first scan signal on the first scan line and transmit a first reset voltage on the first reset signal line to the second terminal of the drive module.

[0009] The first reset module includes a first sub-transistor and a second sub-transistor. Along the extension direction of the first scan line, each pair of adjacent pixel circuits shares one first sub-transistor.

[0010] Optionally, the first sub-transistor is connected between the first reset signal line and the first terminal of the second sub-transistor, and the second terminal of the second sub-transistor is connected to the second terminal of the driving module.

[0011] Optionally, the pixel circuit further includes:

[0012] The second reset module is connected between the second reset signal line and the first end of the light-emitting module. The control end of the second reset module is connected to the second scan line. The second reset module is used to respond to the second scan signal on the second scan line and transmit the second reset voltage on the second reset signal line to the first end of the light-emitting module.

[0013] Preferably, the first scan line is multiplexed as the second scan line;

[0014] Preferably, the second reset module includes a second reset transistor, the control electrode of the second reset transistor is connected to the second scan line, the first electrode of the second reset transistor is connected to the second reset signal line, and the second electrode of the second reset transistor is connected to the first end of the light-emitting module;

[0015] Preferably, the first reset module is used in the first reset phase to transmit the first reset voltage on the first reset signal line to the second terminal of the drive module in response to the first scan signal on the first scan line.

[0016] The second reset module is used to transmit the second reset voltage on the second reset signal line to the first terminal of the light-emitting module in response to the second scan signal on the second scan line during the first reset phase.

[0017] Preferably, the driving module includes a driving transistor, the first electrode of which is connected to the first light-emitting control module, and the second electrode of which is connected to the second light-emitting control module;

[0018] Preferably, the first light-emitting control module includes a first light-emitting control transistor, the control electrode of the first light-emitting control transistor is connected to the light-emitting control line, the first electrode of the first light-emitting control transistor is connected to the first power line, and the second electrode of the first light-emitting control transistor is connected to the first end of the driving module; the first light-emitting control transistor is used to control whether the first power supply voltage provided by the first power line is transmitted to the first end of the driving module according to the light-emitting control signal on the light-emitting control line.

[0019] Preferably, the second light-emitting control module includes a second light-emitting control transistor, the control electrode of the second light-emitting control transistor is connected to the light-emitting control line, the first electrode of the second light-emitting control transistor is connected to the second terminal of the driving module, and the second electrode of the second light-emitting control transistor is connected to the first terminal of the light-emitting module; the second light-emitting control transistor is used to control whether the driving module transmits driving current to the light-emitting module according to the light-emitting control signal on the light-emitting control line;

[0020] Preferably, the light-emitting module includes a light-emitting element, the first electrode of the light-emitting element is connected to the second light-emitting control module, and the second electrode of the light-emitting element is connected to the second power supply;

[0021] Preferably, the first light-emitting control module is used to control the transmission of a first power supply voltage provided by the first power line to the first terminal of the driving module in response to the light-emitting control signal during the light-emitting phase; the second light-emitting control module is used to control the transmission of driving current to the light-emitting module in response to the light-emitting control signal during the light-emitting phase.

[0022] Optionally, the pixel circuit further includes:

[0023] A data writing module is connected between the data line and the first end of the driving module, and the control end of the data writing module is connected to the third scan line; the data writing module is used to respond to the third scan signal on the third scan line and transmit the data voltage on the data line to the control end of the driving module.

[0024] Preferably, the pixel circuit further includes:

[0025] A threshold compensation module is connected between the second end of the driving module and the control end of the driving module, and the control end of the threshold compensation module is connected to the fourth scan line; the threshold compensation module is used to perform threshold compensation on the driving module in response to the fourth scan signal on the fourth scan line.

[0026] Preferably, the pixel circuit further includes:

[0027] The third reset module is connected between the third reset signal line and the first end of the threshold compensation module, and the control end of the third reset module is connected to the fifth scan line. The third reset module is used to respond to the fifth scan signal on the fifth scan line and transmit the third reset voltage on the third reset signal line to the control end of the drive module through the threshold compensation module.

[0028] Preferably, the pixel circuit further includes:

[0029] A storage module is connected between the first power line and the control terminal of the drive module;

[0030] Preferably, the data writing module is used to respond to the third scan signal on the third scan line during the data writing and threshold compensation phase, and transmit the data voltage through the driving module and the threshold compensation module to the control terminal of the driving module.

[0031] Preferably, the threshold compensation module is used to perform threshold compensation on the driving module in response to the fourth scan signal on the fourth scan line during the data writing and threshold compensation phase.

[0032] Preferably, the third reset module is used in the second reset phase to respond to the fifth scan signal on the fifth scan line and transmit the third reset voltage on the third reset signal line to the control terminal of the drive module through the threshold compensation module.

[0033] Preferably, in a frame, the second reset phase is located before the data writing and threshold compensation phases, and the data writing and threshold compensation phases are located between the light emission phases;

[0034] Preferably, the first reset module is used in the first reset phase to transmit a first reset voltage on the first reset signal line to the second terminal of the driving module in response to a first scan signal on the first scan line; in a frame, the first reset phase is located between the data writing and threshold compensation phase and the light emission phase;

[0035] Preferably, the data writing module includes a data writing transistor, the first electrode of the data writing transistor is connected to the data line, the second electrode of the data writing transistor is connected to the first terminal of the driving module, and the control electrode of the data writing transistor is connected to the third scan line.

[0036] Preferably, the threshold compensation module includes a threshold compensation transistor, the first terminal of the threshold compensation transistor is connected to the second terminal of the driving module, the second terminal of the threshold compensation transistor is connected to the control terminal of the driving module, and the control terminal of the threshold compensation transistor is connected to the fourth scan line.

[0037] Preferably, the third reset module includes a third reset transistor, the first terminal of the third reset transistor is connected to the third reset signal line, the second terminal of the third reset transistor is connected to the first terminal of the threshold compensation module, and the control terminal of the third reset transistor is connected to the fifth scan line;

[0038] Preferably, the threshold compensation transistor is an N-type transistor;

[0039] Preferably, the third reset transistor is an N-type transistor;

[0040] Preferably, the storage module includes a storage capacitor, the first terminal of which is connected to the control terminal of the drive module, and the second terminal of which is connected to the first power line.

[0041] According to another aspect of the present invention, a display panel is provided, the display panel comprising:

[0042] Substrate;

[0043] A first active layer is located on one side of the substrate; the first active layer includes a first active region, which includes a first channel region, a second channel region, and a third channel region that are interconnected.

[0044] A multilayer conductive layer is located on the side of the first active layer away from the substrate; the first active layer and the multilayer conductive layer form at least two pixel circuits, the pixel circuits including a first reset module, the first reset module including a first sub-transistor and a second sub-transistor; the multilayer conductive layer includes a first conductive layer;

[0045] The first scan line is located in the first conductive layer. The orthographic projection of the first scan line on the substrate overlaps with the orthographic projections of the first channel region, the second channel region, and the third channel region on the substrate, respectively.

[0046] Wherein, along the extension direction of the first scan line, for each pair of adjacent pixel circuits, the first channel region is the channel region of the second sub-transistor in one pixel circuit, the third channel region is the channel region of the second sub-transistor in the other pixel circuit, and the second channel region is the channel region of the first sub-transistor in both pixel circuits.

[0047] Optionally, the first scan line extends along a first direction, and the first channel region, the second channel region, and the third channel region are arranged along the first direction;

[0048] Preferably, the first active region further includes a first connecting portion, which extends along the first direction and is connected to the first channel region, the second channel region and the third channel region respectively;

[0049] Preferably, the pixel circuit further includes a driving transistor;

[0050] The first active layer further includes a second active region, the second active region including the channel region of the driving transistor; the gate of the driving transistor is located in the first conductive layer;

[0051] Preferably, the display panel further includes a first connecting line, which is connected between the second terminal of the second sub-transistor and the second terminal of the driving transistor;

[0052] Preferably, the first connecting line is connected to the second terminal of the second sub-transistor through a first via, and the first connecting line is connected to the second terminal of the driving transistor through a second via;

[0053] Preferably, the multilayer conductive layer further includes a second conductive layer, a third conductive layer, and a fourth conductive layer stacked on the side of the first conductive layer away from the substrate;

[0054] The display panel also includes:

[0055] The first reset signal line is located in the third conductive layer;

[0056] The second connection line is located in the fourth conductive layer; the second connection line is connected between the first electrode of the first sub-transistor and the first reset signal line;

[0057] Preferably, the first connecting line is located in the fourth conductive layer;

[0058] Preferably, the orthographic projection of the first reset signal line onto the substrate at least partially overlaps with the orthographic projection of the first scan line onto the substrate;

[0059] Preferably, the second connection line is connected to the first terminal of the first sub-transistor through a third via, and the second connection line is connected to the first reset signal line through a fourth via;

[0060] Preferably, the pixel circuit further includes a second reset transistor, the channel region of the second reset transistor is located in the second active region, and the first scan line partially overlaps with the channel region of the second reset transistor;

[0061] The display panel also includes:

[0062] The second reset signal line includes a first sub-reset line and a second sub-reset line that are interconnected; the second sub-reset line is connected to the first terminal of the second reset transistor.

[0063] Preferably, the second sub-reset line is located in the first conductive layer, the second conductive layer, the third conductive layer, or the fourth conductive layer;

[0064] The orthographic projection of the first sub-reset line onto the substrate overlaps with the orthographic projection of the first active region onto the substrate; the first sub-reset line is located in the second conductive layer, the third conductive layer, or the fourth conductive layer;

[0065] Alternatively, the orthographic projection of the first sub-reset line onto the substrate does not overlap with the orthographic projection of the first active region onto the substrate; the first sub-reset line is located in the first conductive layer, the second conductive layer, the third conductive layer, or the fourth conductive layer;

[0066] The first sub-reset line and the second sub-reset line are configured on different layers; or, the first sub-reset line and the second sub-reset line are configured on the same layer.

[0067] Optionally, the first channel area and the third channel area are arranged along a first direction, and the first channel area and the third channel area are symmetrically arranged; the second channel area is located on the line of symmetry between the first channel area and the third channel area;

[0068] The first scan line includes a main body extending in a first direction and a first extension and a second extension extending in a second direction;

[0069] The orthographic projection of the first extension on the substrate overlaps with the orthographic projection of the first channel region on the substrate, the orthographic projection of the second extension on the substrate overlaps with the orthographic projection of the third channel region on the substrate, and the orthographic projection of the main body on the substrate overlaps with the orthographic projection of the second channel region on the substrate.

[0070] Preferably, the pixel circuit further includes a driving transistor;

[0071] The first active layer further includes a second active region, the second active region including the channel region of the driving transistor; the gate of the driving transistor is located in the first conductive layer;

[0072] Preferably, the display panel further includes a first connecting line, which is connected between the second terminal of the second sub-transistor and the second terminal of the driving transistor;

[0073] Preferably, the first connecting line is connected to the second terminal of the second sub-transistor through a first via, and the first connecting line is connected to the second terminal of the driving transistor through a second via;

[0074] Preferably, the multilayer conductive layer further includes a second conductive layer, a third conductive layer, and a fourth conductive layer stacked on the side of the first conductive layer away from the substrate;

[0075] The display panel also includes:

[0076] The first reset signal line is located in the third conductive layer;

[0077] The second connection line is located in the fourth conductive layer; the second connection line is connected between the first electrode of the first sub-transistor and the first reset signal line;

[0078] Preferably, the first connecting line is located in the fourth conductive layer;

[0079] Preferably, the second connection line is connected to the first terminal of the first sub-transistor through a third via, and the second connection line is connected to the first reset signal line through a fourth via;

[0080] Preferably, the pixel circuit further includes a second reset transistor, the channel region of the second reset transistor is located in the second active region, and the first scan line partially overlaps with the channel region of the second reset transistor;

[0081] The display panel also includes:

[0082] The second reset signal line includes a first sub-reset line and a second sub-reset line that are interconnected; the second sub-reset line is connected to the first terminal of the second reset transistor.

[0083] Preferably, the first sub-reset line is located in the first conductive layer, the second conductive layer, the third conductive layer or the fourth conductive layer, and the second sub-reset line is located in the first conductive layer, the second conductive layer, the third conductive layer or the fourth conductive layer;

[0084] The first sub-reset line and the second sub-reset line are configured on different layers; or, the first sub-reset line and the second sub-reset line are configured on the same layer.

[0085] Optionally, the pixel circuit further includes a first light-emitting control transistor, and the display panel further includes a light-emitting control line, a second connecting line, a power connection line, and a first power line;

[0086] The channel region of the first light-emitting control transistor is located in the second active region, and the projection of the light-emitting control line onto the substrate partially overlaps with the channel region of the first light-emitting control transistor.

[0087] The second terminal of the first light-emitting control transistor is connected to the first terminal of the driving transistor;

[0088] The display panel further includes a third connecting line, which is connected between the first electrode of the first light-emitting control transistor and the power connection line; the power connection line is connected to the first power line.

[0089] Preferably, the third connection line is connected to the first electrode of the first light-emitting control transistor through the fifth via, and the third connection line is connected to the power connection line through the sixth via;

[0090] Preferably, along the extension direction of the first scan line, every two adjacent pixel circuits share one third connection line;

[0091] Preferably, along the extension direction of the first scan line, every two adjacent pixel circuits share one fifth via.

[0092] Preferably, along the extension direction of the first scan line, at least a portion of every two adjacent pixel circuits is symmetrical about the third connection line;

[0093] Preferably, the pixel circuit further includes a storage capacitor, which includes a first capacitor plate and a second capacitor plate, and the gate of the driving transistor is multiplexed to the first capacitor plate.

[0094] The second capacitor plate is connected to the third connecting line through the seventh through hole;

[0095] Preferably, the pixel circuit further includes a second light-emitting control transistor, the channel region of the second light-emitting control transistor is located in the second active region, and the projection of the light-emitting control line onto the substrate partially overlaps with the channel region of the second light-emitting control transistor;

[0096] The first terminal of the second light-emitting control transistor is connected to the second terminal of the driving transistor, and the second terminal of the second light-emitting control transistor is connected to the first terminal of the light-emitting element through the first conductive part;

[0097] Preferably, the pixel circuit further includes a threshold compensation transistor, and the display panel further includes:

[0098] The fourth scan line; the orthographic projection of the fourth scan line onto the substrate overlaps with a portion of the channel region of the threshold compensation transistor;

[0099] The second active layer is located on the side of the first conductive layer away from the substrate; the channel region of the threshold compensation transistor is located in the second active layer;

[0100] A fourth connection line is located on the side of the second active layer away from the substrate; the fourth connection line is connected between the second electrode of the threshold compensation transistor and the gate of the driving transistor;

[0101] The fifth connection line is located on the side of the second active layer away from the substrate; the fifth connection line is connected between the first electrode of the threshold compensation transistor and the second electrode of the driving transistor;

[0102] Preferably, the first active layer comprises a polycrystalline silicon semiconductor material, and the second active layer comprises an oxide semiconductor material;

[0103] Preferably, the orthographic projection of the third connecting line onto the substrate overlaps with the orthographic projection of the fourth scanning line onto the substrate.

[0104] Preferably, the fourth connection line is connected to the second terminal of the threshold compensation transistor through the eighth via, and the fourth connection line is connected to the gate of the driving transistor through the ninth via;

[0105] The fifth connection line is connected to the first terminal of the threshold compensation transistor through the tenth via, and the fifth connection line is connected to the second terminal of the driving transistor through the eleventh via;

[0106] Preferably, the orthographic projection of the eleventh via on the substrate coincides with the orthographic projection of the second via on the substrate;

[0107] Preferably, the light-emitting control line and the first capacitor plate are located in the first conductive layer;

[0108] Preferably, the multilayer conductive layer further includes a fifth conductive layer and a sixth conductive layer stacked on the side of the fourth conductive layer away from the substrate;

[0109] The second capacitor plate is located in the second conductive layer;

[0110] The fourth scan line includes a first sub-line located in the second conductive layer and a second sub-line located in the third conductive layer, wherein the first sub-line is connected to the second sub-line;

[0111] The third connecting line, the fourth connecting line, and the fifth connecting line are located in the fourth conductive layer;

[0112] The power connection line is located in the fifth conductive layer;

[0113] The first power line is located in the sixth conductive layer;

[0114] The first conductive portion includes a first sub-portion located in the fourth conductive layer, a second sub-portion located in the fifth conductive layer, and a third sub-portion located in the sixth conductive layer, and the first sub-portion, the second sub-portion, and the third sub-portion are interconnected.

[0115] Optionally, the pixel circuit further includes a data writing transistor; the channel region of the data writing transistor is located in the second active region; the second terminal of the data writing transistor is connected to the first terminal of the driving transistor;

[0116] The display panel also includes:

[0117] The third scan line is located in the first conductive layer; the orthographic projection of the third scan line on the substrate overlaps with the channel region of the data writing transistor.

[0118] The sixth connecting line is located in the fourth conductive layer;

[0119] The seventh connecting line is located in the fifth conductive layer;

[0120] A data line is located in the sixth conductive layer; the sixth connection line is connected between the first electrode of the data writing transistor and the seventh connection line, and the seventh connection line is connected to the data line.

[0121] Preferably, the orthographic projection of the sixth connecting line onto the substrate overlaps with the orthographic projection of the third scanning line onto the substrate.

[0122] Preferably, the orthographic projection of the sixth connecting line onto the substrate overlaps with the orthographic projection of the seventh connecting line onto the substrate.

[0123] Preferably, the sixth connection line is connected to the seventh connection line through the twelfth via, the sixth connection line is connected to the first terminal of the data writing transistor through the thirteenth via, and the seventh connection line is connected to the data line through the fourteenth via.

[0124] Preferably, the pixel circuit further includes a third reset transistor, the channel region of which is located in the second active layer; the second terminal of the third reset transistor is connected to the first terminal of the threshold compensation transistor.

[0125] The display panel also includes:

[0126] The fifth scan line, the orthogonal projection of the fifth scan line onto the substrate overlaps with the orthogonal projection of the channel region of the third reset transistor onto the substrate;

[0127] The third reset signal line includes a third sub-reset line and a fourth sub-reset line that are interconnected; the fourth sub-reset line is connected to the first terminal of the third reset transistor.

[0128] Preferably, the fifth scan line includes a third sub-line located in the second conductive layer and a fourth sub-line located in the third conductive layer, wherein the third sub-line is connected to the fourth sub-line;

[0129] Preferably, the orthographic projection of the fourth sub-reset line onto the substrate overlaps with the orthographic projection of the third sub-line onto the substrate.

[0130] Preferably, the third sub-reset line is located in the first conductive layer, the second conductive layer, the third conductive layer or the fourth conductive layer, and the fourth sub-reset line is located in the first conductive layer, the second conductive layer, the third conductive layer or the fourth conductive layer;

[0131] The third sub-reset line and the fourth sub-reset line are disposed on different layers; or, the third sub-reset line and the fourth sub-reset line are disposed on the same layer.

[0132] According to another aspect of the present invention, a display device is provided, the display device comprising the display panel described in any embodiment of the present invention.

[0133] The technical solution of this invention, by setting the first reset module to include a first sub-transistor and a second sub-transistor, and along the extension direction of the first scan line, the first sub-transistor in every two adjacent pixel circuits is shared, that is, every two adjacent pixel circuits share one first sub-transistor, which can reduce the number of transistors in each pixel circuit, thereby reducing the space occupied by each pixel circuit, which is beneficial to improving the pixel density of the display panel, and thus improving the performance of the display panel.

[0134] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0135] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0136] Figure 1 This is a schematic diagram of the circuit structure of a display panel provided in an embodiment of the present invention;

[0137] Figure 2 This is a schematic diagram of the circuit structure of another display panel provided in an embodiment of the present invention;

[0138] Figure 3 This is a schematic diagram of the circuit structure of another display panel provided in an embodiment of the present invention;

[0139] Figure 4 This is a schematic diagram of the circuit structure of another display panel provided in an embodiment of the present invention;

[0140] Figure 5 This is a schematic diagram of the circuit structure of another display panel provided in an embodiment of the present invention;

[0141] Figure 6 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0142] Figure 7 This is a schematic diagram of the layout structure of a display panel provided in an embodiment of the present invention;

[0143] Figure 8This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0144] Figure 9 This is a schematic diagram of the layout structure of a first active layer provided in an embodiment of the present invention;

[0145] Figure 10 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0146] Figure 11 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0147] Figure 12 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0148] Figure 13 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0149] Figure 14 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0150] Figure 15 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0151] Figure 16 yes Figure 12 A sectional view along the e1-e2 direction;

[0152] Figure 17 yes Figure 12 A sectional view along the e3-e4 direction;

[0153] Figure 18 yes Figure 14 A sectional view along the e5-e6 direction;

[0154] Figure 19 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0155] Figure 20 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0156] Figure 21 yes Figure 19 A sectional view along the e7-e8 direction;

[0157] Figure 22 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0158] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0159] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0160] As mentioned in the background section, the performance of current OLED display products needs improvement. The inventors have discovered that this problem arises because OLED display products include a display panel, which in turn includes pixel circuits. These pixel circuits contain transistors. To reduce leakage current in the pixel circuits, some transistors are designed as dual-gate transistors. However, dual-gate transistors occupy a large amount of space, which is not conducive to achieving high pixel density. Furthermore, the display panel also includes initialization signal lines. To reduce the impedance on these initialization signal lines, some are designed as meshes, resulting in a large number of traces, which is also detrimental to achieving high pixel density, thus affecting the performance of the display panel.

[0161] Figure 1 This is a schematic diagram of the circuit structure of a display panel provided in an embodiment of the present invention, for reference. Figure 1 The display panel includes: at least two pixel circuits 100; the pixel circuits 100 include:

[0162] The driving module 110 and the first light-emitting control module 120 are connected between the first power line VDD and the first end of the first light-emitting control module 120.

[0163] The second light-emitting control module 130 and the light-emitting module 140 are connected in series between the second terminal of the drive module 110 and the second power supply VSS.

[0164] The first reset module 150 is connected between the first reset signal line Vref1 and the second terminal of the drive module 110. The control terminal of the first reset module 150 is connected to the first scan line S1. The first reset module 150 is used to respond to the first scan signal on the first scan line S1 and transmit the first reset voltage on the first reset signal line Vref1 to the second terminal of the drive module 110.

[0165] The first reset module 150 includes a first sub-transistor T1-1 and a second sub-transistor T1-2. Along the extension direction of the first scan line S1, each pair of adjacent pixel circuits 100 shares one first sub-transistor T1-1.

[0166] In this embodiment, the first power line VDD can provide a first power supply voltage, and the second power line VSS can provide a second power supply voltage. For example, the first power supply voltage may be positive and the second power supply voltage may be negative; or the first power supply voltage may be negative and the second power supply voltage may be positive. This embodiment does not limit the specific voltage. The first light-emitting control module 120 can control whether the first power supply voltage is transmitted to the first terminal of the driving module 110, and the second light-emitting control module 130 can control whether the driving current generated by the driving module 110 is transmitted to the light-emitting module 140. For example, the light-emitting module 140 includes an organic light-emitting diode (OLED), and the light-emitting module 140 can emit light in response to the driving current.

[0167] When the first reset module 150 is turned on, it can transmit the first reset voltage on the first reset signal line Vref1 to the second terminal of the driver module 110 to reset the second terminal of the driver module 110. This avoids the bias problem caused by the driver module 110 being turned on for a long time when the refresh rate of the display panel is low, and prevents the characteristics of the driver module 110 from being affected and affecting the generated drive current. It can improve the problem of image ghosting caused by the hysteresis effect of the driver module 110 when the refresh rate of the display panel is switched. For example, before the light emission stage (e.g., the first reset stage), the first scan signal on the first scan line S1 controls the first reset module 150 to be turned on, so that the first reset module 150 transmits the first reset voltage on the first reset signal line Vref1 to the second terminal of the driver module 110 to reset the second terminal of the driver module 110. During the light-emitting stage, the first light-emitting control module 120 and the second light-emitting control module 130 are turned on, so that the first power line VDD, the first light-emitting control module 120, the driving module 110, the second light-emitting control module 130, the light-emitting module 140 and the second power supply VSS form a current path, so that the driving module 110 generates a driving current and the light-emitting module 140 responds to the driving current to emit light.

[0168] Specifically, by setting the first reset module 150 to include a first sub-transistor T1-1 and a second sub-transistor T1-2, the first sub-transistor T1-1 in every two adjacent pixel circuits 100 is shared along the extension direction X of the first scan line S1. That is, every two adjacent pixel circuits 100 share one first sub-transistor T1-1, which can reduce the number of transistors in each pixel circuit 100, thereby reducing the space occupied by each pixel circuit 100. This is beneficial to improving the pixel density of the display panel, enabling the display panel to display images at a higher density, facilitating the achievement of higher fidelity, thereby improving the display effect of the display panel, and further improving the performance of the display panel.

[0169] Furthermore, the first reset modules 150 of all pixel circuits 100 arranged along the extension direction X of the first scan line S1 are all connected to the same first scan line S1, meaning that the timing of the first reset modules 150 of all pixel circuits 100 arranged along the extension direction X of the first scan line S1 is the same. By setting the first sub-transistor T1-1 in every two adjacent pixel circuits 100 to be shared along the extension direction X of the first scan line S1, it is convenient to realize the second terminal of the row-by-row reset drive module 110.

[0170] The technical solution of this embodiment, by setting the first reset module to include a first sub-transistor and a second sub-transistor, and along the extension direction of the first scan line, the first sub-transistor in every two adjacent pixel circuits is shared, that is, every two adjacent pixel circuits share one first sub-transistor, which can reduce the number of transistors in each pixel circuit, thereby reducing the space occupied by each pixel circuit, which is beneficial to improving the pixel density of the display panel, and thus improving the performance of the display panel.

[0171] Based on the above technical solutions, optionally, refer to Figure 1 The first sub-transistor T1-1 is connected between the first reset signal line Vref1 and the first terminal of the second sub-transistor T1-2, and the second terminal of the second sub-transistor T1-2 is connected to the second terminal of the drive module 110.

[0172] Specifically, the gate of the first sub-transistor T1-1 and the gate of the second sub-transistor T1-2 are connected to the first scan line S1. When the first scan signal on the first scan line S1 controls the first sub-transistor T1-1 and the second sub-transistor T1-2 to be turned on, the first sub-transistor T1-1 transmits the first reset voltage on the first reset signal line Vref1 through the second sub-transistor T1-2 to the second terminal of the drive module 110, thereby resetting the second terminal of the drive module 110.

[0173] Based on the above technical solutions, the following description may also include the structure of the pixel circuit 100, but this is not intended to limit the scope of this application.

[0174] Figure 2 This is a schematic diagram of the circuit structure of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 2 The pixel circuit also includes:

[0175] The second reset module 160 is connected between the second reset signal line Vref2 and the first end of the light-emitting module 140. The control terminal of the second reset module 160 is connected to the second scan line. The second reset module 160 is used to respond to the second scan signal on the second scan line S2 and transmit the second reset voltage on the second reset signal line Vref2 to the first end of the light-emitting module 140.

[0176] Specifically, when the second scan signal on the second scan line S2 controls the second reset module 160 to be turned on, the second reset module 160 transmits the second reset voltage on the second reset signal line Vref2 to the first end of the light-emitting module 140 to reset the first end of the light-emitting module 140.

[0177] Optionally, the first scan line S1 can be multiplexed as the second scan line S2. This reduces the number of scan lines, which helps to reduce the space occupied by the scan lines, facilitates the increase of pixel density of the display panel, and thus improves the performance of the display panel.

[0178] Figure 3 This is a schematic diagram of the circuit structure of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 3 The second reset module 160 includes a second reset transistor T2. The control electrode of the second reset transistor T2 is connected to the second scan line S2. The first electrode of the second reset transistor T2 is connected to the second reset signal line Vref2. The second electrode of the second reset transistor T2 is connected to the first end of the light-emitting module 140.

[0179] In this embodiment, the first electrode of the second reset transistor T2 is the source, and the second electrode of the second reset transistor T2 is the drain; or, the first electrode of the second reset transistor T2 is the drain, and the second electrode of the second reset transistor T2 is the source. This embodiment does not limit the specific electrode.

[0180] Specifically, when the second reset transistor T2 is turned on, it can transmit the second reset voltage on the second reset signal line Vref2 to the first terminal of the light-emitting module 140, resetting the first terminal of the light-emitting module 140 and eliminating residual charge from the previous frame, thus improving the accuracy of light emission from the light-emitting module 140. The second reset transistor T2 can be either an N-type transistor or a P-type transistor. Figure 3 The diagram shows the case where the second reset transistor T2 is a P-type transistor, but it is not limited to that case.

[0181] Optionally, the first reset module 150 is used to transmit the first reset voltage on the first reset signal line Vref1 to the second terminal of the drive module 110 in response to the first scan signal on the first scan line S1 during the first reset phase.

[0182] The second reset module 160 is used in the first reset phase to transmit the second reset voltage on the second reset signal line Vref2 to the first terminal of the light-emitting module 140 in response to the second scan signal on the second scan line S2.

[0183] Specifically, both the first reset module 150 and the second reset module 160 are turned on during the first reset phase, meaning that the turn-on timing of the first reset module 150 and the second reset module 160 is the same, which facilitates the reuse of the first scan line S1 as the second scan line S2.

[0184] Optionally, refer to Figure 3 The driving module 110 includes a driving transistor T3. The first terminal of the driving transistor T3 is connected to the first light-emitting control module 120, and the second terminal of the driving transistor T3 is connected to the second light-emitting control module 130. The driving transistor T3 can generate a driving current to drive the light-emitting module 140 to emit light. The driving transistor T3 can be an N-type transistor or a P-type transistor. Figure 3 The example shows a case where the driving transistor T3 is a P-type transistor, but this is not a limitation. In this example, the first electrode of the driving transistor T3 is the source, and the second electrode is the drain; alternatively, the first electrode of the driving transistor T3 is the drain, and the second electrode is the source. This embodiment is not limited to this.

[0185] Optionally, refer to Figure 3 The first light-emitting control module 120 includes a first light-emitting control transistor T4. The control electrode of the first light-emitting control transistor T4 is connected to the light-emitting control line EM, the first electrode of the first light-emitting control transistor T4 is connected to the first power supply line VDD, and the second electrode of the first light-emitting control transistor T4 is connected to the first terminal of the driving module 110. The first light-emitting control transistor T4 is used to control whether the first power supply voltage provided by the first power supply line VDD is transmitted to the first terminal of the driving module 110 according to the light-emitting control signal on the light-emitting control line EM. The first electrode of the first light-emitting control transistor T4 is the source, and the second electrode is the drain; alternatively, the first electrode of the first light-emitting control transistor T4 is the drain, and the second electrode is the source. This embodiment does not limit the specific application of this method.

[0186] Specifically, the first light-emitting control transistor T4 can be either an N-type transistor or a P-type transistor. Figure 3The illustration shows the case where the first light-emitting control transistor T4 is a P-type transistor, but this is not a limitation. When the first light-emitting control transistor T4 is turned on, it transmits the first power supply voltage on the first power supply line VDD to the first terminal of the drive module 110, facilitating the generation of drive current by the drive module 110.

[0187] Optionally, refer to Figure 3 The second light-emitting control module 130 includes a second light-emitting control transistor T5. The control electrode of the second light-emitting control transistor T5 is connected to the light-emitting control line EM. The first electrode of the second light-emitting control transistor T5 is connected to the second terminal of the driving module 110, and the second electrode of the second light-emitting control transistor T5 is connected to the first terminal of the light-emitting module 140. The second light-emitting control transistor T5 is used to control whether the driving module 110 transmits driving current to the light-emitting module 140 according to the light-emitting control signal on the light-emitting control line EM. The first electrode of the second light-emitting control transistor T5 is the source, and the second electrode is the drain; alternatively, the first electrode of the second light-emitting control transistor T5 is the drain, and the second electrode is the source. This embodiment does not limit the specific application of this method.

[0188] Specifically, the second light-emitting control transistor T5 can be either an N-type transistor or a P-type transistor. Figure 3 The diagram illustrates the case where the second light-emitting control transistor T5 is a P-type transistor, but this is not a limitation. When the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned on, the first power line VDD, the first light-emitting control transistor T4, the driving module 110, the second light-emitting control transistor T5, the light-emitting module 140, and the second power supply VSS form a current path, causing the driving module 110 to generate a driving current, which drives the light-emitting module 140 to emit light.

[0189] Optionally, refer to Figure 3 The light-emitting module 140 includes a light-emitting element OLED. The first electrode of the light-emitting element OLED is connected to the second light-emitting control module 130, and the second electrode of the light-emitting element OLED is connected to the second power supply VSS. The light-emitting element OLED is an organic light-emitting diode. When the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned on, the driving transistor T3 generates a driving current, driving the light-emitting element OLED to emit light.

[0190] Optionally, the first light-emitting control module 120, in response to the light-emitting control signal during the light-emitting phase, controls the first power supply voltage provided by the first power line VDD to be transmitted to the first terminal of the driving module 110; the second light-emitting control module 130, in response to the light-emitting control signal during the light-emitting phase, controls the driving module 110 to transmit driving current to the light-emitting module 140. Thus, the driving module 110 generates driving current during the light-emitting phase, driving the OLED light-emitting element to emit light.

[0191] Based on the above technical solutions, Figure 4 This is a schematic diagram of the circuit structure of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 4 The pixel circuit 100 also includes:

[0192] The data writing module 170 is connected between the data line Data and the first end of the drive module 110. The control terminal of the data writing module 170 is connected to the third scan line S3. The data writing module 170 is used to respond to the third scan signal on the third scan line S3 and transmit the data voltage on the data line Data to the control terminal of the drive module 110.

[0193] Specifically, during the data writing stage, the third scan signal on the third scan line S3 controls the data writing module 170 to be turned on, so that the data writing module 170 transmits the data voltage on the data line Data to the control terminal of the drive module 110, so that the drive module 110 generates a drive current according to the data voltage.

[0194] Optionally, refer to Figure 4 The pixel circuit 100 also includes:

[0195] A threshold compensation module 180 is connected between the second end of the drive module 110 and the control end of the drive module 110. The control end of the threshold compensation module 180 is connected to the fourth scan line S4. The threshold compensation module 180 is used to perform threshold compensation on the drive module 110 in response to the fourth scan signal on the fourth scan line S4.

[0196] Specifically, when the driving module 110 is turned on, the third scan signal on the third scan line S3 controls the data writing module 170 to be turned on, and the fourth scan signal on the fourth scan line S4 controls the threshold compensation module 180 to be turned on, the data writing module 170 transmits the data voltage on the data line Data through the driving module 110 and the threshold compensation module 180 to the control terminal of the driving module 110. This makes the voltage of the driving module 110 change to a voltage related to the data voltage and the threshold voltage of the transistor in the driving module 110, thus realizing data writing and threshold compensation. This allows the driving module 110 to generate a driving current based on the compensated data voltage, ensuring that fluctuations in the threshold voltage of the transistor in the driving module 110 do not affect the driving current generated by the driving module 110, thereby improving the stability of the driving current and enabling the OLED to emit light stably.

[0197] Optionally, refer to Figure 4 The pixel circuit 100 also includes:

[0198] The third reset module 190 is connected between the third reset signal line Vref3 and the first terminal of the threshold compensation module 180. The control terminal of the third reset module 190 is connected to the fifth scan line S5. The third reset module 190 is used to respond to the fifth scan signal on the fifth scan line S5 and transmit the third reset voltage on the third reset signal line Vref3 to the control terminal of the drive module 110 through the threshold compensation module 180.

[0199] Specifically, when the fifth scan signal on the fifth scan line S5 controls the third reset module 190 to be turned on, and the fourth scan signal on the fourth scan line S4 controls the threshold compensation module 180 to be turned on, the third reset module 190 transmits the third reset voltage on the third reset signal line Vref3 to the control terminal of the drive module 110 through the threshold compensation module 180 to reset the control terminal of the drive module 110.

[0200] Optionally, refer to Figure 4 The pixel circuit 100 also includes:

[0201] Storage module 191 is connected between the first power line VDD and the control terminal of drive module 110.

[0202] Specifically, the first power line VDD provides a fixed voltage, that is, one end of the storage module 191 is at a fixed voltage, which can maintain the voltage of the control terminal of the drive module 110 and avoid the situation where the voltage fluctuation of the control terminal of the drive module 110 causes the drive current fluctuation, thereby further improving the stability of the drive current.

[0203] Optionally, refer to Figure 4The data writing module 170 is used to respond to the third scan signal on the third scan line S3 during the data writing and threshold compensation stages, and transmit the data voltage through the drive module 110 and the threshold compensation module 180 to the control terminal of the drive module 110.

[0204] Optionally, refer to Figure 4 The threshold compensation module 180 is used to perform threshold compensation on the drive module 110 in response to the fourth scan signal on the fourth scan line S4 during the data writing and threshold compensation phase.

[0205] Specifically, for example, the data writing stage and the threshold compensation stage are combined into one stage. During the data writing and threshold compensation stages, the driving module 110 is turned on, the third scan signal on the third scan line S3 controls the data writing module 170 to be turned on, and the fourth scan signal on the fourth scan line S4 controls the threshold compensation module 180 to be turned on. The data writing module 170 transmits the data voltage on the data line Data to the first terminal of the driving module 110. The data voltage charges the control terminal of the driving module 110 through the driving module 110 and the threshold compensation module 180, making the voltage of the driving module 110 related to the data voltage and the threshold voltage of the transistor in the driving module 110, thus realizing data writing and threshold compensation. This allows the driving module 110 to generate a driving current based on the compensated data voltage, ensuring that fluctuations in the threshold voltage of the transistor in the driving module 110 do not affect the driving current generated by the driving module 110, thereby improving the stability of the driving current and enabling the OLED to emit light stably.

[0206] Optionally, the third reset module 190 is used in the second reset phase to respond to the fifth scan signal on the fifth scan line S5 and transmit the third reset voltage on the third reset signal line Vref3 to the control terminal of the drive module 110 through the threshold compensation module 180.

[0207] Specifically, in the second reset phase, the fifth scan signal on the fifth scan line S5 controls the third reset module 190 to be turned on, and the fourth scan signal on the fourth scan line S4 controls the threshold compensation module 180 to be turned on. The third reset module 190 transmits the third reset voltage on the third reset signal line Vref3 to the control terminal of the drive module 110 through the threshold compensation module 180 to reset the control terminal of the drive module 110.

[0208] Optionally, in a frame, the second reset phase is located before the data writing and threshold compensation phases, and the data writing and threshold compensation phases are located between the light emission phases. This configuration allows the control terminal of the driver module 110 to be reset first, followed by data writing and threshold compensation, preventing residual voltage at the control terminal of the driver module 110 from affecting the written data voltage. This enables the driver module 110 to better generate drive current based on the threshold-compensated data voltage during the light emission phase.

[0209] Optionally, the first reset module 150 is configured to, in response to the first scan signal on the first scan line S1, transmit the first reset voltage on the first reset signal line Vref1 to the second terminal of the driving module 110 during the first reset phase. In one frame, the first reset phase is located between the data writing and threshold compensation phase and the light emission phase. This configuration allows the second terminal of the driving module 110 and the first terminal of the light emission module 140 to be reset before the light emission phase, preventing the bias state of the driving module 110 from affecting the driving current generated by the driving module 110, and preventing the residual voltage at the first terminal of the light emission module 140 from affecting the brightness of the light emission module 140, thereby improving the display effect of the display panel.

[0210] Figure 5 This is a schematic diagram of the circuit structure of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 5 The data writing module 170 includes a data writing transistor T6. The first terminal of the data writing transistor T6 is connected to the data line Data, the second terminal of the data writing transistor T6 is connected to the first terminal of the driving module 110, and the control terminal of the data writing transistor T6 is connected to the third scan line S3. The first terminal of the data writing transistor T6 is the source, and the second terminal is the drain; alternatively, the first terminal of the data writing transistor T6 is the drain, and the second terminal is the source. This embodiment does not impose a limitation on this configuration.

[0211] The data writing transistor T6 can be either an N-type transistor or a P-type transistor. Figure 5 The diagram illustrates the case where the data write transistor T6 is a P-type transistor, but this is not a limitation. During the data write phase and the threshold compensation phase, the data write transistor T6 is turned on, transferring the data voltage on the data line Data to the control electrode (gate) of the drive transistor T3.

[0212] Optionally, refer to Figure 5The threshold compensation module 180 includes a threshold compensation transistor T7. The first terminal of the threshold compensation transistor T7 is connected to the second terminal of the driving module 110, the second terminal of the threshold compensation transistor T7 is connected to the control terminal of the driving module 110, and the control terminal of the threshold compensation transistor T7 is connected to the fourth scan line S4. The first terminal of the threshold compensation transistor T7 is the source, and the second terminal is the drain; alternatively, the first terminal of the threshold compensation transistor T7 is the drain, and the second terminal is the source. This embodiment does not impose a limitation on this.

[0213] Specifically, the driving module 110 includes a driving transistor T3, the first terminal of a threshold compensation transistor T7 is connected to the second terminal of the driving transistor T3, and the second terminal of the threshold compensation transistor T7 is connected to the control terminal (gate) of the driving transistor T3.

[0214] During the data writing and threshold compensation stages, the driving transistor T3 is turned on, the data writing transistor T6 is turned on, and the threshold compensation transistor T7 is turned on. The data writing transistor T6 transmits the data voltage on the data line Data through the driving transistor T3 and the threshold compensation transistor T7 to the control electrode (gate) of the driving transistor T3. In other words, the data voltage on the data line Data is transmitted to the control electrode (gate) of the driving transistor T3 after threshold compensation, thus realizing data writing and threshold compensation.

[0215] Optionally, refer to Figure 5 The third reset module 190 includes a third reset transistor T8. The first terminal of the third reset transistor T8 is connected to the third reset signal line Vref3, the second terminal of the third reset transistor T8 is connected to the first terminal of the threshold compensation module 180, and the control terminal of the third reset transistor T8 is connected to the fifth scan line S5. The first terminal of the third reset transistor T8 is the source, and the third reset transistor T8 is the drain; alternatively, the first terminal of the third reset transistor T8 is the drain, and the second terminal of the third reset transistor T8 is the source. This embodiment does not impose a limitation on this.

[0216] Specifically, when the fifth scan signal on the fifth scan line S5 controls the third reset transistor T8 to turn on, and the fourth scan signal on the fourth scan line S4 controls the threshold compensation transistor T7 to turn on, the third reset transistor T8 transmits the third reset voltage on the third reset signal line Vref3 through the threshold compensation transistor T7 to the control electrode (gate) of the driving transistor T3, thereby resetting the control electrode (gate) of the driving transistor T3.

[0217] Optionally, refer to Figure 5 The threshold compensation transistor T7 is an N-type transistor. This configuration reduces the leakage current at the gate of the drive transistor T3, thereby making the drive current generated by the drive transistor T3 more stable.

[0218] Optionally, refer to Figure 5 The third reset transistor T8 is an N-type transistor. This configuration reduces the leakage current at the gate of the further driving transistor T3, thereby making the driving current generated by the driving transistor T3 more stable.

[0219] Optionally, refer to Figure 5 The storage module 191 includes a storage capacitor Cst. The first terminal of the storage capacitor Cst is connected to the control terminal of the drive module 110, and the second terminal of the storage capacitor Cst is connected to the first power supply line VDD. In this way, the storage capacitor Cst can maintain the voltage of the control terminal (gate) of the drive transistor T3, making the drive current more stable.

[0220] Figure 6 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention. The following is in conjunction with... Figure 5 The circuit structure of the pixel circuit 100 shown and Figure 6 The timing diagram of the pixel circuit shown illustrates the operation of the pixel circuit, but is not intended to limit this application.

[0221] like Figure 5 and Figure 6 As shown, the working process of the pixel circuit includes the following stages.

[0222] During the second reset phase t1, the fifth scan signal Scan5 on the fifth scan line S5 is high, and the third reset transistor T8 is turned on. The fourth scan signal Scan4 on the fourth scan line S4 is high, and the threshold compensation transistor T7 is turned on. The third reset transistor T8 transmits the third reset voltage on the third reset signal line Vref3 through the threshold compensation transistor T7 to the control electrode (gate) of the driving transistor T3, thereby resetting the control electrode (gate) of the driving transistor T3 and controlling the driving transistor T3 to turn on.

[0223] During the data writing and threshold compensation phase t2, the driving transistor T3 is turned on. The fourth scan signal Scan4 on the fourth scan line S4 is high, and the threshold compensation transistor T7 is turned on. The third scan signal Scan3 on the third scan line S3 is low, and the data writing transistor T6 is turned on. The data writing transistor T6 transmits the data voltage on the data line Data through the driving transistor T3 and the threshold compensation transistor T7, and after threshold compensation, transmits the data voltage on the data line Data to the control electrode (gate) of the driving transistor T3, thus realizing data writing and threshold compensation.

[0224] During the first reset phase t3, the second scan signal Scan2 on the second scan line S2 and the first scan signal Scan1 on the first scan line S1 are at low levels. The second reset transistor T2 is turned on, and the first sub-transistor T1-1 and the second sub-transistor T1-2 are also turned on. The second reset transistor T2 transmits the second reset voltage on the second reset signal line Vref2 to the first electrode of the light-emitting element OLED, resetting the first electrode of the OLED. The first sub-transistor T1-1 transmits the first reset voltage on the first reset signal line Vref1 through the second sub-transistor T1-2 to the second electrode of the driving transistor T3, resetting the second electrode of the driving transistor T3.

[0225] During the light-emitting stage t4, the light-emitting control signal Em on the light-emitting control line EM is at a low level, and the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned on. The first power line VDD, the first light-emitting control transistor T4, the driving transistor T3, the second light-emitting control transistor T5, the light-emitting element OLED, and the second power supply VSS form a current path, which causes the driving transistor T3 to generate a driving current, driving the light-emitting element OLED to emit light.

[0226] This invention also provides a display panel. Figure 7 This is a schematic diagram of the layout structure of a display panel provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of another display panel layout structure provided in an embodiment of the present invention, for reference. Figure 7 or Figure 8 The display panel includes:

[0227] Substrate 101;

[0228] The first active layer 102 is located on one side of the substrate 101; the first active layer 102 includes a first active region 1021, and the first active region 1021 includes a first channel region A1, a second channel region A2 and a third channel region A3 that are interconnected.

[0229] A multilayer conductive layer is located on the side of the first active layer 102 away from the substrate 101; the first active layer 192 and the multilayer conductive layer form at least two pixel circuits 100, each pixel circuit 100 including a first reset module 150, the first reset module 150 including a first sub-transistor T1-1 and a second sub-transistor T1-2; the multilayer conductive layer includes a first conductive layer M1.

[0230] The first scan line S1 is located in the first conductive layer M1. The orthographic projection of the first scan line S1 on the substrate 101 overlaps with the orthographic projections of the first channel region A1, the second channel region A2, and the third channel region A3 on the substrate 101, respectively.

[0231] Wherein, along the extension direction X of the first scan line S1, for each pair of adjacent pixel circuits 100, the first channel region A1 is the channel region of the second sub-transistor T1-2 in one of the pixel circuits 100, the third channel region A3 is the channel region of the second sub-transistor T1-2 in the other pixel circuit 100, and the second channel region A2 is the channel region of the first sub-transistor T1-1 in both pixel circuits 100.

[0232] The substrate 101 serves as a support, protector, and buffer. The substrate 101 can be a flexible substrate or a rigid substrate; this embodiment does not limit the specific substrate. The first active layer 102 can include a polycrystalline silicon semiconductor material. The first active region 1021 can be, for example,... Figure 7 The "W" shape shown can also be as follows: Figure 8 The "T" shape shown.

[0233] Specifically, the orthographic projection of the first scan line S1 onto the substrate 101 overlaps with the orthographic projection of the first channel region A1 onto the substrate 101, forming the gate of the second sub-transistor T1-2 in one of every two adjacent pixel circuits 100. The orthographic projection of the first scan line S1 onto the substrate 101 overlaps with the orthographic projection of the third channel region A3 onto the substrate 101, forming the gate of the second sub-transistor T1-2 in the other of every two adjacent pixel circuits 100. The orthographic projection of the first scan line S1 onto the substrate 101 overlaps with the orthographic projection of the second channel region A2 onto the substrate 101, forming the gate of the first sub-transistor T1-1 in both of every two adjacent pixel circuits 100. Thus, along the extension direction X of the first scan line S1, the first sub-transistor T1-1 in every two adjacent pixel circuits 100 is shared, that is, every two adjacent pixel circuits 100 share one first sub-transistor T1-1, which can reduce the number of transistors in each pixel circuit 100, thereby reducing the space occupied by each pixel circuit 100, which is beneficial to increasing the pixel density of the display panel, enabling the display panel to display images at a higher density, achieving a higher degree of realism, thereby improving the display effect of the display panel, and further improving the performance of the display panel.

[0234] Based on the above technical solution, the structure of the display panel will be further described below, but this is not intended to limit the scope of this application.

[0235] In one implementation, Figure 9 This is a schematic diagram of the layout structure of a first active layer provided in an embodiment of the present invention, such as... Figure 9As shown, the first scan line S1 extends along the first direction X, and the first channel region A1, the second channel region A2, and the third channel region A3 are arranged along the first direction X. This reduces the space occupied by the pixel circuit 100 in the second direction Y, facilitating an increase in the pixel density of the display panel. The second direction Y intersects with the first direction X.

[0236] Optionally, such as Figure 9 As shown, the first active region 1021 also includes a first connecting portion A4, which extends along a first direction X and is connected to the first channel region A1, the second channel region A2, and the third channel region A3, respectively. In this way, the first connecting portion A4, the first channel region A1, the second channel region A2, and the third channel region A3 can be connected into a single structure, forming the first active region 1021, which facilitates the formation of two dual-gate transistors, and thus facilitates the formation of two first reset modules 150. Furthermore, a "W"-shaped first active region 1021 can be formed.

[0237] Optionally, such as Figure 5 and Figure 7 As shown, the pixel circuit 100 also includes a driving transistor T3;

[0238] The first active layer 102 further includes a second active region 1022, which includes the channel region of the driving transistor T3; the gate T31 of the driving transistor T3 is located in the first conductive layer M1. The driving transistor T3 can generate a driving current, facilitating the driving of the light-emitting element to emit light.

[0239] Figure 10 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 10 The display panel also includes a first connecting line L1, which connects the second terminal of the second sub-transistor T1-2 to the second terminal of the driving transistor T3. This connects the second terminal of the second sub-transistor T1-2 to the second terminal of the driving transistor T3.

[0240] Optionally, refer to Figure 10 The first connecting line L1 is connected to the second terminal of the second sub-transistor T1-2 through the first via V1, and the first connecting line L1 is connected to the second terminal of the driving transistor T3 through the second via.

[0241] Specifically, the first via V1 and the second via V2 are filled with conductive material, so that the first connecting line L1 is electrically connected to the second electrode of the second sub-transistor T1-2 through the first via V1, and the first connecting line L1 is electrically connected to the second electrode of the driving transistor T3 through the second via, thereby making the second electrode of the second sub-transistor T1-2 electrically connected to the second electrode of the driving transistor T3.

[0242] Optionally, refer to Figure 10 The multilayer conductive layer also includes a second conductive layer M2, a third conductive layer M3 and a fourth conductive layer M4 stacked on the side of the first conductive layer M1 away from the substrate 101;

[0243] The display panel also includes:

[0244] The first reset signal line Vref1 is located in the third conductive layer M3;

[0245] The second connection line L2 is located in the fourth conductive layer M4; the second connection line L2 is connected between the first electrode of the first sub-transistor T1-1 and the first reset signal line Vref1.

[0246] Specifically, by setting the second connection line L2, the first terminal of the first sub-transistor T1-1 can be connected to the first reset signal line Vref1. When the first scan signal on the first scan line S1 controls the first sub-transistor T1-1 and the second sub-transistor T1-2 to turn on, the first sub-transistor T1-1 transmits the first reset voltage on the first reset signal line Vref1 through the second sub-transistor T1-2 to the second terminal of the driving transistor T3, thus resetting the second terminal of the driving transistor T3.

[0247] Optionally, refer to Figure 10 The first connection line L1 is located in the fourth conductive layer M4. In this way, it can avoid affecting the routing of scan lines and other traces, and will not overlap with the first active layer 102 to form a new transistor.

[0248] Optionally, refer to Figure 10 The orthographic projection of the first reset signal line Vref1 onto the substrate 101 at least partially overlaps with the orthographic projection of the first scan line S1 onto the substrate 101. This arrangement reduces the space occupied by the traces, thereby improving the pixel density of the display panel.

[0249] Optionally, refer to Figure 10 The second connection line L2 is connected to the first terminal of the first sub-transistor T1-1 through the third via V3, and the second connection line L2 is connected to the first reset signal line Vref1 through the fourth via V4.

[0250] Specifically, the third via V3 and the fourth via V4 are filled with conductive material, so that the second connecting line L2 is electrically connected to the first electrode of the first sub-transistor T1-1 through the third via V3, and the second connecting line L2 is electrically connected to the first reset signal line Vref1 through the fourth via V4, thereby making the first electrode of the first sub-transistor T1-1 electrically connected to the first reset signal line Vref1.

[0251] Optionally, refer to Figure 5 and Figure 10The pixel circuit 100 also includes a second reset transistor T2, the channel region of which is located in the second active region 1022, and the first scan line S1 partially overlaps with the channel region of the second reset transistor T2.

[0252] The display panel also includes:

[0253] The second reset signal line Vref2 includes a first sub-reset line V21 and a second sub-reset line V22 that are connected to each other; the second sub-reset line V22 is connected to the first terminal of the second reset transistor T2.

[0254] Specifically, the first scan line S1 overlaps with the channel region of the second reset transistor T2 to form the gate of the second reset transistor T2. The second electrode of the second reset transistor T2 is connected to the first electrode of the light-emitting element OLED.

[0255] For a row of pixel circuits 100, each pixel circuit 100 corresponds to a second sub-reset line V22, such that the second reset transistor T2 in each pixel circuit 100 is connected to the corresponding second sub-reset line V22. The first sub-reset line V21 connects the second sub-reset lines V22 to form a second reset signal line Vref2, which facilitates the transmission of the second reset voltage.

[0256] Optionally, the second sub-reset line V22 is located in the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, or the fourth conductive layer M4;

[0257] The orthographic projection of the first sub-reset line V21 onto the substrate 101 overlaps with the orthographic projection of the first active region 1021 onto the substrate 101; the first sub-reset line V21 is located in the second conductive layer M2, the third conductive layer M3, or the fourth conductive layer M4.

[0258] Alternatively, the orthographic projection of the first sub-reset line V21 onto the substrate 101 does not overlap with the orthographic projection of the first active region 1021 onto the substrate 101; the first sub-reset line V21 is located in the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, or the fourth conductive layer M4.

[0259] The first sub-reset line V21 and the second sub-reset line V22 are set on different layers; or, the first sub-reset line V21 and the second sub-reset line V22 are set on the same layer.

[0260] Specifically, the second sub-reset line V22 can be located in any one of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4.

[0261] When the orthographic projection of the first sub-reset line V21 onto the substrate 101 overlaps with the orthographic projection of the first active region 1021 onto the substrate 101, the first sub-reset line V21 can be located in any one of the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4. This avoids the first sub-reset line V21 overlapping with the first active region 1021 to form a new transistor.

[0262] When the orthographic projection of the first sub-reset line V21 onto the substrate 101 does not overlap with the orthographic projection of the first active region 1021 onto the substrate 101, the first sub-reset line V21 can be located in any one of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4.

[0263] In some implementations, the first sub-reset line V21 can be arranged on the same layer as the second sub-reset line V22. Then, all the first sub-reset lines V21 and second sub-reset lines V22 corresponding to a row of pixel circuits 100 can be connected into an integrated structure, which facilitates the fabrication of the second reset signal line Vref2.

[0264] In some implementations, the first sub-reset line V21 can be set on a different layer from the second sub-reset line V22, which facilitates flexible routing.

[0265] It should be noted that, Figure 10 The diagram shows the case where the first sub-reset line V21 is located in the third conductive layer M3 and the second sub-reset line V22 is located in the fourth conductive layer M4, but it is not limited to this case.

[0266] In another implementation, alternatively, such as Figure 8 As shown, the first channel region A1 and the third channel region A3 are arranged along the first direction X, and the first channel region A1 and the third channel region A3 are symmetrically arranged; the second channel region A2 is located on the line of symmetry between the first channel region A1 and the third channel region A3.

[0267] The first scan line S1 includes a main body S11 extending along the first direction X and a first extension S12 and a second extension S13 extending along the second direction Y.

[0268] The orthographic projection of the first extension S12 onto the substrate 101 overlaps with the orthographic projection of the first channel region A1 onto the substrate 101. The orthographic projection of the second extension S13 onto the substrate 101 overlaps with the orthographic projection of the third channel region A3 onto the substrate 101. The orthographic projection of the main body S11 onto the substrate 101 overlaps with the orthographic projection of the second channel region A2 onto the substrate 101.

[0269] Specifically, the first channel region A1 and the third channel region A3 are arranged along the first direction X, and the first channel region A1 and the third channel region A3 are symmetrically arranged; the second channel region A2 is located on the line of symmetry between the first channel region A1 and the third channel region A3, making the first active region 1021 "T" shaped. The orthographic projection of the first extension S12 on the substrate 101 overlaps with the orthographic projection of the first channel region A1 on the substrate 101, forming the gate of the second sub-transistor T1-2 in one of the two adjacent pixel circuits 100. The orthographic projection of the second extension S13 on the substrate 101 overlaps with the orthographic projection of the third channel region A3 on the substrate 101, forming the gate of the second sub-transistor T1-2 in the other of the two adjacent pixel circuits 100. The orthographic projection of the main body S11 onto the substrate 101 overlaps with the orthographic projection of the second channel region A2 onto the substrate 101, forming the gate of the first sub-transistor T1-1 of each of the two adjacent pixel circuits 100.

[0270] Optionally, such as Figure 5 and Figure 8 As shown, the pixel circuit 100 also includes a driving transistor T3;

[0271] The first active layer 102 also includes a second active region 1022, which includes the channel region of the driving transistor T3; the gate T31 of the driving transistor T3 is located in the first conductive layer M1. Figure 8 The driving transistor T3 shown is Figure 7 The driving transistor T3 shown has the same structure and the same beneficial effects, so it will not be described again here.

[0272] Figure 11 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 11 The display panel also includes a first connecting line L1, which is connected between the second terminal of the second sub-transistor T1-2 and the second terminal of the driving transistor T3. Figure 11 The first connecting line L1 shown is Figure 10 The structure of the first connecting line L1 shown is similar and has the same beneficial effects, so it will not be described again here.

[0273] Optionally, refer to Figure 11 The first connecting line L1 is connected to the second terminal of the second sub-transistor T1-2 through the first via V1, and the first connecting line L1 is connected to the second terminal of the driving transistor T3 through the second via V2.

[0274] Optionally, refer to Figure 11 The multilayer conductive layer also includes a second conductive layer M2, a third conductive layer M3 and a fourth conductive layer M4 stacked on the side of the first conductive layer M1 away from the substrate 101;

[0275] The display panel also includes:

[0276] The first reset signal line Vref1 is located in the third conductive layer M3;

[0277] The second connection line L2 is located in the fourth conductive layer M4; the second connection line L2 is connected between the first electrode of the first sub-transistor T1-1 and the first reset signal line Vref1.

[0278] Figure 11 The first reset signal line Vref1 shown is... Figure 10 The structure of the first reset signal line Vref1 shown is similar. Figure 11 The second connecting line L2 shown is Figure 10 The structure of the second connecting line L2 shown is similar, and it has the same beneficial effects, so it will not be described in detail here.

[0279] Optionally, refer to Figure 11 The first connecting line L1 is located in the fourth conductive layer M4.

[0280] Optionally, refer to Figure 11 The second connection line L2 is connected to the first terminal of the first sub-transistor T1-1 through the third via V3, and the second connection line L2 is connected to the first reset signal line Vref1 through the fourth via V4.

[0281] Optionally, refer to Figure 5 and Figure 11 The pixel circuit 100 also includes a second reset transistor T2, the channel region of which is located in the second active region 1022, and the first scan line S1 partially overlaps with the channel region of the second reset transistor T2.

[0282] The display panel also includes:

[0283] The second reset signal line Vref2 includes a first sub-reset line V21 and a second sub-reset line V22 that are connected to each other; the second sub-reset line V21 is connected to the first terminal of the second reset transistor T2.

[0284] Optionally, the first sub-reset line V21 is located in the first conductive layer M1, the second conductive layer M2, the third conductive layer M3 or the fourth conductive layer M4, and the second sub-reset line V22 is located in the first conductive layer M1, the second conductive layer M2, the third conductive layer M3 or the fourth conductive layer M4.

[0285] The first sub-reset line V21 and the second sub-reset line V22 are set on different layers; or, the first sub-reset line V21 and the second sub-reset line V22 are set on the same layer.

[0286] Specifically, the second sub-reset line V22 can be located in any one of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4. The first sub-reset line V21 can be located in any one of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4.

[0287] In some implementations, the first sub-reset line V21 can be arranged on the same layer as the second sub-reset line V22. Then, all the first sub-reset lines V21 and second sub-reset lines V22 corresponding to a row of pixel circuits 100 can be connected into an integrated structure, which facilitates the fabrication of the second reset signal line Vref2.

[0288] In some implementations, the first sub-reset line V21 can be set on a different layer from the second sub-reset line V22, which facilitates flexible routing.

[0289] It should be noted that, Figure 11 The diagram shows the case where the first sub-reset line V21 is located in the first conductive layer M1 and the second sub-reset line V22 is located in the fourth conductive layer M4, but it is not limited to this case.

[0290] Figure 11 and Figure 10 The difference is that, Figure 10 The setting of the first active zone 1021 in the middle and Figure 11 The settings of the first active region 1022 are different. Figure 10 The setting of the second reset signal line Vref2 and Figure 11 The settings for the second reset signal line Vref2 are different.

[0291] Based on the above technical solutions, the layout structure of the display panel will be further described below according to the structure that the pixel circuit 100 may also include, but this is not intended to limit this application.

[0292] Figure 12 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention. Figure 13 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 12 or Figure 13 The pixel circuit 100 also includes a first light-emitting control transistor T4, and the display panel also includes a light-emitting control line EM, a power connection line VL, and a first power line VDD.

[0293] The channel region of the first light-emitting control transistor T4 is located in the second active region 1022, and the orthogonal projection of the light-emitting control line EM on the substrate partially overlaps with the channel region of the first light-emitting control transistor T4.

[0294] The second terminal of the first light-emitting control transistor T4 is connected to the first terminal of the driving transistor T3;

[0295] The display panel also includes a third connection line L3, which is connected between the first electrode of the first light-emitting control transistor T4 and the power connection line VL; the power connection line VL is connected to the first power line VDD.

[0296] Specifically, such as Figure 5 As shown, when the first light-emitting control transistor T4 is turned on, the first light-emitting control transistor T4 transmits the first power supply voltage on the first power supply line VDD to the first terminal of the driving transistor T3, so that the driving transistor T3 can generate driving current.

[0297] The orthographic projection of the light-emitting control line EM onto the substrate overlaps with the channel region of the first light-emitting control transistor T4, forming the gate of the first light-emitting control transistor T4. By providing a third connection line L3, the first terminal of the first light-emitting control transistor T4 is connected to the power connection line VL, thereby connecting the first terminal of the first light-emitting control transistor T4 to the first power line VDD through the power connection line VL.

[0298] By setting the power connection line VL, the power connection line VL and the first power line VDD can form a mesh structure, which makes it easier to reduce the impedance on the first power line VDD, thereby reducing voltage drop loss.

[0299] Optionally, refer to Figure 12 or Figure 13 The third connection line L3 is connected to the first terminal of the first light-emitting control transistor T4 through the fifth via V5, and the third connection line L3 is connected to the power connection line VL through the sixth via V6.

[0300] Specifically, the fifth via V5 and the sixth via V6 are filled with conductive material, so that the third connecting line L3 is electrically connected to the first electrode of the first light-emitting control transistor T4, and the third connecting line L3 is electrically connected to the power connection line VL, thereby making the first electrode of the first light-emitting control transistor T4 electrically connected to the power connection line VL.

[0301] Optionally, the power connection line VL is connected to the first power line VDD through the fifteenth via V15. The fifteenth via V15 is filled with conductive material, so that the power connection line VL is electrically connected to the first power line VDD.

[0302] Optionally, refer to Figure 12 or Figure 13 Along the extension direction X of the first scan line S1, every two adjacent pixel circuits 100 share a third connection line L3. This arrangement reduces the number of traces and facilitates increasing the pixel density of the display panel.

[0303] Optionally, refer to Figure 12 or Figure 13 Along the extension direction X of the first scan line S1, every two adjacent pixel circuits 100 share a fifth via V5. This reduces the space occupied by the pixel circuits 100, thereby facilitating an increase in the pixel density of the display panel.

[0304] Optionally, refer to Figure 12 or Figure 13 Along the extension direction X of the first scan line, at least a portion of every two adjacent pixel circuits 100 is symmetrical about the third connecting line L3. For example... Figure 12 or Figure 13 As shown, transistors of the same type in every two adjacent pixel circuits 100 are symmetrical about the third connection line L3. For example, the driving transistor T3 of every two adjacent pixel circuits 100 is symmetrical about the third connection line L3, the second sub-transistors T1-2 of every two adjacent pixel circuits 100 are symmetrical about the third connection line L3, the second reset transistor T2 of every two adjacent pixel circuits 100 is symmetrical about the third connection line L3, the first light-emitting control transistor T4 of every two adjacent pixel circuits 100 is symmetrical about the third connection line L3, and the second light-emitting control transistor T5 of every two adjacent pixel circuits 100 is symmetrical about the third connection line L3. The storage capacitor Cst in every two adjacent pixel circuits 100 is symmetrical about the third connection line L3.

[0305] This makes it easier for some traces (such as the third connecting line L3) to be shared, thereby increasing the pixel density of the display panel.

[0306] Optionally, refer to Figure 12 or Figure 13 The pixel circuit 100 also includes a storage capacitor Cst, which includes a first capacitor plate C1 and a second capacitor plate C2. The gate T31 of the driving transistor T3 is multiplexed as the first capacitor plate C1.

[0307] The second capacitor plate C2 is connected to the third connecting line L3 through the seventh via V7.

[0308] Specifically, the gate T31 of the driving transistor T3 is reused as the first capacitor plate C1, which reduces the number of conductive blocks, thereby reducing the space occupied by the pixel circuit 100 and improving the pixel density of the display panel. It also reduces the number of film layers, facilitating a thinner and lighter display panel design.

[0309] The seventh via V7 is filled with conductive material, which makes the second capacitor plate C2 electrically connected to the third connecting line L3, and then the second capacitor plate C2 is connected to the power connection line VL through the third connecting line L3, and then connected to the first power line VDD.

[0310] Optionally, refer to Figure 12 or Figure 13 The pixel circuit 100 also includes a second light-emitting control transistor T5, the channel region of the second light-emitting control transistor T5 is located in the second active region 1022, and the orthogonal projection of the light-emitting control line EM on the substrate 101 partially overlaps with the channel region of the second light-emitting control transistor T5.

[0311] The first terminal of the second light-emitting control transistor T5 is connected to the second terminal of the driving transistor T3, and the second terminal of the second light-emitting control transistor T5 is connected to the first terminal 104 of the light-emitting element OLED through the first conductive part B1. For example, the first terminal 104 of the light-emitting element OLED is the anode.

[0312] The second terminal of the second reset transistor T2 is connected to the second terminal of the second light-emitting control transistor T5 through the second active region 1022, thereby enabling the second terminal of the second reset transistor T2 to be connected to the first terminal 104 of the light-emitting element OLED.

[0313] Specifically, when the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned on, the first power line VDD, the first light-emitting control transistor T4, the driving transistor T3, the second light-emitting control transistor T5, the light-emitting element OLED, and the second power supply VSS form a current path, so that the driving transistor T3 generates a driving current and drives the light-emitting element OLED to emit light.

[0314] It should be noted that, in order to illustrate the first conductive part B1, Figure 13 The first electrode 104 of the OLED light-emitting element is not shown in the diagram. Figure 13 The first electrode 104 of the OLED light-emitting element in the display panel shown can be connected with... Figure 12 The structure of the first electrode 104 of the OLED light-emitting element is the same.

[0315] Figure 14 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention. Figure 15 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 14 or Figure 15 The pixel circuit 100 also includes a threshold compensation transistor T7, and the display panel also includes:

[0316] Fourth scan line S4; The orthogonal projection of the fourth scan line S4 onto the substrate 101 overlaps with the channel region of the threshold compensation transistor T7;

[0317] The second active layer 103 is located on the side of the first conductive layer M1 away from the substrate 101; the channel region of the threshold compensation transistor T7 is located in the second active layer 103.

[0318] The fourth connection line L4 is located on the side of the second active layer 103 away from the substrate 101; the fourth connection line L4 is connected between the second terminal of the threshold compensation transistor T7 and the gate of the driving transistor T3.

[0319] The fifth connection line L5 is located on the side of the second active layer 103 away from the substrate 101; the fifth connection line L5 is connected between the first terminal of the threshold compensation transistor T7 and the second terminal of the driving transistor T3.

[0320] Specifically, the orthogonal projection of the fourth scan line S4 onto the substrate 101 overlaps with the channel region of the threshold compensation transistor T7, forming the gate of the threshold compensation transistor T7. By providing the fourth connection line L4 and the fifth connection line L5, the threshold compensation transistor T7 is connected between the gate of the driving transistor T3 and the second electrode of the driving transistor T3, thereby performing threshold compensation on the driving transistor T3.

[0321] Optionally, the first active layer 102 comprises a polysilicon semiconductor material, and the second active layer 103 comprises an oxide semiconductor material. This makes the first reset transistor, second reset transistor T2, first light-emitting control transistor T4, and second light-emitting control transistor T5 formed by the driving transistor T3, the first sub-transistor T1-1, and the second sub-transistor T1-2 polysilicon transistors, such as P-type transistors. The threshold compensation transistor T7 is an oxide transistor, such as an N-type transistor. This configuration reduces the leakage current at the gate of the driving transistor T3, thereby making the driving current generated by the driving transistor T3 more stable.

[0322] Optionally, the orthographic projection of the third connecting line L3 onto the substrate 101 overlaps with the orthographic projection of the fourth scan line S4 onto the substrate 101. This arrangement reduces the space occupied by the traces, thereby improving the pixel density of the display panel.

[0323] Optionally, refer to Figure 14 or Figure 15 The fourth connection line L4 is connected to the second terminal of the threshold compensation transistor T7 through the eighth via V8, and the fourth connection line L4 is connected to the gate of the driving transistor T3 through the ninth via V9.

[0324] The fifth connection line L5 is connected to the first terminal of the threshold compensation transistor T7 through the tenth via V10, and the fifth connection line L5 is connected to the second terminal of the driving transistor T3 through the eleventh via V11.

[0325] Specifically, the eighth via V8, the ninth via V9, the tenth via V10, and the eleventh via V11 are filled with conductive material, so that the second terminal of the threshold compensation transistor T7 is electrically connected to the gate of the driving transistor T3, and the first terminal of the threshold compensation transistor T7 is electrically connected to the second terminal of the driving transistor T3.

[0326] Optionally, refer to Figure 14 or Figure 15 The orthographic projection of the eleventh via V11 onto the substrate 101 coincides with the orthographic projection of the second via V2 onto the substrate 101. This arrangement reduces the space occupied by the pixel circuit 100, which is beneficial for increasing the pixel density of the display panel.

[0327] Optionally, refer to Figure 14 or Figure 15 The light-emitting control line EM and the first capacitor plate C1 are located on the first conductive layer M1. This ensures that there are neither too many nor too few traces and conductive blocks on the first conductive layer M1, which facilitates layout design.

[0328] Figure 16 yes Figure 12 A sectional view along the e1-e2 direction. Figure 17 yes Figure 12 A sectional view along the e3-e4 direction. Figure 18 yes Figure 14 A sectional view along the e5-e6 direction, optionally, refer to Figures 12 to 18 The multilayer conductive layer also includes a fifth conductive layer M5 and a sixth conductive layer M6 stacked on the side of the fourth conductive layer M4 away from the substrate 101.

[0329] The second capacitor plate C2 is located on the second conductive layer M2;

[0330] The fourth scan line S4 includes a first sub-line S41 located in the second conductive layer M2 and a second sub-line S42 located in the third conductive layer M3, wherein the first sub-line S41 is connected to the second sub-line S42.

[0331] The third connecting line L3, the fourth connecting line L4 and the fifth connecting line L5 are located in the fourth conductive layer M4;

[0332] The power connection line VL is located on the fifth conductive layer M5;

[0333] The first power line VDD is located in the sixth conductive layer M6;

[0334] The first conductive part B1 includes a first sub-part B11 located in the fourth conductive layer M4, a second sub-part B12 located in the fifth conductive layer M5, and a third sub-part B13 located in the sixth conductive layer M6. The first sub-part B11, the second sub-part B12, and the third sub-part B13 are interconnected.

[0335] Specifically, the second capacitor plate C2 is located on the second conductive layer M2, thereby overlapping with the first capacitor plate C1 located on the first conductive layer M1 to form a storage capacitor Cst.

[0336] The first sub-line S41 overlaps with the channel region of the threshold compensation transistor T7 to form the first gate of the threshold compensation transistor T7, and the second sub-line S42 overlaps with the channel region of the threshold compensation transistor T7 to form the second gate of the threshold compensation transistor T7, making the threshold compensation transistor T7 a dual-gate transistor, which can further reduce the leakage current of the gate of the driving transistor T3. Connecting the first sub-line S41 and the second sub-line S42 makes the voltages of the first gate and the second gate of the threshold compensation transistor T7 the same, which facilitates the control of the turn-on and turn-off of the threshold compensation transistor T7.

[0337] The third connecting line L3, the fourth connecting line L4, and the fifth connecting line L5 are located in the fourth conductive layer M4. This allows most of the connecting lines to be placed in the fourth conductive layer M4, which facilitates the routing design.

[0338] By setting the power connection line VL to the fifth conductive layer M5, it is easy to connect to the first power line VDD located on the sixth conductive layer M6.

[0339] The first sub-part B11, located in the fourth conductive layer M4, is connected to the second electrode of the second light-emitting control transistor T5 through a via. The second sub-part B12, located in the fifth conductive layer M5, is connected to the first sub-part B11 through a via. The third sub-part B13, located in the sixth conductive layer M6, is connected to the second sub-part B12 through a via, and the third sub-part B13 is also connected to the first electrode of the light-emitting element OLED through a via. This connects the second electrode of the second light-emitting control transistor T5 to the first electrode of the light-emitting element OLED.

[0340] Among them, such as Figure 18 As shown, for example, the second electrode of the driving transistor T3 is the drain. The fifth connection line L5 is connected to the drain region of the driving transistor T3 in the first active layer 102 through the eleventh via V11, so that the fifth connection line L5 is connected to the second electrode of the driving transistor T3. The electrode connection principle of other transistors is similar and will not be described in detail here.

[0341] Figure 19 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention. Figure 20 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention. Figure 21 yes Figure 19 A sectional view along the e7-e8 direction, optionally, refer to Figures 19 to 21The pixel circuit 100 also includes a data writing transistor T6; the channel region of the data writing transistor T6 is located in the second active region 1022; the second terminal of the data writing transistor T6 is connected to the first terminal of the driving transistor T3.

[0342] The display panel also includes:

[0343] The third scan line S3 is located in the first conductive layer M1; the orthographic projection of the third scan line S3 on the substrate 101 overlaps with the channel region of the data writing transistor T6.

[0344] The sixth connecting line L6 is located in the fourth conductive layer M4;

[0345] The seventh connection line L7 is located in the fifth conductive layer M5;

[0346] The data line Data is located on the sixth conductive layer M6; the sixth connection line L6 is connected between the first electrode of the data writing transistor and the seventh connection line L7, and the seventh connection line L7 is connected to the data line Data.

[0347] Specifically, the orthogonal projection of the third scan line S3 onto the substrate 101 overlaps with a portion of the channel region of the data writing transistor T6, forming the gate of the data writing transistor T6. Since the channel region of the data writing transistor T6 is located in the second active region 1022, the data writing transistor T6 is a polysilicon transistor, such as a P-type transistor. By providing the sixth electrical connection line L6 and the seventh connection line L7, the first terminal of the data writing transistor is easily connected to the data line Data.

[0348] Optionally, refer to Figures 19 to 21 The orthographic projection of the sixth connecting line L6 onto the substrate 101 overlaps with the orthographic projection of the third scan line S3 onto the substrate 101. This arrangement reduces the space occupied by the traces and helps to improve the pixel density of the display panel.

[0349] Optionally, refer to Figures 19 to 21 The orthographic projection of the sixth connecting line L6 onto the substrate 101 overlaps with the orthographic projection of the seventh connecting line L7 onto the substrate 101. This further reduces the space occupied by the traces, which is beneficial for further increasing the pixel density of the display panel.

[0350] Optionally, refer to Figures 19 to 21 The sixth connection line L6 is connected to the seventh connection line L7 through the twelfth via V12. The sixth connection line L6 is connected to the first terminal of the data writing transistor T6 through the thirteenth via V13. The seventh connection line L7 is connected to the data line Data through the fourteenth via V14.

[0351] Specifically, the twelfth via V12, the thirteenth via V13, and the fourteenth via V14 are filled with conductive material, enabling electrical connection between the first electrode of the data writing transistor and the data line Data. By using the seventh connection line L7 for transition, the excessive depth of the fourteenth via V14 can be avoided, thus preventing the data line Data from easily failing and improving the reliability of the display panel.

[0352] Optionally, such as Figure 14 , Figure 15 , Figure 19 or Figure 20 As shown, the pixel circuit 100 also includes a third reset transistor T8, the channel region of which is located in the second active layer 103; the second terminal of the third reset transistor T8 is connected to the first terminal of the threshold compensation transistor T7.

[0353] The display panel also includes:

[0354] The fifth scan line S5, the orthogonal projection of the fifth scan line S5 on the substrate overlaps with the orthogonal projection of the channel region of the third reset transistor T8 on the substrate 101.

[0355] The third reset signal line Vref3 includes a third sub-reset line V31 and a fourth sub-reset line V32 that are connected to each other; the fourth sub-reset line V32 is connected to the first terminal of the third reset transistor T8.

[0356] Specifically, the channel region of the third reset transistor T8 is located in the second active layer 103, making the third reset transistor T8 an oxide transistor, such as an N-type transistor. The orthogonal projection of the fifth scan line S5 onto the substrate overlaps with the orthogonal projection of the channel region of the third reset transistor T8 onto the substrate 101, forming the gate of the third reset transistor T8. When the fifth scan signal on the fifth scan line S5 controls the third reset transistor T8 to turn on, the third reset transistor T8 transmits the third reset voltage on the third reset signal line Vref3 through the threshold compensation transistor T7 to the gate of the driving transistor T3, resetting the gate of the driving transistor T3.

[0357] For a row of pixel circuits 100, every two pixel circuits 100 correspond to a fourth sub-reset line V32, such that the third reset transistor T8 in every two pixel circuits 100 is connected to the corresponding fourth sub-reset line V32. The third sub-reset line V31 connects the fourth sub-reset line V32 to form a third reset signal line Vref3, which facilitates the transmission of the third reset voltage.

[0358] Optionally, such as Figure 14 , Figure 15 , Figure 19 or Figure 20As shown, the fifth scan line S5 includes a third sub-line S51 located in the second conductive layer M2 and a fourth sub-line S52 located in the third conductive layer M3, with the third sub-line S51 and the fourth sub-line S52 connected.

[0359] Specifically, the third sub-line S51 overlaps with the second active layer 103 to form the first gate of the third reset transistor T8, and the fourth sub-line S52 overlaps with the second active layer 103 to form the second gate of the third reset transistor T8, making the third reset transistor T8 a dual-gate transistor, thereby further reducing the leakage current of the gate of the driving transistor T3. The third sub-line S51 and the fourth sub-line S52 are connected so that the voltages of the first gate and the second gate of the third reset transistor T8 are the same, which facilitates the control of the turn-on and turn-off of the third reset transistor T8.

[0360] Optionally, the orthographic projection of the fourth sub-reset line V32 onto the substrate 101 overlaps with the orthographic projection of the third sub-line S51 onto the substrate 101. This arrangement reduces the space occupied by the traces and helps to improve the pixel density of the display panel.

[0361] Optionally, the third sub-reset line V31 is located in the first conductive layer M1, the second conductive layer M2, the third conductive layer M3 or the fourth conductive layer M4, and the fourth sub-reset line V32 is located in the first conductive layer M1, the second conductive layer M2, the third conductive layer M3 or the fourth conductive layer M4.

[0362] The third sub-reset line V31 and the fourth sub-reset line V32 are set on different layers; or, the third sub-reset line V31 and the fourth sub-reset line V32 are set on the same layer.

[0363] Specifically, the third sub-reset line V31 is located in any one of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4, and the fourth sub-reset line V32 is located in any one of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4. The third sub-reset line V31 and the fourth sub-reset line V32 can be arranged in the same layer, allowing them to be connected into a single structure, thus simplifying the fabrication process. Alternatively, the third sub-reset line V31 and the fourth sub-reset line V32 can be arranged in different layers, facilitating flexible routing.

[0364] Figure 14 , Figure 15 , Figure 19 and Figure 20 The example shows the case where the third sub-reset line V31 is located in the first conductive layer M1 and the fourth sub-reset line V32 is located in the fourth conductive layer M4, but it is not limited to this case.

[0365] This embodiment also provides a display device. Figure 22This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Figure 22 As shown, the display device includes the display panel provided in any of the above embodiments. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, or digital photo frame. Since the display device includes the display panel provided in any embodiment of the present invention, it possesses the same beneficial effects as the display panel provided in any embodiment of the present invention, and will not be elaborated further here.

[0366] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: At least two pixel circuits; The pixel circuit includes: A driving module and a first light-emitting control module, wherein the first light-emitting control module is connected between the first power line and the first end of the first light-emitting control module; The second light-emitting control module and the light-emitting module are connected in series between the second end of the driving module and the second power supply. A first reset module is connected between a first reset signal line and a second terminal of the drive module, and the control terminal of the first reset module is connected to a first scan line; the first reset module is used to respond to a first scan signal on the first scan line and transmit a first reset voltage on the first reset signal line to the second terminal of the drive module. The first reset module includes a first sub-transistor and a second sub-transistor. Along the extension direction of the first scan line, each pair of adjacent pixel circuits shares one first sub-transistor.

2. The display panel according to claim 1, characterized in that, The first sub-transistor is connected between the first reset signal line and the first terminal of the second sub-transistor, and the second terminal of the second sub-transistor is connected to the second terminal of the driving module.

3. The display panel according to claim 1, characterized in that, The pixel circuit also includes: The second reset module is connected between the second reset signal line and the first end of the light-emitting module. The control end of the second reset module is connected to the second scan line. The second reset module is used to respond to the second scan signal on the second scan line and transmit the second reset voltage on the second reset signal line to the first end of the light-emitting module. Preferably, the first scan line is multiplexed as the second scan line; Preferably, the second reset module includes a second reset transistor, the control electrode of the second reset transistor is connected to the second scan line, the first electrode of the second reset transistor is connected to the second reset signal line, and the second electrode of the second reset transistor is connected to the first end of the light-emitting module; Preferably, the first reset module is used in the first reset phase to transmit the first reset voltage on the first reset signal line to the second terminal of the drive module in response to the first scan signal on the first scan line. The second reset module is used to transmit the second reset voltage on the second reset signal line to the first terminal of the light-emitting module in response to the second scan signal on the second scan line during the first reset phase. Preferably, the driving module includes a driving transistor, the first electrode of which is connected to the first light-emitting control module, and the second electrode of which is connected to the second light-emitting control module; Preferably, the first light-emitting control module includes a first light-emitting control transistor, the control electrode of the first light-emitting control transistor is connected to the light-emitting control line, the first electrode of the first light-emitting control transistor is connected to the first power line, and the second electrode of the first light-emitting control transistor is connected to the first end of the driving module; the first light-emitting control transistor is used to control whether the first power supply voltage provided by the first power line is transmitted to the first end of the driving module according to the light-emitting control signal on the light-emitting control line. Preferably, the second light-emitting control module includes a second light-emitting control transistor, the control electrode of the second light-emitting control transistor is connected to the light-emitting control line, the first electrode of the second light-emitting control transistor is connected to the second terminal of the driving module, and the second electrode of the second light-emitting control transistor is connected to the first terminal of the light-emitting module; the second light-emitting control transistor is used to control whether the driving module transmits driving current to the light-emitting module according to the light-emitting control signal on the light-emitting control line; Preferably, the light-emitting module includes a light-emitting element, the first electrode of the light-emitting element is connected to the second light-emitting control module, and the second electrode of the light-emitting element is connected to the second power supply; Preferably, the first light-emitting control module is used to control the transmission of a first power supply voltage provided by the first power line to the first terminal of the driving module in response to the light-emitting control signal during the light-emitting phase; the second light-emitting control module is used to control the transmission of driving current to the light-emitting module in response to the light-emitting control signal during the light-emitting phase.

4. The display panel according to claim 1, characterized in that, The pixel circuit also includes: A data writing module is connected between the data line and the first end of the driving module, and the control end of the data writing module is connected to the third scan line; the data writing module is used to respond to the third scan signal on the third scan line and transmit the data voltage on the data line to the control end of the driving module. Preferably, the pixel circuit further includes: A threshold compensation module is connected between the second end of the driving module and the control end of the driving module, and the control end of the threshold compensation module is connected to the fourth scan line; the threshold compensation module is used to perform threshold compensation on the driving module in response to the fourth scan signal on the fourth scan line. Preferably, the pixel circuit further includes: The third reset module is connected between the third reset signal line and the first end of the threshold compensation module, and the control end of the third reset module is connected to the fifth scan line. The third reset module is used to respond to the fifth scan signal on the fifth scan line and transmit the third reset voltage on the third reset signal line to the control end of the drive module through the threshold compensation module. Preferably, the pixel circuit further includes: A storage module is connected between the first power line and the control terminal of the drive module; Preferably, the data writing module is used to respond to the third scan signal on the third scan line during the data writing and threshold compensation phase, and transmit the data voltage through the driving module and the threshold compensation module to the control terminal of the driving module. Preferably, the threshold compensation module is used to perform threshold compensation on the driving module in response to the fourth scan signal on the fourth scan line during the data writing and threshold compensation phase. Preferably, the third reset module is used in the second reset phase to respond to the fifth scan signal on the fifth scan line and transmit the third reset voltage on the third reset signal line to the control terminal of the drive module through the threshold compensation module. Preferably, in a frame, the second reset phase is located before the data writing and threshold compensation phases, and the data writing and threshold compensation phases are located between the light emission phases; Preferably, the first reset module is used in the first reset phase to transmit a first reset voltage on the first reset signal line to the second terminal of the driving module in response to a first scan signal on the first scan line; in a frame, the first reset phase is located between the data writing and threshold compensation phase and the light emission phase; Preferably, the data writing module includes a data writing transistor, the first electrode of the data writing transistor is connected to the data line, the second electrode of the data writing transistor is connected to the first terminal of the driving module, and the control electrode of the data writing transistor is connected to the third scan line. Preferably, the threshold compensation module includes a threshold compensation transistor, the first terminal of the threshold compensation transistor is connected to the second terminal of the driving module, the second terminal of the threshold compensation transistor is connected to the control terminal of the driving module, and the control terminal of the threshold compensation transistor is connected to the fourth scan line. Preferably, the third reset module includes a third reset transistor, the first terminal of the third reset transistor is connected to the third reset signal line, the second terminal of the third reset transistor is connected to the first terminal of the threshold compensation module, and the control terminal of the third reset transistor is connected to the fifth scan line; Preferably, the threshold compensation transistor is an N-type transistor; Preferably, the third reset transistor is an N-type transistor; Preferably, the storage module includes a storage capacitor, the first terminal of which is connected to the control terminal of the drive module, and the second terminal of which is connected to the first power line.

5. A display panel, characterized in that, include: Substrate; A first active layer is located on one side of the substrate; the first active layer includes a first active region, which includes a first channel region, a second channel region, and a third channel region that are interconnected. A multilayer conductive layer is located on the side of the first active layer away from the substrate; the first active layer and the multilayer conductive layer form at least two pixel circuits, the pixel circuits including a first reset module, the first reset module including a first sub-transistor and a second sub-transistor; the multilayer conductive layer includes a first conductive layer; The first scan line is located in the first conductive layer. The orthographic projection of the first scan line on the substrate overlaps with the orthographic projections of the first channel region, the second channel region, and the third channel region on the substrate, respectively. Wherein, along the extension direction of the first scan line, for each pair of adjacent pixel circuits, the first channel region is the channel region of the second sub-transistor in one pixel circuit, the third channel region is the channel region of the second sub-transistor in the other pixel circuit, and the second channel region is the channel region of the first sub-transistor in both pixel circuits.

6. The display panel according to claim 5, characterized in that, The first scan line extends along a first direction, and the first channel region, the second channel region, and the third channel region are arranged along the first direction; Preferably, the first active region further includes a first connecting portion, which extends along the first direction and is connected to the first channel region, the second channel region and the third channel region respectively; Preferably, the pixel circuit further includes a driving transistor; The first active layer further includes a second active region, the second active region including the channel region of the driving transistor; the gate of the driving transistor is located in the first conductive layer; Preferably, the display panel further includes a first connecting line, which is connected between the second terminal of the second sub-transistor and the second terminal of the driving transistor; Preferably, the first connecting line is connected to the second terminal of the second sub-transistor through a first via, and the first connecting line is connected to the second terminal of the driving transistor through a second via; Preferably, the multilayer conductive layer further includes a second conductive layer, a third conductive layer, and a fourth conductive layer stacked on the side of the first conductive layer away from the substrate; The display panel also includes: The first reset signal line is located in the third conductive layer; The second connection line is located in the fourth conductive layer; the second connection line is connected between the first electrode of the first sub-transistor and the first reset signal line; Preferably, the first connecting line is located in the fourth conductive layer; Preferably, the orthographic projection of the first reset signal line onto the substrate at least partially overlaps with the orthographic projection of the first scan line onto the substrate; Preferably, the second connection line is connected to the first terminal of the first sub-transistor through a third via, and the second connection line is connected to the first reset signal line through a fourth via; Preferably, the pixel circuit further includes a second reset transistor, the channel region of the second reset transistor is located in the second active region, and the first scan line partially overlaps with the channel region of the second reset transistor; The display panel also includes: The second reset signal line includes a first sub-reset line and a second sub-reset line that are interconnected; the second sub-reset line is connected to the first terminal of the second reset transistor. Preferably, the second sub-reset line is located in the first conductive layer, the second conductive layer, the third conductive layer, or the fourth conductive layer; The orthographic projection of the first sub-reset line onto the substrate overlaps with the orthographic projection of the first active region onto the substrate; the first sub-reset line is located in the second conductive layer, the third conductive layer, or the fourth conductive layer; Alternatively, the orthographic projection of the first sub-reset line onto the substrate does not overlap with the orthographic projection of the first active region onto the substrate; the first sub-reset line is located in the first conductive layer, the second conductive layer, the third conductive layer, or the fourth conductive layer; The first sub-reset line and the second sub-reset line are configured on different layers; or, the first sub-reset line and the second sub-reset line are configured on the same layer.

7. The display panel according to claim 5, characterized in that, The first channel area and the third channel area are arranged along a first direction, and the first channel area and the third channel area are symmetrically arranged; the second channel area is located on the line of symmetry between the first channel area and the third channel area; The first scan line includes a main body extending in a first direction and a first extension and a second extension extending in a second direction; The orthographic projection of the first extension on the substrate overlaps with the orthographic projection of the first channel region on the substrate, the orthographic projection of the second extension on the substrate overlaps with the orthographic projection of the third channel region on the substrate, and the orthographic projection of the main body on the substrate overlaps with the orthographic projection of the second channel region on the substrate. Preferably, the pixel circuit further includes a driving transistor; The first active layer further includes a second active region, the second active region including the channel region of the driving transistor; the gate of the driving transistor is located in the first conductive layer; Preferably, the display panel further includes a first connecting line, which is connected between the second terminal of the second sub-transistor and the second terminal of the driving transistor; Preferably, the first connecting line is connected to the second terminal of the second sub-transistor through a first via, and the first connecting line is connected to the second terminal of the driving transistor through a second via; Preferably, the multilayer conductive layer further includes a second conductive layer, a third conductive layer, and a fourth conductive layer stacked on the side of the first conductive layer away from the substrate; The display panel also includes: The first reset signal line is located in the third conductive layer; The second connection line is located in the fourth conductive layer; the second connection line is connected between the first electrode of the first sub-transistor and the first reset signal line; Preferably, the first connecting line is located in the fourth conductive layer; Preferably, the second connection line is connected to the first terminal of the first sub-transistor through a third via, and the second connection line is connected to the first reset signal line through a fourth via; Preferably, the pixel circuit further includes a second reset transistor, the channel region of the second reset transistor is located in the second active region, and the first scan line partially overlaps with the channel region of the second reset transistor; The display panel also includes: The second reset signal line includes a first sub-reset line and a second sub-reset line that are interconnected; the second sub-reset line is connected to the first terminal of the second reset transistor. Preferably, the first sub-reset line is located in the first conductive layer, the second conductive layer, the third conductive layer or the fourth conductive layer, and the second sub-reset line is located in the first conductive layer, the second conductive layer, the third conductive layer or the fourth conductive layer; The first sub-reset line and the second sub-reset line are configured on different layers; or, the first sub-reset line and the second sub-reset line are configured on the same layer.

8. The display panel according to claim 6 or 7, characterized in that, The pixel circuit further includes a first light-emitting control transistor, and the display panel further includes a light-emitting control line, a second connecting line, a power connecting line, and a first power line; The channel region of the first light-emitting control transistor is located in the second active region, and the projection of the light-emitting control line onto the substrate partially overlaps with the channel region of the first light-emitting control transistor. The second terminal of the first light-emitting control transistor is connected to the first terminal of the driving transistor; The display panel further includes a third connecting line, which is connected between the first electrode of the first light-emitting control transistor and the power connection line; the power connection line is connected to the first power line. Preferably, the third connecting line is connected to the first electrode of the first light-emitting control transistor through the fifth via, and the third connecting line is connected to the power supply connecting line through the sixth via; Preferably, along the extension direction of the first scan line, every two adjacent pixel circuits share one third connection line; Preferably, along the extension direction of the first scan line, every two adjacent pixel circuits share one fifth via. Preferably, along the extension direction of the first scan line, at least a portion of every two adjacent pixel circuits is symmetrical about the third connection line; Preferably, the pixel circuit further includes a storage capacitor, which includes a first capacitor plate and a second capacitor plate, and the gate of the driving transistor is multiplexed to the first capacitor plate. The second capacitor plate is connected to the third connecting line through the seventh through hole; Preferably, the pixel circuit further includes a second light-emitting control transistor, the channel region of the second light-emitting control transistor is located in the second active region, and the projection of the light-emitting control line onto the substrate partially overlaps with the channel region of the second light-emitting control transistor; The first terminal of the second light-emitting control transistor is connected to the second terminal of the driving transistor, and the second terminal of the second light-emitting control transistor is connected to the first terminal of the light-emitting element through the first conductive part; Preferably, the pixel circuit further includes a threshold compensation transistor, and the display panel further includes: The fourth scan line; the orthographic projection of the fourth scan line onto the substrate overlaps with a portion of the channel region of the threshold compensation transistor; The second active layer is located on the side of the first conductive layer away from the substrate; the channel region of the threshold compensation transistor is located in the second active layer; A fourth connection line is located on the side of the second active layer away from the substrate; the fourth connection line is connected between the second electrode of the threshold compensation transistor and the gate of the driving transistor; The fifth connection line is located on the side of the second active layer away from the substrate; the fifth connection line is connected between the first electrode of the threshold compensation transistor and the second electrode of the driving transistor; Preferably, the first active layer comprises a polycrystalline silicon semiconductor material, and the second active layer comprises an oxide semiconductor material; Preferably, the orthographic projection of the third connecting line onto the substrate overlaps with the orthographic projection of the fourth scanning line onto the substrate. Preferably, the fourth connection line is connected to the second terminal of the threshold compensation transistor through the eighth via, and the fourth connection line is connected to the gate of the driving transistor through the ninth via; The fifth connection line is connected to the first terminal of the threshold compensation transistor through the tenth via, and the fifth connection line is connected to the second terminal of the driving transistor through the eleventh via; Preferably, the orthographic projection of the eleventh via on the substrate coincides with the orthographic projection of the second via on the substrate; Preferably, the light-emitting control line and the first capacitor plate are located in the first conductive layer; Preferably, the multilayer conductive layer further includes a fifth conductive layer and a sixth conductive layer stacked on the side of the fourth conductive layer away from the substrate; The second capacitor plate is located in the second conductive layer; The fourth scan line includes a first sub-line located in the second conductive layer and a second sub-line located in the third conductive layer, wherein the first sub-line is connected to the second sub-line; The third connecting line, the fourth connecting line, and the fifth connecting line are located in the fourth conductive layer; The power connection line is located in the fifth conductive layer; The first power line is located in the sixth conductive layer; The first conductive portion includes a first sub-portion located in the fourth conductive layer, a second sub-portion located in the fifth conductive layer, and a third sub-portion located in the sixth conductive layer, and the first sub-portion, the second sub-portion, and the third sub-portion are interconnected.

9. The display panel according to claim 8, characterized in that, The pixel circuit further includes a data writing transistor; the channel region of the data writing transistor is located in the second active region; the second terminal of the data writing transistor is connected to the first terminal of the driving transistor. The display panel also includes: The third scan line is located in the first conductive layer; the orthographic projection of the third scan line on the substrate overlaps with the channel region of the data writing transistor. The sixth connecting line is located in the fourth conductive layer; The seventh connecting line is located in the fifth conductive layer; A data line is located in the sixth conductive layer; the sixth connection line is connected between the first electrode of the data writing transistor and the seventh connection line, and the seventh connection line is connected to the data line. Preferably, the orthographic projection of the sixth connecting line onto the substrate overlaps with the orthographic projection of the third scanning line onto the substrate. Preferably, the orthographic projection of the sixth connecting line onto the substrate overlaps with the orthographic projection of the seventh connecting line onto the substrate. Preferably, the sixth connection line is connected to the seventh connection line through the twelfth via, the sixth connection line is connected to the first terminal of the data writing transistor through the thirteenth via, and the seventh connection line is connected to the data line through the fourteenth via. Preferably, the pixel circuit further includes a third reset transistor, the channel region of which is located in the second active layer; the second terminal of the third reset transistor is connected to the first terminal of the threshold compensation transistor. The display panel also includes: The fifth scan line, the orthographic projection of the fifth scan line on the substrate overlaps with the orthographic projection of the channel region of the third reset transistor on the substrate; The third reset signal line includes a third sub-reset line and a fourth sub-reset line that are interconnected; the fourth sub-reset line is connected to the first terminal of the third reset transistor. Preferably, the fifth scan line includes a third sub-line located in the second conductive layer and a fourth sub-line located in the third conductive layer, wherein the third sub-line is connected to the fourth sub-line; Preferably, the orthographic projection of the fourth sub-reset line onto the substrate overlaps with the orthographic projection of the third sub-line onto the substrate. Preferably, the third sub-reset line is located in the first conductive layer, the second conductive layer, the third conductive layer or the fourth conductive layer, and the fourth sub-reset line is located in the first conductive layer, the second conductive layer, the third conductive layer or the fourth conductive layer; The third sub-reset line and the fourth sub-reset line are disposed on different layers; or, the third sub-reset line and the fourth sub-reset line are disposed on the same layer.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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