Pixel circuit, display panel and driving method

Abstract

Embodiments of the present application disclose a pixel circuit, a display panel and a driving method. The pixel circuit comprises a driving module, a compensation module, a voltage transmission module and a first storage module, the compensation module is connected between a first control end and a first end of the driving module, a second end of the voltage transmission module is electrically connected to a second end of the driving module, a first end of the voltage transmission module is electrically connected to a first signal line, and the first storage module is electrically connected to the first control end of the driving module. A display frame comprises at least one of a second initialization stage and a write stage and a first initialization stage. In the first initialization stage, the voltage transmission module and the compensation module are turned on, and the first signal line transmits a first initialization voltage. In the second initialization stage, the voltage transmission module is turned on, the compensation module is turned off, and the first signal line transmits a second initialization voltage different from the first initialization voltage. In the write stage, the first signal line transmits a data voltage. The embodiments of the present application can improve display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a pixel circuit, a display panel, and a driving method. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display panels needs improvement. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the background, this application provides a pixel circuit, a display panel, and a driving method, which aim to improve the performance of the display panel.

[0005] This application provides a pixel circuit, including: a driving module, a compensation module, a voltage transmission module, and a first storage module.

[0006] The compensation module is connected between the first control terminal and the first terminal of the drive module, the second terminal of the voltage transmission module is electrically connected to the second terminal of the drive module, the first terminal of the voltage transmission module is electrically connected to the first signal line, and the first storage module is electrically connected to the first control terminal of the drive module. The pixel circuit has a display frame, which includes a first initialization phase. During the first initialization phase, the voltage transmission module and the compensation module are turned on, and the first signal line transmits the first initialization voltage. The display frame also includes a second initialization phase and / or a write phase. During the second initialization phase, the voltage transmission module is turned on, the compensation module is turned off, and the first signal line transmits the second initialization voltage; the first initialization voltage and the second initialization voltage are different. During the writing phase, the first signal line transmits the data voltage.

[0007] This application embodiment also provides a pixel circuit, including: a driving module, a voltage transmission module, and a first storage module; The light-emitting element is connected between the first end of the driving module and the second power line. The second end of the voltage transmission module is electrically connected to the second end of the driving module. The first end of the voltage transmission module is electrically connected to the first signal line. The first storage module is electrically connected to the first control end of the driving module. The pixel circuit has a display frame, which includes a first initialization phase. During the first initialization phase, the voltage transmission module is turned on, and the first signal line transmits the first initialization voltage. The display frame also includes a second initialization phase and / or a write phase. During the second initialization phase, the voltage transmission module is turned on, and the first signal line transmits the second initialization voltage; the first initialization voltage and the second initialization voltage are different. During the writing phase, the first signal line transmits the data voltage.

[0008] This application also provides a display panel, including the pixel circuit provided in any embodiment of this application.

[0009] This application embodiment also provides a display panel, including at least one first selection circuit and multiple first signal lines; The first selection circuit includes a second switch module, a third switch module, and multiple first switch modules. The first terminals of the multiple first switch modules are electrically connected to different first signal lines, and the second terminals of the multiple first switch modules are electrically connected. The first terminal of the second switch module and the first terminal of the third switch module are electrically connected to the second terminal of the first switch module. The first terminal of the second switch module is connected to a first voltage, and the first terminal of the third switch module is connected to a second voltage. During the first time period, the first switch module is turned on, the second switch module is turned on, and the third switch module is turned off; During the second time period, the first switch module is turned on, the second switch module is turned off, and the third switch module is turned on.

[0010] This application embodiment also provides a driving method applied to a pixel circuit or a display panel provided in this application embodiment. The pixel circuit has a display frame, the display frame includes a first initialization phase, and the display frame further includes a second initialization phase and / or a writing phase. The driving method includes: Corresponding to the same pixel circuit: During the first initialization phase, the voltage transmission module and the compensation module are turned on, and the first signal line transmits the first initialization voltage. During the second initialization phase, the voltage transmission module is turned on, the compensation module is turned off, and the first signal line transmits the second initialization voltage; the first initialization voltage and the second initialization voltage are different. During the writing phase, the first signal line transmits the data voltage.

[0011] In this embodiment, the compensation module is connected between the first control terminal and the first terminal of the driving module, the second terminal of the voltage transmission module is electrically connected to the second terminal of the driving module, the first terminal of the voltage transmission module is electrically connected to the first signal line, and the first storage module is electrically connected to the first control terminal of the driving module. The pixel circuit has a display frame, which includes a first initialization phase. In the first initialization phase, the voltage transmission module and the compensation module are turned on, and the first signal line transmits the first initialization voltage. The display frame also includes a second initialization phase and / or a write phase. In the second initialization phase, the voltage transmission module is turned on, the compensation module is turned off, and the first signal line transmits the second initialization voltage. The first initialization voltage and the second initialization voltage are different. In the write phase, the first signal line transmits a data voltage. This configuration can improve ghosting and / or trailing, and / or reduce the number of transistors, simplify the structure of the pixel circuit, and help improve the pixel resolution (PPI) and display effect. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this application.

[0014] Figure 2 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0015] Figure 3 This is a timing waveform diagram of a display frame provided in an embodiment of this application.

[0016] Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0017] Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0018] Figure 6 This is a timing waveform diagram of another display frame provided in an embodiment of this application.

[0019] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0020] Figure 8 This is a timing waveform diagram of another display frame provided in an embodiment of this application.

[0021] Figure 9 This is a timing waveform diagram of another display frame provided in an embodiment of this application.

[0022] Figure 10 This is a timing waveform diagram of another display frame provided in an embodiment of this application.

[0023] Figure 11 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0024] Figure 12 This is a timing waveform diagram of another display frame provided in an embodiment of this application.

[0025] Figure 13 This is a timing waveform diagram of another display frame provided in an embodiment of this application.

[0026] Figure 14 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0027] Figure 15 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0028] Figure 16 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0029] Figure 17 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0030] Figure 18 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0031] Figure 19 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0032] Figure 20 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0033] Figure 21 A flowchart of a driving method provided in an embodiment of this application.

[0034] Figure 22 A flowchart of another driving method provided in an embodiment of this application.

[0035] Figure 23 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0038] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0039] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0040] For certain elements, terms such as "above" or "over" are sometimes used when describing the position of an element located in the Z direction, and "below" or "under" are used when describing the position of an element located in the opposite direction. Furthermore, when using terms such as "above," "over," "below," "under," and "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly connected, but also the state where the two elements are separated by a gap or other elements. Additionally, the terms "first," "second," and "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance or order. At least one may include one or more. At least one may include one or more. At least part may include part or all. The first direction and the second direction intersect, for example, they may be perpendicular. At least one may include one or more. Connections may include direct connections or indirect connections. Equal or identical means equal or identical within a reasonable range of errors such as manufacturing errors, process errors, and measurement errors. The transistor may be a P-type transistor or an N-type transistor. A P-type transistor is turned on when its gate is connected to a low level and turned off when its gate is connected to a high level. An N-type transistor conducts when its gate is connected to a high level and turns off when its gate is connected to a low level. One of the first and second terminals of the same transistor can be the source, and the other can be the drain. P-type transistors can include polysilicon transistors. N-type transistors can include metal-oxide transistors, such as IGZO (indium gallium zinc oxide) transistors. For example, all transistors in a pixel circuit may have the same channel type. For example, the active layer of each (or all) transistor in a pixel circuit may be made of the same material, thus simplifying the manufacturing process. Two pulses overlapping can mean that at least a portion of the time period of one pulse is the same as at least a portion of the time period of the other pulse. Two pulses overlapping is equivalent to at least a portion of the time periods corresponding to the two pulses being the same.

[0041] This application provides a pixel circuit. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. See also... Figure 1 The pixel circuit 200 includes: a driving module 10, a compensation module 30, a voltage transmission module 20, and a first storage module 40.

[0042] The compensation module 30 is connected between the first control terminal G and the first terminal D of the drive module 10. The second terminal of the voltage transmission module 20 is electrically connected to the second terminal S of the drive module 10. The first terminal of the voltage transmission module 20 is electrically connected to the first signal line L1. The first storage module 40 is electrically connected to the first control terminal G of the drive module 10.

[0043] The pixel circuit 200 has a display frame. The display frame includes a first initialization phase T1.

[0044] During the first initialization phase T1, the voltage transmission module 20 and the compensation module 30 are turned on, and the first signal line L1 transmits the first initialization voltage Vref1. That is, during the first initialization phase T1, the first signal line L1 is connected to the first initialization voltage Vref1, which can be transmitted to the first terminal of the voltage transmission module 20.

[0045] For example, in the first initialization phase T1, the first terminal of the voltage transmission module 20 is connected to the first initialization voltage Vref1. The first control terminal G of the drive module 10 leaks current to the first terminal of the voltage transmission module 20 and / or the first signal line L1 through the conducting compensation module 30, drive module 10, and voltage transmission module 20 until the voltage of the first control terminal G of the drive module 10 is Vref1-Vth, thereby initializing the first control terminal G of the drive module 10. Here, Vth is the threshold voltage of the drive module 10.

[0046] For example, the display frame also includes a second initialization phase T5 and / or a write phase T2.

[0047] For example, in the second initialization phase T5, the voltage transmission module 20 is turned on, the compensation module 30 is turned off, and the first signal line L1 transmits the second initialization voltage Vref2. The first initialization voltage Vref1 and the second initialization voltage Vref2 are different. That is, in the second initialization phase T5, the first signal line L1 is connected to the second initialization voltage Vref2, which can be transmitted to the first terminal of the voltage transmission module 20.

[0048] For example, in the second initialization stage T5, the first terminal of the voltage transmission module 20 is connected to the second initialization voltage Vref2. The second initialization voltage Vref2 can be transmitted to the second terminal S of the drive module 10 through the conducting voltage transmission module 20 to initialize the second terminal S of the drive module 10. By reasonably setting the second initialization voltage Vref2, a larger voltage difference is achieved between the first control terminal G and the second terminal S of the drive module 10, which is beneficial for adjusting the bias state of the drive module 10, thereby improving image retention and / or ghosting. By transmitting the first initialization voltage Vref1 and the second initialization voltage Vref2 in a time-division multiplexing manner through the same module or the same transistor (e.g., the voltage transmission module 20), the number of transistors can be reduced, the structure of the pixel circuit can be simplified, and the pixel resolution (PPI) can be improved.

[0049] For example, during the write phase T2, the first signal line L1 transmits the data voltage Vdata. That is, during the write phase T2, the first signal line L1 is connected to the data voltage Vdata, which can be transmitted to the first terminal of the voltage transmission module 20. By transmitting the first initialization voltage Vref1 and the data voltage Vdata in a time-division multiplexing manner through the same module or the same transistor (e.g., the voltage transmission module 20), the number of transistors can be reduced, the structure of the pixel circuit can be simplified, and the pixel resolution PPI can be improved.

[0050] For example, by transmitting the first initialization voltage Vref1, the second initialization voltage Vref2, and the data voltage Vdata in a time-division manner through the same module or the same transistor (e.g., voltage transmission module 20), the number of transistors can be reduced, the structure of the pixel circuit can be simplified, and the pixel resolution PPI can be improved.

[0051] In this embodiment, the compensation module 30 is connected between the first control terminal G and the first terminal D of the driving module 10. The second terminal of the voltage transmission module 20 is electrically connected to the second terminal S of the driving module 10, and the first terminal of the voltage transmission module 20 is electrically connected to the first signal line L1. The first storage module 40 is electrically connected to the first control terminal G of the driving module 10. The pixel circuit has a display frame, which includes a first initialization phase T1. In the first initialization phase T1, the voltage transmission module 20 and the compensation module 30 are turned on, and the first signal line L1 transmits the first initialization voltage Vref1. The display frame also includes a second initialization phase T5 and / or a write phase T2. In the second initialization phase T5, the voltage transmission module 20 is turned on, the compensation module 30 is turned off, and the first signal line L1 transmits the second initialization voltage Vref2. The first initialization voltage Vref1 and the second initialization voltage Vref2 are different. In the write phase T2, the first signal line L1 transmits the data voltage Vdata. This configuration can improve ghosting and / or trailing, and / or reduce the number of transistors, simplify the structure of the pixel circuit, and help improve the pixel resolution (PPI) and display effect.

[0052] For example, the driving module 10 and the light-emitting element 100 can be connected in series between the first power line and the second power line. For example, during the light-emitting phase, the driving module 10 can generate a driving current to drive the light-emitting element 100 to emit light. The light-emitting element 100 may include a light-emitting diode, such as an organic light-emitting diode. The first power line can be used to transmit a first power supply voltage VDD. The second power line can be used to transmit a second power supply voltage VSS. For example, during the light-emitting phase, one of the first power supply voltage and the second power supply voltage is a high voltage, and the other is a low voltage. For example, during the light-emitting phase, the first power supply voltage VDD is a high voltage, such as a positive voltage, and the second power supply voltage VSS is a low voltage, such as a second voltage VSSL, such as a negative voltage.

[0053] For example, the light-emitting element 100 may include a light-emitting diode, such as an organic light-emitting diode. For example, one of the first and second ends of the light-emitting element 100 may be an anode, and the other a cathode. For example, the first end of the light-emitting element 100 may be an anode, and the second end may be a cathode. Alternatively, for example, the first end of the light-emitting element 100 may be a cathode, and the second end may be an anode. The second end of the light-emitting element 100 may be connected to a second power supply voltage VSS and / or electrically connected to a second power supply line.

[0054] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. For example, see... Figure 2 The driving module 10 may include a driving transistor M1. The driving module 10 or the driving transistor M1 may include a P-type transistor (see [reference needed]). Figure 2 The driving transistor M1 can be a metal-oxide-semiconductor transistor (MODS) or an N-type transistor. The first gate of the driving transistor M1 can be the first control terminal G of the driving module 10. The second gate of the driving transistor M1 can be the second control terminal B of the driving module 10. The second terminal (e.g., the source) of the driving transistor M1 can be the second terminal S of the driving module 10. The first terminal (e.g., the drain) of the driving transistor M1 can be the first terminal D of the driving module 10. During the light-emitting phase, the driving module 10 can generate a driving current based on the voltage between the first control terminal G and the second terminal S of the driving module 10. The driving transistor M1 can include a metal-oxide-semiconductor transistor (MODS) or a polysilicon transistor (PST). The driving transistor M1 can include an N-type polysilicon transistor.

[0055] For example, one of the first control terminal G and the second control terminal B of the driving module 10 is the bottom gate of the driving transistor M1, and the other is the top gate of the driving transistor M1. That is, one of the first gate and the second gate of the driving transistor M1 is the bottom gate of the driving transistor M1, and the other is the top gate of the driving transistor M1. For example, the first gate of the driving transistor M1 can be either the bottom gate or the top gate. The bottom gate and the top gate of the driving transistor M1 can be located on opposite sides of the active portion of the driving transistor M1 along the thickness direction of the active portion of the driving transistor M1. For example, the bottom gate of the driving transistor M1 is located below the active portion of the driving transistor M1, and the top gate of the driving transistor M1 is located above the active portion of the driving transistor M1.

[0056] For example, the first control terminal G of the drive module 10 or the first gate of the drive transistor M1 can be a top gate.

[0057] In some embodiments, the drive module 10 includes only one control terminal, such as a first control terminal, and the drive module 10 has no second control terminal.

[0058] For example, the first end of the first storage module 40 is electrically connected to the first control terminal G of the drive module 10, and the second end of the first storage module 40 is electrically connected to the first power line.

[0059] For example, see Figure 2 The first storage module 40 may include a first capacitor C1. For example, the first terminal of the first capacitor C1 may be the first end of the first storage module 40, and the second terminal of the first capacitor C1 may be the second end of the first storage module 40.

[0060] For example, see Figure 2 The voltage transmission module 20 may include a second transistor M2. The voltage transmission module 20 or the second transistor M2 may include a P-type transistor (see [reference needed]). Figure 2 The second transistor M2 can be a metal-oxide-semiconductor transistor or an N-type transistor. The gate of the second transistor M2 can be the control terminal of the voltage transmission module 20. The first terminal of the second transistor M2 can be the first terminal of the voltage transmission module 20. The second terminal of the second transistor M2 can be the second terminal of the voltage transmission module 20. The voltage transmission module 20 or the second transistor M2 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0061] For example, see Figure 2 The compensation module 30 may include a third transistor M3. The compensation module 30 or the third transistor M3 may include a P-type transistor (see [reference needed]). Figure 2 The third transistor M3 can be a metal-oxide-semiconductor transistor or an N-type transistor. The gate of the third transistor M3 can be the control terminal of the compensation module 30. The first terminal of the third transistor M3 can be the first terminal of the compensation module 30. The second terminal of the third transistor M3 can be the second terminal of the compensation module 30. The compensation module 30 or the third transistor M3 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0062] For example, during the writing phase T2, the voltage transmission module 20 and the compensation module 30 are turned off.

[0063] For example, the display frame also includes a threshold compensation phase T3. For example, in the threshold compensation phase T3, the compensation module 30 is turned on.

[0064] For example, in the threshold compensation stage T3, the voltage transmission module 20 and the compensation module 30 are turned on. In the threshold compensation stage T3, the data voltage Vdata can be charged to the first control terminal G of the drive module 10 via the turned-on voltage transmission module 20, drive module 10, and compensation module 30, that is, threshold voltage compensation is performed on the drive module 10 until the voltage at the first control terminal G of the drive module 10 is Vdata + Vth. This means Vdata + Vth is stored in the first storage module 40.

[0065] Threshold compensation ensures that during the light-emitting phase, the magnitude of the driving current generated by the driving module 10 is independent of or less correlated with the threshold voltage Vth of the driving module 10. Instead, the magnitude of the driving current generated by the driving module 10 is correlated with the data voltage Vdata. This improves display uniformity and avoids or mitigates display unevenness caused by differences in the threshold voltage Vth of the driving modules 10 in different pixel circuits. For example, in the same display frame, the threshold compensation phase T3 follows the writing phase T2. Similarly, in the same display frame, the start time of the threshold compensation phase T3 follows the end time of the writing phase T2.

[0066] For example, in the same display frame, the first initialization phase T1 precedes the write phase T2.

[0067] For example, the control terminal of the voltage transmission module 20 and the control terminal of the compensation module 30 are electrically connected to the same gate line and / or connected to the same gate signal (e.g., the first gate signal S1). This configuration reduces the number of signal lines, which is beneficial for improving pixel resolution (PPI). The control terminals of the voltage transmission module 20 and the compensation module 30 can share the same gate drive circuit, which reduces the number of gate drive circuits and thus helps to reduce the bezel width of the display panel, achieving a narrow bezel.

[0068] For example, the transistors in voltage transmission module 20 and the transistors in compensation module 30 have the same channel type, such as P-type transistors (see [reference]). Figure 2 ) or N-type transistor.

[0069] For example, the voltage transmission module 20 and the compensation module 30 have the same switching state, such as being simultaneously turned on and simultaneously turned off.

[0070] For example, the second control terminal B of the drive module 10 is electrically connected to the second terminal S of the drive module 10. The drive module 10 is a four-terminal device. The second control terminal B of the drive module 10 is shorted to the second terminal S of the drive module 10. When different voltages are applied to the second terminal S of the drive module 10, source-drain switching can be achieved, thereby initializing the first control terminal G of the drive module 10 and performing threshold compensation on the drive module 10.

[0071] For example, the driving module 10 includes a driving transistor M1. One of the first control terminal G and the second control terminal B of the driving module 10 is the top gate of the driving transistor M1, and the other is the bottom gate of the driving transistor M1. The driving module 10 or the driving transistor M1 is a four-terminal device, which is beneficial for initializing the first control terminal G of the driving module 10 during the first initialization phase.

[0072] For example, the first control terminal G of the driving module 10 is the top gate of the driving transistor M1, and the second control terminal B of the driving module 10 is the bottom gate of the driving transistor M1.

[0073] For example, the driving transistor M1 is a P-type transistor, and the second initialization voltage Vref2 is higher than the first initialization voltage Vref1. This configuration ensures that the voltage difference VG-VS between the first control terminal G and the second terminal S of the driving module 10 is a large negative stress, which is beneficial for adjusting the bias state of the driving module 10, thereby improving image retention and / or ghosting. For example, the second initialization voltage Vref2 can be a positive voltage, and the first initialization voltage Vref1 can be a negative voltage.

[0074] Alternatively, for example, the driving transistor M1 is an N-type transistor, and the second initialization voltage Vref2 is lower than the first initialization voltage Vref1. This configuration ensures that the voltage difference VG-VS between the first control terminal G and the second terminal S of the driving module 10 is a large positive stress, which is beneficial for adjusting the bias state of the driving module 10, thereby improving image retention and / or ghosting. For example, the second initialization voltage Vref2 can be negative, and the first initialization voltage Vref1 can be positive.

[0075] For example, the pixel circuit 200 also includes a first light-emitting control module 50. The first light-emitting control module 50 is connected between the first terminal D of the driving module 10 and the first terminal of the light-emitting element 100.

[0076] For example, in the first initialization phase T1, the first light-emitting control module 50 is turned on. For example, in the first initialization phase T1, the first terminal of the voltage transmission module 20 is connected to the first initialization voltage Vref1. The first terminal of the light-emitting element 100 leaks current to the first terminal of the voltage transmission module 20 and / or the first signal line L1 through the turned-on first light-emitting control module 50, driving module 10, and voltage transmission module 20 until the voltage of the first control terminal G of the driving module 10 is Vref1-Vth, so as to initialize the first terminal of the light-emitting element 100.

[0077] For example, the driving module 10 is a four-terminal device. The second control terminal B of the driving module 10 is shorted to the second terminal S of the driving module 10. When different voltages are applied to the second terminal S of the driving module 10, the source-drain switching can be realized, thereby initializing the first control terminal G of the driving module 10, the first terminal of the light-emitting element 100, and the threshold compensation of the driving module 10.

[0078] For example, during the second initialization phase T5 and / or the writing phase T2, the first light-emitting control module 50 is turned off.

[0079] For example, see Figure 2 The first light-emitting control module 50 may include a fifth transistor M5. The first light-emitting control module 50 or the fifth transistor M5 may include a P-type transistor (see [reference needed]). Figure 2The fifth transistor M5 can be a metal-oxide-semiconductor transistor or an N-type transistor. The gate of the fifth transistor M5 can be the control terminal of the first light-emitting control module 50. The first electrode of the fifth transistor M5 can be the first terminal of the first light-emitting control module 50. The second electrode of the fifth transistor M5 can be the second terminal of the first light-emitting control module 50. The first light-emitting control module 50 or the fifth transistor M5 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0080] For example, the pixel circuit 200 also includes a second light-emitting control module 60. The second light-emitting control module 60 is connected between the second end of the driving module 10 and the first power line.

[0081] For example, during the first initialization phase T1, the second light-emitting control module 60 is turned off.

[0082] For example, during the second initialization phase T5 and / or the writing phase T2, the second light emission control module 60 is turned off.

[0083] For example, the display frame also includes a threshold compensation phase T3. For example, in the threshold compensation phase T3, the first light emission control module 50 is turned off. For example, in the threshold compensation phase T3, the second light emission control module 60 is turned off.

[0084] Figure 3 This is a timing waveform diagram of a display frame provided in an embodiment of this application. Figure 3 Applicable to Figure 1 or Figure 2 Pixel circuitry. For example, see... Figure 3 In the same display frame, the width of the turn-off pulse of the gate signal (e.g., the second gate signal EM2) connected to the control terminal of the first light-emitting control module 50 is the same as the width of the turn-off pulse of the gate signal (e.g., the third gate signal EM1) connected to the control terminal of the second light-emitting control module 60, for example, both being W1. With this configuration, the control terminals of the first and second light-emitting control modules 50 can share the same gate driving circuit, reducing the number of gate driving circuits and thus helping to reduce the bezel width of the display panel, achieving a narrow bezel.

[0085] For example, in the same display frame, the turn-off pulse of the gate signal accessed to the control terminal of the first light-emitting control module 50 lags behind the turn-off pulse of the gate signal accessed to the control terminal of the second light-emitting control module 60. For example, the shift register that provides the gate signal to the control terminal of the first light-emitting control module 50 is the successor to the shift register that provides the gate signal to the control terminal of the second light-emitting control module 60.

[0086] For example, in the same display frame, the turn-off pulse of the gate signal accessed by the control terminal of the first light-emitting control module 50 overlaps with the turn-off pulse of the gate signal accessed by the control terminal of the second light-emitting control module 60.

[0087] For example, the transistors in the first light-emitting control module 50 and the transistors in the second light-emitting control module 60 have the same channel type, for example, both are P-type transistors (see [reference]). Figure 2 ) or N-type transistor.

[0088] For example, the first initialization phase T1 occurs before the second initialization phase T5 and / or the write phase T2.

[0089] For example, the voltage VDD on the first power line is a DC voltage.

[0090] For example, the second end of the light-emitting element 100 is electrically connected to the second power supply line.

[0091] For example, the voltage VSS on the second power line is a DC voltage.

[0092] For example, see Figure 2 The second light-emitting control module 60 may include a fourth transistor M4. The second light-emitting control module 60 or the fourth transistor M4 may include a P-type transistor (see [reference needed]). Figure 2 The fourth transistor M4 can be a metal-oxide-semiconductor transistor or an N-type transistor. The gate of the fourth transistor M4 can be the control terminal of the second light-emitting control module 60. The first terminal of the fourth transistor M4 can be the first terminal of the second light-emitting control module 60. The second terminal of the fourth transistor M4 can be the second terminal of the second light-emitting control module 60. The second light-emitting control module 60 or the fourth transistor M4 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0093] Figure 2 The pixel circuits in the system have no micro-short-circuit states in any state, which can achieve low power consumption.

[0094] This application provides a display panel. Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Figure 4 Applicable Figure 1 or Figure 2 Pixel circuitry. For example, see... Figure 4 The display panel 300 may include the pixel circuit 200 provided in the embodiments of this application, possessing the beneficial effects of the pixel circuit in any embodiment of this application, which will not be described in detail here. The display panel 300 may include a display area 301 and a non-display area 302. The pixel circuit 200 may be located in the display area 301. The display panel may include a light-emitting element 100. The light-emitting element 100 may be located in the display area 301. For example, the display panel includes a plurality of pixel circuits 200 arranged in an array.

[0095] For example, the display panel 300 also includes a first selection circuit 70. The first selection circuit 70 includes a plurality of first switch modules 71. The first terminals of the plurality of first switch modules 71 are electrically connected to different first signal lines L1. The second terminals of the plurality of first switch modules 71 are electrically connected.

[0096] For example, multiple first switch modules 71 may have the same switching state, such as being simultaneously on and simultaneously off.

[0097] For example, the control terminals of multiple first switch modules 71 are electrically connected to the same signal line and / or connected to the same control signal (e.g., the first control signal Se). This configuration reduces the number of signal lines.

[0098] Figure 4 An exemplary drawing shows the first selection circuit 70 comprising six first switch modules 71.

[0099] For example, in the first initialization phase T1, the first switch module 71 is turned on, and the second terminal of the first switch module 71 is connected to the first initialization voltage Vref1, which can transmit the first initialization voltage Vref1 to the corresponding first signal line L1 through the turned-on first switch module 71.

[0100] For example, the display panel includes multiple first selection circuits 70. The second terminals of the first switch modules 71 in the different first selection circuits 70 are insulated, that is, not electrically connected.

[0101] For example, the display panel also includes a second selection circuit 80. The second selection circuit 80 includes a plurality of fourth switch modules 81. The first terminals of the plurality of fourth switch modules 81 are electrically connected to different first signal lines L1, and the second terminals of the plurality of fourth switch modules 81 are electrically connected. For example, the second terminals of the fourth switch modules 81 can be electrically connected to pins of a driver chip. This configuration reduces the number of pins on the driver chip.

[0102] For example, multiple fourth switch modules 81 in the same second selection circuit 80 may be turned on in a time-sharing manner. Alternatively, multiple fourth switch modules 81 in the same second selection circuit 80 may not be turned on simultaneously.

[0103] For example, during the writing phase T2, the second terminal of the fourth switch module 81 is connected to the data voltage Vdata.

[0104] For example, the first signal line L1 can be a data line.

[0105] For example, during the writing phase T2 of the corresponding pixel circuit 200, the fourth switch module 81, which is electrically connected to the corresponding pixel circuit, is turned on. With this configuration, the data voltage Vdata corresponding to the pixel circuit 200 can be transmitted to the corresponding pixel circuit 200 through the corresponding fourth switch module 81.

[0106] Figure 4 An exemplary drawing shows the second selection circuit 80 including six fourth switch modules 81.

[0107] For example, pixel circuit 200_1 corresponds to writing stage T21, pixel circuit 200_2 corresponds to writing stage T22, pixel circuit 200_3 corresponds to writing stage T23, pixel circuit 200_4 corresponds to writing stage T24, pixel circuit 200_5 corresponds to writing stage T25, and pixel circuit 200_6 corresponds to writing stage T26.

[0108] For example, the control terminals of multiple fourth switch modules 81 are electrically connected to different signal lines and / or connected to different control signals (e.g., mux1 to mux6).

[0109] For example, the first switch module 71 and the fourth switch module 81 are turned on in a time-sharing manner.

[0110] For example, in the first initialization phase T1, the fourth switch module 81 is turned off.

[0111] For example, during the write phase T2, the first switch module 71 is turned off.

[0112] For example, the display frame also includes a threshold compensation stage T3. The second selection circuit 80 includes n fourth switch modules 81.

[0113] For example, the number of first switch modules 71 in a single first selection circuit 70 may be greater than, less than, or equal to the number of fourth switch modules 81 in a single second selection circuit 80. For example, the first selection circuit 70 includes n first switch modules 71.

[0114] For example, n can be 2, 3, 4, 5, or 6, etc.

[0115] For example, the display panel includes multiple second selection circuits 80. The second terminals of the fourth switch module 81 in the different second selection circuits 80 are insulated, that is, not electrically connected.

[0116] For example, in the same display frame, the end time of the write phase T2 of the n pixel circuits located in the i-th row, electrically connected to the same second selection circuit 80, is before or simultaneously with the start time of the threshold compensation phase T3 of the n pixel circuits located in the i-th row, also electrically connected to the same second selection circuit 80. Here, n is an integer greater than or equal to 2, and i is an integer greater than or equal to 1. For example, in the same display frame, the end time Tx of the write phase T26 is before the start time Ty of the threshold compensation phase T3. Compared to the technical solution where the threshold compensation phase T3 overlaps with the write phase T2 of a portion of the pixel circuits, and the threshold compensation phase T3 does not overlap with the write phase T2 of another portion of the pixel circuits (the light-emitting elements driven by the pixel circuits in the two cases will produce a brightness difference), the threshold compensation phase T3 does not overlap with the write phase T2, which can reduce or eliminate the brightness difference.

[0117] For example, during the threshold compensation phase T3, the first switch module 71 is turned off.

[0118] For example, during the threshold compensation phase T3, the fourth switch module 81 is turned off.

[0119] For example, see Figure 4 The first switching module 71 may include a sixth transistor M6. The first switching module 71 or the sixth transistor M6 may include a P-type transistor (see [reference needed]). Figure 4 The sixth transistor M6 can be a metal-oxide-semiconductor transistor (MOD) or an N-type transistor. The gate of the sixth transistor M6 can be the control terminal of the first switching module 71. The first terminal of the sixth transistor M6 can be the first terminal of the first switching module 71. The second terminal of the sixth transistor M6 can be the second terminal of the first switching module 71. The first switching module 71 or the sixth transistor M6 can include a MOD or a polysilicon transistor.

[0120] For example, see Figure 4 The fourth switching module 81 may include a ninth transistor M9. The fourth switching module 81 or the ninth transistor M9 may include a P-type transistor (see [reference needed]). Figure 4 The ninth transistor M9 can be a metal-oxide-semiconductor transistor or an N-type transistor. The gate of the ninth transistor M9 can be the control terminal of the fourth switching module 81. The first terminal of the ninth transistor M9 can be the first terminal of the fourth switching module 81. The second terminal of the ninth transistor M9 can be the second terminal of the fourth switching module 81. The fourth switching module 81 or the ninth transistor M9 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0121] See also Figure 2The control terminal of the voltage transmission module 20 (which may be the gate of the second transistor M2) is connected to the first gate signal S1, the control terminal of the compensation module 30 (which may be the gate of the third transistor M3) is connected to the first gate signal S1, the control terminal of the first light emission control module 50 (which may be the gate of the fifth transistor M5) is connected to the second gate signal EM2, and the control terminal of the second light emission control module 60 (which may be the gate of the fourth transistor M4) is connected to the first gate signal EM1.

[0122] See also Figure 2 The first capacitor C1 is connected between the first gate of the driving transistor M1 and the first power supply line. The first terminal of the second transistor M2 is connected to at least one of the data voltage Vdata, the second initialization voltage Vref2, and the first initialization voltage Vref1 in a time-division manner. The third transistor M3 is connected between the first gate and the first terminal of the driving transistor M1. The fourth transistor M4 is connected between the second terminal of the driving transistor M1 and the first power supply line. The fifth transistor M5 is connected between the first terminal of the light-emitting element 100 and the first terminal of the driving transistor M1. The second gate of the driving transistor M1 is connected to the second terminal of the driving transistor M1.

[0123] For example, see Figure 2 The driving transistors M1, M2, M3, M4, and M5 are P-type transistors.

[0124] See Figures 2 to 4 The working process of the pixel circuit is described. For example, a display frame may include a first initialization phase T1, a writing phase T2, a threshold compensation phase T3, and a light emission phase T4.

[0125] See Figures 2 to 4During at least a portion of the first initialization phase T1, the first gate signal S1 is at an on level, for example, a low level; the second gate signal EM2 is at an on level, for example, a low level; the third gate signal EM1 is at an off level, for example, a high level; the first control signal Re is at an on level, for example, a low level; and control signals mux1 to mux6 are at an off level, for example, a high level. The first switching module 71 (which may be the sixth transistor M6) is turned on, which can transmit the first initialization voltage Vref1 to the first signal line L1 and the first terminal of the voltage transmission module 20 (which may be the first terminal of the second transistor M2). When the voltage transmission module 20 (which may be the second transistor M2) and the compensation module 30 (which may be the third transistor M3) are turned on, the first control terminal G of the driving module 10 (which may be the first gate of the driving transistor M1), the first terminal of the first storage module 40 (which may be the first electrode of the first capacitor C1), and the first terminal of the light-emitting element 100 can leak current through the turned-on voltage transmission module 20 (which may be the second transistor M2), the driving module 10 (which may be the driving transistor M1), and the compensation module 30 (which may be the third transistor M3) to the first terminal of the voltage transmission module 20 (which may be the first electrode of the second transistor M2), the first signal line L1 to Vref1-Vth, in order to initialize the first control terminal G of the driving module 10 (which may be the first gate of the driving transistor M1), the first terminal of the first storage module 40 (which may be the first electrode of the first capacitor C1), and the first terminal of the light-emitting element 100. Here, Vth may be the threshold voltage of the driving module 10 (which may be the driving transistor M1). The first light-emitting control module 50 (which may be the fifth transistor M5), the second light-emitting control module 60 (which may be the fourth transistor M4), and the fourth switch module 81 (which may be the ninth transistor M9) are turned off.

[0126] See Figures 2 to 4 During at least a portion of the writing phases T21 to T26, the first gate signal S1 is at a shutdown level, for example, a high level; the second gate signal EM2 is at a shutdown level, for example, a high level; the third gate signal EM1 is at a shutdown level, for example, a high level; the first control signal Re is at a shutdown level, for example, a high level; and the control signals mux1 to mux6 are at a conduction level, for example, a low level, during their respective corresponding writing phases T2. The corresponding fourth switch module 81 (which may be the ninth transistor M9) is turned on, which can transmit the corresponding data voltage Vdata to the first signal line L1 and the first terminal of the voltage transmission module 20 (which may be the first terminal of the second transistor M2), which is equivalent to charging the data voltage Vdata to the first signal line L1. The voltage transmission module 20 (which may be the second transistor M2), the compensation module 30 (which may be the third transistor M3), the first light-emitting control module 50 (which may be the fifth transistor M5), the second light-emitting control module 60 (which may be the fourth transistor M4), and the first switch module 71 (which may be the sixth transistor M6) are turned off.

[0127] See Figures 2 to 4 During at least a portion of the threshold compensation phase T3, the first gate signal S1 is at an on level, for example, a low level; the second gate signal EM2 is at an off level, for example, a high level; the third gate signal EM1 is at an off level, for example, a high level; the first control signal Re is at an off level, for example, a high level; and the control signals mux1 to mux6 are at an off level, for example, a high level. When the voltage transmission module 20 (which can be the second transistor M2) and the compensation module 30 (which can be the third transistor M3) are turned on, the data voltage Vdata on the first signal line L1 can be charged through the turned-on voltage transmission module 20 (which can be the second transistor M2), the driving module 10 (which can be the driving transistor M1), and the compensation module 30 (which can be the third transistor M3) to the first control terminal G of the driving module 10 (which can be the first gate of the driving transistor M1) and the first terminal of the first storage module 40 (which can be the first electrode of the first capacitor C1) until the voltage of the first control terminal G of the driving module 10 (which can be the first gate of the driving transistor M1) and the first terminal of the first storage module 40 (which can be the first electrode of the first capacitor C1) is Vdata + Vth, that is, the threshold compensation of the driving module 10 (which can be the driving transistor M1) is achieved. The first light-emitting control module 50 (which can be the fifth transistor M5), the second light-emitting control module 60 (which can be the fourth transistor M4), the first switch module 71 (which can be the sixth transistor M6), and the fourth switch module 81 (which can be the ninth transistor M9) are turned off.

[0128] See Figures 2 to 4 During at least a portion of the light-emitting phase T4, the first gate signal S1 is at an off level, for example, a high level; the second gate signal EM2 is at an on level, for example, a low level; and the third gate signal EM1 is at an on level, for example, a low level. The first light-emitting control module 50 (which may be the fifth transistor M5) and the second light-emitting control module 60 (which may be the fourth transistor M4) are turned on, and the driving current generated by the driving module 10 (which may be the driving transistor M1) drives the light-emitting element 100 to emit light. The driving current I generated by the driving module 10... Where μ is the carrier mobility of driving transistor M1, Cox is the channel capacitance per unit area of ​​driving transistor M1, and W / L is the channel width-to-length ratio of driving transistor M1. For example, if driving transistor M1 is an N-type transistor, μ is the electron mobility of driving transistor M1. For example, if driving transistor M1 is a P-type transistor, μ is the hole mobility of driving transistor M1. VGS can be the voltage difference between the voltage at the first control terminal G and the voltage at the second terminal S of driving module 10. Voltage transmission module 20 (which can be the second transistor M2) and compensation module 30 (which can be the third transistor M3) are turned off.

[0129] For example, the drive current I generated by drive module 10 is related to (Vdata-VDD).2 Related.

[0130] In some embodiments, the driving transistors M1, M2, M3, M4, and M5 are N-type transistors, which can invert the high and low voltages in the timing waveform diagram, that is, replace the high voltage with the low voltage and the low voltage with the high voltage.

[0131] Figure 5 A schematic diagram of another pixel circuit structure provided in an embodiment of this application. For example, see... Figure 5 The control terminals of the voltage transmission module 20 and the compensation module 30 are electrically connected to different gate lines and / or connected to different gate signals. For example, the control terminal of the voltage transmission module 20 is connected to the first gate signal S1, and the control terminal of the compensation module 30 is connected to the fourth gate signal S2.

[0132] For example, see Figure 5 The compensation module 30 or the third transistor M3 includes a first sub-transistor M3_1 and a second sub-transistor M3_2, which are also dual-gate transistors. The first sub-transistor M3_1 and the second sub-transistor M3_2 are connected in series between the first control terminal G and the first terminal D of the drive module 10. For example, the gate of the first sub-transistor M3_1 and the gate of the second sub-transistor M3_2 are connected to the control terminal of the compensation module 30. This configuration can reduce the leakage current of the first control terminal G of the drive module 10 and improve low-frequency flicker.

[0133] Figure 6 This is a timing waveform diagram of another display frame provided in an embodiment of this application. Figure 6 Applicable to Figure 5 Pixel circuitry. For example, see... Figure 6 In the same display frame, the second initialization phase T5 follows the first initialization phase T1.

[0134] For example, in the same display frame, the second initialization phase T5 precedes the write phase T2.

[0135] For example, in the same display frame, the second initialization phase T5 precedes the threshold compensation phase T3.

[0136] For example, in the same display frame, the gate signal (e.g., the first gate signal S1) connected to the control terminal of the voltage transmission module 20 includes at least two conduction pulses.

[0137] For example, in the same display frame, the gate signal (e.g., the fourth gate signal S2) connected to the control terminal of the compensation module 30 includes at least two conduction pulses.

[0138] For example, in the same display frame, at least two conduction pulses of the gate signal (e.g., the fourth gate signal S2) connected to the control terminal of the compensation module 30 include a first conduction pulse P1 and a second conduction pulse P2. The first conduction pulse P1 precedes the second conduction pulse P2.

[0139] For example, in the same display frame, at least two conduction pulses of the gate signal (e.g., the first gate signal S1) connected to the control terminal of the voltage transmission module 20 include a third conduction pulse P3 and a fourth conduction pulse P4. The third conduction pulse P3 precedes the fourth conduction pulse P4. The width W21 of the first conduction pulse P1 is smaller than the width W31 of the third conduction pulse P2. The first conduction pulse P1 overlaps with the third conduction pulse P2.

[0140] For example, the width W22 of the second conduction pulse P2 is less than or equal to the width W32 of the fourth conduction pulse P4, and the second conduction pulse P2 overlaps with the fourth conduction pulse P4.

[0141] This application provides another display panel. Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of this application. Figure 7 Applicable Figure 5 Pixel circuitry. For example, see... Figure 7 The first selection circuit 70 also includes a second switch module 72 and a third switch module 73. The first terminal of the second switch module 72 and the first terminal of the third switch module 73 are electrically connected to the second terminal of the first switch module 71. The first terminal of the second switch module 72 is connected to a first initialization voltage Vref1, and the first terminal of the third switch module 73 is connected to a second initialization voltage Vref2.

[0142] For example, in the first initialization phase T1, the first switch module 71 is turned on, the second switch module 72 is turned on, and the third switch module 73 is turned off. With this configuration, in the first initialization phase T1, the first initialization voltage Vref1 can be transmitted to the first signal line L1 and the first terminal of the voltage transmission module 20 via the turned-on second switch module 72 and the first switch module 71.

[0143] For example, in the second initialization phase T5, the first switch module 71 is turned on, the second switch module 72 is turned off, and the third switch module 73 is turned on. With this configuration, the second initialization voltage Vref2 can be transmitted to the first signal line L1 and the first terminal of the voltage transmission module 20 via the turned-on third switch module 73 and the first switch module 71 in the second initialization phase T5.

[0144] For example, the control terminals of the second switch module 72 and the third switch module 73 are electrically connected to different signal lines and / or connected to different control signals. For example, the control terminal of the second switch module 72 is connected to the second control signal Se1, and the control terminal of the third switch module 73 is connected to the third control signal Se2.

[0145] For example, during the threshold compensation phase T3 and / or the write phase T2, the second switch module 72 and the third switch module 73 are turned off.

[0146] For example, the number of first switch modules 71 in a single first selection circuit 70 may be greater than or equal to 3.

[0147] For example, at least two first signal lines L1 correspond to the same second switch module 72. For example, at least three first signal lines L1 correspond to the same second switch module 72.

[0148] For example, at least two first signal lines L1 correspond to the same third switch module 73. For example, at least three first signal lines L1 correspond to the same third switch module 73.

[0149] For example, see Figure 7 The second switching module 72 may include a seventh transistor M7. The second switching module 72 or the seventh transistor M7 may include a P-type transistor (see [reference needed]). Figure 7 The seventh transistor M7 can be a metal-oxide-semiconductor transistor or an N-type transistor. The gate of the seventh transistor M7 can be the control terminal of the second switching module 72. The first terminal of the seventh transistor M7 can be the first terminal of the second switching module 72. The second terminal of the seventh transistor M7 can be the second terminal of the second switching module 72. The second switching module 72 or the seventh transistor M7 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0150] For example, see Figure 7 The third switching module 73 may include an eighth transistor M8. The third switching module 73 or the eighth transistor M8 may include a P-type transistor (see [reference needed]). Figure 7 The eighth transistor M8 can be a metal-oxide-semiconductor transistor or an N-type transistor. The gate of the eighth transistor M8 can be the control terminal of the third switching module 73. The first terminal of the eighth transistor M8 can be the first terminal of the third switching module 73. The second terminal of the eighth transistor M8 can be the second terminal of the third switching module 73. The third switching module 73 or the eighth transistor M8 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0151] Figures 5 to 7 Corresponding technical solutions and Figures 2 to 4 The working principles of the corresponding technical solutions are similar, and will not be elaborated here. The difference lies in... Figures 5 to 7In the corresponding technical solution, the display frame also includes a second initialization phase T5. During at least a portion of the second initialization phase T5, the first gate signal S1 is at an on level, for example, a low level; the second gate signal EM2 is at an off level, for example, a high level; the third gate signal EM1 is at an off level, for example, a high level; the fourth gate signal S2 is at an off level, for example, a high level; the first control signal Re is at an on level, for example, a low level; control signals mux1 to mux6 are at an off level, for example, a high level; the second control signal Se1 is at an off level, for example, a high level; the third control signal Se2 is at an on level, for example, a low level; the first switch module 71 (which may be the sixth transistor M6) and the third switch module 73 (which may be the eighth transistor M8) are turned on, which can transmit the second initialization voltage Vref2 to the first signal line L1 and the first terminal of the voltage transmission module 20 (which may be the first electrode of the second transistor M2). When the voltage transmission module 20 (which can be the second transistor M2) is turned on, it can transmit the second initialization voltage Vref2 to the second terminal S of the drive module 10 (which can be the second terminal of the drive transistor M1) to initialize the second terminal S of the drive module 10. The compensation module 30 (which can be the third transistor M3), the first light-emitting control module 50 (which can be the fifth transistor M5), the second light-emitting control module 60 (which can be the fourth transistor M4), the second switch module 72 (which can be the seventh transistor M7), and the fourth switch module 81 (which can be the ninth transistor M9) are turned off. Figures 5 to 7 In the corresponding technical solution, during at least a portion of the first initialization phase T1, the second control signal Se1 is at an on level, for example, a low level, and the third control signal Se2 is at an off level, for example, a high level; the first switch module 71 (which may be the sixth transistor M6) and the second switch module 72 (which may be the seventh transistor M7) are turned on, which can transmit the first initialization voltage Vref1 to the first signal line L1 and the first terminal of the voltage transmission module 20 (which may be the first pole of the second transistor M2).

[0152] Figures 5 to 7 In the corresponding technical solution, during the threshold compensation stage T3 and / or the writing stage T2, the second control signal Se1 is at a shutdown level, for example, a high level, and the third control signal Se2 is at a shutdown level, for example, a high level.

[0153] For example, see Figure 6 The width W21 of the first turn-on pulse P1 and the width W22 of the second turn-on pulse P2 are equal. This configuration reduces the design complexity of the gate drive circuit and / or the chip.

[0154] For example, see Figure 6The width W31 of the third turn-on pulse P3 and the width W32 of the fourth turn-on pulse P4 are equal. This configuration reduces the design complexity of the gate drive circuit and / or the chip.

[0155] Figure 8 This is a timing waveform diagram of another display frame provided in an embodiment of this application. Figure 8 Applicable to Figure 5 Pixel circuitry. For example, see... Figure 6 The width W21 of the first conduction pulse P1 and the width W22 of the second conduction pulse P2 are not equal. For example, see Figure 6 The width W22 of the second conduction pulse P2 and the width W32 of the fourth conduction pulse P4 are equal. This setting can increase the duration of threshold compensation and improve the compensation effect.

[0156] Figure 5 , Figure 7 , Figure 8 Corresponding technical solutions and Figures 5 to 7 The working principles of the corresponding technical solutions are similar, and will not be elaborated here.

[0157] Figure 9 This is a timing waveform diagram of another display frame provided in an embodiment of this application. Figure 9 Applicable to Figure 5 Pixel circuitry. For example, see... Figure 9 The display frame also includes a third initialization phase T6. In the third initialization phase T6, the voltage transmission module 20 is turned on, the compensation module 30 is turned off, and the first signal line L1 transmits the second initialization voltage Vref2.

[0158] For example, in the third initialization stage T6, the voltage transmission module 20 (which can be the second transistor M2) is turned on, transmitting the second initialization voltage Vref2 to the second terminal S of the drive module 10 (which can be the second electrode of the drive transistor M1) to initialize the second terminal S of the drive module 10. This configuration is beneficial for adjusting the bias state of the drive module 10, thereby improving image retention and / or ghosting.

[0159] For example, in the third initialization stage T6, the first switch module 71 is turned on, the third switch module 73 is turned on, and the second switch module 72 is turned off, so that the second initialization voltage Vref2 can be transmitted to the first signal line L1 and the first terminal of the voltage transmission module 20 (which can be the first terminal of the second transistor M2).

[0160] For example, see Figure 9 In the same display frame, the third initialization phase T6 follows the second initialization phase T5 and / or the write phase T2.

[0161] For example, see Figure 9 For example, the display frame also includes a threshold compensation phase T3. In the threshold compensation phase T3, the voltage transmission module 20 and the compensation module 30 are turned on.

[0162] For example, in the same display frame, the third initialization phase T6 follows the threshold compensation phase T3.

[0163] Figure 5 , Figure 7 , Figure 9 Corresponding technical solutions and Figures 5 to 7 The working principles of the corresponding technical solutions are similar, and will not be elaborated here. The difference lies in... Figure 5 , Figure 7 , Figure 9 In the corresponding technical solution, the display frame also includes a third initialization phase T6. During at least a portion of the third initialization phase T6, the first gate signal S1 is at an on level, for example, a low level; the second gate signal EM2 is at an off level, for example, a high level; the third gate signal EM1 is at an off level, for example, a high level; the fourth gate signal S2 is at an off level, for example, a high level; the first control signal Re is at an on level, for example, a low level; control signals mux1 to mux6 are at an off level, for example, a high level; the second control signal Se1 is at an off level, for example, a high level; the third control signal Se2 is at an on level, for example, a low level; the first switch module 71 (which may be the sixth transistor M6) and the third switch module 73 (which may be the eighth transistor M8) are turned on, which can transmit the second initialization voltage Vref2 to the first signal line L1 and the first terminal of the voltage transmission module 20 (which may be the first electrode of the second transistor M2). When the voltage transmission module 20 (which can be the second transistor M2) is turned on, it can transmit the second initialization voltage Vref2 to the second terminal S of the drive module 10 (which can be the second terminal of the drive transistor M1) to initialize the second terminal S of the drive module 10. The compensation module 30 (which can be the third transistor M3), the first light-emitting control module 50 (which can be the fifth transistor M5), the second light-emitting control module 60 (which can be the fourth transistor M4), the second switch module 72 (which can be the seventh transistor M7), and the fourth switch module 81 (which can be the ninth transistor M9) are turned off.

[0164] Figure 10 This is a timing waveform diagram of another display frame provided in an embodiment of this application. Figure 10 Applicable to Figure 5 The pixel circuit. For example, when the voltage transmission module 20 is turned on during the threshold compensation stage T3, the start time Tz of the first initialization stage T1' of the i+1th row pixel circuit is after the end time Tv of the threshold compensation stage T3 of the i-th row pixel circuit in the same display frame (e.g., the same display frame of the i-th row pixel circuit).

[0165] Figure 10 The first gate signal S1_1, the fourth gate signal S2_1, the third gate signal EM1_1, and the second gate signal EM2_1 of the first row of pixel circuits are illustrated as an example. Figure 10 The first gate signal S1_2, the fourth gate signal S2_2, the third gate signal EM1_2, and the second gate signal EM2_2 of the second row pixel circuit are illustrated as an example.

[0166] Figure 11 A schematic diagram of another pixel circuit structure provided in an embodiment of this application. For example, see... Figure 11 The pixel circuit 200 also includes a second storage module 41. The second storage module 41 is electrically connected to the second terminal S of the driving module 10. For example, the first terminal of the second storage module 41 is electrically connected to the second terminal S of the driving module 10, and the second terminal of the second storage module 41 is connected to the first power line.

[0167] For example, during the write phase T2, the voltage transmission module 20 is turned on and the compensation module 30 is turned off. For example, during the write phase T2, the data voltage Vdata can be transmitted through the turned-on voltage transmission module 20 to the second terminal S of the drive module 10 and the first terminal of the second storage module 41, that is, the data voltage Vdata is stored in the second storage module 41.

[0168] The display frame also includes a threshold compensation stage T3. In threshold compensation stage T3, the voltage transmission module 20 is turned off, and the compensation module 30 is turned on. For example, in threshold compensation stage T3, the data voltage Vdata at the first terminal of the second storage module 41 is charged to the first control terminal G of the driving module 10 via the turned-on driving module 10 and the compensation module 30, i.e., threshold voltage compensation is performed on the driving module 10 until the voltage at the first control terminal G of the driving module 10 is Vdata + Vth. That is, Vdata + Vth is stored in the first storage module 40. In the threshold compensation stage T3 of the i-th row pixel circuit, the voltage transmission module 20 of the i-th row pixel circuit is turned off so that the first initialization voltage Vref1 is simultaneously connected to the first terminal of the voltage transmission module 20 of the (i+1)-th row pixel circuit. This allows for synchronization of the threshold compensation stage T3 of the i-th row pixel circuit and the first initialization stage T1' of the (i+1)-th row pixel circuit, which is beneficial for improving the refresh rate.

[0169] Figure 12 This is a timing waveform diagram of another display frame provided in an embodiment of this application. Figure 12 Applicable to Figure 11 Pixel circuitry. For example, see... Figure 12 In the same display frame, the gate signal (e.g., the fourth gate signal S2) connected to the control terminal of the compensation module 30 includes at least two conduction pulses.

[0170] For example, see Figure 12 In the same display frame, the gate signal (e.g., the first gate signal S1) connected to the control terminal of the voltage transmission module 20 includes a turn-on pulse.

[0171] For example, see Figure 11 The second storage module 41 may include a second capacitor C2. For example, the first terminal of the second capacitor C2 may be the first terminal of the second storage module 41, and the second terminal of the second capacitor C2 may be the second terminal of the second storage module 41.

[0172] Figure 7 , Figure 11 , Figure 12 Corresponding technical solutions and Figures 5 to 7 The working principles of the corresponding technical solutions are similar, and will not be elaborated here. The difference lies in the signal timing of the control terminal of the voltage transmission module 20. Figure 11 A second storage module 41 is set in the pixel circuit.

[0173] Figure 7 , Figure 11 , Figure 12 In the corresponding technical solution, during at least a portion of the writing phases T21 to T26, the first gate signal S1 is at an on level, for example, a low level; the second gate signal EM2 is at an off level, for example, a high level; the third gate signal EM1 is at an off level, for example, a high level; the fourth gate signal S2 is at an off level, for example, a high level; the first control signal Re is at an off level, for example, a high level; the second control signal Se1 is at an off level, for example, a high level; the third control signal Se2 is at an off level, for example, a high level; and control signals mux1 to mux6 are at an on level, for example, a low level, during their respective corresponding writing phases T2. The corresponding fourth switch module 81 (which may be the ninth transistor M9) is turned on, which can transmit the corresponding data voltage Vdata to the first signal line L1 and the first terminal of the voltage transmission module 20 (which may be the first terminal of the second transistor M2), which is equivalent to charging the data voltage Vdata to the first signal line L1. When the voltage transmission module 20 (which can be the second transistor M2) is turned on, the corresponding data voltage Vdata can be transmitted to the second terminal S of the drive module 10 (which can be the second terminal of the drive transistor M1) and the first terminal of the second storage module 41 (which can be the first terminal of the second capacitor C2), that is, the data voltage Vdata is stored in the second storage module 41 (which can be the second capacitor C2). The compensation module 30 (which can be the third transistor M3), the first light-emitting control module 50 (which can be the fifth transistor M5), the second light-emitting control module 60 (which can be the fourth transistor M4), the first switch module 71 (which can be the sixth transistor M6), the second switch module 72 (which can be the seventh transistor M7), and the third switch module 73 (which can be the eighth transistor M8) are turned off.

[0174] Figure 7 , Figure 11 , Figure 12 In the corresponding technical solution, during at least a portion of the threshold compensation stage T3, the first gate signal S1 is at a turn-off level, for example, a high level; the second gate signal EM2 is at a turn-off level, for example, a high level; the third gate signal EM1 is at a turn-off level, for example, a high level; the fourth gate signal S2 is at a turn-on level, for example, a low level; and the control signals mux1 to mux6 are at a turn-off level, for example, a high level. When the compensation module 30 (which can be the third transistor M3) is turned on, the data voltage Vdata at the first terminal of the second storage module 41 (which can be the first electrode of the second capacitor C2) can be charged through the turned-on drive module 10 (which can be the drive transistor M1) and the compensation module 30 (which can be the third transistor M3) to the first control terminal G of the drive module 10 (which can be the first gate of the drive transistor M1) and the first terminal of the first storage module 40 (which can be the first electrode of the first capacitor C1) until the voltage at the first control terminal G of the drive module 10 (which can be the first gate of the drive transistor M1) and the first terminal of the first storage module 40 (which can be the first electrode of the first capacitor C1) is Vdata + Vth, thus achieving threshold compensation for the drive module 10 (which can be the drive transistor M1). The voltage transmission module 20 (which can be the second transistor M2), the first light-emitting control module 50 (which can be the fifth transistor M5), the second light-emitting control module 60 (which can be the fourth transistor M4), and the fourth switch module 81 (which can be the ninth transistor M9) are turned off.

[0175] Figure 13 This is a timing waveform diagram of another display frame provided in an embodiment of this application. Figure 13 Applicable to Figure 11 The pixel circuit. For example, in a pixel circuit 200 including a second storage module 41, when the voltage transmission module 20 is turned off during the threshold compensation stage T2, the first initialization stage T1' of the (i+1)th row pixel circuit overlaps with the threshold compensation stage T3 of the i-th row pixel circuit in the same display frame (e.g., the same display frame of the i-th row pixel circuit). This configuration is beneficial for improving the refresh rate.

[0176] Figure 14 A schematic diagram of another display panel provided in an embodiment of this application. For example, see... Figure 14 The first selection circuit 70 includes at least one of the second switch module 72 and the third switch module 73. The first selection circuit 70 may not have a first switch module 71. Figure 14 Applicable Figure 1 , Figure 2 , Figure 5 or Figure 11 The pixel circuitry. Compared to Figure 14 The technical solution, Figure 7 The technical solution can reduce the number of transistors. Figure 7 The more first switch modules 71 there are in a single first selection circuit 70, the more beneficial it is to reduce the number of transistors, which is equivalent to multiple first signal lines L1 sharing the second switch module 72 and the third switch module 73.

[0177] For example, see Figure 14 The single second selection circuit 80 includes a fourth switch module 81.

[0178] For example, see Figure 14 The first signal line L1 is configured to correspond one-to-one with the second switch module 72.

[0179] For example, see Figure 14 The first signal line L1 is configured to correspond one-to-one with the third switch module 73.

[0180] Figure 15 A schematic diagram of another display panel provided in an embodiment of this application. For example, see... Figure 14 or Figure 15 The second ends of any two fourth switch modules 81 are insulated, that is, they are not electrically connected. Figure 15 Applicable Figure 1 , Figure 2 , Figure 5 or Figure 11 Pixel circuit.

[0181] In some embodiments, the first signal line L1 transmits a first initialization voltage Vref1 and a second initialization voltage Vref2. The first signal line L1 does not transmit a data voltage Vdata. The first signal line L1 may extend along a first direction X. The same first signal line L1 is connected to the first end of the voltage transmission module 20 of a plurality of pixel circuits 200 located in the same row. Alternatively, the first signal line L1 may extend along a second direction Y. The same first signal line L1 is connected to the first end of the voltage transmission module 20 of a plurality of pixel circuits 200 located in the same column.

[0182] Based on the same inventive concept, this application provides another pixel circuit. Figure 16 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. See also... Figures 1 to 15 or Figure 16 The pixel circuit 200 includes a driving module 10, a voltage transmission module 20, and a first storage module 40.

[0183] The light-emitting element 100 is connected between the first terminal D and the second power line of the driving module 10. The second terminal of the voltage transmission module 20 is electrically connected to the second terminal S of the driving module 10. The first terminal D of the voltage transmission module 20 is electrically connected to the first signal line L1. The first storage module 40 is electrically connected to the first control terminal G of the driving module 10.

[0184] The pixel circuit has a display frame, which includes a first initialization phase T1.

[0185] In the first initialization phase T1, the voltage transmission module 20 is turned on, and the first signal line L1 transmits the first initialization voltage Vref1. For example, in the first initialization phase T1, the first terminal of the voltage transmission module 20 is connected to the first initialization voltage Vref1, and the first terminal of the light-emitting element 100 leaks current to the first terminal of the voltage transmission module 20 and / or the first signal line L1 through the turned-on driving module 10 and the voltage transmission module 20 until the voltage of the first terminal of the light-emitting element 100 is Vref1-Vth, so as to initialize the first terminal of the light-emitting element 100.

[0186] The display frame also includes a second initialization phase T5 and / or a write phase T2.

[0187] During the second initialization phase T5, the voltage transmission module 20 is turned on, and the first signal line L1 transmits the second initialization voltage Vref2. The first initialization voltage Vref1 and the second initialization voltage Vref2 are different.

[0188] For example, in the second initialization stage T5, the first terminal of the voltage transmission module 20 is connected to the second initialization voltage Vref2. The second initialization voltage Vref2 can be transmitted to the second terminal S of the drive module 10 through the conducting voltage transmission module 20 to initialize the second terminal S of the drive module 10. By reasonably setting the second initialization voltage Vref2, a larger voltage difference is achieved between the first control terminal G and the second terminal S of the drive module 10, which is beneficial for adjusting the bias state of the drive module 10, thereby improving image retention and / or ghosting. By transmitting the first initialization voltage Vref1 and the second initialization voltage Vref2 in a time-division manner through the same module (e.g., the voltage transmission module 20), the number of transistors can be reduced, the structure of the pixel circuit can be simplified, and the pixel resolution (PPI) can be improved.

[0189] During the write phase T2, the first signal line L1 transmits the data voltage Vdata. By transmitting the first initialization voltage Vref1 and the data voltage Vdata in a time-division multiplexing manner through the same module (e.g., voltage transmission module 20), the number of transistors can be reduced, the structure of the pixel circuit can be simplified, and the pixel resolution PPI can be improved.

[0190] This embodiment can be combined with some or all of the technical features in the above embodiments, which will not be repeated here.

[0191] Figure 17 A schematic diagram of another pixel circuit structure provided in an embodiment of this application. For example, see... Figure 17 The second control terminal B of the drive module 10 is electrically connected to the second terminal S of the drive module 10. The drive module 10 is a four-terminal device. The second control terminal B of the drive module 10 is shorted to the second terminal S of the drive module 10. When different voltages are applied to the second terminal S of the drive module 10, source-drain switching can be achieved, thereby initializing the first control terminal G of the drive module 10 and performing threshold compensation on the drive module 10.

[0192] For example, see Figure 17 The pixel circuit 200 also includes a first light-emitting control module 50. The first light-emitting control module 50 is connected between the first terminal D of the driving module 10 and the first terminal of the light-emitting element 100.

[0193] For example, in the first initialization phase T1, the first light-emitting control module 50 is turned on. For example, in the first initialization phase T1, the first terminal of the voltage transmission module 20 is connected to the first initialization voltage Vref1. The first terminal of the light-emitting element 100 leaks current to the first terminal of the voltage transmission module 20 and / or the first signal line L1 through the turned-on first light-emitting control module 50, driving module 10, and voltage transmission module 20 until the voltage of the first control terminal G of the driving module 10 is Vref1-Vth, so as to initialize the first terminal of the light-emitting element 100.

[0194] The pixel circuit 200 may include part or all of the driving module 10, compensation module 30, voltage transmission module 20, first storage module 40, first light emission control module 50, second light emission control module 60 and second storage module 41.

[0195] Figure 18 A schematic diagram of another display panel provided in an embodiment of this application. For example, see... Figure 18 The display panel 300 also includes a first gate driving circuit 400. The first gate driving circuit 400 includes multiple cascaded first shift registers 401. The control terminals of the first light emission control module 50 and the second light emission control module 60 in the same pixel circuit 200 are electrically connected to the output terminals of different first shift registers 401, that is, they share the same gate driving circuit.

[0196] For example, the control terminal of the first light-emitting control module 50 is electrically connected to the output terminal of the corresponding first shift register 401 via the second gate line L3. The second gate line L3 can transmit the second gate signal EM2.

[0197] For example, the control terminal of the second light-emitting control module 60 is electrically connected to the output terminal of the corresponding first shift register 401 via the third gate line L2. The third gate line L2 can transmit the third gate signal EM1.

[0198] For example, the control terminal of the second light-emitting control module 60 in the i-th row pixel circuit 200 is electrically connected to the output terminal of the j-th stage first shift register 401. Similarly, the control terminal of the first light-emitting control module 50 in the i-th row pixel circuit 200 is electrically connected to the output terminal of the (j+1)-th stage first shift register 401. Here, j is an integer greater than or equal to 1.

[0199] For example, the control terminal of the second light-emitting control module 60 in the (i+1)th row pixel circuit 200 is electrically connected to the output terminal of the (j+1)th stage first shift register 401.

[0200] For example, the first gate driving circuit 400 is located only on one side of the two opposite sides of the display panel 300 along the first direction X, that is, single-sided driving, so as to reduce the bezel width of the display panel and achieve a narrow bezel.

[0201] Figure 19 A schematic diagram of another display panel provided in an embodiment of this application. For example, see... Figure 19 The display panel 300 also includes a first gate line L4 and at least one second gate driving circuit 500. The second gate driving circuit 500 includes a plurality of cascaded second shift registers 501. The control terminals of the voltage transmission module 20 and / or the compensation module 30 are electrically connected to the output terminals of the second shift registers 501. For example, the control terminals of the voltage transmission module 20 and / or the compensation module 30 are electrically connected to the output terminals of the corresponding second shift registers 501 via the first gate line L4. The first gate line L4 can transmit a first gate signal S1.

[0202] For example, see Figure 19 The display panel 300 also includes two second gate driving circuits 500, such as 500a and 500b. The two second gate driving circuits 500 are located on opposite sides of the display panel 300 along the first direction X, that is, dual-side driving.

[0203] For example, the control terminal of the same voltage transmission module 20 is electrically connected to two second gate drive circuits 500 (e.g., 500a and 500b).

[0204] For example, the control terminal of the same compensation module 30 is electrically connected to two second gate drive circuits 500 (e.g., 500a and 500b).

[0205] For example, multiple first signal lines L1 are arranged along the first direction X.

[0206] For example, the two ends of the first gate line L4 along the first direction X are electrically connected to the output terminals of the second shift register 501 in the second gate drive circuit 500 on both sides.

[0207] Optionally, the display panel 300 includes gate lines (e.g., L2, L3, L4), and the pixel circuit 200 is electrically connected to the gate lines (e.g., gate lines L2, L3, L4, etc.), which extend along a first direction X. For example, multiple gate lines are arranged along a second direction Y. The first direction X (which may be a row direction) intersects with the second direction Y (which may be a column direction), for example, perpendicularly.

[0208] For example, multiple first signal lines L1 (which may be data lines) may extend along the second direction Y and be arranged along the first direction X.

[0209] For example, the multiple rows of pixel circuits 200 are arranged along the second direction Y. For example, each row of pixel circuits 200 includes a plurality of pixel circuits 200 arranged along the first direction X.

[0210] For example, shift registers of the same stage can shift a pulse signal input to the input terminal and then output it to the output terminal. For example, in two adjacent shift register stages, the output terminal of the previous shift register can be electrically connected to the input terminal of the next shift register.

[0211] Figure 20 A schematic diagram of another display panel provided in an embodiment of this application. For example, see... Figure 21 In the same pixel circuit 200, the control terminals of the first light-emitting control module 50 and the second light-emitting control module 60 are electrically connected to different gate driving circuits. For example, the control terminal of the first light-emitting control module 50 can be electrically connected to the gate driving circuit 400b, and the control terminal of the second light-emitting control module 60 can be electrically connected to the gate driving circuit 400a.

[0212] Based on the same inventive concept, embodiments of this application provide another display panel. See also Figure 7 or Figure 15 The display panel 300 includes at least one first selection circuit 70 and multiple first signal lines L1.

[0213] The first selection circuit 70 includes a second switch module 72, a third switch module 73, and a plurality of first switch modules 71. The first terminals of the plurality of first switch modules 71 are electrically connected to different first signal lines L1, and the second terminals of the plurality of first switch modules 71 are electrically connected.

[0214] The first terminal of the second switch module 72 and the first terminal of the third switch module 73 are electrically connected to the second terminal of the first switch module 71. The first terminal of the second switch module 73 is connected to a first voltage (e.g., the first initialization voltage Vref1), and the first terminal of the third switch module 73 is connected to a second voltage (e.g., the second initialization voltage Vref2).

[0215] During the first time period (e.g., the first initialization phase T1), the first switch module 71 is turned on, the second switch module 72 is turned on, and the third switch module 73 is turned off. For example, during the first time period (e.g., the first initialization phase T1), the first voltage (e.g., the first initialization voltage Vref1) is transmitted to the first signal line L1 via the turned-on first switch module 71 and the second switch module 72.

[0216] During the second time period (e.g., the second initialization phase T5), the first switch module 71 is turned on, the second switch module 72 is turned off, and the third switch module 73 is turned on. For example, during the second time period (e.g., the second initialization phase T5), the second voltage (e.g., the second initialization voltage Vref2) is transmitted to the first signal line L1 via the turned-on first switch module 71 and the third switch module 73.

[0217] This configuration reduces the number of transistors and simplifies the circuit structure.

[0218] This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0219] For example, the number of first switch modules 71 in a single first selection circuit 70 is greater than or equal to 3. For example, the number of first switch modules 71 in a single first selection circuit 70 can be 3, 4, 5, 6, 7, or 8, etc. For example, the number of first switch modules 71 in a single first selection circuit 70 can be an even number.

[0220] For example, multiple first switch modules 71 may have the same switching state, and / or the control terminals of multiple first switch modules 71 may be electrically connected to the same signal line L1 and / or connected to the same control signal.

[0221] For example, the display panel 300 also includes a pixel circuit 200. The first signal line L1 is connected to the pixel circuit 200.

[0222] This application provides a driving method. Figure 21 This is a flowchart illustrating a driving method provided in an embodiment of this application. The driving method can be applied to a pixel circuit or a display panel provided in an embodiment of this application. The pixel circuit has a display frame. The display frame includes a first initialization phase T1. The display frame also includes a second initialization phase T5 and / or a write phase T2. The driving method includes: Corresponding to the same pixel circuit: Step S110: In the first initialization stage T1, the voltage transmission module 20 and the compensation module 30 are turned on, and the first signal line L1 transmits the first initialization voltage Vref1.

[0223] In step S120, during the second initialization phase T5, the voltage transmission module 20 is turned on, the compensation module 30 is turned off, and the first signal line L1 transmits the second initialization voltage Vref2. The first initialization voltage Vref1 and the second initialization voltage Vref2 are different.

[0224] Step S130: In the writing stage T2, the first signal line L1 transmits the data voltage Vdata.

[0225] The driving method of this application embodiment can be applied to the pixel circuit 200 of any embodiment of this application or to the display panel 300 of any embodiment of this application, and has the beneficial effects of the pixel circuit of any embodiment of this application, which will not be described again here. This embodiment can be combined with some or all of the features in the above embodiments, which will not be described again here.

[0226] For example, the driving method includes at least one of steps S120 and S130, and step S110.

[0227] Based on the same inventive concept, this application provides another driving method. Figure 22 A flowchart of another driving method provided in an embodiment of this application. This driving method can be applied to a pixel circuit or a display panel provided in an embodiment of this application. The pixel circuit has a display frame. The display frame includes a first initialization phase T1. The display frame also includes a second initialization phase T5 and / or a write phase T2. The driving method includes: Corresponding to the same pixel circuit: Step S210: In the first initialization phase T1, the voltage transmission module 20 is turned on, and the first signal line L1 transmits the first initialization voltage Vref1.

[0228] In step S220, during the second initialization phase T5, the voltage transmission module 20 is turned on, and the first signal line L1 transmits the second initialization voltage Vref2. The first initialization voltage Vref1 and the second initialization voltage Vref2 are different.

[0229] Step S230: In the writing stage T2, the first signal line L1 transmits the data voltage Vdata.

[0230] The driving method of this application embodiment can be applied to the pixel circuit 200 of any embodiment of this application or to the display panel 300 of any embodiment of this application, and has the beneficial effects of the pixel circuit of any embodiment of this application, which will not be described again here. This embodiment can be combined with some or all of the features in the above embodiments, which will not be described again here.

[0231] For example, the driving method includes at least one of steps S220 and S230, and step S210.

[0232] Figure 23 This is a schematic diagram of a display device provided in an embodiment of this application. This application also provides a display device 1, including the display panel 300 provided in any embodiment of this application.

[0233] For example, the display device includes a photosensitive element and a display panel provided in any embodiment of this application. The photosensitive element is used to receive light transmitted through the light-transmitting area. The photosensitive element may include one or more of a camera, a fingerprint recognition module, an ambient light sensor, an infrared sensor, etc.

[0234] For example, the display panel or display device may include a third capacitor connected to the first signal line L1. The third capacitor can be used to store the data voltage Vdata connected to the first signal line L1 during the writing stage T2, so that in the subsequent threshold compensation stage T3, the data voltage Vdata on the first signal line L1 can be charged to the first control terminal G of the driving module 10 through the conducting voltage transmission module 20, driving module 10, and compensation module 30.

[0235] Display devices include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablets, e-books, televisions, access control systems, smart landlines, consoles, laptops, wearable devices, in-vehicle displays, virtual reality (VR) and augmented reality (AR) and other near-eye display devices with display functions.

[0236] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0237] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0238] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes: a driving module, a compensation module, a voltage transmission module, and a first storage module. The compensation module is connected between the first control terminal and the first terminal of the drive module, the second terminal of the voltage transmission module is electrically connected to the second terminal of the drive module, the first terminal of the voltage transmission module is electrically connected to the first signal line, and the first storage module is electrically connected to the first control terminal of the drive module. The pixel circuit has a display frame, which includes a first initialization phase. During the first initialization phase, the voltage transmission module and the compensation module are turned on, and the first signal line transmits the first initialization voltage. The display frame further includes a second initialization phase and / or a write phase. During the second initialization phase, the voltage transmission module is turned on, the compensation module is turned off, and the first signal line transmits the second initialization voltage; the first initialization voltage and the second initialization voltage are different. During the writing phase, the first signal line transmits data voltage.

2. The pixel circuit according to claim 1, characterized in that, During the writing phase, the voltage transmission module and the compensation module are turned off. The display frame further includes a threshold compensation stage, during which the voltage transmission module and the compensation module are turned on; Preferably, within the same display frame, the threshold compensation phase occurs after the write phase. In the same display frame, the first initialization phase precedes the write phase; Preferably, the control terminal of the voltage transmission module and the control terminal of the compensation module are electrically connected to the same gate line and / or connected to the same gate signal; Preferably, the transistors in the voltage transmission module have the same channel type as the transistors in the compensation module.

3. The pixel circuit according to claim 1, characterized in that, The second control terminal of the drive module is electrically connected to the second terminal of the drive module; Preferably, the driving module includes a driving transistor, wherein one of the first control terminal and the second control terminal of the driving module is the top gate of the driving transistor, and the other is the bottom gate of the driving transistor. Preferably, the first control terminal of the driving module is the top gate of the driving transistor, and the second control terminal of the driving module is the bottom gate of the driving transistor; Preferably, the driving transistor is a P-type transistor, and the second initialization voltage is higher than the first initialization voltage; or, the driving transistor is an N-type transistor, and the second initialization voltage is lower than the first initialization voltage. Preferably, the pixel circuit further includes a first light-emitting control module, which is connected between a first end of the driving module and a first end of the light-emitting element. During the first initialization phase, the first light-emitting control module is turned on; During the second initialization phase and / or the writing phase, the first light emission control module is turned off; Preferably, the pixel circuit further includes a second light-emitting control module, which is connected between the second terminal of the driving module and the first power line. During the first initialization phase, the second light-emitting control module is turned off. During the second initialization phase and / or the writing phase, the second light emission control module is turned off; Preferably, the display frame further includes a threshold compensation stage, in which the compensation module is turned on and the first light-emitting control module and the second light-emitting control module are turned off. Preferably, in the same display frame, the width of the turn-off pulse of the gate signal accessed by the control terminal of the first light-emitting control module is the same as the width of the turn-off pulse of the gate signal accessed by the control terminal of the second light-emitting control module. Preferably, in the same display frame, the turn-off pulse of the gate signal accessed by the control terminal of the first light-emitting control module lags behind the turn-off pulse of the gate signal accessed by the control terminal of the second light-emitting control module. Preferably, the transistors in the first light-emitting control module and the transistors in the second light-emitting control module have the same channel type; Preferably, the first initialization phase occurs before the second initialization phase and / or the write phase; Preferably, the voltage on the first power line is a DC voltage; Preferably, the second end of the light-emitting element is electrically connected to the second power line, and the voltage on the second power line is a DC voltage.

4. The pixel circuit according to claim 1, characterized in that, In the same display frame, the second initialization phase follows the first initialization phase; Preferably, in the same display frame, the second initialization phase precedes the writing phase; Preferably, in the same display frame, the gate signal connected to the control terminal of the voltage transmission module includes at least two conduction pulses; In the same display frame, the gate signal accessed by the control terminal of the compensation module includes at least two conduction pulses; Preferably, in the same display frame, the at least two conduction pulses of the gate signal accessed by the control terminal of the compensation module include a first conduction pulse and a second conduction pulse; the first conduction pulse precedes the second conduction pulse. In the same display frame, at least two conduction pulses of the gate signal accessed by the control terminal of the voltage transmission module include a third conduction pulse and a fourth conduction pulse. The third conduction pulse is before the fourth conduction pulse. The width of the first conduction pulse is smaller than the width of the third conduction pulse. The first conduction pulse overlaps with the third conduction pulse. Preferably, the width of the second conduction pulse is less than or equal to the width of the fourth conduction pulse, and the second conduction pulse overlaps with the fourth conduction pulse; Preferably, the display frame further includes a third initialization phase, in which the voltage transmission module is turned on, the compensation module is turned off, and the first signal line transmits a second initialization voltage. In the same display frame, the third initialization phase follows the second initialization phase and / or the write phase; Preferably, the display frame further includes a threshold compensation stage, in which the voltage transmission module and the compensation module are turned on; in the same display frame, the third initialization stage follows the threshold compensation stage.

5. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a second storage module, which is electrically connected to the second terminal of the driving module. During the writing phase, the voltage transmission module is turned on and the compensation module is turned off. The display frame also includes a threshold compensation stage, in which the voltage transmission module is turned off and the compensation module is turned on. Preferably, in the same display frame, the gate signal accessed by the control terminal of the compensation module includes at least two conduction pulses; Preferably, in the same display frame, the gate signal connected to the control terminal of the voltage transmission module includes a turn-on pulse.

6. A pixel circuit, characterized in that, The pixel circuit includes: a driving module, a voltage transmission module, and a first storage module; The light-emitting element is connected between the first end of the driving module and the second power line. The second end of the voltage transmission module is electrically connected to the second end of the driving module. The first end of the voltage transmission module is electrically connected to the first signal line. The first storage module is electrically connected to the first control end of the driving module. The pixel circuit has a display frame, which includes a first initialization phase. During the first initialization phase, the voltage transmission module is turned on, and the first signal line transmits the first initialization voltage. The display frame further includes a second initialization phase and / or a write phase. During the second initialization phase, the voltage transmission module is turned on, and the first signal line transmits the second initialization voltage; the first initialization voltage and the second initialization voltage are different. During the writing phase, the first signal line transmits data voltage.

7. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1-6.

8. The display panel according to claim 7, characterized in that, The display panel further includes a first selection circuit, which includes a plurality of first switch modules. The first ends of the plurality of first switch modules are electrically connected to different first signal lines, and the second ends of the plurality of first switch modules are electrically connected to; During the first initialization phase, the first switch module is turned on, and the second terminal of the first switch module is connected to the first initialization voltage. Preferably, the multiple first switch modules have the same switching state, and / or the control terminals of the multiple first switch modules are electrically connected to the same signal line and / or connected to the same control signal; Preferably, the first selection circuit further includes a second switch module and a third switch module, the first terminal of the second switch module and the first terminal of the third switch module are electrically connected to the second terminal of the first switch module, the first terminal of the second switch module is connected to the first initialization voltage, and the first terminal of the third switch module is connected to the second initialization voltage; During the first initialization phase, the first switch module is turned on, the second switch module is turned on, and the third switch module is turned off. During the second initialization phase, the first switch module is turned on, the second switch module is turned off, and the third switch module is turned on. Preferably, the control terminals of the second switch module and the third switch module are electrically connected to different signal lines and / or connected to different control signals; Preferably, the display panel further includes a second selection circuit, which includes a plurality of fourth switch modules. The first terminals of the plurality of fourth switch modules are electrically connected to different first signal lines, and the second terminals of the plurality of fourth switch modules are electrically connected to each other. The plurality of fourth switch modules in the same second selection circuit are turned on in a time-division manner; During the writing phase, the second terminal of the fourth switching module is connected to the data voltage; During the writing phase of the corresponding pixel circuit, the fourth switch module electrically connected to the corresponding pixel circuit is turned on; Preferably, the control terminals of the plurality of fourth switch modules are electrically connected to different signal lines and / or connected to different control signals; Preferably, the display frame further includes a threshold compensation stage, and the second selection circuit includes n fourth switch modules. In the same display frame, the end time of the write phase of the n pixel circuits located in the i-th row that are electrically connected to the same second selection circuit is before the start time of the threshold compensation phase of the n pixel circuits located in the i-th row that are electrically connected to the same second selection circuit; where n is an integer greater than or equal to 2 and i is an integer greater than or equal to 1. Preferably, during the threshold compensation phase, when the voltage transmission module is turned on, in the same display frame, the start time of the first initialization phase of the pixel circuit in the (i+1)th row is after the end time of the threshold compensation phase of the pixel circuit in the i-th row. Alternatively, if the pixel circuit includes a second storage module, and the voltage transmission module is turned off during the threshold compensation phase, in the same display frame, the first initialization phase of the pixel circuit in the (i+1)th row overlaps with the threshold compensation phase of the pixel circuit in the i-th row. Preferably, the display panel further includes a first gate driving circuit, which includes a plurality of cascaded first shift registers, wherein the control terminals of the first light-emitting control module and the second light-emitting control module in the same pixel circuit are electrically connected to the output terminals of different first shift registers; Preferably, the display panel further includes at least one second gate driving circuit, the second gate driving circuit including a plurality of cascaded second shift registers, and the control terminal of the voltage transmission module and / or the control terminal of the compensation module is electrically connected to the output terminal of the second shift register; Preferably, the display panel further includes two second gate driving circuits, which are located on opposite sides of the display panel along the first direction. The control terminal of the same voltage transmission module is electrically connected to both second gate driving circuits, and / or the control terminal of the same compensation module is electrically connected to both second gate driving circuits. Preferably, the plurality of the first signal lines are arranged along the first direction.

9. A display panel, characterized in that, Includes at least one first selection circuit and multiple first signal lines; The first selection circuit includes a second switch module, a third switch module, and a plurality of first switch modules. The first terminals of the plurality of first switch modules are electrically connected to different first signal lines, and the second terminals of the plurality of first switch modules are electrically connected. The first terminal of the second switch module and the first terminal of the third switch module are electrically connected to the second terminal of the first switch module. The first terminal of the second switch module is connected to a first voltage, and the first terminal of the third switch module is connected to a second voltage. During the first time period, the first switch module is turned on, the second switch module is turned on, and the third switch module is turned off. During the second time period, the first switch module is turned on, the second switch module is turned off, and the third switch module is turned on.

10. A driving method, characterized in that, Applied to a pixel circuit as described in any one of claims 1-5 or a display panel as described in claim 7 or 8, the pixel circuit having a display frame, the display frame including a first initialization phase, the display frame further including a second initialization phase and / or a write phase, the driving method comprising: Corresponding to the same pixel circuit: During the first initialization phase, the voltage transmission module and the compensation module are turned on, and the first signal line transmits the first initialization voltage. During the second initialization phase, the voltage transmission module is turned on, the compensation module is turned off, and the first signal line transmits the second initialization voltage; the first initialization voltage and the second initialization voltage are different. During the writing phase, the first signal line transmits data voltage.

Images