Display apparatus and control method thereof, storage medium

Abstract

The application discloses a display device and a control method thereof and a storage medium, relates to the technical field of display, and the method comprises the following steps: acquiring a current refresh rate of a display device, and acquiring a required repeated refresh number of the display device in a same frame when the display device reaches a preset target refresh rate under the current refresh rate; in the case that a global frame start signal generated based on a data enable signal is detected in the display device, acquiring display data required by the display device in a target frame in which the global frame start signal is located; and based on the repeated refresh number, repeatedly refreshing the display device according to the display data in the target frame. The application solves the technical problem that the display device is prone to flickering.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to display devices and their control methods and storage media. Background Technology

[0002] In the pixel circuitry of OLED (Organic Light-Emitting Diode) display panels, switching devices (such as TFTs (Thin-Film Transistors)) experience leakage current when off. The lower the refresh rate, the longer the single-frame cycle, and the longer the pixel's capacitance maintains the driving voltage. The voltage decay caused by leakage current is more pronounced at higher refresh rates, making flickering more likely during refresh rate switching.

[0003] The above content is only used to help understand the technical solutions of the embodiments of this application, and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main objective of this application is to provide a display device and its control method and storage medium, which aims to solve the technical problem that display devices are prone to flickering.

[0005] To achieve the above objectives, embodiments of this application provide a control method for a display device, the method comprising: The current refresh rate of the display device is obtained, and the number of refresh cycles required by the display device within the same frame is obtained when the display brightness of the display device reaches the preset target refresh rate at the current refresh rate. When a global frame start signal generated based on a data enable signal is detected in the display device, the display data required by the display device in the target frame where the global frame start signal is located is obtained. Based on the number of refreshes, the display device is refreshed repeatedly within the target frame according to the display data.

[0006] In one embodiment, the step of obtaining the number of refresh cycles required by the display device within the same frame when the display brightness reaches the preset target refresh rate at the current refresh rate includes: Calculate the ratio of the current refresh rate to the preset target refresh rate to obtain the refresh ratio; The refresh ratio is rounded up to obtain the number of repeated refreshes.

[0007] In one embodiment, the control method for the display device further includes: In a set of preset intervals consisting of multiple preset refresh intervals, the target refresh interval in which the current refresh rate is located is obtained. The preset refresh interval includes an upper limit refresh rate of the interval, and the absolute value of the difference between the upper limit refresh rates of any two intervals in the set of preset intervals is less than a preset flicker threshold. The upper limit refresh rate of the target refresh range is used as the preset target refresh rate.

[0008] In one embodiment, the step of repeatedly refreshing the display device according to the display data within the target frame based on the number of refresh cycles includes: Through the timing controller in the display device, within the target frame, starting from the global frame start signal, with the frame duration of the preset target refresh rate as the interval, an intra-frame start signal is generated sequentially in a number equal to the number of repeated refreshes. Based on each of the intra-frame start signals, the display device is driven to display data repeatedly within the target frame according to the display data.

[0009] In one embodiment, the step of sequentially driving the display device to display according to the display data within the target frame based on each of the intra-frame start signals includes: For the first intra-frame start signal within the target frame, during the refresh period triggered by the first intra-frame start signal, the display device is driven to display according to the display data obtained from the system-on-a-chip of the display device, and the display data is stored in the frame buffer memory of the display device; For each intra-frame start signal other than the first intra-frame start signal within the target frame, the stored display data is retrieved from the frame buffer memory, and the display device is driven to display during the refresh period triggered by the other intra-frame start signal.

[0010] In one embodiment, the control method for the display device further includes: If a refresh stop signal is detected during the refresh period triggered by the start signal within each frame, the gate line of each pixel row in the display device is set to a preset stop level to stop the refresh during the refresh period.

[0011] In one embodiment, the control method for the display device further includes: For each frame start signal, the timing controller in the display device outputs a refresh stop signal within a preset short duration before the frame start signal is generated and adjacent to the generation time of the frame start signal.

[0012] In addition, to achieve the above objectives, the display device includes a system-on-a-chip (SoC), a timing controller, and a display panel; the output of the SoC is connected to the input of the timing controller, and the output of the timing controller is connected to the display panel. The system-on-a-chip is used to output a data enable signal, and the timing controller is used to output a global frame start signal based on the data enable signal. It is also used to obtain the number of times the display device needs to refresh within the same frame when the display brightness reaches the preset target refresh rate at the current refresh rate. The timing controller is also used to obtain the display data required by the display panel in the target frame where the global frame start signal is located from the system-on-chip, and to repeatedly refresh the display panel in the target frame according to the display data based on the number of refreshes.

[0013] In one embodiment, the display device includes a frame buffer memory, which is disposed within the timing controller, or the frame buffer memory is disposed outside the timing controller and connected to the timing controller. The frame buffer memory is used to store the display data output during the refresh period triggered by the first intra-frame start signal of the target frame.

[0014] Furthermore, to achieve the above objectives, embodiments of this application also provide a computer-readable storage medium storing a program implementing a control method for a display device. When the program for the control method for the display device is executed by a processor, it implements the steps of the control method for the display device as described above.

[0015] One or more technical solutions proposed in this application have at least the following technical effects: This application obtains the current refresh rate of the display device and the display brightness when the display device is working at the current refresh rate, and the number of refreshes required in the same frame when the display brightness reaches the preset target refresh rate; when a global frame start signal generated based on a data enable signal is detected, the display data required by the display device in the target frame where the global frame start signal is located is obtained, and then the display device is refreshed repeatedly in the target frame according to the display data based on the number of refreshes.

[0016] Therefore, this application performs multiple refreshes on the display device within the same target frame, ensuring that each refresh within the same frame drives the display device according to the display data. This is equivalent to dividing a single frame period into multiple shorter periods, allowing the capacitors of the pixels in the display device to be recharged before the voltage significantly decays. This effectively compensates for the voltage decay accumulated due to the extended frame period, thereby ensuring that the actual display brightness at the current refresh rate is consistent with the display brightness at the preset target refresh rate. Consequently, when the refresh rate of the display device changes, the display brightness remains stable at different refresh rates, avoiding brightness differences caused by voltage decay at low refresh rates, and thus eliminating flicker during refresh rate switching. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of the embodiments of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of an OLED pixel unit; Figure 2 This is a flowchart illustrating one embodiment of the control method for the display device in this application. Figure 3 This is a schematic diagram comparing the duration of the effective display area and the vertical blanking area at a refresh rate of 48Hz in the control method of the display device according to an embodiment of this application. Figure 4 This is a schematic diagram comparing the duration of the effective display area and the vertical blanking area at a refresh rate of 240Hz in the control method of the display device according to an embodiment of this application. Figure 5 This is a schematic diagram of a data enable signal, a global frame start signal, and an intra-frame start signal in an example of a control method for a display device according to an embodiment of this application. Figure 6 This is a schematic diagram of a data enable signal, a global frame start signal, and an intra-frame start signal in another example of the control method for a display device according to an embodiment of this application. Figure 7 This is a schematic diagram of a data enable signal, an intra-frame start signal, and a refresh stop signal in another example of the control method for a display device according to an embodiment of this application. Figure 8 This is a waveform diagram of the gate lines connecting each pixel row in the control method of the display device according to an embodiment of this application; Figure 9 This is a schematic diagram of module connections for one embodiment of the display device according to this application. Figure 10 This is a schematic diagram of module connections for another embodiment of the display device shown in this application.

[0020] Explanation of icon numbers: 100. System-on-a-chip; 200. Timing controller; 300. Display panel; 400. Frame buffer memory.

[0021] The objectives, features, and advantages of the embodiments described in this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of the embodiments of this application and are not intended to limit the embodiments of this application.

[0023] To better understand the technical solutions of the embodiments of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0024] OLED technology has gained widespread application due to its advantages, including low power consumption, fast response time, wide viewing angle, high-resolution display, wide temperature range, flexible screen design, and relatively lightweight finished products. The smallest pixel driving unit in an OLED can be a 3T1C architecture; for example, refer to... Figure 1 , Figure 1 This is a schematic diagram of the smallest pixel driving unit in an OLED; ELVDD is the positive power supply voltage terminal for the pixel, ELVSS is the negative power supply voltage terminal for the pixel, DATA is the data line, Gate is the gate line, and Sensor is the pixel sensing signal line. Figure 1 In the diagram, T1 is the data control TFT, used to control the charging and discharging of capacitor C; T2 is the drive control TFT, used to control the current reaching the OLED, thereby controlling the OLED's brightness; and T3 is the sensing TFT, used to detect the current flowing through T2 or the potential of the OLED device's anode. T3 is controlled by the sensor. Figure 1 In the circuit shown, T1 is not an ideal device, so there will be leakage current during the off period of T1, which will lead to the voltage decay of the pixel. The duration of leakage is different for different refresh rates. Compared with high refresh rates, low refresh rates will have more severe leakage, which will make the display device prone to flickering when switching refresh rates.

[0025] This embodiment provides a control method for a display device. This embodiment obtains the current refresh rate of the display device and the display brightness of the display device when it is working at the current refresh rate. When the display brightness reaches the preset target refresh rate, the number of refresh cycles required in the same frame is determined. When a global frame start signal generated based on a data enable signal is detected, the display data required by the display device in the target frame where the global frame start signal is located is obtained. Then, based on the number of refresh cycles, the display device is refreshed repeatedly in the target frame according to the display data.

[0026] Therefore, this embodiment performs multiple refreshes on the display device within the same target frame, ensuring that each refresh within the same frame drives the display device to display according to the display data. This is equivalent to dividing a single frame period into multiple shorter periods, allowing the capacitors of the pixels in the display device to be recharged before the voltage significantly decays. This effectively compensates for the voltage decay accumulated due to the extended frame period, thus ensuring that the actual display brightness at the current refresh rate is consistent with the display brightness at the preset target refresh rate. Consequently, when the refresh rate of the display device changes, the display brightness remains stable at different refresh rates, avoiding brightness differences caused by voltage decay at low refresh rates, thereby eliminating flicker during refresh rate switching.

[0027] Based on this, embodiments of this application provide a control method for a display device, referring to... Figure 2 , Figure 2 This is a flowchart illustrating one embodiment of the control method for a display device according to this application. The control method for the display device includes steps S10 to S30: Step S10: Obtain the current refresh rate of the display device, and obtain the number of times the display device needs to refresh repeatedly within the same frame when the display brightness reaches the preset target refresh rate at the current refresh rate; It should be noted that the current refresh rate is the screen refresh frequency of the display device in the current actual application, measured in Hz, such as 60Hz or 30Hz. The current refresh rate can be obtained from the system-on-a-chip (SoC) of the display device. The preset target refresh rate is a pre-set reference refresh rate at which the display device has the desired display brightness. For example, the preset target refresh rate can be preset to the highest refresh rate supported by the display device (such as 120Hz), or a fixed refresh rate that ensures no flicker, etc. This embodiment does not specifically limit this.

[0028] The refresh count refers to the number of times the display device needs to be refreshed according to the same display data within the same target frame. It is used to compensate for brightness attenuation caused by leakage current. The refresh count includes the original refresh required for that frame.

[0029] For example, the refresh rate can be calculated as the ratio of the current refresh rate to the preset target refresh rate. The refresh rate can then be rounded up to obtain the number of refreshes. For instance, if the current refresh rate is 90Hz and the preset target refresh rate is 240Hz, the ratio is 2.666, which, after rounding up, results in 3 refreshes.

[0030] In other embodiments, a preset refresh rate and preset repetition number mapping table can be pre-stored in the non-volatile memory of the display device. During runtime, the current refresh rate is directly used as an index to look up the refresh repetition number in the preset refresh rate mapping table, without the need for real-time calculation.

[0031] For example, you can refer to Figure 3 and Figure 4 , Figure 3 This diagram illustrates the comparison of the duration of the effective display area and the vertical blanking area at a 48Hz refresh rate. Figure 3 This only visually illustrates the relative duration of the two, without specifying the exact number of lines. Taking this embodiment as an example, at 48Hz, the effective display area (Active) corresponds to 1080 lines in one frame, while the vertical blanking area (V-blanking) corresponds to 4470 lines. The duration of the effective display area is significantly shorter than the duration of the vertical blanking area. (Refer to...) Figure 4 , Figure 4 This diagram illustrates the duration of the effective display area and the vertical blanking area at a 240Hz refresh rate. It only shows the relative size of their durations, without row count markings. At the same resolution (1080 active rows in the effective display area) at 240Hz, the V-blanking area is only 30 rows. In this case, the duration of the effective display area is longer than the duration of the vertical blanking area. At different refresh rates, the number of pixel rows in the effective display area remains constant, while the number of pixel rows in the vertical blanking area varies with the refresh rate; that is, the lower the refresh rate, the more pixel rows the vertical blanking area contains. By adjusting the number of pixel rows in the vertical blanking area at different refresh rates, the charging time per row of pixels can be kept consistent across different refresh rates.

[0032] The longer the vertical blanking region lasts, the more voltage leaks into the pixels, resulting in lower brightness at low refresh rates compared to high refresh rates. This, in turn, can cause flickering during refresh rate switching. Therefore, this embodiment can determine the number of refresh cycles required by the display device within the same frame at the current refresh rate. This allows for subsequent re-driving of the display device according to the required refresh cycle number within the same frame after detecting the global frame start signal, thereby reducing flicker.

[0033] Step S20: If a global frame start signal generated based on a data enable signal is detected in the display device, the display data required by the display device in the target frame where the global frame start signal is located is obtained. It should be noted that the data enable signal is the DE signal. The data enable signal is output by the SOC. The global frame start signal is a frame start signal generated by the timing controller based on the data enable signal, used to identify the start time of a complete frame period. For example, when the rising edge of the DE signal is detected, the timing controller can output the global frame start signal.

[0034] The target frame is the frame containing the global frame start signal, and it continues from the global frame start signal until the next global frame start signal arrives. All repeated refresh operations are completed within this target frame.

[0035] Display data refers to the pixel data of a single frame of image to be displayed within the target frame. It is typically provided by the system-on-a-chip (SoC) and includes the grayscale voltage required for each pixel in the display device within the target frame. Display data can be obtained from the SoC. For example, the global frame start signal can be used as the starting point of the target frame, at which point the display data corresponding to the target frame can be received from the SoC.

[0036] Step S30: Based on the number of refreshes, the display device is refreshed repeatedly according to the display data within the target frame.

[0037] It should be noted that repeatedly refreshing the display device means repeatedly outputting display data to the display panel of the display device according to the number of refreshes within the frame duration corresponding to the target frame, so as to repeatedly refresh the display device according to the display data within the target frame.

[0038] For example, within the target frame, the timing controller generates intra-frame start signals at intervals equal to the number of refresh repetitions, starting from the global frame start signal and with the frame duration of the preset target refresh rate as the interval. Each time the timing controller outputs an intra-frame start signal, it triggers a refresh drive on the display panel according to the display data. In non-integer divisible scenarios (such as a current refresh rate of 90Hz, a preset target refresh rate of 240Hz, and a refresh repetition count of 3), the last refresh can only output partial display data due to the remaining time of the target frame. That is, the last refresh within the target frame may be truncated by the next global frame start signal.

[0039] Therefore, even if the current refresh rate is low, resulting in a longer single-frame cycle, the driving voltage on the pixel capacitor is no longer continuously decaying over a long period of time. Instead, it is periodically refreshed and reset multiple times within a single frame, allowing the pixel to recover to the driving voltage level corresponding to the target brightness in each refresh cycle. This process improves the average brightness within the target frame, making it more consistent with the display brightness perceived by the human eye at the preset target refresh rate. This physically compensates for the voltage decay caused by leakage current, reducing the difference in display brightness when switching from a high refresh rate to a range that is not easily perceived by the human eye, effectively improving the flicker problem.

[0040] This embodiment obtains the current refresh rate of the display device and the display brightness of the display device when it is working at the current refresh rate. It calculates the number of refreshes required in the same frame to reach the display brightness at the preset target refresh rate. When a global frame start signal generated based on the data enable signal is detected, the display data required by the display device in the target frame where the global frame start signal is located is obtained. Then, the display device is refreshed repeatedly in the target frame according to the display data based on the number of refreshes.

[0041] Therefore, this embodiment performs multiple refreshes on the display device within the same target frame, ensuring that each refresh within the same frame drives the display device to display according to the display data. This is equivalent to dividing a single frame period into multiple shorter periods, allowing the capacitors of the pixels in the display device to be recharged before the voltage significantly decays. This effectively compensates for the voltage decay accumulated due to the extended frame period, thus ensuring that the actual display brightness at the current refresh rate is consistent with the display brightness at the preset target refresh rate. Consequently, when the refresh rate of the display device changes, the display brightness remains stable at different refresh rates, avoiding brightness differences caused by voltage decay at low refresh rates, thereby eliminating flicker during refresh rate switching.

[0042] In a feasible embodiment, step S20 further includes steps S21 to S22: Step S21: Calculate the ratio of the current refresh rate to the preset target refresh rate to obtain the refresh ratio; It should be noted that the refresh rate is the ratio of the current refresh rate to the preset target refresh rate. The refresh rate can be used to characterize how many frame periods corresponding to the preset target refresh rate can theoretically be accommodated within one frame period of the current refresh rate. The refresh rate can be an integer or a non-integer.

[0043] Step S22: Round the refresh ratio up to get the number of refreshes.

[0044] It should be noted that when the refresh rate is an integer, the result of rounding up is equal to itself; when the refresh rate is a non-integer containing decimals, the result of rounding up is the smallest integer greater than that value. For example, when the current refresh rate is 60Hz and the preset target refresh rate is 240Hz, the refresh rate is 4 and the number of refreshes is also 4. When the current refresh rate is 90Hz and the preset target refresh rate is 240Hz, the refresh rate is 2.67, and the number of refreshes is 3 when rounded up.

[0045] For example, the current refresh rate can be obtained through a timing controller in the display device. The timing controller can then determine the number of refresh cycles based on the current refresh rate and a preset target refresh rate. For instance, the number of refresh cycles can be obtained by rounding up the ratio of the current refresh rate to the preset target refresh rate. The obtained current refresh rate is the refresh rate corresponding to the target frame.

[0046] This embodiment determines the number of refresh cycles based on a preset target refresh rate and the current refresh rate, ensuring that the number of refresh cycles performed within the target frame always meets the requirements for compensating for leakage voltage attenuation: when the refresh ratio is an integer, the display brightness can accurately reach the level of the preset target refresh rate; when the refresh ratio is not an integer, a larger number of refresh cycles is obtained by rounding up, so that the brightness attenuation caused by leakage can be compensated regardless of the current refresh rate, making the display brightness consistent under different refresh rates, thereby eliminating the flicker that can be perceived by the human eye when switching refresh rates.

[0047] In a feasible embodiment, the control method for the display device further includes steps A10 to A20: Step A10: In the preset interval set consisting of multiple preset refresh intervals, obtain the target refresh interval where the current refresh rate is located. The preset refresh interval includes the upper limit refresh rate of the interval, and the absolute value of the difference between the upper limit refresh rates of any two intervals in the preset interval set is less than the preset flicker threshold. Step A20: Use the upper limit refresh rate of the target refresh range as the preset target refresh rate.

[0048] It should be noted that the preset refresh interval is a pre-defined range of refresh rates, defined by the upper and lower limits of the interval. The upper limit refresh rate refers to the highest refresh rate within the preset refresh interval, and will serve as the corresponding preset target refresh rate for all refresh rates within that interval.

[0049] A preset refresh interval set refers to a set of multiple preset refresh intervals that collectively cover the refresh rate range supported by the display device. The absolute value of the difference between the upper limit refresh rates of any two intervals in the preset refresh interval set is less than a preset flicker threshold. The target refresh interval is a preset refresh interval determined from the preset interval set that contains the current refresh rate value.

[0050] The preset flicker threshold is determined based on the refresh rate range from which flicker is perceptible to the human eye when the display device switches refresh rates. When the absolute value of the difference between two refresh rates is less than the preset flicker threshold, the difference in display brightness presented by the display device at these two refresh rates is perceived by the human eye as having no noticeable flicker. When the absolute value of the difference between two refresh rates is greater than or equal to the preset flicker threshold, the difference in display brightness presented by the display device at these two refresh rates may be perceived by the human eye as flicker.

[0051] For display devices, flickering doesn't necessarily occur only when the refresh rate ranges from the device's minimum to its maximum. Rather, the human eye can perceive screen flickering caused by brightness differences when the refresh rate change exceeds a preset flicker threshold. For example, a display panel may not exhibit VRR flickering when switching between 60Hz and 70Hz, but it will show noticeable VRR flickering when switching between 60Hz and 180Hz.

[0052] If the maximum refresh rate supported by the display device is used as the uniform preset target refresh rate, then regardless of the current refresh rate level, the display brightness must be compensated to the display brightness corresponding to the maximum refresh rate. Although there will be no flickering, it will lead to an unnecessary increase in power consumption.

[0053] To achieve a balance between eliminating flicker and reducing power consumption, this embodiment determines the target refresh interval of the current refresh rate and uses the upper limit refresh rate of the target refresh interval as the preset target refresh rate corresponding to the current refresh rate. This ensures that the display brightness at the current refresh rate reaches the display brightness at the preset target refresh rate. Specifically, in this embodiment, the refresh rate span at which VRR flickering occurs can be determined first, i.e., the preset flicker threshold. For example, if testing determines that the display device flickers when the refresh rate span reaches 130Hz, then the preset flicker threshold is set to 130Hz. When dividing the preset refresh interval, it is necessary to ensure that the absolute value of the difference between the upper limit refresh rates of any two intervals in the preset interval set is less than the preset flicker threshold, i.e., less than 130Hz.

[0054] For example, the full refresh rate range of a display device can be divided into two preset refresh intervals: the first preset refresh interval is [60Hz, 120Hz], and the second preset refresh interval is (120Hz, 240Hz). When the current refresh rate falls within the first preset refresh interval, the upper limit of the interval, 120Hz, is set as the preset target refresh rate, and all refresh rates within the first preset refresh interval use 120Hz as the preset target refresh rate. When the current refresh rate falls within the second preset refresh interval, the upper limit of the interval, 240Hz, is set as the preset target refresh rate, and all refresh rates within the second preset refresh interval use 240Hz as the preset target refresh rate.

[0055] Therefore, this embodiment determines the preset target refresh rate by dividing the refresh rate into different levels, which can reduce power consumption without the human eye being able to perceive flicker.

[0056] In a feasible embodiment, step S30 further includes steps S31 to S32: Step S31: Through the timing controller in the display device, within the target frame, starting from the global frame start signal, at intervals of the frame duration of the preset target refresh rate, the number of frame start signals is generated sequentially, equal to the number of repeated refreshes. It should be noted that the intra-frame start signal is a pulse signal autonomously generated by the timing controller during the refresh period of the target frame. The generation of each intra-frame start signal marks the beginning of a new refresh scan operation within that target frame. The total number of intra-frame start signals equals the number of refresh repetitions. Intra-frame start signals are generated sequentially within the target frame in a number equal to the number of refresh repetitions. The first intra-frame start signal within the target frame is synchronized with the global frame start signal, and the time interval between two adjacent intra-frame start signals within the target frame is the frame duration of the preset target refresh rate.

[0057] Frame duration for preset target refresh rate: This refers to the time length corresponding to a complete refresh operation of a single frame, calculated based on the preset target refresh rate. This duration is the reciprocal of the preset target refresh rate and is used as the time interval between the start signals of two adjacent frames.

[0058] For example, when the global frame start signal arrives, the timing controller generates the first intra-frame start signal, and then generates intra-frame start signals sequentially at intervals equal to the frame duration of the preset target refresh rate. The number of intra-frame start signals within the same target frame is the number of refresh repetitions. The interval between two adjacent intra-frame start signals within the same target frame is the frame duration of the preset target refresh rate.

[0059] Step S32: Based on the start signal within each frame, drive the display device to display repeatedly according to the display data within the target frame.

[0060] In this embodiment, for each intra-frame start signal, after the intra-frame start signal is output, the timing controller will output display data to the display panel, so that display data can be output multiple times in the target frame. The number of times display data is output in the same target frame is the number of refreshes. When the refresh ratio is not an integer, the display data output after the last intra-frame start signal in the target frame will be interrupted.

[0061] This embodiment uses a timing controller to sequentially generate intra-frame start signals within the target frame at intervals equal to the frame duration of the preset target refresh rate. The display is then repeatedly driven based on each intra-frame start signal, dividing a long frame period at a low refresh rate into multiple short periods. Within each short period, the display device is refreshed using the same display data. Because the time interval between each refresh is shortened to the frame duration of the preset target refresh rate, the pixel capacitors can be periodically recharged to the target grayscale voltage within the same frame. Therefore, the average display brightness within the target frame is effectively maintained at the level corresponding to the preset target refresh rate, ensuring that the display brightness at the current refresh rate is consistent with the display brightness at the preset target refresh rate, eliminating flicker caused by brightness differences during refresh rate switching. Although multiple refreshes occur within the target frame, since they are all based on the same display data, the refresh rate perceived by the human eye is still the current refresh rate, but the display brightness perceived by the human eye is consistent with the preset target refresh rate.

[0062] For example, you can refer to Figure 5 , Figure 5 The diagram illustrates the data enable signal DE, the global frame start signal STV1, and the intra-frame start signal STV2. The data enable signal DE exhibits periodic high and low level changes. The high-level interval of DE corresponds to the effective image data output period. Upon detecting the rising edge of DE, the timing controller synchronously generates the global frame start signal STV1. STV1 identifies the start time of a single target frame. The global frame start signal STV1 is a narrow pulse signal, generated only once per target frame. The intra-frame start signal STV2 is also a narrow pulse, and multiple STV2 signals are generated within a target frame. Figure 5 As can be seen from the data, the target frame contains two intra-frame start signals, which divide the target frame into the first sub-frame and the second sub-frame. This indicates that the target frame is refreshed twice. The first STV2 in the target frame is triggered synchronously with the STV1 in the same target frame, which starts the refresh of the first sub-frame. When the second intra-frame start signal is output, the refresh is started in the second sub-frame. The time interval between two adjacent STV2s in the target frame is equal to the frame duration corresponding to the preset target refresh rate. After each STV2 in the target frame is output, the timing controller will input display data based on the target frame to the display panel of the display device.

[0063] In a feasible embodiment, step S32 further includes steps S321 to S322: Step S321: For the first intra-frame start signal in the target frame, during the refresh period triggered by the first intra-frame start signal, drive the display device to display according to the display data obtained from the system-on-a-chip of the display device, and store the display data in the frame buffer memory of the display device; It should be noted that the first intra-frame start signal is the first intra-frame start signal generated within the target frame. The first intra-frame start signal can be synchronized with the global frame start signal.

[0064] The refresh period triggered by the first intra-frame start signal is the time period from the moment the first intra-frame start signal is triggered until the arrival of the next intra-frame start signal. Within the refresh interval triggered by the first intra-frame start signal, the corresponding grayscale voltage is written to each pixel in the display panel line by line according to the display data obtained from the system-on-a-chip, so as to complete one refresh drive for the display data.

[0065] The system-on-a-chip (SoC) is the main control chip in a display device, used to output data enable signals and display data. The frame buffer is a storage device used to store a complete frame of display data; it can be a separate memory chip or integrated within the timing controller. The frame buffer can support multiple reads after a single write operation.

[0066] For example, the timing controller integrates a frame buffer memory. When the first intra-frame start signal is generated, the timing controller receives display data from the system-on-a-chip, outputs the display data to the display panel according to the line scan timing to drive the display, and writes the display data line by line into the internal frame buffer memory to complete the storage.

[0067] In other embodiments, the frame buffer memory is set up independently of the timing controller but connected to it. When the first intra-frame start signal is generated, the timing controller receives display data from the system-on-a-chip and, while driving the display panel, sends the display data to an external frame buffer memory for storage.

[0068] This embodiment stores the display data triggered by the initial signal within the first frame into the frame buffer memory. This data storage is completed synchronously during the first refresh of the target frame, eliminating the need to request the same data from the system-on-a-chip (SoC) during subsequent refreshes within the same frame. This reduces the number of data transfers between the SoC and the display driver circuit, thus lowering system power consumption. Furthermore, storing the display data in the frame buffer memory ensures that the display data used in subsequent refreshes within the same target frame is completely consistent with the initial refresh.

[0069] Step S322: For each intra-frame start signal other than the first intra-frame start signal within the target frame, retrieve the stored display data from the frame buffer memory and drive the display device to display during the refresh period triggered by the other intra-frame start signal.

[0070] It should be noted that each time a new intra-frame start signal is generated, the timing controller initiates a read operation request to the frame buffer memory, retrieving the same set of display data stored in step S321. After retrieval, the timing controller outputs the display data to the display panel to drive the display panel in the display device. Specifically, the timing controller can read the stored display data line by line from the frame buffer memory and drive the display panel according to the row scanning timing of the display panel. During this process, the system-on-a-chip (SoC) does not need to participate; the timing controller independently completes the refresh actions corresponding to each new intra-frame start signal.

[0071] This embodiment ensures that during the multiple refreshes of the target frame, the system-on-a-chip (SoC) only needs to transmit display data once during the first refresh. Subsequent refreshes are handled entirely by the timing controller and frame buffer memory, eliminating the need for the SoC to repeatedly participate in data transmission. Furthermore, since the display data used during the refresh period triggered by the first intra-frame start signal and the refresh periods triggered by other intra-frame start signals within the target frame is identical, the pixel charging voltage remains consistent across all refreshes within the target frame. This helps maintain the average display brightness within the entire target frame stably at the level corresponding to the preset target refresh rate, effectively eliminating flickering during refresh rate switching.

[0072] In a feasible embodiment, the control method of the display device further includes step B10: if a refresh stop signal is detected during the refresh period triggered by the start signal in each frame, the gate line of each pixel row in the display device is set to a preset stop level to stop the refresh during the refresh period.

[0073] It should be noted that the refresh stop signal is a control signal generated by the timing controller. It is used to forcibly interrupt the currently ongoing refresh operation before the refresh period triggered by the start signal within a frame has ended. The refresh stop signal is usually generated just before the start signal of the next frame or the start signal of the next global frame arrives.

[0074] The preset stop level is a pre-set voltage level applied to the gate line that turns off the thin-film transistors (TFTs) of a pixel. When the gate line is set to the preset stop level, the TFTs in the corresponding pixel row stop conducting, and data voltage cannot be written to the pixel capacitor. The preset gate stop level can be VGL.

[0075] When the current refresh rate and the preset target refresh rate are not divisible by an integer, the time boundary of the target frame cannot precisely accommodate an integer number of complete refreshes of the preset target refresh rate frame duration. During the refresh period triggered by the last intra-frame start signal, the next global frame start signal arrives before all pixel rows have been traversed. If, during the refresh period triggered by the last intra-frame start signal within the target frame, scanning continues to move the pixel rows in the display panel, the currently incomplete refresh will overlap with the first refresh of the next target frame, potentially leading to two different frames of display data existing simultaneously on the display panel, causing screen tearing or other abnormalities. By outputting a refresh stop signal and uniformly setting all gate lines to the preset stop level, the current refresh action can be terminated before the next global frame start signal arrives, causing all pixel rows to enter a shutdown state. Therefore, after the next global frame start signal arrives, the timing controller can restart the row scan from the first row of pixels on the display panel, driving the display data of the next target frame to refresh normally.

[0076] In a feasible embodiment, the control method of the display device further includes step C10: for each intra-frame start signal, the timing controller in the display device outputs a refresh stop signal within a preset short duration before the intra-frame start signal is generated and adjacent to the generation time of the intra-frame start signal.

[0077] It should be noted that the preset short duration is a pre-set time length that immediately precedes the generation time of the start signal within each frame, and is used to define the output time window of the refresh stop signal. The value of the preset short duration should be short enough to ensure that the refresh stop signal and the start signal within the frame are sequentially continuous.

[0078] For example, before generating each intra-frame start signal, the timing controller outputs a refresh stop signal within a preset short duration; after outputting the refresh stop signal, the timing controller generates the intra-frame start signal. In other embodiments, the refresh stop signal may also be output within a preset short duration adjacent to the end time of each global frame start signal.

[0079] For example, you can refer to Figure 6 , Figure 6 This demonstrates the different scenarios for the data enable signal DE, the global frame start signal STV1, and the intra-frame start signal when the current refresh rate is not an integer multiple of the preset target refresh rate. Figure 6 The example shown is the intra-frame start signal with a current refresh rate of 90Hz and a preset target refresh rate of 240Hz. Figure 6The STV2(1) and STV2(2) shown illustrate different cases of intra-frame start signals. Three intra-frame start signals are generated within the target frame, corresponding to three refresh cycles. The first intra-frame start signal is triggered synchronously with the STV1 of the same frame. In STV2(1), 11, 12, and 13 correspond to the first, second, and third subframes within the target frame, respectively. In STV2(2), 21, 22, and 23 also correspond to the first, second, and third subframes within the target frame. The difference between STV2(1) and STV2(2) is that the duration of the third subframe in STV2(1) is shorter than that of the first and second subframes in STV2(1). The duration of the third subframe in STV2(2) is the same as that of the first and second subframes in STV2(2), but the third subframe in STV2(2) will cover the refresh period corresponding to the next global frame start signal.

[0080] Therefore, in order to avoid timing conflicts caused by the last refresh in the previous target frame not being completed when the global frame start signal of the next target frame arrives, this embodiment outputs a refresh stop signal in advance within a preset short period of time before the start signal in each frame is generated, so as to reset the output of the level converter, so that when the next global frame start signal arrives, scanning can start from the first row of pixels on the display panel.

[0081] For example, refer to Figure 7 , Figure 7 The diagram shows the data enable signal DE, the intra-frame start signal STV2, and the refresh stop signal Stop. The refresh stop signal can also be a narrow pulse signal. Figure 7 As can be seen, a refresh stop signal is output before the rising edge of the start signal STV2 in each frame. The refresh stop signal is also a narrow pulse signal.

[0082] For example, you can also refer to Figure 8 , Figure 8 This diagram illustrates the waveforms of the gate lines connecting each pixel row in a display device. Figure 8 As can be seen, the gate lines of each pixel row in the display device switch to a high level row by row, for example, Figure 8 In the image, the gate lines Gate(n) of the nth row of pixels, Gate(n+1) of the (n+1)th row of pixels, and Gate(n+2) of the (n+2)th row of pixels are all configured to a preset stop level after the timing controller outputs a refresh stop signal. At this time, the thin-film transistors of all pixel rows are synchronously turned off, and the screen refresh operation stops. When a new STVn is output, the gate lines are switched to a high level row by row according to the top-down scanning order, starting from the gate line corresponding to the first row of pixels. The thin-film transistors of each row of pixels are turned on in turn, and the grayscale voltage required for each pixel in that row is output row by row. For example, refer to... Figure 8 , Figure 8 The gate lines Gate (1) of the first row of pixels, Gate (2) of the second row of pixels, and Gate (3) of the third row of pixels are turned on in sequence. STVn can be the global frame start signal STV1 or the intra-frame start signal STV2.

[0083] Specifically, TCON sends a refresh stop signal to the level converter LS, which pulls all outputs of LS low and sets all gate lines to the preset stop level. To reduce TCON's computation, a refresh stop signal is also added before DE arrives and STV1 is about to output. Therefore, TCON does not need to distinguish whether the refresh stop signal is added before STV1 or STV2. In this embodiment, refresh stop signals are added before both STV1 and STV2, thus eliminating the need for TCON to distinguish between STV1 and STV2 before outputting the refresh stop signal, thereby reducing TCON's computational burden.

[0084] This embodiment outputs a refresh stop signal within a preset short duration adjacent to the start signal generation time in each frame. This ensures that before each new refresh operation begins, the gate lines of each pixel row in the display panel are pre-set to a preset stop level, guaranteeing that the previous refresh operation (whether completed naturally or interrupted) has completely ended. This provides a definite initial state for the next refresh (starting scanning from the first pixel row of the display panel), thus ensuring the reliability of the display device.

[0085] Furthermore, based on the above embodiments of this application, in another embodiment of this application, the same or similar content as the above embodiments can be referred to the above description, and will not be repeated hereafter. Based on this, refer to... Figure 9 The display device includes a system-on-a-chip 100, a timing controller 200, and a display panel 300; the output of the system-on-a-chip 100 is connected to the input of the timing controller 200, and the output of the timing controller 200 is connected to the display panel 300. The system-on-a-chip 100 is used to output a data enable signal, and the timing controller 200 is used to output a global frame start signal based on the data enable signal. It is also used to obtain the number of times the display device needs to refresh within the same frame when the display brightness reaches the preset target refresh rate at the current refresh rate. The timing controller 200 is also used to obtain the display data required by the display panel 300 in the target frame where the global frame start signal is located from the system-on-chip 100, and refresh the display panel 300 repeatedly in the target frame according to the display data based on the number of refreshes.

[0086] It should be noted that the system-on-a-chip (SoC) is the SOC in the display device. In this embodiment, the timing controller can obtain the display data required for the target frame from the SOC. The timing controller is the TCON. The display panel is the panel in the display device that displays the image. The display panel includes multiple pixel rows, and each pixel row includes multiple pixels.

[0087] In this embodiment, the timing controller can obtain the current refresh rate of the display device, and also obtain the number of refresh cycles required for the display device to achieve the display brightness at a preset target refresh rate within the same frame at the current refresh rate. The system-on-a-chip (SoC) can output a data enable signal, and the timing controller can generate a global frame start signal based on the data enable signal. It can also obtain the display data within the target frame where the global frame start signal is located from the SoC. Furthermore, the timing controller can repeatedly refresh the display device within the target frame according to the display data based on the number of refresh cycles.

[0088] This embodiment performs multiple refreshes on the display device within the same target frame, ensuring that each refresh within the same frame drives the display panel according to the display data. This is equivalent to dividing a single frame period into multiple shorter periods, allowing the capacitors of the pixels in the display panel to be recharged before the voltage significantly decays. This effectively compensates for the voltage decay accumulated due to the extended frame period, thus ensuring that the actual display brightness at the current refresh rate is consistent with the display brightness at the preset target refresh rate. Therefore, when the refresh rate of the display device changes, the display brightness remains stable at different refresh rates, avoiding brightness differences caused by voltage decay at low refresh rates, thereby eliminating flicker during refresh rate switching.

[0089] In one feasible embodiment, refer to Figure 10 The display device includes a frame buffer memory, which may be located inside the timing controller or outside the timing controller and connected to the timing controller. The frame buffer is used to store the display data output during the refresh period triggered by the start signal of the first frame of the target frame.

[0090] It should be noted that the frame buffer memory is a storage unit in a display device used to temporarily store at least one complete frame of display data. This storage unit can be implemented by random access memory and has the ability to write, retain, and read data multiple times, enabling it to repeatedly provide the same display data to the timing controller within the time range of the target frame. The first intra-frame start signal is the first frame start signal generated by the timing controller within the target frame, which is synchronized with the global frame start signal in timing, marking the start of the first refresh operation within the target frame.

[0091] The frame buffer can be located inside the timing controller. The timing controller performs data writing and reading operations on the frame buffer internally. The timing controller reads data directly from the internal frame buffer, resulting in low data access latency.

[0092] In other embodiments, the frame buffer memory can also be located externally to the timing controller. When the frame buffer memory is located externally to the timing controller, it is connected to the timing controller. During the refresh period triggered by the start signal within the first frame of the target frame, the timing controller receives display data from the system-on-a-chip (SoC) and, while driving the display panel, sends the display data to the frame buffer memory for storage. During subsequent refreshes within the same target frame, the timing controller reads the display data from the frame buffer memory. By placing the frame buffer memory externally to the timing controller, its configuration is not limited by the internal storage resources of the timing controller chip.

[0093] By storing the display data output during the initial refresh of the target frame in a frame buffer, subsequent refreshes within the target frame can directly retrieve this display data from the frame buffer without needing to request data from the system-on-a-chip (SoC). This avoids the SoC performing additional data retransmissions to accommodate repeated refreshes, allowing the SoC to update and distribute display data at a normal frame rate.

[0094] The display device in this application embodiment may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (such as in-vehicle navigation terminals), and other devices capable of displaying images such as digital TVs and desktop computers.

[0095] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0096] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0097] This embodiment provides a computer-readable storage medium having computer-readable program instructions stored thereon, which are used to execute the control method of the display device in the first embodiment described above.

[0098] The computer-readable storage medium provided in this application embodiment may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor devices, apparatuses, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable EPROM (Electrical Programmable Read Only Memory) or flash memory, optical fiber, portable compact disk CD-ROM (compact discread-only memory), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution device, apparatus, or apparatus. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0099] The aforementioned computer-readable storage medium may be included in the display device or may exist independently without being assembled into the display device.

[0100] The aforementioned computer-readable storage medium carries one or more programs that, when executed by a display device, cause the display device to: acquire the current refresh rate of the display device and acquire the number of refresh cycles required within the same frame for the display device to achieve the display brightness at a preset target refresh rate at the current refresh rate; acquire the display data required by the display device within the target frame where the global frame start signal is located, if a global frame start signal generated based on a data enable signal is detected within the display device; and repeatedly refresh the display device according to the display data within the target frame based on the number of refresh cycles.

[0101] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a LAN (local area network) or WAN (wide area network)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0102] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of devices, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based device that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0103] The modules described in the embodiments of this disclosure can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0104] The computer-readable storage medium provided in this application embodiment stores computer-readable program instructions for executing the control method of the above-described display device, aiming to solve the technical problem of flickering in display devices. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application embodiment are the same as the beneficial effects of the control method of the display device provided in the above-described embodiments, and will not be repeated here.

[0105] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the control method for the display device as described above.

[0106] The computer program product provided in this application aims to solve the technical problem of flickering in display devices. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the display device control method provided in the above embodiments, and will not be repeated here.

[0107] The above are merely preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structural or procedural transformations made using the description and drawings of the present application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present application.

Claims

1. A control method for a display device, characterized in that, The method includes: The current refresh rate of the display device is obtained, and the number of refresh cycles required by the display device within the same frame is obtained when the display brightness of the display device reaches the preset target refresh rate at the current refresh rate. When a global frame start signal generated based on a data enable signal is detected in the display device, the display data required by the display device in the target frame where the global frame start signal is located is obtained. Based on the number of refreshes, the display device is refreshed repeatedly within the target frame according to the display data.

2. The control method for the display device as described in claim 1, characterized in that, The step of obtaining the number of refresh cycles required by the display device within the same frame when the display device reaches the display brightness at the current refresh rate and a preset target refresh rate includes: Calculate the ratio of the current refresh rate to the preset target refresh rate to obtain the refresh ratio; The refresh ratio is rounded up to obtain the number of repeated refreshes.

3. The control method for the display device as described in claim 1, characterized in that, The control method for the display device further includes: In a set of preset intervals consisting of multiple preset refresh intervals, the target refresh interval in which the current refresh rate is located is obtained. The preset refresh interval includes an upper limit refresh rate of the interval, and the absolute value of the difference between the upper limit refresh rates of any two intervals in the set of preset intervals is less than a preset flicker threshold. The upper limit refresh rate of the target refresh range is used as the preset target refresh rate.

4. The control method for the display device as described in claim 1, characterized in that, The step of repeatedly refreshing the display device according to the display data within the target frame based on the number of refreshes includes: Through the timing controller in the display device, within the target frame, starting from the global frame start signal, with the frame duration of the preset target refresh rate as the interval, an intra-frame start signal is generated sequentially in a number equal to the number of repeated refreshes. Based on each of the intra-frame start signals, the display device is driven to display data repeatedly within the target frame according to the display data.

5. The control method for the display device as described in claim 4, characterized in that, The step of sequentially driving the display device to display according to the display data within the target frame based on each of the intra-frame start signals includes: For the first intra-frame start signal within the target frame, during the refresh period triggered by the first intra-frame start signal, the display device is driven to display according to the display data obtained from the system-on-a-chip of the display device, and the display data is stored in the frame buffer memory of the display device; For each intra-frame start signal other than the first intra-frame start signal within the target frame, the stored display data is retrieved from the frame buffer memory, and the display device is driven to display during the refresh period triggered by the other intra-frame start signal.

6. The control method for the display device as described in claim 4, characterized in that, The control method for the display device further includes: If a refresh stop signal is detected during the refresh period triggered by the start signal within each frame, the gate line of each pixel row in the display device is set to a preset stop level to stop the refresh during the refresh period.

7. The control method for the display device as described in claim 6, characterized in that, The control method for the display device further includes: For each frame start signal, the timing controller in the display device outputs a refresh stop signal within a preset short duration before the frame start signal is generated and adjacent to the generation time of the frame start signal.

8. A display device, characterized in that, The display device includes a system-on-a-chip (SoC), a timing controller, and a display panel; the output of the SoC is connected to the input of the timing controller, and the output of the timing controller is connected to the display panel. The system-on-a-chip is used to output a data enable signal, and the timing controller is used to output a global frame start signal based on the data enable signal. It is also used to obtain the number of times the display device needs to refresh within the same frame when the display brightness reaches the preset target refresh rate at the current refresh rate. The timing controller is also used to obtain the display data required by the display panel in the target frame where the global frame start signal is located from the system-on-chip, and to repeatedly refresh the display panel in the target frame according to the display data based on the number of refreshes.

9. The display device as claimed in claim 8, characterized in that, The display device includes a frame buffer memory, which is disposed within the timing controller or disposed outside the timing controller and connected to the timing controller. The frame buffer memory is used to store the display data output during the refresh period triggered by the first intra-frame start signal of the target frame.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and the computer-readable storage medium stores a program that implements a control method for a display device. The program that implements the control method for a display device is executed by a processor to implement the steps of the control method for a display device as described in any one of claims 1 to 7.

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