Pixel driving circuit based on gray scale self-adaptive reset, driving method, display panel and display device

Abstract

The application provides a pixel driving circuit based on gray scale adaptive reset, a driving method, a display panel and a display device. The pixel driving circuit comprises a gray scale adaptive reset circuit, a driving circuit, a storage circuit, a first reset circuit, a second reset circuit, a compensation circuit, a light-emitting control circuit and a light-emitting element. The gray scale adaptive reset circuit can generate a corresponding reset voltage according to a gray scale voltage input from a gray scale voltage input end and reset a first node connected with the driving circuit according to the reset voltage. According to the specific driving mode, the application independently applies different reset voltages to each pixel according to different display gray scales, so that the high and low gray scale flickers of the screen can reach the effect that the human eyes cannot see when the low refresh rate is displayed.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and in particular to a pixel driving circuit, driving method, display panel and display device based on grayscale adaptive reset. Background Technology

[0002] After each frame of light emission is completed, the storage nodes inside the pixel driving circuit retain residual charge, causing the node potential to deviate from the preset standard initial potential. If the next frame's data signal is written directly, the residual charge will superimpose on the newly written signal, leading to display defects such as image ghosting and brightness distortion. Existing technologies typically use a globally uniform voltage to reset the storage node potential, but this reset scheme has a drawback: the node voltage reset effect varies with grayscale changes, resulting in inconsistent screen flicker across different grayscale levels during low refresh rate displays.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] To address the problems in the prior art, the purpose of this application is to provide a pixel driving circuit, driving method, display panel, and display device based on grayscale adaptive reset, which aims to solve the problem that screen flicker cannot be consistent across different grayscale levels when displaying at low refresh rates due to existing node reset schemes.

[0005] The first aspect of this application provides a pixel driving circuit based on grayscale adaptive resetting, characterized in that it includes: A grayscale adaptive reset circuit is provided, which is connected to the grayscale voltage input terminal, the scan signal input terminal group, the first voltage input terminal, the first power supply terminal, and the first node, respectively. A driving circuit, which is connected to the first node, the second node and the third node respectively; A storage circuit, wherein the storage circuit is connected to the first power supply terminal and the second node respectively; A first reset circuit is connected to a first scan signal input terminal, a second voltage input terminal, and a second node, respectively. A compensation circuit is connected to the scan signal input terminal group, the second node, and the third node, respectively. The second reset circuit is connected to the scan signal input terminal group, the third voltage input terminal, and the first terminal of the light-emitting element; the second terminal of the light-emitting element is also connected to the second power supply terminal. A light-emitting control circuit is connected to the first power supply terminal, the driving circuit, the enable signal input terminal, and the first terminal of the light-emitting element. The grayscale adaptive reset circuit is used to generate a corresponding reset voltage based on the grayscale voltage input at the grayscale voltage input terminal and reset the first node accordingly.

[0006] In one embodiment of the first aspect of this application, the grayscale adaptive reset circuit includes: a data writing sub-circuit, a first reset sub-circuit, a second reset sub-circuit, a third reset sub-circuit, and a storage sub-circuit; the scan signal input terminal group includes: a second scan signal input terminal, a third scan signal input terminal, a fourth scan signal input terminal, and a fifth scan signal input terminal; The data writing sub-circuit is connected to the grayscale voltage input terminal, the second scan signal input terminal, and the first node, respectively; the first reset sub-circuit is connected to the third scan signal input terminal, the first node, and the fourth node, respectively; the data writing sub-circuit and the first reset sub-circuit are configured to write the grayscale voltage of the grayscale voltage input terminal to the fourth node, respectively; the first reset sub-circuit is further configured to reset the voltage of the first node according to the voltage of the fourth node; The second reset sub-circuit is connected to the first power supply terminal, the fifth node, and the fourth scan signal input terminal, respectively. The second reset sub-circuit is configured to write the voltage of the first power supply terminal to the fifth node. The third reset sub-circuit is connected to the fifth node, the first voltage input terminal and the fifth scan signal input terminal respectively, and the third reset sub-circuit is configured to write the voltage of the first voltage input terminal to the fifth node; The storage sub-circuit is connected to the fourth node and the fifth node respectively, and the storage sub-circuit is configured to store the grayscale voltage.

[0007] In one embodiment of the first aspect of this application, the data writing sub-circuit includes a first transistor, and the first reset sub-circuit includes an eighth transistor; wherein, the gate of the first transistor is connected to a second scan signal input terminal, the first electrode is connected to the grayscale voltage input terminal, and the second electrode is connected to the first node; the gate of the eighth transistor is connected to a third scan signal input terminal, the first electrode is connected to the first node, and the second electrode is connected to the fourth node.

[0008] In one embodiment of the first aspect of this application, the second reset sub-circuit includes a ninth transistor, the gate of which is connected to a fourth scan signal input terminal, the first terminal of which is connected to the first power supply terminal, and the second terminal of which is connected to the fifth node.

[0009] In one embodiment of the first aspect of this application, the third reset sub-circuit includes a tenth transistor, the gate of which is connected to a fifth scan signal input terminal, the first terminal of which is connected to the first voltage input terminal, and the second terminal of which is connected to the fifth node.

[0010] In one embodiment of the first aspect of this application, the storage sub-circuit includes a first capacitor, the capacitance of which increases as the refresh rate decreases.

[0011] In one embodiment of the first aspect of this application, the capacitance value of the parasitic capacitance of the first node is less than the capacitance value of the first capacitor.

[0012] A second aspect of this application also provides a driving method for driving the pixel driving circuit based on grayscale adaptive resetting as described above, the method comprising:

[0013] During the first frame, after resetting the voltage of the second node, the grayscale adaptive reset circuit generates a corresponding reset voltage based on the grayscale voltage input at the grayscale voltage input terminal and stores the threshold voltage of the driving circuit, and then controls the light-emitting element to emit light. During each frame from the second frame to the Nth frame, the grayscale adaptive reset circuit resets the voltage of the first node according to the reset voltage, and then provides an enable signal to the enable signal input terminal to make the light-emitting element emit light.

[0014] In one embodiment of the second aspect of this application, the first frame includes: a reset phase, a threshold voltage storage phase, a reset voltage generation phase, and a light emission phase; During the reset phase, the voltage of the second node is reset using the first reset circuit; During the threshold voltage storage stage, a grayscale voltage is written to the grayscale adaptive reset circuit and the threshold voltage of the driving circuit is stored in the storage circuit through the compensation circuit. During the reset voltage generation stage, the gray-scale adaptive reset circuit generates a corresponding reset voltage based on the gray-scale voltage input at the gray-scale voltage input terminal. During the light-emitting phase, an enable signal is provided to the enable signal input terminal to make the light-emitting element emit light.

[0015] A third aspect of this application also provides a display panel, including the pixel driving circuit based on grayscale adaptive reset as described above.

[0016] A fourth aspect of this application also provides a display device, including the display panel described above.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application.

[0018] The pixel driving circuit, driving method, display panel, and display device based on grayscale adaptive resetting of this application have the following beneficial effects: This application uses a specific driving method to apply differentiated reset voltages to each pixel independently based on different display grayscale levels, so that the flickering of both high and low grayscale levels on the screen is invisible to the human eye when displaying at low refresh rates. Attached Figure Description

[0019] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0020] Figure 1 This is a schematic block diagram of a pixel driving circuit based on grayscale adaptive reset according to an embodiment of this application.

[0021] Figure 2 This is a schematic block diagram of a grayscale adaptive reset circuit according to an embodiment of this application.

[0022] Figure 3 This is a schematic diagram of the specific circuit structure of a pixel driving circuit based on grayscale adaptive reset according to an embodiment of this application.

[0023] Figure 4 This is a schematic diagram of the transistor switching in stage 1 of the first frame of an embodiment of this application.

[0024] Figure 5 This is a schematic diagram of the transistor switching on and off in stage 2 of the first frame of an embodiment of this application.

[0025] Figure 6 This is a schematic diagram of the transistor switching on and off in stage 3 of the first frame of an embodiment of this application.

[0026] Figure 7 This is a schematic diagram of the transistor switching on and off in stage 4 of the first frame of an embodiment of this application.

[0027] Figure 8 This is a schematic diagram of the transistor switching on and off during the light-emitting stage according to an embodiment of this application.

[0028] Figure 9 This is a schematic diagram of the transistor switching during the reset phase according to an embodiment of this application.

[0029] Figure 10 This is a timing diagram of a pixel driving circuit in operation according to an embodiment of this application.

[0030] Figure 11 This is a flowchart of a driving method according to an embodiment of this application.

[0031] Component labeling: First transistor T1, Second transistor T2, Third transistor T3, Fourth transistor T4, Fifth transistor T5, Sixth transistor T6, Seventh transistor T7, Eighth transistor T8, Ninth transistor T9, Tenth transistor T10, First scan signal input terminal Sn1 n-1 The second scan signal input terminal Sn1 n Third scan signal input terminal Sn2 n Fourth scan signal input terminal Rn1 n Fifth scan signal input terminal Rn2 n Enable signal input terminal EN n LED L, first power supply terminal ELVDD, second power supply terminal ELVSS, first voltage input terminal VINT1, second voltage input terminal VINT2, third voltage input terminal VINT3, first capacitor Cstress, second capacitor Cst. Detailed Implementation

[0032] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted.

[0033] The use of terms such as "first," "second," and similar terms in the specific description does not indicate any order, quantity, or importance, but is merely used to distinguish different components. Furthermore, in the description of this invention, terms such as "upper," "lower," etc., indicate orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings. These are merely for ease of description and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention.

[0034] It should be noted that, unless otherwise specified, the embodiments of the present invention and the features in different embodiments can be combined with each other.

[0035] like Figure 1 As shown, this application embodiment provides a pixel driving circuit based on grayscale adaptive reset, including: grayscale adaptive reset circuit 1, driving circuit 2, storage circuit 3, first reset circuit 4, compensation circuit 5, second reset circuit 6, light-emitting element 7, and light-emitting control circuit 8.

[0036] Among them, the grayscale adaptive reset circuit 1 is connected to the grayscale voltage input terminal DATA, the scan signal input terminal group S, the first voltage input terminal VINT1, the first power supply terminal ELVDD and the first node N1 respectively.

[0037] The scanning signal input terminal group S includes several scanning signal input terminals. In this embodiment, the input of several scanning signal input terminals can be controlled according to a specific driving timing sequence to generate a corresponding reset voltage based on the grayscale voltage input from the grayscale voltage input terminal, and to reset the first node N1 connected to the driving circuit 2 according to the reset voltage. When the grayscale voltage changes, the reset voltage generated by the grayscale adaptive reset circuit 1 will also change accordingly, so as to achieve the effect of generating different reset voltages according to different grayscale voltages. In addition, the reset voltage contains grayscale voltage information. Therefore, by using the reset voltage to reset the first node N1, the consistency of the voltage reset effect under each grayscale can be achieved, so that the flickering of high and low grayscale levels on the screen during low refresh rate display is invisible to the human eye.

[0038] The drive circuit 2 is connected to the first node N1, the second node N2, and the third node N3, respectively. The drive circuit turns on and off according to the voltage of the second node N2, and also controls the drive current flowing through the drive circuit 2 according to the voltage relationship between the first node N1 and the second node N2.

[0039] Storage circuit 3 is connected to the first power supply terminal ELVDD and the second node N2, respectively. Storage circuit 3 is used to store the threshold voltage of drive circuit 2 during the threshold voltage storage phase.

[0040] The first reset circuit 4 is connected to the first scan signal input terminal Sn1. n The second voltage input terminal VINT2 and the second node N2 are used to set the voltage of the second node N2 to the voltage of the second voltage input terminal VINT2 during the reset phase, so as to establish a reference potential for subsequent threshold voltage storage.

[0041] The compensation circuit 5 is connected to the scan signal input group S, the second node N2, and the third node N3, respectively. When turned on, the compensation circuit, together with the storage circuit, the second node N2, the third node N3, and the driving circuit 2, forms a threshold voltage storage path associated with the driving circuit 2. At this time, the conduction characteristics of the driving circuit 2 can be used to store its threshold voltage, establishing a voltage difference containing threshold voltage information for the storage circuit.

[0042] The second reset circuit 6 is connected to the scan signal input terminal group S, the third voltage input terminal VINT3, and the first terminal of the light-emitting element 7. The second terminal of the light-emitting element 7 is also connected to the second power supply terminal ELVSS. The second reset circuit 6 is used to set the voltage of the first terminal of the light-emitting element 7 to the voltage of the third voltage input terminal VINT3 during the reset phase, so as to clear residual charge, eliminate afterimages, and ensure that the working start point of each frame is consistent.

[0043] The light-emitting control circuit 8 is connected to the first power supply terminal ELVDD, the driver circuit 2, and the enable signal input terminal EN, respectively. n And the first end of the light-emitting element 7. When the light-emitting control circuit 8 is turned on, it will form a current path with the driving circuit 2 to make the light-emitting element 7 emit light.

[0044] It should be noted that the aforementioned beneficial effects do not mean that all implementation methods must simultaneously possess all the technical effects. In specific applications, the corresponding technical effects can be obtained based on the transistor parameters, capacitor parameters, scanning timing of the pixel driving circuit, and the operating conditions of the display panel.

[0045] Figure 2 for Figure 1 Structural block diagram of the mid-grayscale adaptive reset circuit. (See diagram below.) Figure 2 As shown, the grayscale adaptive reset circuit 1 may include a data writing sub-circuit 11, a first reset sub-circuit 12, a second reset sub-circuit 13, a third reset sub-circuit 14, and a storage sub-circuit 15. The scan signal input terminal group may include a second scan signal input terminal Sn1. n Third scan signal input terminal Sn2 n Fourth scan signal input terminal Rn1 n and the fifth scan signal input terminal Rn2 n .

[0046] The data writing sub-circuit 11 is connected to the grayscale voltage input terminal DATA and the second scan signal input terminal Sn1, respectively. n And the first node N1. The data writing sub-circuit 11 is configured to write the grayscale voltage of the grayscale voltage input terminal DATA to the first node N1.

[0047] Specifically, the second scan signal input terminal Sn1 n This is used to provide a second scan signal. The second scan signal is used to control the data writing sub-circuit 11, causing the data writing sub-circuit 11 to conduct in response to the second scan signal, thereby establishing a conductive path between the grayscale voltage input terminal DATA and the first node N1. In one embodiment, the second scan signal has an effective level for controlling the conduction of the data writing sub-circuit 11.

[0048] When the data writing sub-circuit 11 is turned on, the gray level voltage of the gray level voltage input terminal DATA can be transmitted to the first node N1 through the data writing sub-circuit 11, so that the voltage of the first node N1 becomes a gray level voltage.

[0049] The first reset sub-circuit 12 is connected to the third scan signal input terminal Sn2. n The first reset sub-circuit 12 is configured to write the voltage of the first node N1 to the fourth node N4, or write the voltage of the fourth node N4 to the first node N1.

[0050] Specifically, the third scan signal input terminal Sn2 n This is used to provide a third scan signal. The third scan signal is used to control the first reset sub-circuit 12, causing the first reset sub-circuit 12 to conduct in response to the second scan signal, thereby establishing a conductive path between the first node N1 and the fourth node N4. In one embodiment, the third scan signal has an effective level for controlling the first reset sub-circuit 12 to conduct.

[0051] When the first reset sub-circuit 12 is turned on, the voltage of the first node N1 can be transmitted to the fourth node N4 through the first reset sub-circuit 12, or the voltage of the fourth node N4 can be transmitted to the first node N1 through the first reset sub-circuit 12.

[0052] In one embodiment, in order to write the grayscale voltage to the fourth node N4 so that a corresponding reset voltage can be generated based on the grayscale voltage in the future, the data writing sub-circuit 11 and the first reset sub-circuit 12 need to be turned on simultaneously to establish a conductive path from the grayscale voltage input terminal DATA to the first node N1 and then to the fourth node N4, so that the grayscale voltage of the grayscale voltage input terminal DATA is transmitted to the fourth node N4 via the first node N1.

[0053] The second reset sub-circuit 13 is connected to the first power supply terminal ELVDD, the fifth node N5, and the fourth scan signal input terminal Rn1, respectively. n The second reset sub-circuit 13 is configured to write the voltage of the first power supply terminal ELVDD to the fifth node N5.

[0054] Specifically, the fourth scan signal input terminal Rn1 n A fourth scan signal is provided. The fourth scan signal is used to control the second reset sub-circuit 13, causing the second reset sub-circuit 13 to conduct in response to the fourth scan signal, thereby establishing a conductive path between the first power supply terminal ELVDD and the fifth node N5. In one embodiment, the fifth scan signal has an effective level for controlling the conduction of the second reset sub-circuit 13.

[0055] When the second reset sub-circuit 13 is turned on, the voltage of the first power supply terminal ELVDD can be transmitted to the fifth node N5 through the second reset sub-circuit 13, so that the voltage of the fifth node N5 becomes the voltage of the first power supply terminal ELVDD.

[0056] The third reset sub-circuit 14 is connected to the fifth node N5, the first voltage input terminal VINT1, and the fifth scan signal input terminal Rn2, respectively. n The third reset sub-circuit 14 is configured to write the voltage of the first voltage input terminal VINT1 to the fifth node N5.

[0057] Specifically, the fifth scan signal input terminal Rn2 n A fifth scan signal is provided. The fifth scan signal is used to control the third reset sub-circuit 14, causing the third reset sub-circuit 14 to conduct in response to the fifth scan signal, thereby establishing a conductive path between the first voltage input terminal VINT1 and the fifth node N5. In one embodiment, the fifth scan signal has an effective level for controlling the conduction of the third reset sub-circuit 14.

[0058] When the third reset sub-circuit 14 is turned on, the voltage of the first voltage input terminal VINT1 can be transmitted to the fifth node N5 through the third reset sub-circuit 14, so that the voltage of the fifth node N5 becomes the voltage of the first voltage input terminal VINT1.

[0059] The storage sub-circuit 15 is connected to the fourth node N4 and the fifth node N5 respectively, and the storage sub-circuit 15 is configured to store grayscale voltage.

[0060] In one embodiment, by simultaneously controlling the data writing sub-circuit 11, the first reset sub-circuit 12 and the second reset sub-circuit 13 to be turned on, the voltages of the first node N1 and the fourth node N4 are set to grayscale voltages, and the voltage of the fifth node is set to the voltage ELVDD of the first power supply terminal. The storage sub-circuit 15 will follow the voltage changes of the two nodes to complete the charge flow, thereby forming a stable voltage difference containing grayscale voltage information.

[0061] When the voltage of the fifth node N5 is set to the voltage of the first voltage input terminal VINT1, the storage sub-circuit 15 can use this voltage difference to change the voltage of the fourth node N4, thereby generating a reset voltage containing grayscale voltage.

[0062] In this embodiment, the first scan signal input terminal Sn1 n-1 The received scan signal is the scan drive signal for the (n-1)th row, and the second scan signal input terminal Sn1. n The received scan signal is the scan drive signal for the nth row. The third scan signal input terminal Sn2 n Fourth scan signal input terminal Rn1 nand the fifth scan signal input terminal Rn2 n They can be connected to different scan lines. In this embodiment, the scan line, also known as the gate line or G line for short, is the control line of the horizontally arranged, row-by-row switching pixel thin-film transistors (TFTs) in the pixel driving circuit.

[0063] Figure 3 exhibit Figure 1 The circuit diagram shown is a detailed representation of the circuit structure. Figure 3 As shown, the data writing sub-circuit includes a first transistor T1.

[0064] The gate of the first transistor T1 is connected to the second scan signal input terminal Sn1. n The first terminal of the first transistor T1 is connected to the grayscale voltage input terminal DATA, and the second terminal of the first transistor T1 is connected to the first node N1.

[0065] Therefore, the first transistor T1 is positioned between the grayscale voltage input terminal DATA and the first node N1, and connected to the second scan signal input terminal Sn1. n The second scan signal provides control. When the second scan signal is at an active level, the first transistor T1 is turned on, forming a grayscale voltage transmission path between the grayscale voltage input terminal DATA and the first node N1, so that the grayscale voltage of the grayscale voltage input terminal DATA is transmitted to the first node N1 through the grayscale voltage transmission path.

[0066] When the second scan signal is at an invalid level, the first transistor T1 is turned off, and an open circuit is formed between the grayscale voltage input terminal DATA and the first node N1.

[0067] It should be noted that the specific device type of the first transistor T1 can be set according to the process conditions and control logic of the pixel driving circuit, and this application does not make any specific limitations in this regard.

[0068] In one embodiment, the first terminal of the first transistor T1 can be the source or the drain, and the second terminal of the first transistor T1 can be the source or the drain accordingly.

[0069] In one embodiment, the first transistor T1 is a P-type thin-film transistor. The second scan signal uses a low level as the active level and a high level as the inactive level. When the second scan signal is low, the first transistor T1 is turned on, forming a gray-scale voltage transmission path between the gray-scale voltage input terminal DATA and the first node N1, so that the gray-scale voltage of the gray-scale voltage input terminal DATA is transmitted to the first node N1 through the gray-scale voltage transmission path.

[0070] When the second scan signal is high, the first transistor T1 is turned off, and an open circuit is formed between the grayscale voltage input terminal DATA and the first node N1.

[0071] This document only illustrates the implementation of the first transistor T1 by way of example. In specific applications, the effective and ineffective levels of the second scan signal can be adjusted according to the type of transistor used to turn the first transistor T1 on or off. This disclosure does not make any specific limitations in this regard.

[0072] Continue reading Figure 3 The first reset sub-circuit includes an eighth transistor T8. The gate of the eighth transistor T8 is connected to the third scan signal input terminal Sn2. n The first terminal of the eighth transistor T8 is connected to the first node N1, and the second terminal of the eighth transistor T8 is connected to the fourth node N4.

[0073] Therefore, the eighth transistor T8 is positioned between the first node N1 and the fourth node N4, and is connected to the third scan signal input terminal Sn2. n The third scan signal provides control. When the third scan signal is at an active level, the eighth transistor T8 is turned on, forming a voltage transmission path between the first node N1 and the fourth node N4. The voltage of the first node N1 can be transmitted to the fourth node N4 through this voltage transmission path, and similarly, the voltage of the fourth node N4 can also be transmitted to the first node N1 through this voltage transmission path.

[0074] When the third scan signal is at an invalid level, the eighth transistor T8 is turned off, and an open circuit is formed between the first node N1 and the fourth node N4.

[0075] It should be noted that the specific device type of the eighth transistor T8 can be set according to the process conditions and control logic of the pixel driving circuit, and this application does not make any specific restrictions on it.

[0076] In one embodiment, the first terminal of the eighth transistor T8 can be the source or the drain, and the second terminal of the eighth transistor T8 can be the source or the drain accordingly.

[0077] In one embodiment, the eighth transistor T8 is a P-type thin-film transistor. The third scan signal uses a low level as the active level and a high level as the inactive level. When the second scan signal is low, the eighth transistor T8 is turned on, forming a voltage transmission path between the first node N1 and the fourth node N4. The voltage of the first node N1 is transmitted to the fourth node N4 through this voltage transmission path, or the voltage of the fourth node N4 is transmitted to the first node N1 through this voltage transmission path.

[0078] When the third scan signal is high, the eighth transistor T8 is turned off, and an open circuit is formed between the first node N1 and the fourth node N4.

[0079] This document only illustrates the implementation of the eighth transistor T8. In specific applications, the effective and ineffective levels of the third scan signal can be adjusted according to the type of transistor used to turn the eighth transistor T8 on or off. This application does not impose any specific limitations on this.

[0080] In one embodiment, during the threshold voltage storage stage, while the second scan signal controls the first transistor T1 to turn on, the third scan signal also synchronously controls the eighth transistor T8 to turn on, so that the first transistor T1 and the eighth transistor T8 are turned on at the same time, establishing a conductive path from the grayscale voltage input terminal DATA to the first node N1 and then to the fourth node N4. After the grayscale voltage of the grayscale voltage input terminal DATA is transmitted to the first node N1, it is then transmitted from the first node N1 to the fourth node N4.

[0081] In one embodiment, during the reset phase, the third scan signal controls the eighth transistor T8 to turn on, establishing a transmission path between the first node N1 and the fourth node N4. The voltage of the fourth node N4 can be transmitted to the first node N1, thereby resetting the voltage of the first node N1.

[0082] like Figure 3 As shown, the second reset sub-circuit includes a ninth transistor T9. The gate of the ninth transistor T8 is connected to the fourth scan signal input terminal Rn1. n The first terminal of the ninth transistor T9 is connected to the first power supply terminal ELVDD, and the second terminal of the ninth transistor T9 is connected to the fifth node N5.

[0083] Therefore, the ninth transistor T9 is positioned between the first power supply terminal ELVDD and the fifth node N5, and is connected to the fourth scan signal input terminal Rn1. n The fourth scan signal provides control. When the fourth scan signal is at an active level, the ninth transistor T9 is turned on, forming a power supply voltage transmission path between the first power supply terminal ELVDD and the fifth node N5. The voltage of the first power supply terminal ELVDD can be transmitted to the fifth node N5 through this power supply voltage transmission path.

[0084] When the fourth scan signal is at an invalid level, the ninth transistor T9 is turned off, and an open circuit is formed between the first power supply terminal ELVDD and the fifth node N5.

[0085] It should be noted that the specific device type of the ninth transistor T9 can be set according to the process conditions and control logic of the pixel driving circuit, and this application does not make any specific limitations in this regard.

[0086] In this embodiment, the first terminal of the ninth transistor T9 can be either the source or the drain, and the second terminal of the ninth transistor T9 can be either the source or the drain.

[0087] In one embodiment, the ninth transistor T9 is a P-type thin-film transistor. The fourth scan signal uses a low level as the active level and a high level as the inactive level. When the fourth scan signal is low, the ninth transistor T9 is turned on, forming a power supply voltage transmission path between the first power supply terminal ELVDD and the fifth node N5. The voltage of the first power supply terminal ELVDD is transmitted to the fifth node N5 through this power supply voltage transmission path.

[0088] When the third scan signal is high, the ninth transistor T9 is turned off, and an open circuit is formed between the first node N1 and the fourth node N4.

[0089] This document only illustrates the implementation of the ninth transistor T9. In specific applications, the effective and ineffective levels of the third scan signal can be adjusted according to the type of transistor used to turn the ninth transistor T9 on or off. This application does not impose any specific limitations on this.

[0090] In one embodiment, during the threshold voltage storage stage, the second scan signal controls the first transistor T1 to turn on, and the third scan signal also controls the eighth transistor T8 to turn on. At the same time, the third scan signal controls the ninth transistor T9 to turn on, so that the first transistor T1, the eighth transistor T8, and the ninth transistor T9 are turned on simultaneously. This establishes a transmission path from the grayscale voltage input terminal DATA to the first node N1 and then to the fourth node N4, as well as a transmission path from the first power supply terminal ELVDD to the fifth node N5. After the grayscale voltage of the grayscale voltage input terminal DATA is transmitted to the first node N1, it is then transmitted from the first node N1 to the fourth node N4, and the voltage of the first power supply terminal ELVDD is transmitted to the fifth node N5.

[0091] In one embodiment, after the second scan signal, the third scan signal, and the fourth scan signal return to an invalid level, the first transistor T1, the eighth transistor T8, and the ninth transistor T9 are all turned off. The transmission paths between the grayscale voltage input terminal DATA and the first node N1, the first node N1 and the fourth node N4, and the fifth node N5 and the first power supply terminal ELVDD are all disconnected. The first node N1 and the fourth node N4 remain at grayscale voltage, and the voltage of the fifth node N5 remains at the voltage of the first power supply terminal ELVDD.

[0092] like Figure 3 As shown, the third reset sub-circuit includes a tenth transistor T10. The gate of the tenth transistor T10 is connected to the fifth scan signal input terminal Rn2. n The first terminal of the tenth transistor T10 is connected to the fifth node N5, and the second terminal of the tenth transistor T10 is connected to the first voltage input terminal VINT1.

[0093] Therefore, the tenth transistor T10 is positioned between the first voltage input terminal VINT1 and the fifth node N5, and is connected to the fifth scan signal input terminal Rn2. n The fifth scan signal provides control. When the fifth scan signal is at an active level, the tenth transistor T10 is turned on, forming a first voltage input voltage transmission path between the first voltage input terminal VINT1 and the fifth node N5. The voltage of the first voltage input terminal VINT1 can be transmitted to the fifth node N5 through this first voltage input voltage transmission path.

[0094] When the fifth scan signal is at an invalid level, the tenth transistor T10 is turned off, and an open circuit is formed between the first voltage input terminal VINT1 and the fifth node N5.

[0095] It should be noted that the specific device type of the tenth transistor T10 can be set according to the process conditions and control logic of the pixel driving circuit, and this application does not make any specific restrictions on it.

[0096] In one embodiment, the tenth transistor T10 is a P-type thin-film transistor. The fifth scan signal uses a low level as the active level and a high level as the inactive level. When the fifth scan signal is low, the tenth transistor T10 is turned on, forming a first voltage input voltage transmission path between the first voltage input terminal VINT1 and the fifth node N5. The voltage of the first voltage input terminal VINT1 is transmitted to the fifth node N5 through this first voltage input voltage transmission path.

[0097] When the fifth scan signal is high, the tenth transistor T10 is turned off, and an open circuit is formed between the first voltage input terminal VINT1 and the fourth node N4.

[0098] This document only illustrates the implementation of the tenth transistor T10 by way of example. In specific applications, the effective and ineffective levels of the fifth scan signal can be adjusted according to the type of transistor used to turn the tenth transistor T10 on or off. This disclosure does not make any specific limitations in this regard.

[0099] In one embodiment, the first terminal of the tenth transistor T10 can be the source or the drain, and the second terminal of the tenth transistor T10 can be the source or the drain accordingly.

[0100] like Figure 3 As shown, the storage sub-circuit includes a first capacitor Cstress. One end of the first capacitor Cstress is connected to the fifth node N5, and the other end of the first capacitor Cstress is connected to the fourth node N4.

[0101] In one embodiment, during the threshold voltage storage stage, the grayscale voltage is transmitted to the first node N1 and the fourth node N4, and the voltage of the first power supply terminal ELVDD is transmitted to the fifth node N5. Thus, the first capacitor Cstress will follow the voltage changes of the two nodes to complete the charge flow, thereby forming a stable voltage difference containing grayscale voltage information.

[0102] Subsequently, when the input voltage of the first voltage input terminal VINT1 is transmitted to the fifth node N5, the voltage of the fifth node changes from the voltage of the first power supply terminal ELVDD to the voltage of the first voltage input terminal VINT1. The first capacitor Cstress will use this potential difference to change the potential difference of the fourth node N4. The changed voltage of the fourth node N4 is the reset voltage, which is used to reset the voltage of the first node N1 in the subsequent reset stage.

[0103] In one embodiment, the capacitance value of the first capacitor increases as the refresh rate of the display panel decreases. This application mainly targets low refresh rate display circuits. Specifically, when the refresh rate is 15Hz, the capacitance value of the first capacitor is 30pF; when the refresh rate is 5Hz, the capacitance value of the first capacitor is 100pF; and when the refresh rate is 1Hz, the capacitance value of the first capacitor is 500pF. Furthermore, the capacitance value of the first capacitor is greater than the parasitic capacitance of the first node N1, and the parasitic capacitance of the first node N1 is less than 1pF, to ensure that multiple resets do not affect the reset voltage. It should be understood that parasitic capacitance is not a deliberately designed capacitor element in the circuit design, but rather an inherent capacitance effect between conductors, a stray capacitance generated by the circuit system, and an unintended parasitic parameter.

[0104] like Figure 3 As shown, the first reset circuit includes a sixth transistor T6. The gate of the sixth transistor T6 is connected to the first scan signal input terminal Sn1. n-1 The first terminal of the sixth transistor T6 is connected to the second voltage input terminal VINT2, and the second terminal of the sixth transistor T6 is connected to the second node N2.

[0105] Therefore, the sixth transistor T6 is positioned between the second voltage input terminal VINT2 and the second node N2, and is connected to the first scan signal input terminal Sn1. n-1 The first scan signal is provided for control. When the first scan signal is at an active level, the sixth transistor T6 is turned on, forming a voltage transmission path between the second voltage input terminal VINT2 and the second node N2. This allows the voltage of the second voltage input terminal VINT2 to be transmitted to the second node N2 via the voltage transmission path, thereby setting the voltage of the second node N2 to the voltage of the second voltage input terminal VINT2, and establishing a reference potential for subsequent threshold voltage storage.

[0106] When the first scan signal is at an invalid level, the sixth transistor T6 is turned off, and an open circuit is formed between the second voltage input terminal VINT2 and the second node N2.

[0107] It should be noted that the specific device type of the sixth transistor T6 can be set according to the process conditions and control logic of the pixel driving circuit, and this application does not make any specific restrictions on it.

[0108] In one embodiment, the first terminal of the sixth transistor T6 can be the source or the drain, and the second terminal of the sixth transistor T6 can be the source or the drain accordingly.

[0109] like Figure 3 As shown, the driving circuit includes a second transistor T2. The gate of the second transistor T2 is connected to a second node N2, allowing the transistor to be turned on and off according to the voltage at the second node N2. The first terminal of the second transistor T2 is connected to a first node N1, and the second terminal is connected to a third node N3. The second transistor T2 can generate a corresponding driving current during the light-emitting phase, thereby driving the light-emitting element to emit light.

[0110] In one embodiment, the first terminal of the second transistor T2 can be the source or the drain, and the second terminal of the second transistor T2 can be the source or the drain accordingly.

[0111] During the threshold voltage storage phase, the second transistor T2 can gradually change its conduction state based on the voltage difference between the second node N2 and the first node N1. When the potential of the second node N2 changes to a state corresponding to the threshold voltage characteristics of the second transistor T2, a voltage difference containing threshold voltage information can be established for the storage circuit.

[0112] It should be noted that the specific device type of the second transistor T2 can be set according to the process conditions and control logic of the pixel driving circuit, and this application does not impose specific limitations on it. Figure 2 As shown, the compensation circuit includes a third transistor T3. The gate of the third transistor T3 is connected to the second scan signal input terminal Sn1. n The first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is connected to the third node N3.

[0113] Therefore, the third transistor T3 is input from the second scan signal terminal Sn1 nThe second scan signal provides control. When the second scan signal is at an active level, the third transistor T3 is turned on, connecting the second node N2 and the third node N3 to form a threshold voltage storage path together with the storage circuit, the second node N2, the third node N3, and the driving circuit 2. When the second scan signal is at an inactive level, the third transistor T3 is turned off, forming an open circuit between the second node N2 and the third node N3.

[0114] It should be noted that the specific device type of the third transistor T3 can be set according to the process conditions and control logic of the pixel driving circuit, and this application does not make any specific restrictions on it.

[0115] In one embodiment, the first terminal of the third transistor T3 can be the source or the drain, and the second terminal of the third transistor T3 can be the source or the drain accordingly.

[0116] In one embodiment, the third transistor T3 is a P-type thin-film transistor. The second scan signal uses a low level as the active level and a high level as the inactive level. When the second scan signal is low, the third transistor T3 is turned on, connecting the second node N2 and the third node N3. When the second scan signal is inactive, the third transistor T3 is turned off, creating an open circuit between the second node N2 and the third node.

[0117] This description merely exemplifies the implementation of the third transistor T3. In specific applications, the effective and ineffective levels of the second scan signal can be adjusted according to the type of transistor used to turn the third transistor T3 on or off. This disclosure does not impose specific limitations in this regard. Figure 3 As shown, the storage circuit includes a second capacitor Cst. One end of the second capacitor is connected to the first power supply terminal ELVDD, and the other end of the second capacitor is connected to the second node N2.

[0118] During the threshold voltage storage stage, the second transistor T2 can gradually change its conduction state according to the voltage difference between the second node N2 and the first node N1. At the same time, the second capacitor Cst will adjust the voltage of the second node N2. When the potential of the second node N2 changes to a state corresponding to the threshold voltage characteristics of the second transistor T2, the voltage difference across the second capacitor contains the threshold voltage information.

[0119] like Figure 3 As shown, the second reset circuit includes a seventh transistor T7. The gate of the seventh transistor T7 is connected to the third scan signal input terminal Sn2. n The first terminal of the seventh transistor T7 is connected to the third voltage input terminal VINT3, and the second terminal of the seventh transistor T7 is connected to the first terminal of the light-emitting element.

[0120] Therefore, the seventh transistor T7 is positioned between the third voltage input terminal VINT3 and the first terminal of the light-emitting element, and is connected to the third scan signal input terminal Sn2. n The third scan signal provides control. When the third scan signal is at an active level, the seventh transistor T7 is turned on, forming a third voltage input voltage transmission path between the third voltage input terminal VINT3 and the first terminal of the light-emitting element. The voltage of the third voltage input terminal VINT3 can be transmitted to the first terminal of the light-emitting element through this third voltage input voltage transmission path.

[0121] When the third scan signal is at an invalid level, the seventh transistor T7 is turned off, and an open circuit is formed between the third voltage input terminal VINT3 and the first terminal of the light-emitting element.

[0122] It should be noted that the specific device type of the seventh transistor T7 can be set according to the process conditions and control logic of the pixel driving circuit, and this application does not make any specific limitations on this.

[0123] In one embodiment, the first terminal of the seventh transistor T7 can be the source or the drain, and the second terminal of the seventh transistor T7 can be the source or the drain accordingly.

[0124] In one embodiment, the seventh transistor T7 is a P-type thin-film transistor. The third scan signal uses a low level as the active level and a high level as the inactive level. When the second scan signal is low, the seventh transistor T7 is turned on, forming a voltage transmission path between the seventh transistor T7 and the first terminal of the light-emitting element. The voltage at the third voltage input terminal VINT3 is transmitted to the first terminal of the light-emitting element through this voltage transmission path to reset the voltage at the first terminal of the light-emitting element.

[0125] When the third scan signal is high, the seventh transistor T7 is turned off, and an open circuit is formed between the third voltage input terminal VINT3 and the first terminal of the light-emitting element.

[0126] This document only illustrates the implementation of the seventh transistor T7. In specific applications, the effective and ineffective levels of the third scan signal can be adjusted according to the type of transistor used to turn the seventh transistor T7 on or off. This application does not impose any specific limitations on this.

[0127] In one embodiment, the first terminal of the seventh transistor T7 can be the source or the drain, and the second terminal of the seventh transistor T7 can be the source or the drain accordingly.

[0128] like Figure 1 As shown, the light-emitting control circuit 8 includes a first light-emitting control sub-circuit and a second light-emitting control sub-circuit. The first light-emitting control sub-circuit is connected to the first power supply terminal ELVDD and the enable signal input terminal EN, respectively.n And the first node N1. The second light-emitting control sub-circuit is connected to the first terminal of the light-emitting element 7 and the enable signal input terminal EN. n And the third node N3.

[0129] Continue reading Figure 3 The first light-emitting control sub-circuit includes a fourth transistor T4. The gate of the fourth transistor T4 is connected to the enable signal input terminal EN. n The first terminal of the fourth transistor T4 is connected to the first power supply terminal ELVDD, and the second terminal of the fourth transistor T4 is connected to the first node N1.

[0130] Therefore, the fourth transistor T4 is positioned between the first power supply terminal ELVDD and the first node N1, and is connected to the enable signal input terminal EN. n The provided enable signal controls the operation. When the enable signal is at an active level, the fourth transistor T4 is turned on, forming a voltage transmission path between the first power supply terminal ELVDD and the first node N1. When the enable signal is at an inactive level, the fourth transistor T4 is turned off, forming an open circuit between the first power supply terminal ELVDD and the first node N1.

[0131] It should be noted that the specific device type of the fourth transistor T4 can be set according to the process conditions and control logic of the pixel driving circuit, and this application does not make any specific restrictions on it.

[0132] In this embodiment, the first terminal of the fourth transistor T4 can be either the source or the drain, and the second terminal of the fourth transistor T4 can be either the source or the drain.

[0133] In one embodiment, the fourth transistor T4 is a P-type thin-film transistor. The enable signal uses a low level as the active level and a high level as the inactive level. When the enable signal is low, the fourth transistor T4 is turned on, forming a path between the first power supply terminal ELVDD and the first node N1. When the enable signal is high, the fourth transistor T4 is turned off, forming an open circuit between the first power supply terminal ELVDD and the first node N1.

[0134] This document only illustrates the implementation of the fourth transistor T4 by way of example. In specific applications, the effective and ineffective levels of the enable signal can be adjusted according to the type of transistor used to turn the fourth transistor T4 on or off. This disclosure does not make any specific limitations in this regard.

[0135] The second light-emitting control sub-circuit includes a fifth transistor T5. The gate of the fifth transistor T5 is connected to the enable signal input terminal EN. n The first terminal of the fifth transistor T5 is connected to the third node N3, and the second terminal of the fifth transistor T5 is connected to the first terminal of the light-emitting element.

[0136] Therefore, the fifth transistor T5 is positioned between the first end of the light-emitting element and the third node N3, and is connected to the enable signal input terminal EN. n The provided enable signal controls the circuit. When the enable signal is at an active level, the fifth transistor T5 is turned on, forming a path between the first terminal of the light-emitting element and the third node N3. When the enable signal is at an inactive level, the fifth transistor T5 is turned off, forming an open circuit between the first terminal of the light-emitting element and the third node N3.

[0137] It should be noted that the specific device type of the fifth transistor T5 can be set according to the process conditions and control logic of the pixel driving circuit, and this application does not make any specific restrictions on it.

[0138] In one embodiment, the fifth transistor T5 is a P-type thin-film transistor. The enable signal uses a low level as the active level and a high level as the inactive level. When the enable signal is low, the fifth transistor T5 is turned on, forming a path between the first terminal of the light-emitting element and the third node N3. When the enable signal is high, the fifth transistor T5 is turned off, forming an open circuit between the first terminal of the light-emitting element and the third node N3.

[0139] This document only illustrates the implementation of the fifth transistor T5 by way of example. In specific applications, the effective and ineffective levels of the enable signal can be adjusted according to the type of transistor used to turn the fifth transistor T5 on or off. This application does not make any specific limitations in this regard.

[0140] In one embodiment, since the fourth transistor T4 and the fifth transistor T5 share the same enable signal input terminal EN... n This allows the fourth transistor T4 and the fifth transistor T5 to be turned on simultaneously during the light-emitting stage. At this time, the fourth transistor T4, the fifth transistor T5, and the second transistor T2 form a current path, and the light-emitting element is driven to emit light by the driving circuit of the second transistor T2.

[0141] In this embodiment, the first terminal of the fifth transistor T5 can be either the source or the drain, and the second terminal of the fifth transistor T5 can be either the source or the drain.

[0142] In one embodiment, the light-emitting element may be, for example, an organic light-emitting diode (OLED), or other light-emitting device that can be driven by a pixel driving circuit with a driving current or driving voltage. This embodiment does not limit the specific light-emitting element.

[0143] In this technical field, a light-emitting diode (LED) is a semiconductor device capable of converting electrical energy into light energy. The first end of the light-emitting element is the anode of the LED, and the second end of the light-emitting element is the cathode of the LED.

[0144] like Figure 2As shown, the second end of the light-emitting element 7 is also connected to the second power supply terminal ELVSS. The voltage of the first power supply terminal ELVDD is higher than the voltage of the second power supply terminal ELVSS, so as to form a positive current path from top to bottom, causing the light-emitting element to conduct and emit light.

[0145] In one specific embodiment, the voltage of the first power supply terminal ELVDD is 3V, the voltage of the second power supply terminal ELVSS is -3V, the voltage of the first voltage input terminal VINT2 is 5V, the voltage of the second voltage input terminal VINT2 is -3V, and the voltage of the third voltage input terminal VINT3 is -3V. The grayscale voltage of the grayscale input terminal is between 1 and 5V. The first scan signal input terminal Sn1 n-1 Second scan signal input terminal Sn1 n Third scan signal input terminal Sn2 n Fourth scan signal input terminal Rn1 n Fifth scan signal input terminal Rn2 n and the enable signal input terminal EN n Input is 6V. It should be noted that this is merely an exemplary embodiment and is not intended to limit the scope of the present solution.

[0146] In one specific embodiment, the fourth scan signal input terminal Rn1 n The fourth scan signal and the second scan signal input terminal Sn1 n The waveform of the second scan signal can be exactly the same.

[0147] The circuit diagram of this application has been described in detail above. The working principle of the pixel driving circuit of the embodiment of this application will be described in detail below with reference to the accompanying drawings: In the display panel, not all pixels can be synchronously written with grayscale signals. The driving circuit adopts a line-by-line scanning mode, sequentially selecting each row of pixels to complete the writing of the corresponding grayscale signal. All pixels complete one complete round of signal configuration, which is equivalent to completing one image refresh. This complete image refresh cycle is defined as one frame.

[0148] The refresh cycles generated sequentially, according to the order of refresh execution, are denoted as the first frame, the second frame, ..., the Nth frame (N is a positive integer); the value of N is directly related to the refresh rate and display duration. The first frame cycle is used to complete the initial configuration of the pixel driving circuit. Starting from the second frame, the display panel enters the normal grayscale writing and image display working state.

[0149] The first frame of the driving pixel circuit in this application mainly includes a reset stage, a threshold voltage storage stage, a reset voltage generation stage, and a light emission stage.

[0150] like Figure 4As shown, during the reset phase, the first scan signal and the fifth scan signal are both at a low level, while the second scan signal, the third scan signal, the fourth scan signal, and the enable control signal are all at a high level.

[0151] At this time, the second transistor T2, the sixth transistor T6, and the tenth transistor T10 are all turned on, while the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all turned off.

[0152] The voltage at the second voltage input terminal VINT2 is transmitted to the second node N2 via the conducting sixth transistor T6, thereby setting the voltage of the second node N2 to the voltage at the second voltage input terminal VINT2, i.e., N2 = VINT2, providing a reference voltage for subsequent threshold voltage storage.

[0153] like Figure 5 As shown, during the threshold voltage storage stage, the second scan signal, the third scan signal, and the fourth scan signal are all at a low level, while the first scan signal, the fifth scan signal, and the enable control signal are all at a high level.

[0154] At this time, the first transistor T1, the third transistor T3, the eighth transistor T8, and the ninth transistor T9 are all turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are all turned off.

[0155] The grayscale voltage at the grayscale voltage input terminal DATA is transmitted to the first node N1 and the fourth node N4 via the conducting first transistor T1 and eighth transistor T8, respectively, i.e., N1=N4=DATA. The voltage at the first power supply terminal ELVDD is transmitted to the fifth node N5 via the ninth transistor T9, i.e., N5=ELVDD.

[0156] Meanwhile, the potential of the second node N2 gradually increases. When the potential of the second node N2 rises to N2 = DATA + Vth_T2, the second transistor T2 reaches the critical cutoff state. This causes the second capacitor Cst to store the threshold voltage Vth_T2 of the second transistor T2, so as to realize the threshold voltage compensation of the second transistor T2 in subsequent stages.

[0157] After the threshold voltage storage phase ends, such as Figure 6 As shown, the first scan signal, the second scan signal, the third scan signal, the fourth scan signal, the fifth scan signal, and the enable control signal are all at a high level.

[0158] At this time, transistors T1, T3, T4, T5, T6, T7, T8, T9, and T10 are all turned off, and the voltages of nodes N1, N4, and N5 remain unchanged, i.e., N1=N4=DATA and N5=ELVDD.

[0159] Then the reset voltage generation stage begins, such as... Figure 7 As shown, the fifth scan signal is low, while the first scan signal, second scan signal, third scan signal, fourth scan signal, and enable control signal are all high.

[0160] At this time, the tenth transistor T10 is turned on, while the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all turned off.

[0161] The voltage at the first voltage input terminal VINT1 is transmitted to the fifth node N5 via the tenth transistor T10. Combined with the voltage difference between the fourth node N4 and the fifth node N5 established in the previous stage, the voltage at the fourth node N4 is coupled to DATA+VINT1-ELVDD by the first capacitor Cstress. At this point, the voltage at the fourth node N4 is the reset voltage. That is, N5 = VINT1, N4 = DATA+VINT1-ELVDD.

[0162] like Figure 8 As shown, during the light-emitting stage, the enable signal and the fifth scan signal are at a low level, while the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal are all at a high level.

[0163] At this time, the fourth transistor T4, the fifth transistor T5, and the tenth transistor T10 are all turned on, while the first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all turned off.

[0164] A light-emitting path is formed between the first power supply terminal ELVDD, the fourth transistor T4, the second transistor T2, the fifth transistor T5, and the light-emitting element. At this time, the second transistor T2 is in the conducting state under the voltage of the second node N2, and generates a driving current to drive the light-emitting element to emit light. Due to the voltage of the second node N2, the driving current is no longer limited by the threshold voltage.

[0165] It should be noted that the voltage of the fourth node N4 remains at the reset voltage (i.e., DATA+VINT1-ELVDD) before the next reset phase. It can be seen that the voltage of the fourth node N4 contains the grayscale voltage information of the grayscale voltage input terminal DATA.

[0166] During each subsequent frame, the voltage of the first node N1 can be reset according to the reset voltage of the fourth node N4, and then the light-emitting element can be driven to emit light.

[0167] Each frame of the second and Nth frames of the driving pixel circuit in this application includes a reset phase and an emission phase.

[0168] like Figure 9 As shown, during the reset phase, the third and fifth scan signals are both low, while the first, second, and fourth scan signals, as well as the enable signal, are all high.

[0169] At this time, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 are all turned on, while the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are all turned off.

[0170] The fourth node N4 writes the reset voltage to the first node N1 through the conducting eighth transistor T8, i.e., N1 = DATA + VINT1 - ELVDD. At the same time, the voltage of the third voltage input terminal VINT2 is transmitted to the first terminal of the light-emitting element through the conducting seventh transistor T7.

[0171] like Figure 8 As shown, during the light-emitting stage, the enable signal and the fifth scan signal are at a low level, while the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal are all at a high level. At this time, the fourth transistor T4, the fifth transistor T5, and the tenth transistor T10 are all turned on, while the first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all turned off.

[0172] A light-emitting path is formed between the first power supply terminal ELVDD, the fourth transistor T4, the second transistor T2, the fifth transistor T5, and the light-emitting element. At this time, the second transistor T2 is in the conducting state under the voltage of the second node N2, and generates a driving current to drive the light-emitting element to emit light.

[0173] It should be noted that, starting from the second frame, the voltage of the first node N1 is reset in each frame based on the voltage of the fourth node N4 (reset voltage). Since the parasitic capacitance of the first node N1 is much smaller than the first capacitor Ctress, multiple resets can be performed without affecting the reset voltage.

[0174] In summary, this invention, through the aforementioned specific driving method, applies differentiated reset voltages to each pixel independently based on different display grayscale levels, so that the flickering of both high and low grayscale levels on the screen during low refresh rate display is invisible to the human eye.

[0175] In one embodiment, the number of resets is related to the AOD refresh rate. For example, when the refresh rate is 15Hz, the number of resets is 3; when the refresh rate is 5Hz, the number of resets is 11; and when the refresh rate is 1Hz, the number of resets is 59.

[0176] To better illustrate the driving method of the present invention, a specific embodiment is provided below: The 5Hz AOD refresh rate provides 12 frames per second. The pixel drive circuitry is initialized and configured during the first frame; from the second to the twelfth frame, the display panel enters normal grayscale writing and image display operation. First, combine with the attached... Figure 3 and appendix Figure 10 Explanation of the driving timing during the first frame: Stage A: First scan signal input terminal Sn1 n-1 Second scan signal input terminal Sn1 n Third scan signal input terminal Sn2 n Fourth scan signal input terminal Rn1 n All inputs are high level, and the fifth scan signal input terminal Rn2 n When the input is low, the enable signal input terminal EN is activated. n When the input changes from low to high, both the fourth transistor T4 and the fifth transistor T5 are turned off.

[0177] Stage B: Second scan signal input terminal Sn1 n Third scan signal input terminal Sn2 n Fourth scan signal input terminal Rn1 n Enable signal input terminal EN n The input is still high, and the fifth scan signal input terminal Rn2 n The input is still low, and the first scan signal input terminal Sn1 n-1 When the input changes from high level to low level, the second transistor T2 and the sixth transistor turn on, writing the voltage of the second voltage input terminal VINT2 to the second node N2.

[0178] Stage C: Second scan signal input terminal Sn1 n Third scan signal input terminal Sn2 n Fourth scan signal input terminal Rn1 n Enable signal input terminal EN n The input is still high, and the first scan signal input terminal Sn1 n-1 and the fifth scan signal input terminal Rn2 n When the input changes from low to high, the tenth transistor T10 is turned off.

[0179] Stage D: First scan signal input terminal Sn1n-1 Fifth scan signal input terminal Rn2 n Enable signal input terminal EN n The input is still high, and the second scan signal input terminal Sn1 n Third scan signal input terminal Sn2 n Fourth scan signal input terminal Rn1 n When the input is low, transistors T1, T3, T7, T8, and T9 are turned on. The grayscale voltage of the grayscale input terminal DATA is written to the first node N1 and the fourth node N4. The voltage of the third voltage input terminal VINT3 is written to the first terminal of the light-emitting element, and the voltage of the first power supply terminal ELVDD is written to the fifth node.

[0180] Stage E: First scan signal input terminal Sn1 n-1 Second scan signal input terminal Sn1 n Third scan signal input terminal Sn2 n Fourth scan signal input terminal Rn1 n Enable signal input terminal EN n All inputs are high level, and the fifth scan signal input terminal Rn2 n When the input is low, the tenth transistor T10 is turned on, and the voltage of the first voltage input terminal VINT1 is written to the fifth node N5. The voltage of the fourth node N4 is coupled to DATA+ VINT1-ELVDD by the first capacitor Cstress.

[0181] Stage F: First scan signal input terminal Sn1 n-1 Second scan signal input terminal Sn1 n Third scan signal input terminal Sn2 n Fourth scan signal input terminal Rn1 n All inputs are high level, and the fifth scan signal input terminal Rn2 n When the input is low, the enable signal input terminal EN is activated. n When the input changes from high level to low level, the fourth transistor T4 and the fifth transistor T5 are turned on, and the light-emitting element emits light.

[0182] The time interval corresponding to the first frame is from the start time of stage A to the end time of stage F.

[0183] The driving timing is the same for each frame from the second frame to the twelfth frame. The driving timing for the second frame is explained below: Stage G: First scan signal input terminal Sn1 n-1 Second scan signal input terminal Sn1 n Third scan signal input terminal Sn2 nFourth scan signal input terminal Rn1 n All inputs are high level, and the fifth scan signal input terminal Rn2 n When the input scan signal is low, the enable signal input terminal EN... n When the input changes from low to high level in stage F, the fourth transistor T4 and the fifth transistor T5 are turned off.

[0184] Stage H: First scan signal input terminal Sn1 n-1 Second scan signal input terminal Sn1 n Fourth scan signal input terminal Rn1 n Enable signal input terminal EN n All inputs are high level, and the fifth scan signal input terminal Rn2 n The input scan signal is low, and the third scan signal input terminal Sn2 n When the input goes low, the eighth transistor T8 turns on, and the fourth node N4 writes the voltage DATA+ VINT1-ELVDD to the first node N1, thus achieving grayscale adaptive reset.

[0185] Stage I: First scan signal input terminal Sn1 n-1 Second scan signal input terminal Sn1 n Third scan signal input terminal Sn2 n Fourth scan signal input terminal Rn1 n All inputs are high level, and the fifth scan signal input terminal Rn2 n When the input scan signal is low, the enable signal input terminal EN... n When the input changes from high level to low level in stage F, the fourth transistor T4 and the fifth transistor T5 turn on, and the light-emitting element emits light.

[0186] Each frame from the third to the twelfth repeats the process of phase G, phase H, and phase I.

[0187] Based on the same inventive concept, another aspect of the present invention provides a display panel including the pixel driving circuit described above. This display panel can be applied to any product or component with display function, such as mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, and navigators. Specific implementations of this display panel can be found in the embodiments of the pixel driving circuit described above, and the technical effects of the pixel driving circuit are obtained therefrom. Repeated descriptions of the technical solutions and effects are not repeated here.

[0188] Based on the same inventive concept, another aspect of the embodiments of the present invention provides a display device. The display device provided by the embodiments of the present invention can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0189] Figure 11 This disclosure illustrates a driving method for a pixel driving circuit based on grayscale adaptive resetting as described in any of the above embodiments, including but not limited to the following steps: Step 1001: During the first frame, after resetting the voltage of the second node, the grayscale adaptive reset circuit generates a corresponding reset voltage based on the grayscale voltage input at the grayscale voltage input terminal, and stores the threshold voltage of the driving circuit, and then controls the light-emitting element to emit light. Step 1002: During each frame from the second frame to the Nth frame, the grayscale adaptive reset circuit resets the voltage of the first node according to the grayscale it stores, and then provides an enable signal to the enable signal input terminal to make the light-emitting element emit light.

[0190] The specific implementation of the driving method can be referred to the above embodiments, and the beneficial effects of the pixel driving circuit based on grayscale adaptive reset can be obtained. It will not be elaborated here.

[0191] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A pixel driving circuit based on grayscale adaptive resetting, characterized in that, include: Gray-scale adaptive reset circuit (1), the gray-scale adaptive reset circuit (1) is connected to the gray-scale voltage input terminal (DATA), the scan signal input terminal group (S), the first voltage input terminal (VINT1), the first power supply terminal (ELVDD) and the first node (N1) respectively. The driving circuit (2) is connected to the first node (N1), the second node (N2) and the third node (N3) respectively. Storage circuit (3), which is connected to the first power supply terminal (ELVDD) and the second node (N2) respectively. The first reset circuit (4) is connected to the first scan signal input terminal (Sn1). n-1 ), the second voltage input terminal (VINT2) and the second node (N2); The compensation circuit (5) is connected to the scan signal input terminal group (S), the second node (N2) and the third node (N3) respectively. The second reset circuit (6) is connected to the scan signal input terminal group (S), the third voltage input terminal (VINT3) and the first terminal of the light-emitting element (7) respectively; the second terminal of the light-emitting element (7) is also connected to the second power supply terminal (ELVSS). The light-emitting control circuit (8) is connected to the first power supply terminal (ELVDD), the driving circuit (2), and the enable signal input terminal (EN). n ) and the first end of the light-emitting element (7); The grayscale adaptive reset circuit (1) is used to generate a corresponding reset voltage based on the grayscale voltage input at the grayscale voltage input terminal (DATA) and reset the first node (N1) accordingly.

2. The pixel driving circuit based on grayscale adaptive resetting according to claim 1, characterized in that, The grayscale adaptive reset circuit (1) includes: a data writing sub-circuit (11), a first reset sub-circuit (12), a second reset sub-circuit (13), a third reset sub-circuit (14), and a storage sub-circuit (15); the scan signal input terminal group (S) includes: a second scan signal input terminal (Sn1) n ), third scan signal input terminal (Sn2) n ), fourth scan signal input terminal (Rn1) n ) and the fifth scan signal input terminal (Rn2) n ); The data writing sub-circuit (11) is connected to the grayscale voltage input terminal (DATA) and the second scan signal input terminal (Sn1), respectively. n The first node (N1) and the first reset sub-circuit (12) are respectively connected to the third scan signal input terminal (Sn2). n The data writing sub-circuit (11) and the first reset sub-circuit (12) are configured to write the grayscale voltage of the grayscale voltage input terminal (DATA) to the fourth node (N4) respectively; the first reset sub-circuit (12) is also configured to reset the voltage (N1) of the first node according to the voltage of the fourth node (N4). The second reset sub-circuit (13) is connected to the first power supply terminal (ELVDD), the fifth node (N5), and the fourth scan signal input terminal (Rn1), respectively. n The second reset sub-circuit (13) is configured to write the voltage of the first power supply terminal (ELVDD) to the fifth node (N5). The third reset sub-circuit (14) is connected to the fifth node (N5), the first voltage input terminal (VINT1), and the fifth scan signal input terminal (Rn2), respectively. n The third reset sub-circuit (14) is configured to write the voltage of the first voltage input terminal (VINT1) to the fifth node (N5). The storage sub-circuit (15) is connected to the fourth node (N4) and the fifth node (N5) respectively, and the storage sub-circuit (15) is configured to store the grayscale voltage.

3. The pixel driving circuit based on grayscale adaptive resetting according to claim 2, characterized in that, The data writing sub-circuit (11) includes a first transistor (T1), and the first reset sub-circuit (12) includes an eighth transistor (T8); wherein the gate of the first transistor (T1) is connected to the second scan signal input terminal (Sn1). n The first terminal is connected to the grayscale voltage input terminal (DATA), and the second terminal is connected to the first node (N1); the gate of the eighth transistor (T8) is connected to the third scan signal input terminal (Sn2). n The first pole is connected to the first node (N1), and the second pole is connected to the fourth node (N4).

4. The pixel driving circuit based on grayscale adaptive resetting according to claim 2, characterized in that, The second reset sub-circuit (13) includes a ninth transistor (T9), the gate of which is connected to the fourth scan signal input terminal (Rn1). n The first pole is connected to the first power supply terminal (ELVDD), and the second pole is connected to the fifth node (N5).

5. The pixel driving circuit based on grayscale adaptive resetting according to claim 2, characterized in that, The third reset sub-circuit (14) includes a tenth transistor (T10), the gate of which is connected to the fifth scan signal input terminal (Rn2). n The first terminal is connected to the first voltage input terminal (VINT1), and the second terminal is connected to the fifth node (N5).

6. The pixel driving circuit based on grayscale adaptive resetting according to claim 2, characterized in that, The storage sub-circuit (15) includes a first capacitor (Cstress), the capacitance of which increases as the refresh rate decreases.

7. The pixel driving circuit based on grayscale adaptive resetting according to claim 6, characterized in that, The parasitic capacitance of the first node (N1) is less than the capacitance of the first capacitor (Cstress).

8. A driving method, characterized in that, The method for driving the pixel driving circuit based on grayscale adaptive resetting as described in any one of claims 1 to 7 includes: During the first frame, after resetting the voltage of the second node, the grayscale adaptive reset circuit generates a corresponding reset voltage based on the grayscale voltage input at the grayscale voltage input terminal and stores the threshold voltage of the driving circuit, and then controls the light-emitting element to emit light. During each frame from the second frame to the Nth frame, the grayscale adaptive reset circuit resets the voltage of the first node according to the reset voltage, and then provides an enable signal to the enable signal input terminal to make the light-emitting element emit light.

9. The pixel driving method according to claim 8, characterized in that, The first frame includes: a reset phase, a threshold voltage storage phase, a reset voltage generation phase, and a light emission phase; During the reset phase, the voltage of the second node is reset using the first reset circuit; During the threshold voltage storage stage, a grayscale voltage is written to the grayscale adaptive reset circuit and the threshold voltage of the driving circuit is stored in the storage circuit through the compensation circuit. During the reset voltage generation stage, the gray-scale adaptive reset circuit generates a corresponding reset voltage based on the gray-scale voltage input at the gray-scale voltage input terminal. During the light-emitting phase, an enable signal is provided to the enable signal input terminal to make the light-emitting element emit light.

10. A display panel, characterized in that, Includes the pixel driving circuit based on grayscale adaptive reset as described in any one of claims 1 to 7.

11. A display device, characterized in that, Includes the display panel as described in claim 10.

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