Pixel driving circuit and display panel

Abstract

A pixel driving circuit and a display panel. The pixel driving circuit comprises a first light-emitting control module, a driving module and a second light-emitting control module. In each light-emitting stage of the pixel driving circuit, the driving module is kept conducting. The light-emitting stage comprises at least one sub-stage, in which one of the first pulse width modulation signal and the second pulse width modulation signal is kept at an effective level, and the other pulse width modulation signal comprises at least one invalid level pulse. Through the alternating cooperation of the two pulse width modulation signals, by keeping one of the pulse width modulation signals at an effective level and outputting an invalid level pulse for the other pulse width modulation signal, the on-off state of the light-emitting path can be determined by the pulse width modulation signal outputting the invalid level pulse, so as to reduce the level inversion frequency of one of the pulse width modulation signals while maintaining the equivalent dimming effect, and reduce the power consumption of the corresponding driving integrated circuit.

Description

Technical Field

[0001] This application belongs to the field of display device technology, and in particular relates to a pixel driving circuit and a display panel. Background Technology

[0002] Active-matrix organic light-emitting diode (AMOLED) display panels have gradually gained a foothold in the high-end mobile phone market due to their significant advantages in display color saturation, power consumption, and foldability.

[0003] AMOLED displays typically employ a dimming technology that combines direct current (DC) and pulse width modulation (PWM). In PWM dimming, the emission control signal (EM) within a single frame consists of multiple pulses. As the number of EM pulses increases, the number of EM drive circuits that need to operate simultaneously also increases. Under excessive load, the corresponding drive integrated circuits are prone to causing display abnormalities on the display panel. Summary of the Invention

[0004] To address the problems existing in the prior art, the purpose of this application is to provide a pixel driving circuit and a display panel.

[0005] A first aspect of this application provides a pixel driving circuit, comprising: a first light-emitting control module, a first terminal of which is connected to a power supply terminal, and a control terminal of which is used to receive a first pulse width modulation signal; a driving module, the first terminal of which is connected to a second terminal of which is connected to the light-emitting control module, and the control terminal of which is connected to a control node, the driving module being used to control the conduction current of which is based on the voltage of the control node; and a second light-emitting control module, the first terminal of which is connected to the second terminal of which is connected to the driving module, the second terminal of which is connected to a light-emitting unit, and the control terminal of which is used to receive a second pulse width modulation signal; wherein the driving module remains on in each light-emitting stage of the pixel driving circuit; each light-emitting stage includes at least one sub-stage, wherein in the sub-stage, one of the first pulse width modulation signal and the second pulse width modulation signal maintains an active level, and the other pulse width modulation signal includes at least one inactive level pulse.

[0006] In one embodiment, the light emission stage includes a first sub-stage and a second sub-stage; in the first sub-stage, the first pulse width modulation signal maintains an active level, and the second pulse width modulation signal includes multiple inactive level pulses and multiple active level pulses; in the second sub-stage, the second pulse width modulation signal maintains an active level, and the first pulse width modulation signal includes multiple inactive level pulses and multiple active level pulses.

[0007] In one embodiment, the number of effective level pulses of the first pulse width modulation signal in the first sub-stage is equal to the number of effective level pulses of the second pulse width modulation signal in the second sub-stage.

[0008] In one embodiment, the first pulse width modulation signal and the second pulse width modulation signal have the same frequency and a delay time of half a cycle, wherein the width of the effective level pulse of the first pulse width modulation signal and the second pulse width modulation signal is greater than the width of the invalid level pulse.

[0009] In one embodiment, the first light-emitting control module includes a first transistor, the driving module includes a second transistor, and the second light-emitting control module includes a third transistor; a first terminal of the first transistor is connected to the power supply terminal, a second terminal of the first transistor is connected to the first terminal of the second transistor, and a control terminal of the first transistor is used to receive the first pulse width modulation signal; a second terminal of the second transistor is connected to the first terminal of the third transistor, and a control terminal of the second transistor is connected to the control node; a second terminal of the third transistor is connected to the light-emitting unit, and a control terminal of the third transistor is used to receive the second pulse width modulation signal.

[0010] In one embodiment, the pixel driving circuit further includes a dimming module connected to the control node, which is used to configure the voltage of the control node according to the data signal during the data writing phase.

[0011] In one embodiment, the dimming module includes a fourth transistor, a fifth transistor, and a charging capacitor; a first terminal of the charging capacitor is connected to a first terminal of the first light-emitting control module, and a second terminal of the charging capacitor is connected to the control node; a first terminal of the fourth transistor is used to receive a data signal, a second terminal of the fourth transistor is connected to a first terminal of the driving module, and a control terminal of the fourth transistor is used to receive a first control signal; a first terminal of the fifth transistor is connected to a second terminal of the driving module, a second terminal of the fifth transistor is connected to the control node, and a control terminal of the fifth transistor is used to receive a second control signal.

[0012] In one embodiment, the pixel driving circuit further includes an initialization module, which is connected to the second terminal of the control node and the second light emission control module. The initialization module is used to configure the voltage of the second terminal of the control node and the second light emission control module according to the reference voltage during the initialization phase.

[0013] In one embodiment, the initialization module includes a sixth transistor and a seventh transistor; the first terminal of the sixth transistor is used to receive the reference voltage, the second terminal of the sixth transistor is connected to the control node, and the control terminal of the sixth transistor is used to receive a third control signal; the first terminal of the seventh transistor is used to receive the reference voltage, the second terminal of the seventh transistor is connected to the second terminal of the second light-emitting control module, and the control terminal of the seventh transistor is used to receive a fourth control signal.

[0014] A second aspect of this application provides a display panel including the pixel driving circuit described above.

[0015] The beneficial effects of this application embodiment compared with the prior art are as follows: When the first light-emitting control module, the driving module, and the second light-emitting control module are all turned on, a light-emitting current path is formed, thereby providing driving current to the light-emitting unit to make it emit light; when either light-emitting control module is turned off, the current path is cut off, and the light-emitting unit is turned off. Therefore, by alternating the two pulse width modulation signals, by keeping one pulse width modulation signal at an effective level while the other pulse width modulation signal outputs an invalid level pulse, the on / off state of the light-emitting path can be determined by the pulse width modulation signal that outputs an invalid level pulse. This reduces the number of level flips of one of the pulse width modulation signals while maintaining the equivalent dimming effect, thereby reducing the power consumption of the corresponding driving integrated circuit. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a pixel driving circuit provided in an embodiment of this application; Figure 2 A waveform diagram of a pulse width modulation signal provided in an embodiment of this application; Figure 3 Another waveform diagram of a pulse width modulation signal provided in an embodiment of this application; Figure 4 A detailed circuit diagram of a pixel driving circuit provided in an embodiment of this application.

[0017] Reference numerals: 10, pixel driving circuit; 20, light-emitting unit; 30, display panel; 100, first light-emitting control module; 200, driving module; 300, second light-emitting control module; 400, dimming module; 500, initialization module. Detailed Implementation

[0018] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0022] It should be noted that the light emission control signal is typically provided by the light emission control driver circuit, and the timing of its high and low levels determines whether a pixel emits or extinguishes light. As the number of pulses in the light emission control signal within a frame increases, the power consumption of the driver IC in the light emission control driver circuit also increases significantly. For example, when the number of pulses in the light emission control signal within a frame is 32, the driver IC needs to drive 32 sets of light emission control signal lines simultaneously, theoretically increasing its dynamic power consumption to 32 times that of the single-pulse mode. When the driver IC is overloaded, the light emission control signal may fail to output properly, leading to display abnormalities such as uneven brightness, flickering, or screen tearing.

[0023] Figure 1 A schematic diagram of a pixel driving circuit according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows: A pixel driving circuit 10 includes: a first light emission control module 100, a driving module 200, and a second light emission control module 300.

[0024] The first terminal of the first light-emitting control module 100 is used to connect to the power supply terminal, and the control terminal of the first light-emitting control module 100 is used to receive the first pulse width modulation signal EM1. The power supply terminal can provide the power supply voltage ELVDD.

[0025] The first end of the driving module 200 is connected to the second end of the first light-emitting control module 100, and the control end of the driving module 200 is connected to the control node N1. The driving module 200 is used to control the conduction current of the driving module 200 according to the voltage of the control node N1.

[0026] It is understandable that the on-state current of the driving module 200 is the driving current used to drive the light-emitting unit 20. During the light-emitting phase, the driving module 200 can continuously provide a constant driving current according to the voltage of the control node N1, thereby ensuring the uniformity of the light emission brightness.

[0027] The first end of the second light-emitting control module 300 is connected to the second end of the driving module 200. The second end of the second light-emitting control module 300 is used to connect to the light-emitting unit 20. The control end of the second light-emitting control module 300 is used to receive the second pulse width modulation signal EM2.

[0028] It is understandable that the first pulse width modulation signal EM1 can precisely control the on and off of the first light emission control module 100, and the second pulse width modulation signal EM2 can precisely control the on and off of the second light emission control module 300, thereby achieving fine regulation of the light emission period of the light emission unit 20.

[0029] In each light-emitting stage of the pixel driving circuit 10, the driving module 200 remains on.

[0030] The light-emitting stage includes at least one sub-stage. In this sub-stage, one of the first pulse width modulation (PWM) signal EM1 and the second PWM signal EM2 maintains an active level, while the other PWM signal includes at least one inactive level pulse. Specifically, the active level refers to the level at which the corresponding light-emitting control module is turned on, and the inactive level refers to the level at which the corresponding light-emitting control module is turned off. In the sub-stage, the PWM signal maintaining an active level controls the corresponding light-emitting control module to remain on, while the PWM signal containing the inactive level pulse controls the corresponding light-emitting control module to periodically turn off according to the pulse sequence.

[0031] It is understandable that when the first light-emitting control module 100, the driving module 200 and the second light-emitting control module 300 are all turned on, a light-emitting current path is formed, thereby providing driving current to the light-emitting unit 20 to make it emit light; and when any light-emitting control module is turned off, the current path is cut off and the light-emitting unit 20 is turned off.

[0032] Therefore, by alternating the two pulse width modulation signals, one pulse width modulation signal is kept at an effective level while the other pulse width modulation signal outputs an invalid level pulse. This allows the on / off state of the light emission path to be determined by the pulse width modulation signal that outputs an invalid level pulse. In this way, while maintaining the equivalent dimming effect, the number of level flips of one of the pulse width modulation signals is reduced, thereby reducing the power consumption of the corresponding driver integrated circuit.

[0033] The effective level and the invalid level can be either high level and low level, or low level and high level, depending on the type of device used in the pixel driving circuit 10.

[0034] In one embodiment, such as Figure 2 As shown, the luminescence stage includes a first sub-stage and a second sub-stage.

[0035] In the first sub-stage, the first pulse width modulation signal EM1 remains at an active level, and the second pulse width modulation signal EM2 includes multiple invalid level pulses and multiple active level pulses.

[0036] In the second sub-stage, the second pulse width modulation signal EM2 remains at an active level, while the first pulse width modulation signal EM1 includes multiple invalid level pulses and multiple active level pulses.

[0037] It is understandable that the levels of the first pulse width modulation signal EM1 and the second pulse width modulation signal EM2 will switch between valid and invalid levels, thereby forming corresponding valid level pulses and invalid level pulses.

[0038] In the first sub-stage, the on / off state of the light-emitting path is determined by the second pulse width modulation signal EM2, and the light-emitting unit 20 alternates between on and off at the pulse frequency of the second pulse width modulation signal EM2. In the second sub-stage, the on / off state of the light-emitting path is determined by the first pulse width modulation signal EM1, and the light-emitting unit 20 alternates between on and off at the pulse frequency of the first pulse width modulation signal EM1. Through the alternating cooperation of the two sub-stages, the total number of light-emitting pulses of the driving current in one frame is equal to the sum of the number of pulses of the second pulse width modulation signal EM2 in the first sub-stage and the number of pulses of the first pulse width modulation signal EM1 in the second sub-stage. Thus, while maintaining the equivalent dimming effect, the two driving integrated circuits work alternately, significantly reducing the switching frequency of a single driving integrated circuit, and thereby effectively reducing the dynamic power consumption of the driving integrated circuit.

[0039] In one embodiment, such as Figure 2 As shown, the number of effective level pulses of the first pulse width modulation signal EM1 in the first sub-stage is equal to the number of effective level pulses of the second pulse width modulation signal EM2 in the second sub-stage.

[0040] By ensuring that the number of effective level pulses output by the two pulse width modulation signals in their respective sub-stages is equal, the loads of the two driver integrated circuits can be made completely symmetrical, thereby achieving uniformity in the specifications of the driver integrated circuits, which is beneficial for thermal equalization and design simplification.

[0041] For example, in some embodiments, in the first sub-stage, the second pulse width modulation signal EM2 outputs 16 valid level pulses, and in the second sub-stage, the first pulse width modulation signal EM1 also outputs 16 valid level pulses. Thus, the light-emitting unit 20 experiences a total of 32 light-emitting pulses in one frame, which is equivalent to the dimming effect of a traditional 32 Pulse.

[0042] In some embodiments, the light emission stage can be divided into an even number of sub-stages, such as 4 or 6, with the first sub-stage and the second sub-stage appearing alternately. The first pulse width modulation signal EM1 and the second pulse width modulation signal EM2 take turns playing the normally-on role and the pulse role in adjacent sub-stages, further refining the load distribution and reducing the instantaneous power consumption peak.

[0043] In some embodiments, a brief full-off buffer period can be inserted during sub-stage switching. During the full-off buffer period, both the first pulse width modulation signal EM1 and the second pulse width modulation signal EM2 remain at an invalid level, and the light-emitting unit 20 is completely turned off to ensure a smooth transition of the sub-stage and improve the stability and reliability of the light-emitting timing.

[0044] In some embodiments, the duty cycles of the first pulse width modulation signal EM1 and the second pulse width modulation signal EM2 can be independently adjusted in the first and second sub-stages to compensate for brightness differences in the light-emitting unit 20 caused by temperature or aging, thereby maintaining overall display uniformity. For example, if the brightness of the light-emitting unit 20 is detected to be too low in the first sub-stage, the duty cycle of the second pulse width modulation signal EM2 in that sub-stage can be appropriately increased to increase the light-emitting time of that sub-stage, thereby compensating for insufficient brightness; and vice versa. Through this dynamic duty cycle adjustment, the brightness uniformity of the display panel 30 can be further improved, the service life of the display module can be extended, and the user's visual experience can be enhanced.

[0045] In one embodiment, such as Figure 3 As shown, the first pulse width modulation signal EM1 and the second pulse width modulation signal EM2 have the same frequency, and the width of the effective level pulse of the first pulse width modulation signal EM1 and the second pulse width modulation signal EM2 is greater than the width of the invalid level pulse. The delay time between the first pulse width modulation signal EM1 and the second pulse width modulation signal EM2 is greater than the width of the invalid level pulse and less than the width of the effective level pulse.

[0046] Understandably, in this embodiment, the two light-emitting control modules are periodically turned on. Since the first pulse width modulation signal EM1 and the second pulse width modulation signal EM2 have the same frequency, and the delay time between them is greater than the width of the invalid level pulse but less than the width of the valid level pulse, theoretically, at most one pulse width modulation signal is on its transition edge at any given time. This avoids the simultaneous switching of the two light-emitting control modules, effectively reducing the instantaneous power consumption of the corresponding driver integrated circuit. Simultaneously, since the valid level pulse widths of both pulse width modulation signals are greater than the invalid level pulse widths (i.e., the duty cycle of the valid level is greater than 50%), there is an overlapping region in the valid level ranges of the two pulse width modulation signals. Within the overlapping region, both light-emitting control modules are turned on simultaneously, and the light-emitting unit 20 is illuminated; in the non-overlapping region, at least one light-emitting control module is turned off, and the light-emitting unit 20 is extinguished. For any one of the effective level pulses of the pulse width modulation (PWM) signal, the ineffective level pulse of the other PWM signal is located in the middle region of the effective level pulse. This divides the single effective level pulse of the PWM signal into two parts, and the two parts of the effective level pulse form two overlapping regions. Consequently, the light-emitting unit 20 generates two light-emitting pulses within a single cycle of the PWM signal, effectively doubling the light-emitting frequency. This achieves a higher visual refresh rate while maintaining a low signal flip frequency, effectively reducing the flicker phenomenon perceptible to the human eye. Specifically, taking the first PWM signal EM1 as an example, its effective level pulse is divided into two sub-pulses by the ineffective level pulse of the second PWM signal EM2. Each sub-pulse overlaps with the effective level range of the second PWM signal EM2, thereby generating two light-emitting pulses within one cycle of the first PWM signal EM1.

[0047] While achieving the same equivalent emission frequency, compared with the prior art, the level switching frequency of the pulse width modulation signal in this embodiment can be reduced by half, and the duration of a single cycle can be doubled, thereby effectively reducing the power consumption of the driver integrated circuit.

[0048] For example, both the first pulse width modulation signal EM1 and the second pulse width modulation signal EM2 provide 16 effective level pulses. The pixel driving circuit 10 can generate 32 light-emitting pulses in one light-emitting stage, which is equivalent to a traditional 32-pulse dimming scheme. This achieves a higher equivalent number of light-emitting pulses without increasing the single-channel signal flip frequency, thereby improving the visual refresh rate while maintaining low driving power consumption and electromagnetic interference levels. In addition, by reasonably setting the duty cycle and delay time of the two signals, the width and interval of the light-emitting pulses can be flexibly adjusted to further meet the differentiated requirements of dimming accuracy and visual comfort in different application scenarios.

[0049] In some embodiments, the delay time of the first pulse width modulation signal EM1 and the second pulse width modulation signal EM2 is half the width of the effective level pulse.

[0050] In one embodiment, such as Figure 4 As shown, the first light-emitting control module 100 includes a first transistor T1, the driving module 200 includes a second transistor T2, and the second light-emitting control module 300 includes a third transistor T3.

[0051] The first terminal of the first transistor T1 is connected to the power supply terminal, the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2, and the control terminal of the first transistor T1 is used to receive the first pulse width modulation signal EM1.

[0052] The second terminal of the second transistor T2 is connected to the first terminal of the third transistor T3, and the control terminal of the second transistor T2 is connected to the control node N1.

[0053] The second terminal of the third transistor T3 is used to connect to the light-emitting unit 20, and the control terminal of the third transistor T3 is used to receive the second pulse width modulation signal EM2.

[0054] It should be noted that during the light-emitting stage, the second transistor T2 operates in the saturation region, and its conduction current is determined by the difference between the voltage of the control node N1 and the source voltage of the second transistor T2.

[0055] The specific types of the first transistor T1, the second transistor T2, and the third transistor T3 can be selected according to process requirements and performance indicators. For example, the first transistor T1, the second transistor T2, and the third transistor T3 can all be P-type thin-film transistors. Specifically, in some embodiments, the first transistor T1, the second transistor T2, and the third transistor T3 can all be P-type low-temperature polycrystalline silicon thin-film transistors, which have high carrier mobility and good stability, and can meet the requirements of high refresh rate display drivers for switching speed and current accuracy. The first terminal of the first transistor T1, the first terminal of the second transistor T2, and the first terminal of the third transistor T3 correspond to their sources, respectively; the second terminals of the first transistor T1, the second transistor T2, and the third transistor T3 correspond to their drains, respectively; and the control terminals of the first transistor T1, the second transistor T2, and the third transistor T3 correspond to their gates, respectively. The three transistors can be manufactured using the same type of thin-film transistor process, resulting in good process compatibility, no need for additional masking steps, and low manufacturing costs.

[0056] It should be noted that when the first transistor T1, the second transistor T2, and the third transistor T3 are all P-type transistors, the effective levels of the first pulse width modulation signal EM1 and the second pulse width modulation signal EM2 are low. That is, when both the first pulse width modulation signal EM1 and the second pulse width modulation signal EM2 are low, the first transistor T1 and the third transistor T3 are turned on, and the driving module 200 provides driving current to the light-emitting unit 20 under the control of the control node N1, thus lighting up the light-emitting unit 20. When at least one pulse width modulation signal is high, the corresponding transistor is turned off, and the light-emitting unit 20 is turned off.

[0057] In one embodiment, such as Figure 4 As shown, the pixel driving circuit 10 also includes a dimming module 400, which is connected to the control node N1. The dimming module 400 is used to configure the voltage of the control node N1 according to the data signal during the data writing stage. The dimming module 400 can be controlled by the line scan signal to realize line-by-line data writing.

[0058] Specifically, the data signal can be an analog voltage signal generated by the corresponding driving circuit according to the preset grayscale level or brightness requirements.

[0059] It should be noted that a single frame emission cycle typically includes three main stages: initialization, data writing, and emission. During the data writing stage, the emission control module can be switched off to prevent the OLED from emitting light during the writing process. The dimming module 400 can write and store the data signal from the external data line into the control node N1. After data writing is complete, the emission stage begins. The dimming module 400 disconnects from the control node N1, and the voltage of the control node N1 is maintained by the energy storage element. The drive module 200 transmits a constant drive current based on the voltage of the control node N1. By writing different voltages into the control node N1 according to the data signal through the dimming module 400, different currents are output by the drive transistor, thereby achieving different grayscale levels of brightness display, which is the foundation of color image display.

[0060] Meanwhile, the dimming module 400 can integrate a conduction threshold compensation function, that is, during the data writing stage, the voltage amplitude of the data signal is adjusted to compensate for the threshold voltage deviation of the drive module 200, thereby improving the display uniformity.

[0061] In one embodiment, such as Figure 4 As shown, the dimming module 400 includes a fourth transistor T4, a fifth transistor T5, and a charging capacitor C1.

[0062] The first end of the charging capacitor C1 is connected to the first end of the first light-emitting control module 100, and the second end of the charging capacitor C1 is connected to the control node N1.

[0063] The first terminal of the fourth transistor T4 is used to receive data signals, the second terminal of the fourth transistor T4 is connected to the first terminal of the drive module 200, and the control terminal of the fourth transistor T4 is used to receive the first control signal.

[0064] The first terminal of the fifth transistor T5 is connected to the second terminal of the driving module 200, the second terminal of the fifth transistor T5 is connected to the control node N1, and the control terminal of the fifth transistor T5 is used to receive the second control signal.

[0065] The specific types of the fourth transistor T4 and the fifth transistor T5 can be selected according to process requirements and performance specifications. For example, both the fourth transistor T4 and the fifth transistor T5 can be P-type thin-film transistors. The first terminal of both the fourth transistor T4 and the fifth transistor T5 are sources, the second terminals of both are drains, and the control terminals of both are gates. In some embodiments, the fifth transistor T5 can use the same scan signal S1 as the fourth transistor T4, thereby simplifying the control timing.

[0066] The first and second control signals can control the conduction and cutoff of the fourth transistor T4 and the fifth transistor T5 respectively, so that the data signal is accurately written into the control node N1 during the data writing stage, and the voltage of the control node N1 is kept stable by the charging capacitor C1 during the light-emitting stage, ensuring uniform output of the drive current.

[0067] In some embodiments, such as Figure 4 As shown, the first control signal and the second control signal can be provided using the same scan signal line to simplify the routing layout and reduce the driving complexity.

[0068] Specifically, during the data writing phase, the first and second control signals are active, and the fourth transistor T4 and the fifth transistor T5 are simultaneously turned on. The gate of the second transistor T2 (control node N1) is shorted to its drain through the fifth transistor T5, and the second transistor T2 operates in a diode-connected state. The data signal is loaded to the control node N1 through the dimming module 400. During this process, automatic compensation of the threshold voltage can be achieved.

[0069] The charging capacitor C1 can serve as a storage capacitor to maintain the voltage of the control node N1, and its capacitive coupling effect can be used to boost the voltage. No additional capacitor is required, thus saving pixel area.

[0070] In one embodiment, such as Figure 4As shown, the pixel driving circuit 10 also includes an initialization module 500, which is connected to the second terminal of the control node N1 and the second light emission control module 300. The initialization module 500 is used to configure the voltage of the second terminal of the control node N1 and the second light emission control module 300 according to the reference voltage Vrefn during the initialization phase.

[0071] The initialization phase is located before the data writing phase of each frame. Its function is to reset the voltage of the control node N1 and the second terminal (i.e. the input terminal of the light-emitting unit 20) of the second light-emitting control module 300 to a known reference potential through the initialization module 500, eliminate the influence of the residual voltage of the previous frame, ensure that the starting state of the data signal writing of each frame is consistent, and avoid image sticking and flicker problems.

[0072] For control node N1, the initialization module 500 pulls the voltage of control node N1 to a reference potential, which can provide a unified starting point for subsequent data signal writing, improving writing accuracy and consistency. For the second terminal of the second light-emitting control module 300, the initialization module 500 can prevent the light-emitting unit 20 from exhibiting weak leakage current light emission (i.e., dark state is too bright) during the non-light-emitting stage, thus improving display contrast.

[0073] In some embodiments, multiple reference voltages Vrefn with different voltage levels can be used to differentiate the initialization voltage of the control node N1 and the second terminal of the second light-emitting control module 300, so as to further optimize the compensation effect and dark state performance.

[0074] In one embodiment, such as Figure 4 As shown, the initialization module 500 includes a sixth transistor T6 and a seventh transistor T7.

[0075] The first terminal of the sixth transistor T6 is used to receive the reference voltage Vrefn, the second terminal of the sixth transistor T6 is connected to the control node N1, and the control terminal of the sixth transistor T6 is used to receive the third control signal S2.

[0076] The first terminal of the seventh transistor T7 is used to receive the reference voltage Vrefn, the second terminal of the seventh transistor T7 is connected to the second terminal of the second light-emitting control module 300, and the control terminal of the seventh transistor T7 is used to receive the fourth control signal S3.

[0077] The specific types of the sixth transistor T6 and the seventh transistor T7 can be selected according to process requirements and performance specifications. For example, both the sixth transistor T6 and the seventh transistor T7 can be P-type thin-film transistors. The first terminal of both the sixth transistor T6 and the seventh transistor T7 are sources, the second terminal of both the sixth transistor T6 and the seventh transistor T7 are drains, and the control terminal of both the sixth transistor T6 and the seventh transistor T7 are gates.

[0078] Independent initialization timing can be achieved by controlling the conduction and cutoff of the sixth transistor T6 and the seventh transistor T7 respectively through the third control signal S2 and the fourth control signal S3. When the third control signal S2 is valid, the sixth transistor T6 is turned on, and the reference voltage Vrefn is written to the control node N1 through the sixth transistor T6, completing the initialization of the control node N1. When the fourth control signal S3 is valid, the seventh transistor T7 is turned on, and the reference voltage Vrefn is written to the second terminal of the second light-emitting control module 300 through the seventh transistor T7, completing the initialization of the input terminal of the light-emitting unit 20. The two initialization processes can be performed simultaneously or in a time-division manner, and the specific timing can be flexibly adjusted according to the driving requirements. For example, in time-division initialization, the sixth transistor T6 and the seventh transistor T7 are turned on sequentially at different time periods, first initializing the control node N1 and then initializing the second terminal of the second light-emitting control module 300, or vice versa, thereby avoiding crosstalk caused by the simultaneous charging and discharging of the two nodes.

[0079] In some embodiments, the fourth control signal S2 may be the same as the first control signal and the second control signal.

[0080] This application also provides a display panel 30, which includes a pixel driving circuit 10 as described in any of the above embodiments.

[0081] Specifically, the display panel 30 includes a plurality of light-emitting units 20 arranged in an array, and each light-emitting unit 20 is connected to a corresponding pixel driving circuit 10. The pixel driving circuit 10 includes: a first light-emitting control module 100, a driving module 200, and a second light-emitting control module 300.

[0082] The first terminal of the first light-emitting control module 100 is used to connect to the power supply terminal, and the control terminal of the first light-emitting control module 100 is used to receive the first pulse width modulation signal EM1.

[0083] The first end of the driving module 200 is connected to the second end of the first light-emitting control module 100, and the control end of the driving module 200 is connected to the control node N1. The driving module 200 is used to control the conduction current of the driving module 200 according to the voltage of the control node N1.

[0084] Understandably, during the light-emitting phase, the driving module 200 can continuously provide a constant driving current based on the voltage of the control node N1, thereby ensuring the uniformity of the light emission brightness.

[0085] The first end of the second light-emitting control module 300 is connected to the second end of the driving module 200. The second end of the second light-emitting control module 300 is used to connect to the light-emitting unit 20. The control end of the second light-emitting control module 300 is used to receive the second pulse width modulation signal EM2.

[0086] It is understandable that the first pulse width modulation signal EM1 can precisely control the on and off of the first light emission control module 100, and the second pulse width modulation signal EM2 can precisely control the on and off of the second light emission control module 300, thereby achieving fine regulation of the light emission period of the light emission unit 20.

[0087] In each light-emitting stage of the pixel driving circuit 10, the driving module 200 remains on.

[0088] The light-emitting stage includes at least one sub-stage. In this sub-stage, one of the first pulse width modulation (PWM) signal EM1 and the second PWM signal EM2 maintains an active level, while the other PWM signal includes at least one inactive level pulse. Specifically, the active level refers to the level at which the corresponding light-emitting control module is turned on, and the inactive level refers to the level at which the corresponding light-emitting control module is turned off. In the sub-stage, the light-emitting control module corresponding to the PWM signal maintaining an active level remains on, while the light-emitting control module corresponding to the PWM signal containing the inactive level pulse is periodically turned off according to the pulse sequence.

[0089] It is understandable that when the first light-emitting control module 100, the driving module 200 and the second light-emitting control module 300 are all turned on, a light-emitting current path is formed, thereby providing driving current to the light-emitting unit 20 to make it emit light; and when any light-emitting control module is turned off, the current path is cut off and the light-emitting unit 20 is turned off.

[0090] Therefore, by alternating the two pulse width modulation signals, one of the pulse width modulation signals is kept at an effective level while the other outputs an invalid level pulse, the on / off state of the light emission path can be determined by the pulse width modulation signal that outputs an invalid level pulse. This reduces the number of level flips of one of the pulse width modulation signals while maintaining the equivalent dimming effect, thereby reducing the power consumption of the corresponding driver integrated circuit.

[0091] This application also provides a display device, which includes a pixel driving circuit 10 or a display panel 30 as described in any of the above embodiments. Since the display device includes the pixel driving circuit 10 of any of the above embodiments, it has the beneficial effects of the pixel driving circuit 10 of any of the above embodiments, which will not be elaborated further here.

[0092] The display devices in this application include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0093] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0094] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0095] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A pixel driving circuit, characterized in that, include: A first light-emitting control module (100) has a first end for connecting to a power supply end and a control end for receiving a first pulse width modulation signal. A driving module (200) is provided, wherein a first end of the driving module (200) is connected to a second end of the first light-emitting control module (100), and a control end of the driving module (200) is connected to a control node. The driving module (200) is used to control the conduction current of the driving module (200) according to the voltage of the control node. The second light-emitting control module (300) has a first end connected to the second end of the driving module (200), the second end of the second light-emitting control module (300) is used to connect to the light-emitting unit, and the control end of the second light-emitting control module (300) is used to receive the second pulse width modulation signal. In each light-emitting stage of the pixel driving circuit, the driving module (200) remains on; The light-emitting stage includes at least one sub-stage, in which one of the first pulse width modulation signal and the second pulse width modulation signal maintains an active level, and the other pulse width modulation signal includes at least one inactive level pulse.

2. The pixel driving circuit as described in claim 1, characterized in that, The light-emitting stage includes a first sub-stage and a second sub-stage; In the first sub-stage, the first pulse width modulation signal remains at an active level, and the second pulse width modulation signal includes multiple inactive level pulses and multiple active level pulses; In the second sub-stage, the second pulse width modulation signal remains at an active level, and the first pulse width modulation signal includes multiple invalid level pulses and multiple active level pulses.

3. The pixel driving circuit as described in claim 2, characterized in that, The number of effective level pulses of the first pulse width modulation signal in the first sub-stage is equal to the number of effective level pulses of the second pulse width modulation signal in the second sub-stage.

4. The pixel driving circuit as described in claim 1, characterized in that, The first pulse width modulation signal and the second pulse width modulation signal have the same frequency, and the width of the effective level pulse of the first pulse width modulation signal and the second pulse width modulation signal is greater than the width of the invalid level pulse. The delay time between the first pulse width modulation signal and the second pulse width modulation signal is greater than the width of the invalid level pulse and less than the width of the effective level pulse.

5. The pixel driving circuit as described in claim 1, characterized in that, The first light-emitting control module (100) includes a first transistor, the driving module (200) includes a second transistor, and the second light-emitting control module (300) includes a third transistor; The first terminal of the first transistor is connected to the power supply terminal, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the control terminal of the first transistor is used to receive the first pulse width modulation signal. The second terminal of the second transistor is connected to the first terminal of the third transistor, and the control terminal of the second transistor is connected to the control node; The second terminal of the third transistor is used to connect to the light-emitting unit, and the control terminal of the third transistor is used to receive the second pulse width modulation signal.

6. The pixel driving circuit according to any one of claims 1 to 5, characterized in that, The pixel driving circuit also includes a dimming module (400), which is connected to the control node. The dimming module (400) is used to configure the voltage of the control node according to the data signal during the data writing stage.

7. The pixel driving circuit as described in claim 6, characterized in that, The dimming module (400) includes a fourth transistor, a fifth transistor, and a charging capacitor; The first end of the charging capacitor is connected to the first end of the first light-emitting control module (100), and the second end of the charging capacitor is connected to the control node; The first terminal of the fourth transistor is used to receive data signals, the second terminal of the fourth transistor is connected to the first terminal of the driving module (200), and the control terminal of the fourth transistor is used to receive a first control signal. The first terminal of the fifth transistor is connected to the second terminal of the driving module (200), the second terminal of the fifth transistor is connected to the control node, and the control terminal of the fifth transistor is used to receive the second control signal.

8. The pixel driving circuit according to any one of claims 1 to 5, characterized in that, The pixel driving circuit further includes an initialization module (500), which is connected to the second end of the control node and the second light emission control module (300). The initialization module (500) is used to configure the voltage of the second end of the control node and the second light emission control module (300) according to the reference voltage during the initialization phase.

9. The pixel driving circuit as described in claim 8, characterized in that, The initialization module (500) includes a sixth transistor and a seventh transistor; The first terminal of the sixth transistor is used to receive the reference voltage, the second terminal of the sixth transistor is connected to the control node, and the control terminal of the sixth transistor is used to receive the third control signal. The first terminal of the seventh transistor is used to receive the reference voltage, the second terminal of the seventh transistor is connected to the second terminal of the second light-emitting control module (300), and the control terminal of the seventh transistor is used to receive the fourth control signal.

10. A display panel, characterized in that, Includes the pixel driving circuit as described in any one of claims 1 to 9.

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