Dynamic display driving multistable display

Abstract

A dynamic display driving multi-stable display includes a timing control circuit unit, a driving circuit unit and a panel unit. The timing control circuit unit generates timing control signals. The data signal of the timing control signals includes pixel dynamic display header data and pixel dynamic display waveform data. The driving circuit unit determines pixel display voltage values of pixel display driving signals output to the panel unit according to the pixel dynamic display header data, and determines pixel display driving time lengths of the pixel display driving signals having the pixel display voltage values according to the pixel dynamic display waveform data. Since the driving circuit unit only needs to determine the entire waveform of the pixel display driving signals according to the pixel dynamic display header data and the pixel dynamic display waveform data for each pixel electrode, the clock frequency is independent of the working count, the amount of data to be transmitted can be greatly reduced, and a lower clock frequency can be used, thereby reducing power consumption.

Description

Technical Field

[0001] This invention relates to a display, and more particularly to a dynamic display driven multistable display driven by a low-frequency driving method. Background Technology

[0002] Existing multistable displays, such as cholesterol liquid crystal displays (ChLCDs), exhibit bistable liquid crystal display characteristics. Therefore, these multistable displays require various voltage configurations to drive them when displaying images. For example, such a multistable display has a panel unit, where each pixel is composed of multiple scan electrodes and multiple data electrodes, and a liquid crystal layer is disposed between the line electrodes and the pixel electrodes. When driving the panel unit, a voltage is applied to the line electrodes and the pixel electrodes, creating a specific voltage across the corresponding pixel position, causing the liquid crystal in the liquid crystal layer to rotate to a specific angle.

[0003] However, this multi-stable display requires multiple voltage configurations to drive it. Therefore, in the control signals, the data used to control the voltage configuration of each pixel needs to be transmitted through multiple bits, and multiple voltage configurations cannot be expressed with a single bit. For example, currently, the data used to control the voltage configuration is transmitted through 3 bits of data. That is, every time the voltage configuration of a pixel is changed, 3 bits of data need to be transmitted.

[0004] Furthermore, the multistable display includes a timing controller (TCON) and a driver IC. The timing controller generates a timing control signal to the driver IC, which outputs a pixel drive signal to the line electrodes and the pixel electrodes according to the control signal, thereby driving the multistable display to display a specific image.

[0005] Generally, this timing control circuit unit has a clock output terminal (clock; clk), a display output enable control terminal (display output enable; doe), a display output ground control terminal (display output ground; dog), a digital-to-analog conversion control terminal (digital to analog; d2a), a display start signal control terminal (displaystart pulse; dsp), and multiple data output terminals (data). The clock output terminal (clk), display output enable control terminal (doe), display output ground control terminal (dog), digital-to-analog conversion control terminal (d2a), display start signal control terminal (dsp), and data output terminals of this timing control circuit unit are connected to the driver circuit unit (Driver IC) to output the control signal. The frequency of the clock signal output by the clock output terminal (clk) greatly affects the overall power consumption. The higher the frequency of the clock signal, the greater the overall power consumption.

[0006] For example, consider a multistable display with a Full HD resolution of 1920×1080. When transmitting at a single data rate (SDR), 2 pixels of data are transmitted per clock cycle, meaning 2 pixels are transmitted per clock cycle. Furthermore, the transmission time (T) for each frame is set. line The time complexity is 5 milliseconds (ms). Each pixel of this multi-stable display requires 3 bits of data to be transmitted. Furthermore, since each pixel requires 3 bits of data to be transmitted, and the number of pixels transmitted per clock cycle is 2, the number of data output terminals is 6, calculated as 3 × 2 = 6.

[0007] Furthermore, for each pixel, multiple voltage configurations are required to complete the output within a frame. Therefore, the voltage waveform needs to be adjusted within a frame. For example, there are multiple duty periods within a frame, and the total number of duty periods within a frame is called the duty count. For instance, the duty count can be adjusted as needed and can be set to 64, typically in powers of 2. When the voltage configuration required for each duty period is different, 3 bits of data need to be sent again. Therefore, the more duty periods there are, the more times data needs to be transmitted.

[0008] The clock rate of this multistable display can be calculated using the following formula:

[0009]

[0010] The resolution is 1920. The number of pixels transmitted per clock cycle is 2 in SDR mode. The hold time is set to 1. The duty count can be adjusted as needed and can be set to 64. The transmission time (T) line The value is 5 milliseconds (ms). Substituting the above figures into the formula yields the following Table 1.

[0011]

[0012] Table 1

[0013] As shown in Table 1, under Full HD resolution, the clock rate of this multistable display is quite high because the clock rate is related to the duty count. This results in high power consumption and rapid power consumption. Summary of the Invention

[0014] Given that existing multistable displays have relatively high clock rates, resulting in high power consumption and rapid battery drain, this invention provides a dynamic display driver for multistable displays to reduce the clock rate of the multistable display, thereby reducing power consumption.

[0015] The dynamic display driver multistable display includes a timing control circuit unit (TCON), a driver circuit unit (Driver IC), and a panel unit.

[0016] The timing control circuit unit generates a timing control signal. The drive circuit unit is connected to the timing control circuit unit and receives the timing control signal. The panel unit is connected to the drive circuit unit.

[0017] The timing control signal includes a data signal, which contains pixel dynamic display header data and pixel dynamic display waveform data. The driving circuit unit determines the pixel display voltage value of the pixel display driving signal output to the panel unit based on the pixel dynamic display header data. The driving circuit unit has a half-working total, and it determines the pixel display driving duration for outputting the pixel display driving signal with the pixel display voltage value based on the half-working total and the pixel dynamic display waveform data.

[0018] Because the driving circuit unit determines the pixel display voltage value of the pixel display driving signal output to the panel unit based on the pixel dynamic display header data, and determines the pixel display driving duration of the pixel display driving signal with the pixel display voltage value based on the pixel dynamic display waveform data and its own preset half-duty count, the driving circuit unit only needs to determine the entire waveform of the pixel display driving signal for each pixel electrode based on the pixel dynamic display header data and the pixel dynamic display waveform data. There is no need to readjust the voltage waveform by providing a new voltage value during voltage adjustment. In other words, the clock rate is independent of the duty count. This significantly reduces the amount of data that needs to be transmitted, and allows for the use of a lower clock rate to transmit the same amount of data in the same amount of time, thereby reducing power consumption. Attached Figure Description

[0019] Figure 1 This is a block diagram of the dynamic display driving multistable display of the present invention.

[0020] Figure 2 This is a schematic diagram of the electrode structure of the panel unit 30 of the dynamic display driving multistable display of the present invention.

[0021] Figure 3A This is a waveform diagram of the header setting signal output by the header setting control terminal (dsh) of the first embodiment of the dynamic display driving multistable display of the present invention.

[0022] Figure 3B This is a schematic diagram of the data signal output from the data signal output terminal of the first embodiment of the dynamic display driving multistable display of the present invention.

[0023] Figure 4AThis is a waveform diagram of the header setting signal output by the header setting control terminal (dsh) of the second embodiment of the dynamic display driving multistable display of the present invention.

[0024] Figure 4B This is a schematic diagram of the data signal output from the data signal output terminal of the second embodiment of the dynamic display driving multistable display of the present invention.

[0025] Figure 5A This is a waveform diagram of the header setting signal output by the header setting control terminal (dsh) of the fourth embodiment of the dynamic display driving multistable display of the present invention.

[0026] Figure 5B This is a schematic diagram of the data signal output from the data signal output terminal of the fourth embodiment of the dynamic display driving multistable display of the present invention.

[0027] Figure 6A This is a waveform diagram of the header setting signal output by the header setting control terminal (dsh) of the fifth embodiment of the dynamic display driving multistable display of the present invention.

[0028] Figure 6B This is a schematic diagram of the data signal output from the data signal output terminal of the fifth embodiment of the dynamic display driving multistable display of the present invention.

[0029] Figure 7A This is a schematic diagram of the pixel clearing waveform data of the data signal output from the data signal output terminal of the dynamic display driving multistable display of the present invention.

[0030] Figure 7B This is a schematic diagram of the pixel clearing waveform data of the data signals output from the first to third data output terminals (data 0 to data 3) of the dynamic display driver multistable display of the present invention.

[0031] Figure 8A This is a schematic diagram of the pixel dynamic display header data of the data signal output terminal of the dynamic display driving multistable display of the present invention.

[0032] Figure 8B This is a schematic diagram of the pixel dynamic display header data of the data signals output by the first to third data output terminals (data 0 to data 2) of the dynamic display driver multistable display of the present invention.

[0033] Figure 9A This is a schematic diagram of the pixel dynamic display waveform data of the data signal output from the data signal output terminal of the dynamic display driving multistable display of the present invention.

[0034] Figure 9BThis is a schematic diagram of the pixel dynamic display waveform data of the data signals output by the first to third data output terminals (data 0 to data 2) of the dynamic display driving multi-stable display of the present invention.

[0035] Figure 10 This is a schematic diagram of the data signals output from the first to third data output terminals (data 0 to data 2) of the dynamic display driving multistable display of the present invention.

[0036] Figure 11A This is a waveform diagram of the data driving signal output from the driving circuit unit of the dynamic display driving multistable display of the present invention to the first pixel electrode.

[0037] Figure 11B This is a waveform diagram of the data driving signal output from the driving circuit unit of the dynamic display driving multistable display of the present invention to the second pixel electrode.

[0038] Figure 11C This is another waveform diagram of the data driving signal output to the first pixel electrode by the driving circuit unit of the dynamic display driving multistable display of the present invention.

[0039] Figure 12 This is another block diagram of the dynamic display driving multistable display of the present invention.

[0040] Figure 13 This is a schematic diagram of the data signals output from the first to third data output terminals (data 0 to data 2) of the dynamic display driving multistable display of the present invention.

[0041] Figure 14A This is a waveform diagram of the data driving signal output from the driving circuit unit of the dynamic display driving multistable display of the present invention to the first pixel electrode.

[0042] Figure 14B This is a waveform diagram of the data driving signal output from the driving circuit unit of the dynamic display driving multistable display of the present invention to the second pixel electrode.

[0043] Figure 14C This is a schematic diagram of the conversion control signal output by the digital-to-analog conversion control terminal (d2a) of the dynamic display driving multistable display of the present invention.

[0044] Figure 15 This is another block diagram of the dynamic display driving multistable display of the present invention.

[0045] Figure 16A This is a waveform diagram of the header setting signal output by the header setting control terminal (dsh) of the dynamic display driving multistable display of the present invention.

[0046] Figure 16B This is a schematic diagram of the scanning signal output from the scanning signal output terminal of the dynamic display driving multistable display of the present invention.

[0047] Figure 16C This is a schematic diagram of the conversion control signal output by the digital-to-analog conversion control terminal (d2a) of the dynamic display driving multistable display of the present invention.

[0048] Figure 17A This is a schematic diagram of the line dynamic display header data of the scan signal output terminal of the dynamic display driving multistable display of the present invention.

[0049] Figure 17B This is a schematic diagram of the line dynamic display header data of the scan signals output from the first to third scan output terminals (scan 0 to scan 2) of the dynamic display driver multistable display of the present invention.

[0050] Figure 18A This is a schematic diagram of the line dynamic display waveform data of the scan signal output from the scan signal output terminal of the dynamic display driving multistable display of the present invention.

[0051] Figure 18B This is a schematic diagram of the line dynamic display waveform data of the scan signals output from the first to third scan output terminals (scan 0 to scan 2) of the dynamic display driver multistable display of the present invention.

[0052] Figure 19 This is a schematic diagram of the scanning signals output from the first to third scan output terminals (scan 0 to scan 2) of the dynamic display driving multistable display of the present invention.

[0053] Figure 20A This is a waveform diagram of the scanning drive signal output from the drive circuit unit of the dynamic display driving multistable display of the present invention to the first line electrode.

[0054] Figure 20B This is a waveform diagram of the scanning drive signal output from the driving circuit unit of the dynamic display driving multistable display of the present invention to the second line electrode.

[0055] Figure 20C This is a schematic diagram of the conversion control signal output by the digital-to-analog conversion control terminal (d2a) of the dynamic display driving multistable display of the present invention. Detailed Implementation

[0056] Please see Figure 1 As shown, the dynamic display driven multistable display of the present invention includes a timing control circuit unit 10, a driving circuit unit 20, and a panel unit 30.

[0057] The timing control circuit unit 10 generates a timing control signal. The drive circuit unit 20 is connected to the timing control circuit unit 10 and receives the timing control signal. The panel unit 30 is connected to the drive circuit unit 20 and receives the timing control signal.

[0058] Please see Figure 2 The diagram shows the structure of the panel unit 20 of the multi-stable display. The panel unit 30 is a passive matrix composed of a plurality of intersecting pixel electrodes 31 (rows 1 to n) and a plurality of line electrodes 32 (columns 1 to m), with each pixel electrode 31 and each line electrode 32 forming a pixel at their intersection. In other words, each pixel has a corresponding pixel electrode 31 and a corresponding line electrode 32. Figure 2 In this display panel unit 30, there are n pixel electrodes 31 and m line electrodes 32. The panel unit 30 is driven by the driving circuit unit 20 outputting pixel driving signals to the pixel electrodes 31 and line driving signals to the line electrodes 32. For example, the driving circuit unit 20 sequentially outputs pixel driving signals and line driving signals to the pixel electrodes 31 and the line electrodes 32 in a scanning manner.

[0059] Please see Figure 3A and Figure 3B As shown, the timing control signal includes a data signal 11, and the data signal 11 includes pixel dynamic display header data 111 and pixel dynamic display waveform data 112. The driving circuit unit 20 determines the pixel display voltage value of the pixel display driving signal output to the panel unit 30 based on the pixel dynamic display header data 111. The driving circuit unit 20 also has a half duty count, and the half duty count is data built into the driving circuit unit 20. In one embodiment, the driving circuit unit 20 can also calculate the half duty count multiplied by 2 to obtain a duty count. The driving circuit unit 20 determines the pixel display driving duration of the pixel display driving signal with the pixel display voltage value based on the half duty count and the pixel dynamic display waveform data 112. In this embodiment, the pixel display driving signal is the pixel driving signal output by the driving circuit unit 20 to the pixel electrode 31.

[0060] Since the driving circuit unit 20 determines the pixel display voltage value of the pixel display driving signal output to the panel unit 30 based on the pixel dynamic display header data 111, and determines the pixel display driving duration of the pixel display driving signal with the pixel display voltage value based on the pixel dynamic display waveform data 112 and its own preset half-duty count, the driving circuit unit 20 only needs to determine the entire waveform of the pixel display driving signal for each pixel electrode based on the pixel dynamic display header data 111 and the pixel dynamic display waveform data 112, without needing to readjust the voltage waveform by applying a new voltage during voltage adjustment. In other words, the clock rate is independent of the duty count, which significantly reduces the amount of data that needs to be transmitted, and allows for the use of a lower clock rate to transmit the same amount of data in the same amount of time, thereby reducing power consumption.

[0061] Furthermore, please refer to Figure 4A and Figure 4B As shown, the data signal 11 also includes pixel clear header data 113. The driving circuit unit 20 determines a pixel clear driving signal to be output to the panel unit 30 based on the pixel clear header data 113. Generally, the pixel clear driving signal is a driving signal with a fixed waveform. Therefore, the driving circuit unit 20 can determine the pixel clear voltage value of the pixel clear driving signal based on the data in the pixel clear header data 113, and then output the pixel clear driving signal with a fixed waveform.

[0062] In addition, please see Figure 5A and Figure 5B As shown, the data signal 11 also includes pixel clearing header data 113 and pixel clearing waveform data 114. The driving circuit unit 20 determines the pixel clearing voltage value of the pixel clearing driving signal output to the panel unit 30 based on the pixel clearing header data 113, and the driving circuit unit 20 determines the pixel clearing driving duration of the pixel clearing driving signal with the pixel clearing voltage value based on the half-working total and the pixel clearing waveform data 114. In this embodiment, the pixel clearing driving signal is the pixel driving signal output by the driving circuit unit 20 to the pixel electrode 31.

[0063] In addition, the data signal 11 also includes a blank data 110. For example... Figure 4B As shown, the blank data 110 is located between the pixel header waveform data 113 and the pixel dynamic display header data 111. Alternatively, as... Figure 5BAs shown, the blank data 110 is located between the pixel clearing waveform data 114 and the pixel dynamic display header data 111. The time occupied by the blank data 10 is used by the drive circuit unit 20 to output the pixel clearing drive signal to the panel unit 30.

[0064] In detail, such as Figure 1 As shown, in one embodiment, the timing control circuit unit 10 includes a clock output terminal (clock; clk), a display output enable control terminal (display output enable; doe), a display output ground control terminal (display output ground; dog), and a display start signal control terminal (display start pulse; dsp). The functions of the clock output terminal (clk), the display output enable control terminal (doe), the display output ground control terminal (dog), and the display start signal control terminal (dsp) of the timing control circuit unit 10 are the same as those of the timing control circuit unit 10 of existing multi-stable displays, and will not be described in detail here.

[0065] Furthermore, the timing control circuit unit 10 includes a header setting control terminal (dsh) and a data signal output terminal. In other embodiments, the data output terminal of the timing control circuit unit 10 includes multiple data output terminals (data 0 to data n), such as the first to the (n+1)th data output terminals (data 0 to data n). In this embodiment, the first to the third data output terminals (data 0 to data 2) are used as examples, but this is not a limitation.

[0066] The header setting control terminal (dsh) is connected to the drive circuit unit 20 and outputs a header setting signal 101 to the drive circuit unit 20. The data signal output terminal (data 0) is connected to the drive circuit unit 20 and outputs the data signal 11 to the drive circuit unit 20.

[0067] like Figure 3A and Figure 3B As shown, when the data signal 11 output by the data signal output terminal (data 0~data 2) is the pixel dynamic display header data 111, the header setting signal 101 output by the header setting control terminal (dsh) is a high voltage level. Figure 4A and Figure 4B As shown, or as Figure 5A and Figure 5BAs shown, when the data signal 11 output by the data signal output terminal (data0~data2) is the pixel clear header data 113, the header setting signal 101 output by the header setting control terminal (dsh) is at a high voltage level. However, when the data signal 11 output by the data signal output terminal (data0~data2) is neither the pixel clear header data 113 nor the pixel dynamic display header data 111, the header setting signal 101 output by the header setting control terminal (dsh) is at a low voltage level.

[0068] When the header setting signal 101 output by the header setting control terminal (dsh) is at the high voltage level, it means that the data signal 11 output by the data signal output terminal (data 0) is either the pixel clear header data 113 or the pixel dynamic display header data 111. In this way, the drive circuit unit 20 can determine whether the currently received data signal 11 is the pixel clear header data 113 or the pixel dynamic display header data 111 by using the header setting signal 101.

[0069] Please see Figure 6A and Figure 6B As shown, the pixel clear header data 113 includes a positive clear voltage data 1131 and a negative clear voltage data 1132. Furthermore, the pixel clear header data 113 may also include clear clock data. This clear clock data is the number of clock cycles per unit time of clearing. The number of clock cycles per unit time of clearing refers to the number of clock cycles (clk) required for one duty cycle. For example, the clear clock data is a 3-bit number, and the drive circuit unit 20 pre-stores a bit value lookup table. The drive circuit unit 20 can obtain the corresponding value based on the bit number of the clear clock data by looking up the table. For example, the bit value lookup table is shown in Table 2 below:

[0070]

[0071] Table 2

[0072] Using Table 2 above, the driving circuit unit 20 can read a 3-bit number and look up the value of 0, 2, 4, or 6. For example, reading 000 and 001 both represent the value 0, reading 001 and 010 both represent the value 2, reading 100 and 101 both represent the value 4, and reading 110 and 111 both represent the value 6. For instance, when the clear clock data is set to 100, it means that each corresponding duty period is 4 clock cycles, and so on. Therefore, in this embodiment, the driving circuit unit 20 interprets the 3-bit number as an even number, and this setting facilitates subsequent calculations. In other embodiments of this invention, the driving circuit unit 20 can also interpret 3-bit or multi-bit numbers to obtain a value through other methods, such as methods other than looking up a table.

[0073] Furthermore, the pixel positive clear voltage data 1131 includes a first pixel positive clear voltage value 1131a and a second pixel positive clear voltage value 1131b, and the pixel negative clear voltage data 1132 includes a first pixel negative clear voltage value 1132a and a second pixel negative clear voltage value 1132b. In this embodiment, the first pixel positive clear voltage value 1131a is the first value of the first to third data output terminals (data 0 to data 2), and the first pixel positive clear voltage value 1131a is represented by a 3-bit data, namely V1(0) to V1(2), corresponding to a first voltage V1. For example, the value corresponding to the first voltage V1 is 001, that is, V1(2) = 0, V1(1) = 0, V1(0) = 1. The second pixel positive clear voltage value 1131b is the second value of the first to third data output terminals (data 0 to data 2), and this second pixel positive clear voltage value is also represented by a 3-bit data form, corresponding to the first voltage V1. Similarly, the first pixel negative clear voltage value 1132a is the third value of the first to third data output terminals (data 0 to data 2), and this first pixel negative clear voltage value is represented by a 3-bit data form, namely V4(0) to V4(2), corresponding to a fourth voltage V4. For example, the value corresponding to the fourth voltage V4 is 100, that is, V4(2) = 1, V4(1) = 0, V4(0) = 0. The second pixel negative clear voltage value 1132b is the fourth value of the first to third data output terminals (data0 to data 2), and this second pixel negative clear voltage value 1132b is also represented by a 3-bit data form, corresponding to the fourth voltage V4.

[0074] Please see Figure 7A and Figure 7BAs shown, the pixel clearing waveform data 114 includes multiple pixel electrode clearing data 1141 to 114n. The pixel electrode clearing data 1141 to 114n includes at least one first pixel electrode clearing data 1141, and the first pixel electrode clearing data 1141 includes a first clearing voltage unit number. In this embodiment, the first clearing voltage unit number is the value of the first to third data output terminals (data 0 to data 2), and the first clearing voltage unit number is represented by a 3-bit data format, i.e., pixel1(0) to pixel1(2), corresponding to a first pixel electrode. For example, the first clearing voltage unit number is a combination of the values ​​of the first to third data output terminals (data 0 to data 2). Furthermore, the pixel electrode clearing data 1141 to 114n may also include second to nth pixel electrode clearing data 1142 to 114n, and the second to nth pixel electrode clearing data 1142 to 114n each include a second to nth clearing voltage unit number. Similarly, the second clear voltage unit number is composed of the values ​​of the first to third data output terminals (data 0 to data2), and the second clear voltage unit number is represented by a 3-bit data, namely pixel 2(0) to pixel 2(2), corresponding to a second pixel electrode.

[0075] Furthermore, based on the aforementioned half-working total, the drive circuit unit 20 subtracts the first clear voltage unit number from double the half-working total to determine a first remaining clear voltage unit number. For example, if the half-working total is 6, then double the half-working total is 12. According to the bit value lookup table, when the first clear voltage unit number is 100, it represents the value 4. In this case, double the half-working total minus the first clear voltage unit number is 12 - 4 = 8, so the drive circuit unit 20 sets the first remaining clear voltage unit number to 8. In other examples, when the first clear voltage unit number is 010, it represents the value 2. In this case, double the half-working total minus the first clear voltage unit number is 12 - 2 = 10, so the drive circuit unit 20 sets the first remaining clear voltage unit number to 10.

[0076] In this embodiment, the pixel clearing header data 111 may also include half-work total data. Furthermore, the driving circuit unit 20 can set the half-work total based on the half-work total data in the pixel clearing header data 111.

[0077] Furthermore, when the driving circuit unit 20 determines the pixel clearing drive duration for outputting the pixel clearing drive signal with the pixel clearing voltage value based on the half-working total and the pixel clearing waveform data 114, the driving circuit unit 20 determines a first clearing duration for the pixel clearing drive signal output to the first pixel electrode and having the first positive pixel clearing voltage value based on the first clearing voltage units in the pixel clearing waveform data 112, and the driving circuit unit 20 determines a second clearing duration for the pixel clearing drive signal output to the first pixel electrode and having the second positive pixel clearing voltage value by subtracting the first clearing voltage units from double the half-working total. In other words, the driving circuit unit 20 determines the second clearing duration based on the first remaining clearing voltage units. Furthermore, the driving circuit unit 20 determines a third clearing duration for the pixel clearing drive signal output to the first pixel electrode and having the first pixel negative clearing voltage value based on the first clearing voltage unit number of the pixel clearing waveform data, and the driving circuit unit determines a fourth clearing duration for the pixel clearing drive signal output to the first pixel electrode and having the second pixel negative clearing voltage value based on twice the half-working total number minus the first clearing voltage unit number. In other words, the driving circuit unit 20 also determines the fourth clearing duration based on the first remaining clearing voltage unit number.

[0078] Please see Figure 8A and Figure 8B As shown, the pixel dynamic display header data 111 includes positive display voltage data 1111 and negative display voltage data 1112. Furthermore, the pixel dynamic display header data 111 may also include display clock data, which contains the number of clocks per unit time. The number of clocks per unit time refers to the number of clocks (clk) required for one duty period. For example, according to the bit value lookup table, the display clock data uses a 3-bit number to represent a value, such as 000 representing the value 0, 100 representing the value 4, and 111 representing the value 6. For example, when the display clock data is set to 100, it represents a duty period of 4 clocks (clk).

[0079] Furthermore, the positive display voltage data 1111 includes a first positive display voltage value 1111a and a second positive display voltage value 1111b, and the negative display voltage data 1112 includes a first negative display voltage value 1112a and a second negative display voltage value 1112b. In this embodiment, the first positive display voltage value 1111a is the first value of the first to third data output terminals (data 0 to data 2), and the first positive display voltage value is represented by a 3-bit data, namely V2(0) to V2(2), corresponding to a second voltage V2. For example, the value corresponding to the second voltage V2 is 010, that is, V2(2) = 0, V2(1) = 1, V2(0) = 0. The second pixel positive display voltage value 1111b is the second value of the first to third data output terminals (data 0 to data 2), and the second pixel positive display voltage value is also represented by a 3-bit data form, namely V3(0) to V3(2), corresponding to a third voltage V3. For example, the value corresponding to the third voltage V3 is 011, that is, V3(2) = 0, V3(1) = 1, V3(0) = 1. Similarly, the first pixel negative display voltage value 1112a is the third value of the first to third data output terminals (data 0 to data 2), and the first pixel negative display voltage value 1112a is represented by a 3-bit data form, namely V5(0) to V5(2), corresponding to a fifth voltage V5. For example, the value corresponding to the fifth voltage V5 is 101, that is, V5(2) = 1, V5(1) = 0, V5(0) = 1. The second pixel negative display voltage value 1112b is the fourth value of the first to third data output terminals (data 0 to data 2), and the second pixel negative display voltage value is also represented by a 3-bit data, namely V6(0) to V6(2), corresponding to a sixth voltage V6. For example, the value corresponding to the sixth voltage V6 is 110, that is, V6(2) = 1, V6(1) = 1, V6(0) = 0.

[0080] In one embodiment, the first voltage V1 and the fourth voltage V4 each have the same voltage difference as a common voltage Vcom. In other words, the absolute value of the first voltage V1 minus the common voltage Vcom is equal to the absolute value of the fourth voltage V4 minus the common voltage Vcom. Similarly, the second voltage V2 and the fifth voltage V5 each have the same voltage difference as the common voltage Vcom, and the third voltage V3 and the sixth voltage V6 each have the same voltage difference as the common voltage Vcom.

[0081] Please see Figure 9A and Figure 9BAs shown, the pixel dynamic display waveform data 112 includes multiple pixel electrode display data 1121 to 112n. The pixel electrode display data 1121 to 112n includes at least one first pixel electrode display data 1121, and the first pixel electrode display data 1121 includes a first display voltage unit number. In this embodiment, the first display voltage unit number is the value of the first to third data output terminals (data 0 to data 2), and the first display voltage unit number is represented by a 3-bit data format, i.e., pixel 1(0) to pixel 1(2), corresponding to the first pixel electrode. For example, the first display voltage unit number is a combination of the values ​​of the first to third data output terminals (data 0 to data 2). Furthermore, the pixel electrode display data 1121 to 112n may also include second to nth pixel electrode display data 1122 to 112n, and the second to nth pixel electrode display data 1122 to 112n each include a second to nth display voltage unit number. Similarly, the second display voltage unit number is the value of the first to third data output terminals (data 0 to data 2), and the second display voltage unit number is represented by a 3-bit data, namely pixel 2(0) to pixel 2(2), corresponding to the second pixel electrode.

[0082] Furthermore, based on the aforementioned total number of half-working units, the driving circuit unit 20 subtracts the first display voltage unit number from the total number of half-working units to determine a first remaining display voltage unit number. For example, the total number of half-working units is set to 6. According to the bit value lookup table, when the first display voltage unit number is 100, it represents the value 4. In this case, the total number of half-working units minus the first display voltage unit number is 6 - 4 = 2, so the driving circuit unit 20 sets the first remaining display voltage unit number to 2. In other examples, when the first display voltage unit number is 010, it represents the value 2. In this case, the total number of half-working units minus the first display voltage unit number is 6 - 2 = 4, and the driving circuit unit 20 sets the first remaining display voltage unit number to 4.

[0083] In this embodiment, the pixel dynamic display header data 114 may also include the half-working total data. Furthermore, the driving circuit unit 20 can set the half-working total based on the half-working total data in the pixel dynamic display header data 114.

[0084] Furthermore, when the driving circuit unit 20 determines the pixel display driving duration for outputting the pixel display driving signal with the pixel display voltage value based on the half-working total and the pixel dynamic display waveform data 111, the driving circuit unit 20 determines a first display duration for the pixel display driving signal output to the first pixel electrode and having the first pixel positive display voltage value based on the first display voltage units of the pixel dynamic display waveform data 112, and the driving circuit unit 20 determines a second display duration for the pixel display driving signal output to the first pixel electrode and having the second pixel positive display voltage value based on the half-working total, and the driving circuit unit 20 determines a third display duration for the pixel display driving signal output to the first pixel electrode and having the first pixel positive display voltage value based on the first remaining display voltage units. Furthermore, the driving circuit unit 20 determines a fourth display duration of the pixel display driving signal output to the first pixel electrode and having the negative display voltage value of the first pixel based on the first display voltage unit number of the pixel dynamic display waveform data, and the driving circuit unit 20 determines a fifth display duration of the pixel display driving signal output to the first pixel electrode and having the negative display voltage value of the second pixel based on the half-working total number, and the driving circuit unit 20 determines a sixth display duration of the pixel display driving signal output to the first pixel electrode and having the negative display voltage value of the first pixel based on the first remaining display voltage unit number.

[0085] For example, please refer to Figure 10As shown, the total number of half-work units is an integer of 6. As shown in the first pixel electrode clearing data 1141, the number of first clearing voltage units is 111. As shown in the second pixel electrode clearing data 1142, the number of second clearing voltage units is 111. As shown in the first pixel positive clearing voltage value 1131a, the first pixel positive clearing voltage value is the first voltage V1, i.e., 001. As shown in the second pixel positive clearing voltage value 1131b, the second pixel positive clearing voltage value is the first voltage V1, i.e., 001. As shown in the first pixel negative clearing voltage value 1132a, the first pixel negative clearing voltage value is the fourth voltage V4, i.e., 100. As shown in the second pixel negative clearing voltage value 1132b, the second pixel negative clearing voltage value is the fourth voltage V4, i.e., 100. As shown in the first pixel electrode display data 1121, the number of first display voltage units is 010. As shown in the second pixel electrode display data 1122, the number of second display voltage units is 000. As shown by the positive display voltage value 1111a of the first pixel, the positive display voltage value of the first pixel is the second voltage V2, i.e., 010. As shown by the positive display voltage value 1111b of the second pixel, the positive display voltage value of the second pixel is the third voltage V3, i.e., 011. As shown by the negative display voltage value 1112a of the first pixel, the negative display voltage value of the first pixel is the fifth voltage V5, i.e., 101. As shown by the negative display voltage value 1112b of the second pixel, the negative display voltage value of the second pixel is the sixth voltage V6, i.e., 110.

[0086] For example, in one embodiment, according to the bit value lookup table, when the number of first clear voltage units is 111, the first clear duration of the pixel clear drive signal output by the driving circuit unit 20 to the first pixel electrode, which has the first pixel positive clear voltage value, i.e., the first voltage V1, is 6 working hours. Furthermore, the total number of half-working hours is 6, and double the total number of half-working hours is 12. Therefore, subtracting the first clear duration from the doubled total number of half-working hours results in 12 - 6 = 6, meaning the second clear duration is 6 working hours.

[0087] Next, the driving circuit unit 20 enters the negative half-cycle. The driving circuit unit 20 outputs a pixel clearing driving signal with the negative clearing voltage value of the first pixel, i.e., the fourth voltage V4. The third clearing duration to the first pixel electrode is 6 working hours. Furthermore, since the total number of half-working hours is 6, the double total number of half-working hours minus the first clearing duration is 12-6=6, therefore the fourth clearing duration is 6 working hours.

[0088] Similarly, according to the bit value lookup table, when the number of second clear voltage units is 111, the first clear duration of the pixel clear drive signal output by the drive circuit unit 20 to the second pixel electrode, which has the first pixel positive clear voltage value, V1, is 6 working hours. Furthermore, the total number of half-working hours is 6, and doubling the total number of half-working hours minus the first clear duration is 12 - 6 = 6, therefore the second clear duration is 6 working hours.

[0089] Next, the driving circuit unit 20 enters the negative half-cycle. The driving circuit unit 20 outputs a pixel clearing driving signal with the first pixel negative clearing voltage value, i.e., the fourth voltage V4, and the third clearing duration to the second pixel electrode is 6 working hours. Similarly, since the total number of half-working hours is 6, the double total number of half-working hours minus the first clearing duration is 12-6=6, therefore the fourth clearing duration is 6 working hours.

[0090] In another embodiment, the driving circuit unit 20 may also determine the pixel clearing driving signal output to the panel unit 30 based on the pixel clearing header data 113. Generally, the pixel clearing driving signal is a driving signal with a fixed waveform. Therefore, the driving circuit unit 20 may determine the pixel clearing voltage value of the pixel clearing driving signal based on the data in the pixel clearing header data 113, and then output the pixel clearing driving signal with a fixed waveform.

[0091] Furthermore, when the first display voltage unit number is 010, the first display duration of the pixel display driving signal output by the driving circuit unit 20 to the first pixel electrode, having the first pixel positive display voltage value, i.e., the second voltage V2, is 2 working hours (duty). And since the total number of half-duty periods is 6, the second display duration of the pixel display driving signal output by the driving circuit unit 20 to the first pixel electrode, having the second pixel positive display voltage value, i.e., the first voltage V1, is 6 working hours (duty). Furthermore, since 6-2=4, the first remaining display voltage unit number is set to 4, and the third display duration of the pixel display driving signal output by the driving circuit unit 20 to the first pixel electrode, having the first pixel positive display voltage value, i.e., the second voltage V2, is 4 working hours (duty).

[0092] Next, the driving circuit unit 20 enters the negative half-cycle period. The driving circuit unit 20 then outputs a pixel display driving signal with the first pixel negative display voltage value, i.e., the fifth voltage V5, to the first pixel electrode for the fourth display duration, which is 2 working hours. Since the total number of half-cycles is 6, the fifth display duration of the pixel display driving signal output by the driving circuit unit 20 to the first pixel electrode with the second pixel negative display voltage value, i.e., the fourth voltage V4, is 6 working hours. Furthermore, since the number of first remaining display voltage units is 4, the sixth display duration of the pixel display driving signal output by the driving circuit unit 20 to the first pixel electrode with the first pixel negative display voltage value, i.e., the fifth voltage V5, is 4 working hours.

[0093] Similarly, when the second display voltage unit number is 000, the first display duration of the pixel display drive signal output by the driving circuit unit 20 to the second pixel, which has the positive display voltage value of the first pixel (i.e., the first voltage V1), is 0 working hours (duty). And since the total number of half-working units is 6, the second display duration of the pixel display drive signal output by the driving circuit unit 20 to the second pixel, which has the positive display voltage value of the second pixel (i.e., the second voltage V2), is 6 working hours (duty). Furthermore, since the first remaining display voltage unit number is 6-0=6, the third display duration of the pixel display drive signal output by the driving circuit unit 20 to the second pixel electrode, which has the positive display voltage value of the first pixel (i.e., the first voltage V1), is 6 working hours (duty).

[0094] Next, the driving circuit unit 20 enters the negative half-cycle. The driving circuit unit 20 then outputs a pixel display driving signal with the negative display voltage value of the first pixel, i.e., the fourth voltage V4, to the second pixel for the first display duration, and the fourth display duration is 0 working hours (duty). Since the total number of half-cycles is 6, the fifth display duration of the pixel display driving signal with the negative display voltage value of the second pixel, i.e., the fifth voltage V5, output by the driving circuit unit 20 to the second pixel for 6 working hours (duty). Furthermore, since the number of first remaining display voltage units is 6-0=6, the sixth display duration of the pixel display driving signal with the negative display voltage value of the first pixel, i.e., the fourth voltage V4, output by the driving circuit unit 20 to the second pixel electrode for 6 working hours (duty).

[0095] like Figure 11A and Figure 11B As shown, Figure 11AThis is a waveform diagram of the pixel display drive signal waveform 201 output by the drive circuit unit 20 to the first pixel electrode. Figure 11B This is a waveform diagram of the pixel display drive signal waveform 202 output by the drive circuit unit 20 to the second pixel electrode. Please refer to... Figure 11A and Figure 11C , Figure 11A The pixel display driving signal waveform 201 can be divided into a first voltage waveform 201a and a second voltage waveform 201b, wherein the first voltage waveform 201a is earlier than the second voltage waveform 201b in timing. The first voltage waveform 201a represents the state in which the driving circuit unit 20 controls the first pixel electrode to reset (clear the display content), while the second voltage waveform 201b represents the state in which the driving circuit unit 20 controls the first pixel electrode to perform the first dynamic display of content using a first dynamic signal waveform. Figure 11C The pixel display driving signal waveform 201 can be divided into a third voltage waveform 201c and a fourth voltage waveform 201d, wherein the third voltage waveform 201c is later than the second voltage waveform 201b and earlier than the fourth voltage waveform 201d in timing. The third voltage waveform 201c represents the state in which the driving circuit unit 20 controls the first pixel electrode to perform a second dynamic display of content using a second dynamic signal waveform, and the fourth voltage waveform 201d represents the state in which the driving circuit unit 20 controls the first pixel electrode to perform a third dynamic display of content using a third dynamic signal waveform. Thus, it can be seen that after the driving circuit unit 20 resets (clears the display content), the driving circuit unit 20 sequentially uses the first dynamic signal waveform, the second dynamic signal waveform, and the third dynamic signal waveform to control the first pixel electrode to display content.

[0096] In particular, in this example, and with regard to the second voltage waveform 201b, the first display duration Td1 corresponds to the portion of the second voltage waveform 201b that is at the first voltage V1, the second display duration Td2 corresponds to the portion of the second voltage waveform 201b that is at the second voltage V2, the third display duration Td3 corresponds to the portion of the second voltage waveform 201b that is at the first voltage V1, the fourth display duration Td4 corresponds to the portion of the second voltage waveform 201b that is at the fourth voltage V4, the fifth display duration Td5 corresponds to the portion of the second voltage waveform 201b that is at the fifth voltage V5, and the sixth display duration Td6 corresponds to the portion of the second voltage waveform 201b that is at the fourth voltage V4.

[0097] The pixel display driving signal waveform 201 output by the driving circuit unit 20 to the first pixel electrode and the pixel display driving signal waveform 202 output to the second pixel electrode will vary depending on the different colors and chroma to be modulated by the panel unit 30.

[0098] Additionally, taking a multi-stable display driven by a Full HD resolution driver as an example, its resolution is 1920×1080. When transmitting at a single data rate (SDR), the data of one pixel electrode is transmitted per clock cycle, meaning the number of pixels transmitted per clock cycle is 1. Furthermore, the transmission time (T) for each frame is set. line The time is 5 milliseconds (ms).

[0099] The clock rate for driving the multistable display in this dynamic display is calculated using the following formula:

[0100]

[0101] The resolution is 1920. The number of pixels transmitted per clock clock is 1 at Single Data Rate (SDR). Transmission time (T) line The value is 5 milliseconds (ms). Substituting the above figures into the formula yields the following Table 3.

[0102]

[0103] Table 3

[0104] As can be seen from the comparison of Tables 1 and 3, the clock rate of the dynamic display driving multistable display of the present invention can be significantly reduced. In this way, the dynamic display driving multistable display can adopt a low-frequency driving scheme, thereby effectively reducing power consumption.

[0105] Furthermore, such as Figure 12As shown, in a fourth embodiment, the timing control circuit unit 10 includes a clock output terminal (clock; clk), a display output enable control terminal (display output enable; doe), a display output ground control terminal (display output ground; dog), a display start pulse control terminal (display start pulse; dsp), and a digital-to-analog conversion control terminal (d2a). The functions of the clock output terminal (clk), the display output enable control terminal (doe), the display output ground control terminal (dog), and the display start pulse control terminal (dsp) of the timing control circuit unit 10 are the same as those of the timing control circuit unit 10 of existing multi-stable displays, and will not be described in detail here.

[0106] The digital-to-analog conversion control terminal (d2a) is connected to the drive circuit unit 20.

[0107] Furthermore, the timing control circuit unit 10 also includes the header setting control terminal (dsh) and the data signal output terminal. In other embodiments, the data signal output terminal of the timing control circuit unit 10 may include multiple data output terminals (data 0 to data n), such as the first to the (n+1)th data output terminals (data 0 to data n). In this embodiment, the first to the third data output terminals (data 0 to data 2) are used as examples, but this is not a limitation.

[0108] In this embodiment, when the data signal 11 is the header holding time data, the digital-to-analog converter control terminal (d2a) outputs a count signal 102 that is an even multiple of the total number of half-working sessions. In this embodiment, when the data signal 11 is the header holding time data, the digital-to-analog converter control terminal (d2a) outputs a count signal 102 that is 4 times the total number of half-working sessions, for example, but this is not a limitation.

[0109] Furthermore, when the data signal 11 displays the duration data, the digital-to-analog conversion control terminal (d2a) outputs a count signal 102 that is an even multiple of the total number of half-working sessions. In this embodiment, when the data signal 11 displays the duration data, the digital-to-analog conversion control terminal (d2a) outputs a count signal 102 that is four times the total number of half-working sessions, but this is not a limitation.

[0110] Furthermore, such as Figure 13As shown, in this embodiment, the pixel clearing header data 113 includes a pixel positive clearing voltage data 1131 and a pixel negative clearing voltage data 1132. The pixel positive clearing voltage data 1131 includes a first pixel positive clearing voltage value 1131a and a second pixel positive clearing voltage value 1131b, and the pixel negative clearing voltage data 1132 includes a first pixel negative clearing voltage value 1132a and a second pixel negative clearing voltage value 1132b. In this embodiment, the timing control circuit unit 10 includes the first to third data output terminals (data 0 to data 2), and the first pixel positive clearing voltage value 1131a is the first value of the first to third data output terminals (data 0 to data 2), and the first pixel positive clearing voltage value 1131a is represented by a 3-bit data, namely V1(0) to V1(2), corresponding to a first voltage V1, for example 001. The second pixel positive clear voltage value 1131b is the second value of the first to third data output terminals (data 0 to data 2), and it is also represented by a 3-bit data, corresponding to the first voltage V1, for example, 001. Similarly, the first pixel negative clear voltage value 1132a is the third value of the first to third data output terminals (data 0 to data 2), and it is represented by a 3-bit data, namely V4(0) to V4(2), corresponding to a fourth voltage V4, for example, 100. The second pixel negative clear voltage value 1132b is the fourth value of the first to third data output terminals (data 0 to data 2), and it is also represented by a 3-bit data, corresponding to the fourth voltage V4, for example, 100.

[0111] The pixel clearing waveform data 114 includes multiple pixel electrode clearing data 1141 to 114n. The pixel electrode clearing data 1141 to 114n includes at least one first pixel electrode clearing data 1141, and the first pixel electrode clearing data 1141 includes a first clearing voltage unit number. In this embodiment, the first clearing voltage unit number is two values ​​from the first to third data output terminals (data 0 to data 2), and the first clearing voltage unit number is represented by a 3-bit data format, i.e., pixel 1(0) to pixel 1(2), corresponding to the first pixel electrode. For example, the first clearing voltage unit number of the first pixel electrode clearing data 1141 is 110. Furthermore, the pixel electrode clearing data 1141 to 114n may also include second to nth pixel electrode clearing data 1142 to 114n, and the second to nth pixel electrode clearing data 1142 to 114n each include a second to nth clearing voltage unit number. Similarly, the second clear voltage unit number is the value of the first to third data output terminals (data 0 to data 2), and the second clear voltage unit number is represented by a 3-bit data, namely pixel 2(0) to pixel 2(2). For example, the second clear voltage unit number of the second pixel electrode clear data 1142 is 110.

[0112] Furthermore, when the driving circuit unit 20 determines the pixel clearing drive duration for outputting the pixel clearing drive signal with the pixel clearing voltage value based on the total number of half-working units and the pixel clearing waveform data 114, the driving circuit unit 20 outputs the pixel clearing drive signal with the first positive pixel clearing voltage value to the first pixel electrode between the first to the "number of first clearing voltage units" count signals output from the digital-to-analog conversion control terminal (d2a). The driving circuit unit 20 outputs the pixel clearing drive signal with the second positive pixel clearing voltage value to the first pixel electrode between the "number of first clearing voltage units + 1" to the "number of first clearing voltage units + total number of half-working units" count signals output from the digital-to-analog conversion control terminal (d2a). The driving circuit unit 20 outputs a pixel clearing drive signal with the positive clearing voltage value of the first pixel to the first pixel electrode between the count signals output from the digital-to-analog conversion control terminal (d2a) of "the first clearing voltage unit number + the total number of half-working units + 1" and "twice the total number of half-working units". Furthermore, the driving circuit unit 20 outputs a pixel clearing drive signal with the negative clearing voltage value of the first pixel to the first pixel electrode between the count signals output from the digital-to-analog conversion control terminal (d2a) of "twice the total number of half-working units + 1" and "twice the total number of half-working units + the first clearing voltage unit number". The driving circuit unit 20 outputs a pixel clearing drive signal with the negative clearing voltage value of the second pixel to the first pixel electrode between the count signals output from the digital-to-analog conversion control terminal (d2a) of "twice the total number of half-working units + the number of first clearing voltage units + 1" and "twice the total number of half-working units + the first clearing voltage unit number". The drive circuit unit 20 outputs a pixel clear drive signal with the negative clear voltage value of the first pixel to the first pixel electrode between the number of "three times the total number of half-working units + the number of first clear voltage units + 1" and the number of "four times the total number of half-working units".

[0113] The pixel dynamic display header data 111 sequentially includes a pixel positive display voltage data 1111 and a pixel negative display voltage data 1112. The pixel positive display voltage data 1111 includes a first pixel positive display voltage value 1111a and a second pixel positive display voltage value 1111b, and the pixel negative display voltage data 1112 includes a first pixel negative display voltage value 1112a and a second pixel negative display voltage value 1112b. In this embodiment, the timing control circuit unit 10 includes the first to third data output terminals (data 0 to data 2), and the first pixel positive display voltage value 1111a is the value of the first to third data output terminals (data 0 to data 2), and the first pixel positive display voltage value 1111a is represented by a 3-bit data, namely V2(0) to V2(2), corresponding to a second voltage V2, i.e., 010. The positive display voltage value 1111b of the second pixel is the value of the first to third data output terminals (data 0 to data 2), and the positive display voltage value 1111b of the second pixel is also represented by a 3-bit data form, namely V3(0) to V3(2), corresponding to a third voltage V3, i.e., 011. Similarly, the negative display voltage value 1112a of the first pixel is the value of the first to third data output terminals (data 0 to data 2), and the negative display voltage value 1112a of the first pixel is represented by a 3-bit data form, namely V5(0) to V5(2), corresponding to a fifth voltage V5, i.e., 101. The negative display voltage value of the second pixel is the value of the first to third data output terminals (data 0 to data 2), and the negative display voltage value 1112b of the second pixel is also represented by a 3-bit data form, namely V6(0) to V6(2), corresponding to a sixth voltage V6, i.e., 110.

[0114] The pixel dynamic display waveform data 112 includes multiple pixel electrode display data 1121 to 112n. The pixel electrode display data includes at least one first pixel electrode display data 1121, and the first pixel electrode display data 1121 includes a first display voltage unit number. In this embodiment, the first display voltage unit number is two values ​​from the first to third data output terminals (data 0 to data 2), and the first display voltage unit number is represented by a 3-bit data format, i.e., pixel 1(0) to pixel 1(2), corresponding to the first pixel electrode. For example, the first display voltage unit number of the first pixel electrode display data 1121 is 110. Furthermore, the pixel electrode display data 1121 to 112n may also include second to nth pixel electrode display data 1122 to 112n, and the second to nth pixel electrode display data 1122 to 112n each include a second to nth display voltage unit number. Similarly, the second display voltage unit number is two values ​​of the first to third data output terminals (data 0 to data 2), and the second display voltage unit number is represented by a 3-bit data, namely pixel 2(0) to pixel 2(2), corresponding to the second pixel electrode. For example, the second display voltage unit number of the second pixel electrode displaying data 1122 is 000.

[0115] Furthermore, when the driving circuit unit 20 determines the pixel display driving duration for outputting the pixel display driving signal with the pixel display voltage value based on the total number of half-working units and the pixel dynamic display waveform data 112, the driving circuit unit 20 outputs the pixel display driving signal with the first pixel positive display voltage value to a first pixel electrode between the first to the "first display voltage unit number" count signals output from the digital-to-analog conversion control terminal (d2a). The driving circuit unit 20 outputs the pixel display driving signal with the second pixel positive display voltage value to the first pixel electrode between the "first display voltage unit number + 1" to the "first display voltage unit number + total number of half-working units" count signals output from the digital-to-analog conversion control terminal (d2a). The driving circuit unit 20 outputs a pixel display driving signal with a positive display voltage value for the first pixel to the first pixel electrode between the count signals output from the digital-to-analog conversion control terminal (d2a) of "the first display voltage unit number + the total number of half-working units + 1" and "twice the total number of half-working units". Furthermore, the driving circuit unit 20 outputs a pixel display driving signal with a negative display voltage value for the first pixel to the first pixel electrode between the count signals output from the digital-to-analog conversion control terminal (d2a) of "twice the total number of half-working units + 1" and "twice the total number of half-working units + the first display voltage unit number". The driving circuit unit 20 outputs a pixel display driving signal with a negative display voltage value for the second pixel to the first pixel electrode between the count signals output from the digital-to-analog conversion control terminal (d2a) of "twice the total number of half-working units + the first display voltage unit number + 1" and "three times the total number of half-working units + the first display voltage unit number". The drive circuit unit 20 outputs a pixel display drive signal with the negative display voltage value of the first pixel to the first pixel electrode between the count signals of "three times the total number of half-working units + the number of first display voltage units + 1" to "four times the total number of half-working units" at the digital-to-analog conversion control terminal (d2a).

[0116] For example, the total number of half-work units is an integer of 6. As shown in the first pixel electrode clearing data 1141, the first clearing voltage unit number is 110. As shown in the second pixel electrode clearing data 1142, the second clearing voltage unit number is 110. As shown in the first pixel positive clearing voltage value 1131a, the first pixel positive clearing voltage value is the first voltage V1, i.e., 001. As shown in the second pixel positive clearing voltage value 1131b, the second pixel positive clearing voltage value is the first voltage V1, i.e., 001. As shown in the first pixel negative clearing voltage value 1132a, the first pixel negative clearing voltage value is the fourth voltage V4, i.e., 100. As shown in the second pixel negative clearing voltage value 1132b, the second pixel negative clearing voltage value is the fourth voltage V4, i.e., 100. As shown in the first pixel electrode display data 1121, the first display voltage unit number is 110. As shown in the second pixel electrode display data 1122, the second display voltage unit number is 000. As shown by the positive display voltage value 1111a of the first pixel, the positive display voltage value of the first pixel is the second voltage V2, i.e., 010. As shown by the positive display voltage value 1111b of the second pixel, the positive display voltage value of the second pixel is the third voltage V3, i.e., 011. As shown by the negative display voltage value 1112a of the first pixel, the negative display voltage value of the first pixel is the fifth voltage V5, i.e., 101. As shown by the negative display voltage value 1112b of the second pixel, the negative display voltage value of the second pixel is the sixth voltage V6, i.e., 110.

[0117] Please refer to the following: Figures 14A to 14C As shown, according to the bit value lookup table, since the first clear voltage unit number is 110, the first clear duration of the pixel clear drive signal with the first pixel positive clear voltage value, i.e., the first voltage V1, output by the driving circuit unit 20 to the first pixel electrode is 6 working hours (duty). Therefore, the driving circuit unit 20 outputs the pixel clear drive signal with the first pixel positive clear voltage value, i.e., the first voltage V1, to the first pixel electrode between the first to sixth count signals 102 output by the digital-to-analog conversion control terminal (d2a). Further, the driving circuit unit 20 outputs the pixel clear drive signal with the second pixel positive clear voltage value to the first pixel electrode between the count signals from "the first clear voltage unit number + 1" to "twice the half-working total" output by the digital-to-analog conversion control terminal (d2a).

[0118] Next, the driving circuit unit 20 enters the negative half-cycle. Between the output of the counting signals 102 ("twice the total number of half-cycles + 1") from the digital-to-analog conversion control terminal (d2a) and the output of the counting signals 102 ("twice the total number of half-cycles + the number of first clear voltage units"), the driving circuit unit 20 outputs a pixel clearing drive signal with the first pixel negative clear voltage value, i.e., the fourth voltage V4, to the first pixel electrode. Further, between the output of the counting signals 102 ("twice the total number of half-cycles + the number of first clear voltage units + 1") from the digital-to-analog conversion control terminal (d2a) and the output of the counting signals 102 ("four times the total number of half-cycles"), the driving circuit unit 20 outputs a pixel clearing drive signal with the second pixel negative clear voltage value to the first pixel electrode.

[0119] The generation method of the pixel clearing drive signal output by the drive circuit unit 20 to the second pixel electrode is the same as that output by the drive circuit unit 20 to the first pixel electrode, and will not be described again here.

[0120] Since the first display voltage unit number is 110, the first display duration of the pixel display drive signal with the first pixel positive display voltage value, i.e., the second voltage V2, output by the driving circuit unit 20 to the first pixel electrode is 6 working hours. Therefore, the driving circuit unit 20 outputs the pixel display drive signal with the first pixel positive display voltage value, i.e., the second voltage V2, to the first pixel electrode between the 1st and 6th count signals 102 output from the digital-to-analog conversion control terminal (d2a). Next, the driving circuit unit 20 outputs the pixel display drive signal with the second pixel positive display voltage value, i.e., the third voltage V3, to the first pixel electrode between the 7th and 12th count signals output from the digital-to-analog conversion control terminal (d2a). Furthermore, since the first display voltage unit number is 110 and the first display voltage unit number is 6, the driving circuit unit 20 should output a pixel display driving signal with the positive display voltage value of the first pixel to the first pixel electrode between the count signals 102 of "the first display voltage unit number + the half-working total number + 1" and "twice the half-working total number". In other words, the driving circuit unit 20 should output a pixel display driving signal with the positive display voltage value of the first pixel, i.e., the second voltage V2, to the first pixel electrode between the 13th and 12th count signals 102. However, since there is no interval of the 13th to 12th count signals 102, when the first display voltage unit number is 110, the driving circuit unit 20 no longer outputs a pixel display driving signal with the positive display voltage value of the first pixel, i.e., the second voltage V2, to the first pixel electrode.

[0121] Next, the driving circuit unit 20 enters the negative half-cycle. Between the 13th and 18th count signals 102 output from the digital-to-analog conversion control terminal (d2a), the driving circuit unit 20 outputs a pixel display driving signal with the negative display voltage value of the first pixel, i.e., the fifth voltage V5, to the first pixel electrode. Then, between the 19th and 24th count signals 102 output from the digital-to-analog conversion control terminal (d2a), the driving circuit unit 20 outputs a pixel display driving signal with the negative display voltage value of the second pixel, i.e., the sixth voltage V6, to the first pixel electrode. Since the first display voltage unit number is 110, according to logic similar to the aforementioned, the driving circuit unit 20 no longer outputs a pixel display driving signal with the negative display voltage value of the first pixel, i.e., the fifth voltage V5, to the first pixel electrode.

[0122] Similarly, since the second display voltage unit number is 000, the driving circuit unit 20 should output a pixel display driving signal with the positive display voltage value of the first pixel, i.e., the second voltage V2, to the second pixel electrode between the first and 0th count signals 102. However, since there is no interval of the first to 0th count signals 102, when the second display voltage unit number is 000, the driving circuit unit 20 does not output a pixel display driving signal with the positive display voltage value of the first pixel, i.e., the second voltage V2, to the second pixel electrode. Next, the driving circuit unit 20 outputs a pixel display driving signal with the positive display voltage value of the second pixel, i.e., the third voltage V3, to the second pixel electrode between the first and 6th count signals 102 at the digital-to-analog conversion control terminal (d2a). Furthermore, the driving circuit unit 20 outputs a pixel display driving signal with the positive display voltage value of the first pixel, i.e., the second voltage V2, between the 7th and 12th count signals output from the digital-to-analog conversion control terminal (d2a) to the first pixel electrode.

[0123] When the driving circuit unit 20 enters the negative half-cycle, since the second display voltage unit number is 000, according to logic similar to the above, the driving circuit unit 20 does not output the pixel display driving signal with the negative display voltage value of the first pixel, i.e., the fifth voltage V5, to the second pixel electrode. Next, the driving circuit unit 20 outputs the pixel display driving signal with the negative display voltage value of the second pixel, i.e., the sixth voltage V6, to the second pixel electrode between the 13th and 18th count signals 102 output from the digital-to-analog conversion control terminal (d2a). Furthermore, the driving circuit unit 20 outputs the pixel display driving signal with the negative display voltage value of the first pixel (i.e., the fifth voltage V5) to the second pixel electrode between the 19th and 24th count signals 102 output from the digital-to-analog conversion control terminal (d2a).

[0124] like Figure 14A and Figure 14B As shown, Figure 14A This is a waveform diagram of the pixel display drive signal waveform 201 output by the drive circuit unit 20 to the first pixel electrode. Figure 14B This is a waveform diagram of the pixel display drive signal waveform 202 output by the drive circuit unit 20 to the second pixel.

[0125] For example, consider a multistable display driven by a Full HD resolution driver, with a resolution of 1920×1080. When transmitting at a single data rate (SDR), one pixel of data is transmitted per clock cycle, meaning the number of pixels transmitted per clock cycle is 1. Furthermore, the transmission time (T) for each frame of data is set. line The time is 5 milliseconds (ms).

[0126] The clock rate for driving the multistable display in this dynamic display is calculated using the following formula:

[0127]

[0128] The resolution is 1920. The number of pixels transmitted per clock clock is 1 at Single Data Rate (SDR). Transmission time (T) line The value is 5 milliseconds (ms). Substituting the above figures into the formula yields the following Table 3.

[0129]

[0130] Table 4

[0131] As can be seen from the comparison of Tables 1 and 4, the clock rate of the dynamic display driving multistable display of the present invention can be significantly reduced. In this way, the dynamic display driving multistable display can adopt a low-frequency driving scheme, thereby effectively reducing power consumption.

[0132] In summary, since the clock rate is independent of the duty count, the dynamic display driver multistable display of this invention can achieve the same transmission time (T) within the same transmission time. line Under the conditions of, for example, T line =5ms, the clock rate can be significantly reduced to the kilohertz (kHz) level. In other words, this dynamic display driver for multistable displays can use a low-frequency driving scheme, thereby effectively reducing power consumption.

[0133] Furthermore, the dynamic display driver multistable display of the present invention only needs to transmit data once to complete the transmission of the voltage waveform of a frame. The voltage configuration of multiple working intervals (duties) within a frame can be directly determined based on the pixel dynamic display header data 111 and the pixel dynamic display waveform data 112, without the need to transmit different voltage configurations for each working interval (duty) within a frame for switching. Therefore, for the display start signal control terminal (DSP), the display start signal control terminal (DSP) only needs to output one cycle for each frame, without needing to output one cycle for each working interval (duty), thereby significantly reducing the number of switching times of the output signal of the display start signal control terminal (DSP), and thus reducing dynamic power consumption.

[0134] Furthermore, since the counting signal 102 output by the digital-to-analog conversion control terminal (d2a) is used for counting, the data signal output terminal can continuously transmit data during the holding time of the counting signal 102 output by the digital-to-analog conversion control terminal (d2a), without affecting the digital-to-analog conversion, and thus preventing the generation of data bubbles. In other words, during the holding time of the counting signal 102 output by the digital-to-analog conversion control terminal (d2a), the data signal output terminal (data 0) can continuously transmit data without interrupting the transmission to avoid the generation of data bubbles, thereby further improving transmission efficiency.

[0135] Furthermore, since the counting signal 102 output by the digital-to-analog conversion control terminal (d2a) of the dynamic display driving multistable display of the present invention is used for counting, the waveform data of the first frame needs to be transmitted before the rising edge of the first counting signal 102. During the counting period of the second to nth counting signals 102, the waveform data of the next frame can be transmitted, and the transmission can be completed before the rising edge of the (n+1)th counting signal 102. For example, assuming that the voltage waveform of a frame has 4 working intervals, the data signal output terminal needs to transmit the waveform data of the first frame before the rising edge of the first counting signal 102. During the counting period of the second to fourth counting signals 102, the waveform data of the second frame can be transmitted, and the transmission can be completed before the rising edge of the fifth counting signal 102. This allows for a buffer time between two consecutive frames of waveform data, eliminating the need for tightly continuous transmission and providing greater design flexibility.

[0136] Furthermore, in existing multistable displays, the signal output from the digital-to-analog conversion control terminal (d2a) is used for digital-to-analog conversion. Therefore, in each working interval (duty) of a frame, the digital-to-analog conversion control terminal (d2a) needs to output one cycle of signal. Only after the digital-to-analog conversion control terminal (d2a) outputs one cycle of signal will the data signal output terminal output the waveform data for the next working interval (duty), until the waveform data for the last working interval (duty) is output. More specifically, after the waveform data for the last working interval (duty) of the last frame (frame) is output, the digital-to-analog conversion control terminal (d2a) needs to output another cycle of signal. After the digital-to-analog conversion control terminal (d2a) outputs the last cycle of signal, the data signal output terminal no longer needs to output waveform data. In other words, the data signal output terminal of existing multistable displays only stops outputting waveform data after the signal output of the last digital-to-analog conversion control terminal (d2a).

[0137] However, the counting signal 102 output by the digital-to-analog conversion control terminal (d2a) of the dynamic display driving multistable display of the present invention is for counting purposes. The data signal output terminal only needs to complete the transmission of waveform data before the rising edge of the first counting signal 102. Therefore, after the waveform data of the last frame is output, the data signal output terminal does not need to output the waveform data. That is to say, after the waveform data of the last frame is output, the data signal output terminal does not need to output the waveform data during the period of the counting signal 102 output by the digital-to-analog conversion control terminal (d2a). For example, assuming that the voltage waveform of the last frame has 4 working intervals, the data signal output terminal only needs to complete the transmission of the waveform data of the last frame before the rising edge of the first counting signal 102, and during the counting period of the 1st to 4th counting signals 102 of the last frame, the data signal output terminal does not need to transmit waveform data again.

[0138] Furthermore, as described in the above embodiments, the driving circuit unit 20 determines the pixel display driving voltage value of the pixel display driving signal output to the panel unit 30 based on the pixel dynamic display header data 111, and determines the pixel display driving duration of the pixel display driving signal with the pixel display voltage value based on the half-working total and the pixel dynamic display waveform data 112. Moreover, when the driving circuit unit 20 determines the pixel display driving duration of the pixel display driving signal with the pixel display voltage value based on the half-working total and the pixel dynamic display waveform data 112, the driving circuit unit 20 determines the number of display voltage units based on the waveform data 11b, and then determines the first display duration of the first pixel positive display voltage value based on the number of display voltage units. The driving circuit unit 20 also uses the half-working total as the second display duration of the second pixel positive display voltage value. Further, by subtracting the number of display voltage units from the half-working total, a third display duration of the first pixel positive display voltage value is determined. By applying the logic of the positive half-cycle to the negative half-cycle, the driving circuit unit 20 can determine the fourth display duration for outputting the negative display voltage value of the first pixel, the fifth display duration for outputting the negative display voltage value of the second pixel, and the sixth display duration for outputting the negative display voltage value of the first pixel. In other words, the pixel dynamic display waveform data 112 corresponds to the holding time of each voltage value. When the driving circuit unit 20 receives the pixel dynamic display waveform data 112, it calculates the number of the counting signals 102 output by the digital-to-analog converter control terminal (d2a) based on the pixel dynamic display waveform data 112, thereby calculating the pixel display driving duration of the pixel display driving signal with the pixel display voltage value. Therefore, the driving circuit unit 20 only needs the pixel dynamic display waveform data 112 to determine the entire waveform of the pixel display driving signal for each pixel, thereby significantly reducing the amount of data that needs to be transmitted.

[0139] Furthermore, since the timing control circuit unit 10 only outputs a signal to drive the drive circuit unit 20 to output the line drive signal after the pixel clear header data and the pixel clear waveform data have been output, the timing control circuit unit 10 does not need to provide data during the period when the drive circuit unit 20 outputs the pixel positive clear voltage and the pixel negative clear voltage.

[0140] Please see Figure 15As shown, the timing control circuit unit 10 also includes a scan output terminal. In other embodiments, the scan output terminal of the timing control circuit unit 10 may include multiple scan output terminals (scan 0 to scan n), such as the first to the (n+1)th scan output terminals (scan 0 to scan n). In this embodiment, the first to third data output terminals (scan 0 to scan 2) are used as examples, but this is not a limitation.

[0141] Please see Figures 16A to 16C As shown, the timing control signal includes a scan signal 21, and the scan signal 21 sequentially includes a line dynamic display header data 211 and a line dynamic display waveform data 212. The drive circuit unit 20 determines a line drive voltage value of a line drive signal output to the panel unit 30 based on the line dynamic display header data 211, and the drive circuit unit 20 determines the signal waveform of the line drive signal output to the panel unit 30 based on the line drive voltage value and the line dynamic display waveform data 212.

[0142] For example, please refer to Figure 17A and Figure 17B As shown, the line dynamic display header data 211 includes at least one line positive display voltage data 2111 and one line negative display voltage data 2112, but is not limited thereto. In this embodiment, the timing control circuit unit 10 includes the first to third scan output terminals (scan 0 to scan 2), and the first line positive display voltage data 2111 includes a first line positive display voltage value 2111a and a second line positive display voltage value 2111b, and the first line positive display voltage value 2111a is the value of the first to third scan output terminals (scan 0 to scan 2), i.e., V6(0) to V(2), corresponding to the sixth voltage V6, for example. Figure 19 As shown, the first line is displaying a voltage value of 110 for 2111a. Similarly, the second line is displaying voltage values ​​of 2111bV2(0)~V2(2), corresponding to the second voltage V2, for example... Figure 19 As shown, the positive voltage value 2111b of the second line is 010. The negative voltage data 2112 of the first line includes a negative voltage value 2112a and a negative voltage value 2112b. The negative voltage values ​​2112aV3(0)~V3(2) of the first line correspond to the third voltage V3, for example... Figure 19 As shown, the first line negative display voltage value 2112a is 011. And the second line negative display voltage value 2112b is V5(0)~V5(2), corresponding to the fifth voltage V5, for example... Figure 19 As shown, the negative display voltage value 2112b of the second line is 101.

[0143] Please see Figure 18A and Figure 18B As shown, the scan display waveform data 212 includes multiple line electrode display data 2121 to 212m. The line electrode display data includes at least one first line electrode display data 2121, which contains the type of line drive signal waveform for the first line electrode, while the second line electrode display data 2122 contains the type of line drive signal waveform for the second line electrode. In this embodiment, the first line electrode display data is a combination of values ​​from the first to third scan output terminals (scan0 to scan2), for example... Figure 19 As shown, the data displayed by the first line electrode 2121 is 111. The data displayed by the second line electrode is also a combination of the values ​​from the first to third scan output terminals (scan 0 to scan 2), for example... Figure 19 As shown, the second line electrode displays data 2122 as 000.

[0144] Please see again Figures 20A to 20C As shown, the driving circuit unit 20 determines the waveform of the line drive signal 2001 output to the first line electrode based on the first line electrode display data 2121. For example, if the first line electrode display data 2121 is 111, the driving circuit unit 20 determines that the waveform of the line drive signal 2001 output to the first line electrode is to first output the second voltage V2, then output the fifth voltage V5, and the output duration of the second voltage V2 and the output duration of the fifth voltage V5 are in a 1:1 ratio. For example, the waveform of the line drive signal 2001 output by the driving circuit unit 20 to the first line electrode... Figure 20A As shown, the drive circuit unit 20 outputs a line drive signal with the second voltage V2 to the first line electrode between the first to sixth count signals 102 output from the digital-to-analog conversion control terminal (d2a), and outputs a line drive signal with the fifth voltage V5 to the first line electrode between the seventh to twelfth count signals 102 output from the digital-to-analog conversion control terminal (d2a).

[0145] Furthermore, the driving circuit unit 20 determines the waveform of the line drive signal 2002 output to the second line electrode based on the second line electrode display data 2122. For example, if the second line electrode display data 2122 is 000, the driving circuit unit 20 determines that the waveform of the line drive signal 2002 output to the second line electrode is to first output the fourth voltage V4, then output the first voltage V1, and the output duration ratio of the fourth voltage V4 and the first voltage V1 is 1:1. For instance, the waveform of the line drive signal 2002 output by the driving circuit unit 20 to the second line electrode... Figure 20B As shown, the drive circuit unit 20 outputs a line drive signal with the fourth voltage V4 to the second line electrode between the first to sixth count signals 102 output from the digital-to-analog conversion control terminal (d2a), and outputs a line drive signal with the first voltage V1 to the second line electrode between the seventh to twelfth count signals 102 output from the digital-to-analog conversion control terminal (d2a).

[0146] In one embodiment, the waveform of the line drive signal 2001 output by the drive circuit unit 20 to the first line electrode and the waveform of the line drive signal 2002 output to the second line electrode have a timing delay. For example, the aforementioned 4 times the total number of half-work sessions represents the duration of one work session. The waveform of the line drive signal 2001 output by the drive circuit unit 20 to the first line electrode spans multiple work sessions and presents the following waveform sequence: a reset waveform, a first A waveform, a second A waveform, a first B waveform, a first C waveform, a second C waveform, a third C waveform, and at least one blank waveform. The reset waveform, the first A waveform, the second A waveform, the first B waveform, the first C waveform, the second C waveform, the third C waveform, and the blank waveform each occupy one work session. Furthermore, the waveform of the line drive signal 2001 output by the drive circuit unit 20 to the first line electrode and the waveform of the line drive signal 2002 output to the second line electrode can have a delay of one operating time. For example, when the waveform of the line drive signal 2001 output by the drive circuit unit 20 to the first line electrode is in the form of the second A waveform, the waveform of the line drive signal 2002 output by the drive circuit unit 20 to the second line electrode is in the form of the first A waveform. And when the waveform of the line drive signal 2001 output by the drive circuit unit 20 to the first line electrode is in the form of the first B waveform, the waveform of the line drive signal 2002 output by the drive circuit unit 20 to the second line electrode is in the form of the second A waveform, and so on.

[0147] Furthermore, according to this logic, the panel unit 30 may have a first line electrode and an Lth line electrode, where L is a positive integer greater than 1, and the first line electrode and the Lth line electrode are respectively electrically connected to the driving circuit unit 20. When the driving circuit unit 20 has a waveform of an Lth line drive signal output to the Lth line electrode, where L is a positive integer greater than 1, the waveform of the line drive signal 2001 output by the driving circuit unit 20 to the first line electrode and the waveform of the Lth line drive signal output to the Lth line electrode may have a delay of (L-1) working time. When all line electrodes have completed displaying the at least one blank waveform, that is, after the time delay, when the waveform of the line drive signal 2001 of the first line electrode and the waveform of the Lth line drive signal of the Lth line electrode are both driven by the driving circuit unit 20 to display the at least one blank waveform, then the driving circuit unit 20 has completed updating all line electrodes of the panel unit 30, and thus completed updating one frame of the panel unit 30.

[0148] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical display to create equivalent embodiments without departing from the scope of the technical solution of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the display of the technical solution of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A dynamic display driver for a multistable display, characterized in that, Includes: A timing control circuit unit generates a timing control signal; A driving circuit unit is connected to the timing control circuit unit and receives the timing control signal; A panel unit is connected to the drive circuit unit; The timing control signal includes a data signal, and the data signal includes one pixel of dynamic display header data and one pixel of dynamic display waveform data. The driving circuit unit determines the pixel display voltage value of the pixel display driving signal output to the panel unit based on the pixel dynamic display header data. The driving circuit unit has a half-working total, and the driving circuit unit determines the one-pixel display driving duration of the pixel display driving signal with the pixel display voltage value based on the half-working total and the pixel dynamic display waveform data.

2. The dynamic display driving multistable display as described in claim 1, characterized in that, The data signal also includes one pixel of header clearing data; The driving circuit unit determines the pixel clearing driving signal to be output to the panel unit based on the pixel clearing header data.

3. The dynamic display driving multistable display as described in claim 1, characterized in that, The data signal also includes one pixel clear header data and one pixel clear waveform data; The driving circuit unit determines the pixel clearing voltage value of the pixel clearing driving signal output to the panel unit based on the pixel clearing header data, and the driving circuit unit determines the pixel clearing driving duration of the pixel clearing driving signal with the pixel clearing voltage value based on the pixel clearing waveform data.

4. The dynamic display driving multistable display as described in claim 1, characterized in that, This timing control circuit unit includes: A header setting control terminal is connected to the drive circuit unit, and outputs a header setting signal to the drive circuit unit. A data signal output terminal is connected to the drive circuit unit, and outputs the data signal to the drive circuit unit. Specifically, when the data signal output by the data signal output terminal is the dynamic display header data of the pixel, the header setting signal output by the header setting control terminal is the high voltage level.

5. The dynamic display driving multistable display as described in claim 3, characterized in that, The pixel clearing header data contains one pixel positive clearing voltage data and one pixel negative clearing voltage data; The positive clear voltage data of the pixel includes a first positive clear voltage value and a second positive clear voltage value, and the negative clear voltage data of the pixel includes a first negative clear voltage value and a second negative clear voltage value. The pixel clearing waveform data packet contains multiple pixel electrode clearing data. The pixel electrode clearing data includes at least a first pixel electrode clearing data, and the first pixel electrode clearing data includes a first clearing voltage unit number; Wherein, the first number of clear voltage units and the total number of half-working units are both even numbers, and the drive circuit unit determines a first number of remaining clear voltage units by subtracting the first number of clear voltage units from double the total number of half-working units. Specifically, when the driving circuit unit determines the pixel clearing drive duration for outputting the pixel clearing drive signal with the pixel clearing voltage value based on the half-working total and the pixel clearing waveform data, the driving circuit unit determines a first clearing duration for the pixel clearing drive signal output to a first pixel electrode and having the first pixel positive clearing voltage value based on the first clearing voltage units of the pixel clearing waveform data; the driving circuit unit determines a second clearing duration for the pixel clearing drive signal output to the first pixel electrode and having the second pixel positive clearing voltage value based on the first remaining clearing voltage units; and the driving circuit unit determines a third clearing duration for the pixel clearing drive signal output to the first pixel electrode and having the first pixel negative clearing voltage value based on the first clearing voltage units of the pixel clearing waveform data; and the driving circuit unit determines a fourth clearing duration for the pixel clearing drive signal output to the first pixel electrode and having the second pixel negative clearing voltage value based on the first remaining clearing voltage units.

6. The dynamic display driving multistable display as described in any one of claims 1 to 4, characterized in that, The pixel dynamic display header data includes one pixel of positive display voltage data and one pixel of negative display voltage data; The positive display voltage data of the pixel includes a first positive display voltage value of the pixel and a second positive display voltage value of the pixel, and the negative display voltage data of the pixel includes a first negative display voltage value of the pixel and a second negative display voltage value of the pixel. The pixel dynamic display waveform data packet contains multiple pixel electrode display data. The pixel electrode display data includes at least one first pixel electrode display data, and the first pixel electrode display data includes a first display voltage unit number; Wherein, the first display voltage unit number and the half-working total number are both even numbers, and the driving circuit unit subtracts the first display voltage unit number from the half-working total number to determine a first remaining display voltage unit number; Specifically, when the driving circuit unit determines the pixel display driving duration for outputting the pixel display driving signal with the pixel display voltage value based on the half-working total and the pixel dynamic display waveform data, the driving circuit unit determines a first display duration for the pixel display driving signal output to a first pixel electrode and having the first pixel positive display voltage value based on the first display voltage units of the pixel dynamic display waveform data; the driving circuit unit determines a second display duration for the pixel display driving signal output to the first pixel electrode and having the second pixel positive display voltage value based on the half-working total; and the driving circuit unit determines a second display duration for the pixel display driving signal output to the first pixel electrode and having the second pixel positive display voltage value based on the first remaining display voltage units. The driving circuit unit determines a third display duration for the pixel display driving signal with the positive display voltage value of the first pixel, based on the first display voltage units of the pixel dynamic display waveform data, a fourth display duration for the pixel display driving signal output to the first pixel electrode with the negative display voltage value of the first pixel, a fifth display duration for the pixel display driving signal output to the first pixel electrode with the negative display voltage value of the second pixel, based on the half-working total, and a sixth display duration for the pixel display driving signal output to the first pixel electrode with the negative display voltage value of the first pixel, based on the first remaining display voltage units.

7. The dynamic display driving multistable display as described in claim 3, characterized in that, The timing control circuit unit also includes: A digital-to-analog conversion control terminal is connected to the drive circuit unit, outputs a conversion control signal to the drive circuit unit, and the conversion control signal contains multiple counting signals; The pixel clearing header data includes one pixel positive clearing voltage data and one pixel negative clearing voltage data; The positive clear voltage data of the pixel includes a first positive clear voltage value and a second positive clear voltage value, and the negative clear voltage data of the pixel includes a first negative clear voltage value and a second negative clear voltage value. The pixel clearing waveform data packet contains multiple pixel electrode clearing data. The pixel electrode clearing data includes at least one first pixel electrode clearing data, which includes a first clearing voltage unit number, and the first clearing voltage unit number and the half-working total number are both even numbers; Specifically, when the driving circuit unit determines the pixel clearing drive duration for outputting the pixel clearing drive signal with the pixel clearing voltage value based on the half-working total and the pixel clearing waveform data, the driving circuit unit outputs a pixel clearing drive signal with the first pixel positive clearing voltage value to a first pixel electrode between the first to Ath count signals output from the digital-to-analog conversion control terminal; the driving circuit unit outputs a pixel clearing drive signal with the second pixel positive clearing voltage value to the first pixel electrode between the (A+1)th to (A+B)th count signals output from the digital-to-analog conversion control terminal; and the driving circuit unit outputs a pixel clearing drive signal with the first pixel positive clearing voltage value between the (A+B+1)th to (2B)th count signals output from the digital-to-analog conversion control terminal. The driving circuit unit outputs a pixel clearing drive signal with the positive clearing voltage value to the first pixel electrode between the 2B+1th and 2B+Ath count signals output from the digital-to-analog conversion control terminal, and outputs a pixel clearing drive signal with the negative clearing voltage value of the first pixel to the first pixel electrode between the 2B+A+1th and 3B+Ath count signals output from the digital-to-analog conversion control terminal, and outputs a pixel clearing drive signal with the negative clearing voltage value of the second pixel to the first pixel electrode between the 3B+A+1th and 4Bth count signals output from the digital-to-analog conversion control terminal. Where A is the number of units of the first clear voltage and B is the total number of half-working units.

8. The dynamic display driving multistable display as described in any one of claims 1 to 4, characterized in that, The timing control circuit unit also includes: A digital-to-analog conversion control terminal is connected to the drive circuit unit, outputs a conversion control signal to the drive circuit unit, and the conversion control signal contains multiple counting signals; The pixel dynamic display header data includes one pixel positive display voltage data and one pixel negative display voltage data; The positive display voltage data of the pixel includes a first positive display voltage value of the pixel and a second positive display voltage value of the pixel, and the negative display voltage data of the pixel includes a first negative display voltage value of the pixel and a second negative display voltage value of the pixel. The pixel dynamic display waveform data packet contains multiple pixel electrode display data. The pixel electrode display data includes at least one first pixel electrode display data, which includes a first display voltage unit number, and the first display voltage unit number and the half-working total number are both even numbers; Specifically, when the driving circuit unit determines the pixel display driving duration for outputting the pixel display driving signal with the pixel display voltage value based on the half-working total and the pixel dynamic display waveform data, the driving circuit unit outputs the pixel display driving signal with the first pixel positive display voltage value to a first pixel electrode between the first to Dth count signals output from the digital-to-analog conversion control terminal; the driving circuit unit outputs the pixel display driving signal with the second pixel positive display voltage value to the first pixel electrode between the (D+1)th to (D+B)th count signals output from the digital-to-analog conversion control terminal; and the driving circuit unit outputs the pixel display driving signal with the first pixel positive display voltage value between the (D+B+1)th to (2B)th count signals output from the digital-to-analog conversion control terminal. The driving circuit unit outputs a pixel display driving signal with the positive display voltage value of the first pixel to the first pixel electrode between the 2B+1th and 2B+Dth count signals output from the digital-to-analog conversion control terminal; the driving circuit unit outputs a pixel display driving signal with the negative display voltage value of the first pixel to the first pixel electrode between the 2B+D+1th and 3B+Dth count signals output from the digital-to-analog conversion control terminal; and the driving circuit unit outputs a pixel display driving signal with the negative display voltage value of the first pixel to the first pixel electrode between the 3B+D+1th and 4Bth count signals output from the digital-to-analog conversion control terminal. Where B is the total number of half-working units and D is the number of first display voltage units.

9. The dynamic display driving multistable display as described in claim 1, characterized in that, The timing control signal includes a scanning signal, and the scanning signal includes a line dynamic display header data and a line dynamic display waveform data; The driving circuit unit determines a line drive voltage value of a line drive signal output to the panel unit based on the line dynamic display header data, and the driving circuit unit determines a signal waveform of the line drive signal output to the panel unit based on the line drive voltage value and the line dynamic display waveform data.

10. The dynamic display driving multistable display as described in claim 1, characterized in that, The panel unit has a first line electrode and an Lth line electrode, where L is a positive integer greater than 1, and the first line electrode and the Lth line electrode are respectively electrically connected to the drive circuit unit. Here, 4 times the total number of half-work sessions represents the duration of one work session, when there is a delay of (L-1) work sessions between the waveform of a line drive signal output by the drive circuit unit to the first line electrode and the waveform of a line drive signal output to the Lth line electrode.

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