N_bit id output chip and operating method thereof

Abstract

The application relates to the chip technical field, in particular to an N_bit ID output chip and an operation method thereof, which comprises the following steps: an upper power enabling circuit is used for initializing the chip and mode switching, and is connected with an oscillator, a bias circuit and an efuse IP reading excitation generating circuit; a selection circuit is used for dynamically switching the control signals of a middle repair adjustment PAD and the efuse reading excitation generating circuit; the efuse IP reading excitation generating circuit is used for generating multiple control signals to drive the selection circuit; a repair adjustment circuit is used for calibrating eFuse programming current, and is connected with the oscillator and an N bit efuse IP; a pull-down circuit is used for inhibiting the leakage current in the non-gating state, and is connected with an AVDD port of the N bit efuse IP; and an input and output circuit is used for data mode switching and signal stability monitoring, and is connected with a DATA_OUT port and a driving circuit. The application has the beneficial effects that the standby power consumption is very low, the pin multiplexing technology is used to facilitate the timing judgment, the relatively universal efuse IP is used, the design risk and cost are reduced, and the reliability of the chip is increased.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and specifically to an N-bit ID output chip and its operation method. Background Technology

[0002] With the increasing demand for anti-counterfeiting and authentication across various industries, chips for storing IDs are becoming more widely used. These chips are often integrated with products requiring authentication and are typically used in large quantities.

[0003] In existing technologies, some chips that store IDs reduce ports but increase antennas, leading to increased costs. Others have built-in encryption protocols or switching circuits, which increase the chip's standby power consumption and complexity. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this application proposes an N_bit ID output chip and its operation method, which features very low standby power consumption, utilizes pin multiplexing technology for easy timing determination, and employs the widely applicable efuse IP, thereby reducing design risks and costs and increasing the reliability of the chip.

[0005] The following is the technical solution of the present invention: an N_bit ID output chip, comprising:

[0006] The power-on enable circuit is used to initialize the chip and switch modes, and connects to the oscillator, bias circuit and efuse IP read excitation generation circuit.

[0007] The selection circuit is used to dynamically switch the control signals of the test and repair adjustment PAD and the efuse read excitation generation circuit. It is connected to the N-bit efuse IP through the CS port, READ port, PGM port, and SCLK port.

[0008] The efuse IP read excitation generation circuit is used to generate multiple control signals to drive the selection circuit. It is connected to the selection circuit through the CS2 port, READ2 port, PGM2 port, and SCLK2 port.

[0009] The adjustment circuit is used to calibrate the eFuse programming current and connects the oscillator and the N-bit eFuse IP.

[0010] A pull-down circuit is used to suppress leakage current in the non-selected state and is connected to the AVDD port of the N-bit efuse IP.

[0011] The input / output circuit is used for data mode switching and signal stability monitoring, and connects the DATA_OUT port and the driver circuit.

[0012] As a preferred embodiment of the present invention, the efuse IP read excitation generation circuit includes:

[0013] The first frequency divider receives the oscillator clock signal and outputs the divided signal to the D flip-flop and the fourth logic module;

[0014] A D flip-flop with a clear function outputs an enable signal to the first logic module at its Q input.

[0015] The second frequency divider works in conjunction with the first logic module to generate timing control signals;

[0016] The fourth logic module integrates the outputs of the first frequency divider and the second logic module to generate CS2 / READ2 / PGM2 / SCLK2 control signals.

[0017] As a preferred embodiment of the present invention, the method by which the selection circuit implements signal switching includes:

[0018] In test mode, receive the CS1 / READ1 / PGM1 / SCLK1 signals from the test and adjustment PAD;

[0019] In normal operating mode, switch to the CS2 / READ2 / PGM2 / SCLK2 signal of the efuse read excitation generation circuit;

[0020] The switching logic is controlled by the status signal of the power-on enable circuit.

[0021] As a preferred embodiment of the present invention, the adjustment circuit includes:

[0022] The current calibration module dynamically adjusts the eFuse programmed current threshold according to the oscillator frequency;

[0023] The overcurrent protection module monitors the programmed current in real time and limits its amplitude;

[0024] The feedback compensation unit connects to the DOUT port of the N-bit efuse IP to optimize calibration parameters.

[0025] As a preferred embodiment of the present invention, the pull-down circuit includes:

[0026] At least one NMOS transistor whose drain is connected to the AVDD port of an N-bit efuse IP;

[0027] The control logic module, in the non-selected state, turns on the NMOS transistor to ground the AVDD port;

[0028] A noise suppression filter is connected in parallel between the source of the NMOS transistor and ground.

[0029] As a preferred embodiment of the present invention, the operating modes of the input / output circuit include:

[0030] In the first operating mode, an ID square wave is automatically output after power-on, with a duration of 2 seconds. N One clock cycle;

[0031] In the second working mode, after receiving the activation signal, the ID square wave is output again, and the output timing is kept in phase synchronization with the activation signal.

[0032] The third operating mode continuously monitors the signal integrity of the DATA_OUT port in input mode.

[0033] An operation method for an N_bit ID output chip includes the following steps:

[0034] S1. The power-on enable circuit triggers the oscillator to generate a global clock and adjusts the circuit to calibrate the eFuse programming current to a preset threshold.

[0035] S2. CS2 / READ2 / PGM2 / SCLK2 control signals are generated by cascading frequency dividers, and the selection circuit switches the control signal source according to the working mode.

[0036] S3. When performing eFuse fuse programming, an external high-voltage signal is used, and the refresh judgment circuit triggers the DOUT signal output to the DATA_OUT port;

[0037] S4. Perform CRC check and logic state comparison on the read eFuse data, and adjust the programming current parameters when an anomaly is detected.

[0038] As a preferred embodiment of the present invention, S1 includes:

[0039] The bias circuit voltage stabilizes within 1ms after power-on;

[0040] Establish the initial phase relationship of the frequency divider within 50μs;

[0041] Initial noise at the AVDD port is eliminated within 100ns using a pull-down circuit.

[0042] As a preferred embodiment of the present invention, S3 includes:

[0043] A multi-pulse verification mechanism is used during the programming operation, and the fuse status is read after each programming pulse;

[0044] The burning process is confirmed when the status is consistent after three consecutive reads.

[0045] If no agreement is reached, the programming current is increased and the program is reprogrammed.

[0046] As a preferred embodiment of the present invention, S4 includes:

[0047] Establish a mapping table between fuse states and logic levels;

[0048] The actual output waveform is compared with the expected waveform by feedback from the drive circuit.

[0049] When the error exceeds 5%, the adjustment circuit is triggered to restart the calibration process.

[0050] The beneficial effects of this invention are:

[0051] 1. In this invention, the oscillator and bias circuit are normally open and consume very low power, while other modules are digital circuits with very low standby power consumption.

[0052] 2. In this invention, pin multiplexing technology is used so that the data output port can also be used as an input port, which facilitates timing determination;

[0053] 3. In this invention, the widely applicable efuse IP is used, which reduces design risks and costs and increases the reliability of the chip. Attached Figure Description

[0054] Figure 1 This is a schematic diagram of the chip of the present invention;

[0055] Figure 2 This is a schematic diagram of the efuse IP read excitation generation circuit of the chip of the present invention;

[0056] Figure 3 This is a flowchart of the operation method of the chip of the present invention;

[0057] In the diagram: 100, Chip; 101, Power-on Enable Circuit; 102, Bias Circuit; 103, Oscillator; 104, Adjustment Circuit; 105, Input / Output Circuit; 106, Refresh Judgment Circuit; 107, Efuse IP Read Excitation Generation Circuit; 108, Mid-Test Adjustment PAD; 109, Selection Circuit; 110, N-bit Efuse IP; 111, Pull-down Circuit; 112, Driver Circuit; 114, GND Port; 115, VDD Port; 116, DATA_OUT Port; 201, First Frequency Divider; 202, TIE H; 203, D Flip-Flop; 204, First Logic Module; 205, Second Logic Module; 206, Second Frequency Divider; 207, Third Logic Module; 208, Fourth Logic Module. Detailed Implementation

[0058] To make the technical problems solved by the present invention, the technical solutions adopted, and the technical effects achieved clearer, the technical solutions of the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] Example 1:

[0060] like Figure 1 As shown, an N_bit ID output chip includes: VDD port 115, GND port 114, and DATA_OUT port 116;

[0061] Among them, VDD port 115 is the power supply terminal of chip 100, which provides the power required for chip 100 to work;

[0062] GND port 114 is the ground terminal of chip 100, providing ground for chip 100 to operate;

[0063] DATA_OUT port 116 is the input / output terminal of chip 100. It defaults to input mode. After chip 100 is powered on, DATA_OUT port 116 will automatically output a series of square waves containing ID information. After outputting, DATA_OUT port 116 will switch back to input mode. When an activation signal is received, such as a pulse width signal or timing signal that meets the requirements, DATA_OUT port 116 will switch from input to output mode again, outputting a series of square waves containing ID information in a specific timing sequence with the activation signal.

[0064] The core modules of chip 100 include: power-on enable circuit 101, bias circuit 102, oscillator 103, adjustment circuit 104, mid-test adjustment PAD 108, N-bit efuse IP 110, pull-down circuit 111, selection circuit 109, efuse IP read excitation generation circuit 107, refresh judgment circuit 106, input / output circuit 105, and drive circuit 112.

[0065] Among them, the power-on enable circuit 101 is used for chip 100 initialization and mode switching, and is connected to oscillator 103, bias circuit 102 and efuse IP read excitation generation circuit 107.

[0066] The oscillator 103 is connected to the tuning circuit 104, the power-on enable circuit 101, the bias circuit 102, and the efuse IP read excitation generation circuit 107.

[0067] Adjustment circuit 104 is used to calibrate the eFuse programming current;

[0068] The input / output circuit 105 is connected to the DATA_OUT port 116, the refresh judgment circuit 106, and the drive circuit 112.

[0069] The intermediate test and repair PAD108 is connected through CS1 port, READ1 port, PGM1 port, SCLK1 port and selection circuit 109. The AVDD port 115 in the intermediate test and repair PAD108 is connected to N bit efuse IP110 and pull-down circuit 111.

[0070] Pull-down circuit 111 is used to eliminate signal noise in the unselected state;

[0071] The efuse IP read excitation generation circuit 107 generates multiple control signals (CS2 / READ2 / PGM2 / SCLK2) through a frequency divider cascade, and connects to the selection circuit 109 through the CS2 port, READ2 port, PGM2 port, and SCLK2 port.

[0072] Select circuit 109 dynamically switches the control signal between the test and adjustment PAD 108 and the eFuse read excitation generation circuit, and realizes multi-source signal selection through the port. It is connected to N bit eFuseIP 110 through CS port, READ port, PGM port and SCLK port;

[0073] The N-bit efuse IP110 output terminal DOUT port is connected to the driver circuit 112.

[0074] The signal switching methods implemented by the selection circuit 109 include: receiving the CS1 / READ1 / PGM1 / SCLK1 signals from the test and adjustment PAD 108 in test mode; switching to the CS2 / READ2 / PGM2 / SCLK2 signals from the efuse read excitation generation circuit in normal operation mode; and controlling the switching logic through the status signal of the power-on enable circuit 101.

[0075] The tuning circuit 104 includes: a current calibration module that dynamically adjusts the eFuse programming current threshold according to the frequency of the oscillator 103; an overcurrent protection module that monitors the programming current in real time and limits its amplitude; and a feedback compensation unit that connects to the DOUT port of the N-bit eFuse IP110 to optimize calibration parameters.

[0076] The pull-down circuit 111 includes: at least one NMOS transistor whose drain is connected to the AVDD port 115 of the N-bit efuse IP110; a control logic module that turns on the NMOS transistor to ground the AVDD port 115 in the non-selected state; and a noise suppression filter connected in parallel between the source of the NMOS transistor and ground.

[0077] The input / output circuit 105 has the following operating modes: First operating mode: After power-on, it automatically outputs an ID square wave with a duration of 2 seconds. NThe first operating mode is the first clock cycle; the second operating mode is the second operating mode, which outputs an ID square wave again after receiving the activation signal, and the output timing is kept in phase synchronization with the activation signal; the third operating mode is the third operating mode, which continuously monitors the signal integrity of the DATA_OUT port 116 under the input state.

[0078] like Figure 2 As shown, the efuse IP read excitation generation circuit 107 includes: a first frequency divider 201, a second frequency divider 206, a TIE H 202, a D flip-flop 203 with a clear function, a first logic module 204, a second logic module 205, a third logic module 207, and a fourth logic module 208.

[0079] The first frequency divider 201 is connected to the clock terminals of the power-on enable circuit 101, the oscillator 103, the fourth logic module 208, and the D flip-flop 203.

[0080] TIE H202 is connected to the D terminal of D flip-flop 203;

[0081] The reset terminal of the D flip-flop 203 is connected to the power-on enable circuit 101, and the Q terminal of the D flip-flop 203 is connected to the first logic module 204.

[0082] The first logic module 204 is connected to the first frequency divider 201 and the second frequency divider 206;

[0083] The second logic module 205 is connected to the second frequency divider 206, the third logic module 207 and the fourth logic module 208;

[0084] The second frequency divider 206 is connected to the second logic module 205, the fourth logic module 208, the third logic module 207 and the first logic module 204;

[0085] The fourth logic module 208 is connected to the first frequency divider 201, the first logic module 204, and the second logic module 205. The fourth logic module 208 outputs signals, including CS2, READ2, PGM2, and SCLK2.

[0086] In the eFuse read excitation generation circuit, the first frequency divider 201 receives the clock signal from the oscillator 103 and outputs a divided signal to the D flip-flop 203, the first logic module 204, and the fourth logic module 208; the Q terminal of the D flip-flop 203 outputs an enable signal to the first logic module 204, which works with the second frequency divider 206 to generate timing control signals; the fourth logic module 208 integrates the outputs of the first frequency divider 201 and the second logic module 205 to generate CS2, READ2, PGM2, and SCLK2 signals to drive the selection circuit 109.

[0087] The fourth logic module 208 integrates the outputs of the first frequency divider 201 and the second logic module 205 to generate CS2 / READ2 / PGM2 / SCLK2 control signals.

[0088] The adjustment PAD108 provides external test signals to the selection circuit 109 via CS1 / READ1 / PGM1 / SCLK1. The selection circuit 109 switches to the eFuse read excitation signal (CS2 / READ2 / PGM2 / SCLK2) based on the state of the power-on enable circuit 101 to reduce external interference. The adjustment circuit 104 adjusts the eFuse programming current according to the oscillator 103 frequency. In the non-selected state, the pull-down circuit 111 grounds the AVDD port 115 of the N-bit eFuse IP to suppress leakage current.

[0089] Example 2

[0090] like Figure 3 As shown, an operation method for an N_bit ID output chip includes the following steps:

[0091] S1. Initialization and clock configuration;

[0092] The power-on enable circuit 101 receives the power signal, triggers the oscillator 103 to generate a global clock reference, and initializes the voltage parameters of the bias circuit 102.

[0093] The tuning circuit 104 calibrates the programming current threshold of the N-bit eFuse IP according to the frequency of the oscillator 103 to ensure current stability;

[0094] S2. Multi-source signal generation and selection;

[0095] The eFuse read excitation generation circuit divides the clock of oscillator 103 by the first frequency divider 201 and the second frequency divider 206 to generate timing control signals (CS2 / READ2 / PGM2 / SCLK2).

[0096] Selection circuit 109 dynamically switches the signal source according to the state of power-on enable circuit 101:

[0097] CS1 / READ1 / PGM1 / SCLK1 signals can be received via the PAD108 of the test and adjustment system, or CS2 / READ2 / PGM2 / SCLK2 signals can be generated by the eFuse read excitation circuit.

[0098] S3, dynamic programming and data manipulation;

[0099] The external high-voltage signal is input to the N-bit eFuse IP via the selection circuit 109 to perform the fuse programming operation.

[0100] The adjustment circuit 104 monitors the programming current in real time to prevent overcurrent from damaging the fuse;

[0101] The refresh judgment circuit 106 triggers the N-bit eFuse IP to output the DOUT signal, which is transmitted to the DATA_OUT port 116 of the input / output circuit 105 through the driver circuit 112;

[0102] In the non-selected state, pull-down circuit 111 grounds the AVDD port 115 of the N-bit eFuse IP to suppress leakage current;

[0103] S4, Data Validation and Refresh;

[0104] The input / output circuit 105 transmits the read eFuse data to the refresh judgment circuit 106 for CRC verification and logic state comparison.

[0105] If an abnormal data is detected, such as a fuse not blowing or a logic error, the programming current is adjusted by adjusting circuit 104.

[0106] S5. Noise suppression and state maintenance;

[0107] In signal switching or inactive mode, pull-down circuit 111 grounds the unselected N-bit eFuse IP port to eliminate signal noise;

[0108] The input / output circuit 105 continuously monitors the stability of the DATA_OUT port 116 to ensure that the data is transmitted without distortion.

[0109] S1 includes: stabilizing the voltage of the bias circuit 102 within 1ms after power-on; establishing the initial phase relationship of the frequency divider within 50μs; and eliminating the initial noise of the AVDD port 115 within 100ns through the pull-down circuit 111.

[0110] S3 includes: a multi-pulse verification mechanism during the programming operation, reading the fuse status after each programming pulse; confirming programming completion when the status is consistent after three consecutive reads; increasing the programming current and reprogramming when no consistency is achieved.

[0111] S4 includes: establishing a mapping table between fuse status and logic level; comparing the actual output waveform with the expected waveform through the driver circuit 112; and triggering the trimming circuit 104 to restart the calibration process when the error exceeds 5%.

[0112] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Clearly, those skilled in the art can make various alterations and variations to the invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of equivalents of the invention, the invention is also intended to include these modifications and variations.

Claims

1. An N-bit ID output chip, characterized in that, include: The power-on enable circuit is used to initialize the chip and switch modes, and connects to the oscillator, bias circuit and efuse IP read excitation generation circuit. The selection circuit is used to dynamically switch the control signals of the test and repair adjustment PAD and the efuse read excitation generation circuit. It is connected to the N-bit efuse IP through the CS port, READ port, PGM port, and SCLK port. The efuse IP read excitation generation circuit is used to generate multiple control signals to drive the selection circuit. It is connected to the selection circuit through the CS2 port, READ2 port, PGM2 port, and SCLK2 port. The adjustment circuit is used to calibrate the eFuse programming current and connects the oscillator and the N-bit eFuse IP. The pull-down circuit is used to suppress leakage current in the non-selected state and is connected to the AVDD port of the N-bit efuse IP; the input / output circuit is used for data mode switching and signal stability monitoring and is connected to the DATA_OUT port and the driver circuit.

2. The N-bit ID output chip according to claim 1, characterized in that, The efuse IP read excitation generation circuit includes: The first frequency divider receives the oscillator clock signal and outputs the divided signal to the D flip-flop and the fourth logic module; the D flip-flop with a clear function outputs an enable signal to the first logic module at its Q terminal. The second frequency divider works in conjunction with the first logic module to generate timing control signals; The fourth logic module integrates the outputs of the first frequency divider and the second logic module to generate CS2 / READ2 / PGM2 / SCLK2 control signals.

3. The N-bit ID output chip according to claim 1, characterized in that, The methods by which selection circuits achieve signal switching include: In test mode, receive the CS1 / READ1 / PGM1 / SCLK1 signals from the test and adjustment PAD; In normal operating mode, switch to the CS2 / READ2 / PGM2 / SCLK2 signal of the efuse read excitation generation circuit; The switching logic is controlled by the status signal of the power-on enable circuit.

4. An N-bit ID output chip according to claim 1, characterized in that, The adjustment circuit includes: The current calibration module dynamically adjusts the eFuse programmed current threshold according to the oscillator frequency; The overcurrent protection module monitors the programmed current in real time and limits its amplitude. The feedback compensation unit connects to the DOUT port of the N-bit efuse IP to optimize calibration parameters.

5. An N-bit ID output chip according to claim 1, characterized in that, The pull-down circuit includes: At least one NMOS transistor whose drain is connected to the AVDD port of an N-bit efuse IP; The control logic module, in the non-selected state, turns on the NMOS transistor to ground the AVDD port; A noise suppression filter is connected in parallel between the source of the NMOS transistor and ground.

6. An N-bit ID output chip according to claim 1, characterized in that, The operating modes of the input / output circuit include: In the first operating mode, an ID square wave is automatically output after power-on, with a duration of 2 seconds. N One clock cycle; In the second working mode, after receiving the activation signal, the ID square wave is output again, and the output timing is kept in phase synchronization with the activation signal. The third operating mode continuously monitors the signal integrity of the DATA_OUT port in input mode.

7. An operation method for an N_bit ID output chip, applicable to the N_bit ID output chip according to any one of claims 1-6, characterized in that, Includes the following steps: S1. The power-on enable circuit triggers the oscillator to generate a global clock, and the circuit calibrates the eFuse programming current to a preset threshold. S2. CS2 / READ2 / PGM2 / SCLK2 control signals are generated by cascading frequency dividers, and the selection circuit switches the control signal source according to the working mode. S3. When performing eFuse fuse programming, an external high-voltage signal is used, and the refresh judgment circuit triggers the DOUT signal output to the DATA_OUT port; S4. Perform CRC check and logic state comparison on the read eFuse data, and adjust the programming current parameters when an anomaly is detected.

8. The operation method of an N_bit ID output chip according to claim 7, characterized in that, S1 includes: The bias circuit voltage stabilizes within 1ms after power-on; Establish the initial phase relationship of the frequency divider within 50μs; Initial noise at the AVDD port is eliminated within 100ns using a pull-down circuit.

9. The operation method of an N_bit ID output chip according to claim 7, characterized in that, S3 include: A multi-pulse verification mechanism is used during the programming operation, and the fuse status is read after each programming pulse; The burning process is confirmed to be complete when the status is consistent after three consecutive reads. If no agreement is reached, the programming current is increased and the program is reprogrammed.

10. The operation method of an N_bitID ​​output chip according to claim 7, characterized in that, S4 include: Establish a mapping table between fuse states and logic levels; The actual output waveform is compared with the expected waveform by feedback from the drive circuit. When the error exceeds 5%, the adjustment circuit is triggered to restart the calibration process.

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