Memory structure, memory device and operating method thereof

Abstract

A memory structure, a memory device and an operating method thereof are provided. The memory device includes a plurality of memory cells. The memory cells include a first memory cell. The first memory cell includes a first transistor and a first charge trap transistor. The first transistor is coupled to a first storage node and is configured to transmit a first write bit line signal to the first storage node according to a first write word line signal. The first charge trap transistor is configured to generate a first current signal according to a threshold voltage level of the first charge trap transistor and a voltage level of the first storage node.

Description

Technical Field

[0001] This invention relates to a memory technology, and more particularly to a memory structure, a memory device, and a method of operating the memory device. Background Technology

[0002] In machine learning, memory can be used for both training and inference operations. For training purposes, memory needs virtually unlimited tolerance to accommodate the large number of weight updates in training datasets. For inference purposes, memory needs non-volatility and good retention to keep weights constant with low power consumption. However, to date, there is no general-purpose memory suitable for both training and inference. Therefore, solving these problems is an important issue in this field. Summary of the Invention

[0003] This invention includes a memory device. The memory device includes a plurality of memory cells. Each memory cell includes a first memory cell. The first memory cell includes a first transistor and a first charge-well transistor. The first transistor is coupled to a first storage node and is used to transmit a first write bit line signal to the first storage node according to a first write word line signal. The first charge-well transistor is used to generate a first current signal based on a threshold voltage level of the first charge-well transistor and a voltage level of the first storage node.

[0004] In some embodiments, when the voltage level of the first write word line signal is greater than the threshold voltage level of the first transistor, the first transistor is turned on to perform a write operation, and when the voltage level of the first write word line signal is less than the threshold voltage level of the first transistor, the first transistor is turned off to perform a read operation or maintain the logic state of the first memory cell.

[0005] In some embodiments, a first terminal of the first charge trap transistor is used to receive a first read word line signal, and a second terminal of the first charge trap transistor is used to receive a first read bit line signal. When the first memory cell is in a logic state, the voltage level of the first read word line signal is equal to the voltage level of the first read bit line signal, and when the first memory cell performs a read operation, the voltage level of the first read word line signal is different from the voltage level of the first read bit line signal.

[0006] In some embodiments, when a first logic value is written to a first memory cell, the voltage level of the first write bit line signal is equal to the voltage level of the first write word line signal; when a second logic value is written to the first memory cell, the voltage level of the first write bit line signal is different from the voltage level of the first write word line signal, and the first logic value is different from the second logic value.

[0007] In some embodiments, the memory cell further includes a second memory cell, the second memory cell including: a second transistor coupled to a second storage node and configured to transmit a second write bit line signal to the second storage node according to a first write word line signal; and a second charge trap transistor configured to generate a second current signal, wherein the first memory cell and the second memory cell are further configured to add the first current signal and the second current signal together.

[0008] In some embodiments, the memory device further includes: a first semiconductor structure extending in a first direction; a second semiconductor structure extending in the first direction and separated from the first semiconductor structure in a second direction; and a first gate structure extending in the second direction and surrounding each of the first semiconductor structure and the second semiconductor structure, wherein the first gate structure and the first semiconductor structure are configured to operate as a first transistor, and the first gate structure and the second semiconductor structure are configured to operate as a second transistor.

[0009] In some embodiments, the memory device further includes: a third semiconductor structure coupled to the first semiconductor structure and having a first length in a first direction; and a fourth semiconductor structure coupled to the second semiconductor structure, having a second length greater than the first length in the first direction and isolated from the third semiconductor structure in a second direction, wherein the third semiconductor structure and the fourth semiconductor structure are respectively used to transmit a first write bit line signal and a second write bit line signal.

[0010] In some embodiments, the memory cell further includes a second memory cell, the second memory cell including: a second transistor coupled to a second storage node and configured to transmit a first write bit line signal to the second storage node according to a second write word line signal; and a second charge trap transistor configured to generate a second current signal, wherein the first memory cell and the second memory cell are further configured to add the first current signal and the second current signal together.

[0011] In some embodiments, the memory device further includes: a first semiconductor structure extending in a first direction; a second semiconductor structure extending in the first direction and separated from the first semiconductor structure in a second direction; a first gate structure extending upward in a third direction and surrounding the first semiconductor structure; and a second gate structure extending upward in a third direction, surrounding the second semiconductor structure and separated from the first gate structure in the second direction, wherein the first gate structure and the first semiconductor structure are configured to operate as a first transistor, and the second gate structure and the second semiconductor structure are configured to operate as a second transistor.

[0012] In some embodiments, the memory device further includes: a conductive structure extending in a second direction for transmitting a first write bit line signal to each of the first semiconductor structure and the second semiconductor structure.

[0013] This invention includes a memory structure. The memory structure includes a source structure, a drain structure, a first gate structure, a first semiconductor structure, and a second gate structure. The source structure extends in a first direction. The drain structure extends in the first direction and is separate from the source structure. The first gate structure surrounds each of the source and drain structures and is configured to operate with the source and drain structures as a first charge trap transistor. The first semiconductor structure extends in a second direction and is coupled to the first gate structure. The second gate structure is separate from the first gate structure in the second direction, surrounds the first semiconductor structure, and is configured to operate with the first semiconductor structure as a first transistor.

[0014] In some embodiments, the memory structure further includes: a third gate structure surrounding each of the source structure and the drain structure and configured to operate with the source structure and the drain structure as a second charge trap transistor; and a second semiconductor structure extending in a second direction, separated from the first semiconductor structure in a first direction, and coupled to the third gate structure.

[0015] In some embodiments, the second gate structure further surrounds the second semiconductor structure and is used to operate with the second semiconductor structure as a second transistor, and the drain terminal of the second transistor is coupled to the gate terminal of the second charge trap transistor.

[0016] In some embodiments, the memory structure further includes: a third semiconductor structure coupled to the first semiconductor structure and having a first length in a second direction; and a fourth semiconductor structure coupled to the second semiconductor structure and having a second length in a second direction, wherein the first length is less than the second length.

[0017] In some embodiments, the memory structure further includes: a first oxide structure having a third length in a second direction; and a second oxide structure having a first length in the second direction and used to isolate the third semiconductor structure and the fourth semiconductor structure from each other, wherein the first oxide structure, the third semiconductor structure, the second oxide structure and the fourth semiconductor structure are arranged sequentially in the first direction.

[0018] In some embodiments, the memory structure further includes: a fourth gate structure, separated from the second gate structure in a first direction, surrounding the second semiconductor structure, and configured to operate with the second semiconductor structure as a second transistor, wherein each of the second gate structure and the fourth gate structure extends upward in a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other.

[0019] In some embodiments, the memory structure further includes: a conductive structure extending in a first direction for transmitting a write bit line signal to each of the first semiconductor structure and the second semiconductor structure.

[0020] This invention includes an operating method for a memory device. The operating method includes: writing a first input bit into a first storage node; storing a first weighted bit through a first charge trap transistor coupled to the first storage node; and generating a first current signal flowing through the first charge trap transistor based on the first input bit and the first weighted bit.

[0021] In some embodiments, the operation method further includes: turning on a first transistor via a write word line signal to transmit a first write bit line signal to a first storage node; and turning on a second transistor via a write word line signal to transmit a second write bit line signal to a second storage node, wherein the second storage node is different from the first storage node.

[0022] In some embodiments, the operation method further includes: turning on a first transistor via a first write word line signal to transmit a write bit line signal to a first storage node; and turning on a second transistor via a second write word line signal to transmit a write bit line signal to a second storage node, wherein the second storage node is different from the first storage node. Attached Figure Description

[0023] Figure 1 This is a schematic diagram illustrating a portion of a memory device according to some embodiments of the present invention.

[0024] Figure 2A This is a schematic diagram illustrating a portion of a memory device according to some embodiments of the present invention.

[0025] Figure 2B This is a 3D schematic diagram of a portion of a memory structure illustrated according to some embodiments of the present invention.

[0026] Figure 2C A cross-sectional schematic diagram illustrating further details of a memory structure according to some embodiments of the present invention.

[0027] Figure 3A This is a 3D schematic diagram of a portion of a memory structure illustrated according to some embodiments of the present invention.

[0028] Figure 3B A cross-sectional schematic diagram illustrating further details of a memory structure according to some embodiments of the present invention.

[0029] Figure 4A Illustrations based on some embodiments of the present invention Figure 1 The diagram shows a write operation performed on a memory cell.

[0030] Figure 4B Illustrations based on some embodiments of the present invention Figure 1 The diagram shows a write operation performed on a memory cell.

[0031] Figure 5A Illustrations based on some embodiments of the present invention Figure 1 The diagram shows a read operation performed on a memory cell.

[0032] Figure 5B Illustrations based on some embodiments of the present invention Figure 1 The diagram shows a write operation performed on a memory cell.

[0033] Figure 6A This is a schematic diagram illustrating the relationship between the write word line signal and the current level corresponding to the write transistor, according to some embodiments of the present invention.

[0034] Figure 6B This is a schematic diagram illustrating the relationship between the voltage level of a storage node and the current level corresponding to the read transistor, according to some embodiments of the present invention.

[0035] Figure 7A This is a schematic diagram of a memory device according to some embodiments of the present invention.

[0036] Figure 7B Illustrations based on some embodiments of the present invention Figure 7A The table shows the voltage levels of the signals of the memory device under various conditions.

[0037] Explanation of reference numerals in the attached figures:

[0038] 100, 200A, 700A: Memory devices

[0039] MC1~MCN: Memory Units

[0040] TR1~TRN: Transistors

[0041] CT1~CTN: Charge trap transistors

[0042] WBL, WBL1~WBLN: Write bit line signals

[0043] SN1~SNN: Storage nodes

[0044] WWL, WWL1~WWLN: Write word line signals

[0045] RWL, RWL1~RWLN: Read word line signals

[0046] RBL, RBL1~RBLN: Read bit line signals

[0047] IR1~IRN: Current signals

[0048] IT1: Total Current Signal

[0049] VREAD: Read voltage level

[0050] 200B, 300A: Memory Structure

[0051] SS1: Source structure

[0052] DS1: Drain structure

[0053] IS1: Isolation Structure

[0054] CS1: Channel Structure

[0055] GOX1, GOX2: Gate Oxidation Structure

[0056] GS1~GS3, GS31, GS32: Gate structure

[0057] OX1~OX4: Oxidation Structure

[0058] SI1~SI4: Semiconductor Structure

[0059] SP1, SP2: Source portion

[0060] DP1, DP2: Drain section

[0061] X, Y, Z: Direction

[0062] LX1~LX3: Length

[0063] MS1: Conductive structure

[0064] VT1: Threshold voltage level

[0065] VWWL1, HVWBL, LVWBL, HVSN, LVSN, HVWWL, LVWWL: Voltage Levels

[0066] ILD0, ILD1: Current Levels

[0067] ISNS: Sensing Current Level

[0068] MC1_1~MCN_M: Memory units

[0069] TR1_1, TR1_2, TR2_1, TR2_2: Transistors

[0070] CT1_1, CT1_2, CT2_1, CT2_2: Charge trap transistors

[0071] SN1_1, SN1_2, SN2_1, SN2_2: Storage nodes

[0072] 700B: Form Detailed Implementation

[0073] In this document, when an element is referred to as a "connection" or "coupled," it may mean an "electrical connection" or "electrical coupling." "Connection" or "coupled" can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as "first," "second," etc., are used herein to describe different elements, these terms are merely used to distinguish elements or operations described using the same technical terms. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply any order or sequence, nor are they intended to limit the invention.

[0074] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0075] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms, including "at least one." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms "comprising" and / or "including" specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0076] The following describes several embodiments of the present invention with reference to the accompanying drawings. For clarity, many practical details will be described in conjunction with the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity, some known and conventional structures and elements will be shown in the drawings in a simple schematic manner.

[0077] Figure 1 This is a schematic diagram of a portion of a memory device 100 according to some embodiments of the present invention. In some embodiments, the memory device 100 may be implemented in three dimensions (3D) and as an array to perform multiply-accumulate (MAC) operations.

[0078] In some embodiments, the memory device 100 may include a plurality of memory cells, such as Figure 1The memory cells MC1 to MCN shown are used to store weight bits WB1 to WBN, respectively, in some embodiments.

[0079] like Figure 1 As shown, memory cell MC1 includes transistor TR1 and charge-well transistor CT1. Memory cell MC2 includes transistor TR2 and charge-well transistor CT2. Memory cell MC3 includes transistor TR3 and charge-well transistor CT3, and so on. Memory cell MCN includes transistor TRN and charge-well transistor CTN. In some embodiments, charge-well transistors CT1~CTN can trap charge to have various threshold voltage levels.

[0080] In some embodiments, one end of transistor TR1 is used to receive the write bit line signal WBL1, the other end of transistor TR1 is coupled to storage node SN1, and the control terminal of transistor TR1 is used to receive the write word line signal WWL1. One end of charge trap transistor CT1 is used to receive the read word line signal RWL1, the other end of charge trap transistor CT1 is used to receive the read bit line signal RBL1, and the control terminal of charge trap transistor CT1 is coupled to storage node SN1.

[0081] Similarly, one end of transistor TR2 receives the write bit line signal WBL2, and the other end of transistor TR2 is coupled to storage node SN2. The control terminal of transistor TR2 receives the write word line signal WWL2. One end of charge trap transistor CT2 receives the read word line signal RWL1, and the other end of charge trap transistor CT2 receives the read bit line signal RBL1. The control terminal of charge trap transistor CT2 is coupled to storage node SN2, and so on. One end of transistor TRN receives the write bit line signal WBLN, and the other end of transistor TRN is coupled to storage node SNN. The control terminal of transistor TRN receives the write word line signal WWLN. One end of charge trap transistor CTN receives the read word line signal RWL1, and the other end of charge trap transistor CTN receives the read bit line signal RBL1. The control terminal of charge trap transistor CTN is coupled to storage node SNN.

[0082] In some embodiments, transistors TR1-TRN are used for write operations and are therefore referred to as write transistors. Charge trap transistors CT1-CTN are used for read operations and are therefore referred to as read transistors. In some embodiments, write bit line signals WBL1-WBLN are used to carry input bits IB1-IBN respectively. Transistors TR1-TRN are used to write input bits IB1-IBN to storage nodes SN1-SNN.

[0083] During a read operation, the read bit line signal RBL1 has a ground voltage level, and the read word line signal RWL1 has a read voltage level VREAD that is greater than the ground voltage level, causing the charge trap transistors CT1-CTN to generate current signals IR1-IRN respectively. These current signals IR1-IRN flow through the charge trap transistors CT1-CTN. Then, the memory device 100 sums the current signals IR1-IRN to generate a total current signal IT1. In other words, the current level of the total current signal IT1 is equal to the sum of the current levels of the current signals IR1-IRN.

[0084] In some embodiments, the current levels of current signals IR1~IRN are determined by the logic states of charge trap transistors CT1~CTN, respectively. The logic states of the charge trap transistors can be determined by the threshold voltage level VCT of the charge trap transistors and the voltage level VSN of the storage node.

[0085] Specifically, when the voltage level VSN is greater than the threshold voltage level VCT, the corresponding charge trap transistor is turned on, and the corresponding current signal has a current level HCL. When the voltage level VSN is less than the threshold voltage level VCT, the corresponding charge trap transistor is turned off, and the corresponding current signal has a current level LCL. The current level HCL is greater than the current level LCL.

[0086] For example, when the voltage level VSN1 of storage node SN1 is greater than the threshold voltage level VCT1 of charge trap transistor CT1, charge trap transistor CT1 is turned on, and the current signal IR1 has a current level HCL. When the voltage level VSN1 is less than the threshold voltage level VCT1, charge trap transistor CT1 is turned off, and the current signal IR1 has a current level LCL.

[0087] Similarly, when the voltage level VSN2 of storage node SN2 is greater than the threshold voltage level VCT2 of charge trap transistor CT2, charge trap transistor CT2 is turned on, and the current signal IR2 has a current level HCL. When the voltage level VSN2 is less than the threshold voltage level VCT2, charge trap transistor CT2 is turned off, and the current signal IR2 has a current level LCL, and so on. When the voltage level VSNN of storage node SNN is greater than the threshold voltage level VCTN of charge trap transistor CTN, charge trap transistor CTN is turned on, and the current signal IRN has a current level HCL. When the voltage level VSNN is less than the threshold voltage level VCTN, charge trap transistor CTN is turned off, and the current signal IRN has a current level LCL.

[0088] In some embodiments, charge trap transistors CT1-CTN may have various threshold voltage values ​​to store weight bits WB1-WBN with various logic values, wherein the various threshold voltage values ​​correspond to various conductivities of charge trap transistors CT1-CTN. Storage nodes SN1-SNN may have various voltage values ​​to store input bits IB1-IBN with various logic values.

[0089] In summary, the current level of current signal IR1 corresponds to the product of the logic value of weight bit WB1 and the logic value of input bit IB1. The current level of current signal IR2 corresponds to the product of the logic value of weight bit WB2 and the logic value of input bit IB2, and so on. The current level of current signal IRN corresponds to the product of the logic value of weight bit WBN and the logic value of input bit IBN. The current level of total current signal IT1 corresponds to the sum of the above products. In this way, memory device 100 can perform MAC operations on weight bits WB1~WBN and input bits IB1~IBN.

[0090] In some embodiments, charge trap transistors CT1-CTN can be implemented using thin-film transistors (TFTs). TFTs can be implemented using polysilicon channels or semiconductor oxide channels, such as indium oxide (InO), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), or other materials. In some embodiments, memory cells MC1-MCN can be fabricated using a three-dimensional stackable process.

[0091] In some embodiments, during machine learning training operations, the memory device 100 can operate in Dynamic Random Access Memory (DRAM) mode. The voltage level VSN of the storage node can be charged and discharged in a manner similar to DRAM. The memory device 100 has virtually no tolerance limitations and can be MAC-enabled through a non-destructive read mode.

[0092] In some embodiments, during machine learning inference operations, the memory device 100 can operate in non-volatile memory (NVM) mode. The threshold voltage level VCT of the read transistor is programmable and clearable, and the logic value of the weight bits can be determined by higher and lower threshold voltage levels VCT.

[0093] In some approaches, for training purposes, memory needs to have virtually unlimited tolerance to accommodate the large number of weight updates during training large datasets. For inference purposes, memory needs to be non-volatile and have good retention to keep weights constant with low power consumption. However, the above approaches cannot be applied to both training and inference simultaneously.

[0094] Compared to the above approach, in this embodiment of the invention, the memory device 100 has virtually no limitations in terms of robustness, can perform non-volatile operations, and has good retention. As a result, the memory device 100 performs better when performing machine learning.

[0095] Figure 2A This is a schematic diagram illustrating a portion of a memory device 200A according to some embodiments of the present invention. Please refer to... Figure 2A and Figure 1 Memory device 200A is a variation of memory device 100. The components of memory device 200A follow the same notation as memory device 100. For the sake of brevity, the discussion will focus on the parts of memory device 200A that differ from memory device 100 rather than their similarities.

[0096] Compared to memory device 100, in memory device 200A, each of the control terminals of transistors TR1 to TRN is used to receive the write word line signal WWL1. In other words, transistors TR1 to TRN are simultaneously turned on and simultaneously turned off.

[0097] Figure 2B This is a 3D schematic diagram of a portion of a memory structure 200B according to some embodiments of the present invention. In some embodiments, the memory structure 200B can be manufactured by a stepped etching process or a bit-cost etching process.

[0098] like Figure 2B As shown, the memory structure 200B includes a source structure SS1, a drain structure DS1, an isolation structure IS1, a channel structure CS1, a gate oxide structure GOX1, gate structures GS1~GS3, oxide structures OX1~OX4, and semiconductor structures SI1~SI4.

[0099] In some embodiments, each of the source structure SS1 and the drain structure DS1 is generally cylindrical and extends in the Z direction. An isolation structure IS1 is located between the source structure SS1 and the drain structure DS1, and is used to isolate the source structure SS1 and the drain structure DS1 from each other. In the XY plane, the channel structure CS1 surrounds the isolation structure IS1, the source structure SS1, and the drain structure DS1, the gate oxide structure GOX1 surrounds the channel structure CS1, and each of the gate structures GS1~GS2 and the oxide structures OX1~OX2 surrounds the gate oxide structure GOX1. In some embodiments, the X, Y, and Z directions are perpendicular to each other. In other words, the Z direction is perpendicular to the XY plane.

[0100] like Figure 2BAs shown, each of the gate structures GS1~GS2 and oxide structures OX1~OX2 extends in the XY plane. In the Z direction, oxide structure OX1, gate structure GS1, oxide structure OX2, and gate structure GS2 are arranged sequentially. Oxide structure OX2 is used to isolate gate structures GS1 and GS2 from each other.

[0101] Semiconductor structures SI1 and SI2 extend in the X direction and are separated from each other in the Z direction. Gate structure GS3 extends in the Z direction and surrounds each of semiconductor structures SI1 and SI2 in the ZY plane. Semiconductor structure SI1 includes a source portion SP1 and a drain portion DP1. Semiconductor structure SI2 includes a source portion SP2 and a drain portion DP2. In the X direction, source portions SP1 and SP2 are located on one side of gate structure GS3, and drain portions DP1 and DP2 are located on the other side of gate structure GS3. In the X direction, gate structure GS3 is separated from each of gate structures GS1 and GS2.

[0102] In some embodiments, drain portions DP1 and DP2 are coupled to gate structures GS1 and GS2, respectively. Source portions SP1 and SP2 are coupled to semiconductor structures SI3 and SI4, respectively.

[0103] In the Z direction, oxide structure OX3, semiconductor structure SI3, oxide structure OX4, and semiconductor structure SI4 are arranged sequentially. Each of semiconductor structures SI3~SI4 and oxide structures OX3~OX4 extends in the XY plane. In some embodiments, oxide structure OX4 is used to isolate semiconductor structures SI3 and SI4 from each other.

[0104] In some embodiments, the semiconductor structures SI3-SI4 and the oxide structures OX3-OX4 may have different lengths in the X direction to form a stepped shape. Specifically, in the X direction, the oxide structure OX3 has a length LX1, each of the oxide structure OX4 and the semiconductor structure SI3 has a length LX2, and the semiconductor structure SI4 has a length LX3. The length LX3 is greater than the length LX2, and the length LX2 is greater than the length LX1. Thus, the memory structure 200B may include conductors that contact the semiconductor structures SI3 and SI4 in the Z direction to transmit corresponding signals to the semiconductor structures SI3 and SI4.

[0105] Please refer to Figure 2A and Figure 2BThe memory device 200A can be implemented using memory structure 200B. Specifically, the source structure SS1 can be implemented as the source terminal of charge trap transistors CT1~CTN and used to receive the read word line signal RWL1. The drain structure DS1 can be implemented as the drain terminal of charge trap transistors CT1~CTN and used to receive the read bit line signal RBL1. In other words, memory structure 200B can add current signals IR1~IRN at the drain structure DS1. The gate structure GS1 can be implemented as the gate terminal of charge trap transistor CT1 and coupled to storage node SN1. The gate structure GS2 can be implemented as the gate terminal of charge trap transistor CT2 and coupled to storage node SN2.

[0106] On the other hand, the gate structure GS3 can be implemented as the gate terminal of transistors TR1~TRN and used to receive the write word line signal WWL1. The drain portion DP1 can be implemented as the drain terminal of transistor TR1 and coupled to storage node SN1. The drain portion DP2 can be implemented as the drain terminal of transistor TR2 and coupled to storage node SN2. The source portions SP1 and SP2 can be implemented as the source terminals of transistors TR1 and TR2, respectively. The semiconductor structure SI3 can receive the write bit line signal WBL1 and transmit the write bit line signal WBL1 to the source portion SP1. The semiconductor structure SI4 can receive the write bit line signal WBL2 and transmit the write bit line signal WBL2 to the source portion SP2.

[0107] In some embodiments, for a write transistor, the gate structure GS3 is referred to as a vertical word line, and the semiconductor structures SI3 and SI4 are referred to as parallel bit lines.

[0108] In some embodiments, the channel structure CS1 can be implemented using silicon (Si) or other oxide semiconductor materials. The gate structure GS3 can be implemented using titanium nitride (TiN). Each of the semiconductor structures SI1-SI4 and the gate structures GS1-GS2 can be implemented using silicon (Si). In some variations, each of the semiconductor structures SI1-SI4 and the gate structures GS1-GS2 can also be implemented using indium gallium zinc oxide (IGZO). The isolation structure IS1 can be implemented using a dielectric material.

[0109] Figure 2C A cross-sectional schematic diagram illustrating further details of a memory structure 200B according to some embodiments of the present invention. Figure 2C As shown, the memory structure 200B also includes a gate oxide structure GOX2. In the ZY plane, the gate oxide structure GOX2 surrounds the semiconductor structure SI1, and the gate structure GS3 surrounds the gate oxide structure GOX2. In other words, the gate oxide structure GOX2 is located between the semiconductor structure SI1 and the gate structure GS3.

[0110] like Figure 2C As shown, in the Z direction, a portion of the gate structure GS3 is placed above the semiconductor structure SI1, and another portion of the gate structure GS3 is placed below the semiconductor structure SI1. Furthermore, in the X direction, the gate structure GS3 and the gate structure GS1 are separated from each other.

[0111] Please refer to Figure 1 and Figure 2C During operation, the current signal IR1 flows from the source structure SS1 through the channel structure CS1 to the drain structure DS1. In some embodiments, the channel structure CS1 can be implemented using undoped silicon. The gate structure GS1 can be implemented using polysilicon.

[0112] Figure 3A This is a 3D schematic diagram of a portion of a memory structure 300A according to some embodiments of the present invention. Please refer to... Figure 2B and Figure 3A Memory structure 300A is a variation of memory structure 200B. The components of memory structure 300A use the same numbering system as memory structure 200B. For the sake of brevity, the discussion will focus on the parts of memory structure 300A that differ from memory structure 200B, rather than their similarities.

[0113] Compared to memory structure 200B, memory structure 300A includes gate structures GS31 and GS32 and conductive structure MS1, as well as non-gate structure GS3, semiconductor structures SI3 and SI4 and oxide structures OX3 and OX4.

[0114] like Figure 3A As shown, in the ZY plane, gate structures GS31 and GS32 respectively surround semiconductor structures SI1 and SI2, and are separated from each other in the Z direction. Each of gate structures GS31 and GS32 extends in the Y direction. In the X direction, source portion SP1 and drain portion DP1 are located on both sides of gate structure GS31, and source portion SP2 and drain portion DP2 are located on both sides of gate structure GS32. Conductive structure MS1 is coupled to each of source portion SP1 and source portion SP2 and extends in the Z direction.

[0115] Please refer to Figure 1 and Figure 3AA variation of the memory device 100 can be implemented using memory structure 300A. In this variation, each of transistors TR1 to TRN is used to receive the write bit line signal WBL1. The conductive structure MS1 is used to transmit the write bit line signal WBL1 to each of the source portions SP1 and SP2. The gate structure GS31 can be implemented as the gate terminal of transistor TR1 and is used to receive the write word line signal WWL1. The gate structure GS32 can be implemented as the gate terminal of transistor TR2 and is used to receive the write word line signal WWL2.

[0116] In some embodiments, for a write transistor, gate structures GS31 and GS32 are referred to as parallel word lines, and conductive structure MS1 is referred to as a vertical bit line.

[0117] Figure 3B A cross-sectional schematic diagram illustrating further details of a memory structure 300A according to some embodiments of the present invention. Please refer to... Figure 2C and Figure 3B Memory structure 300A is a variation of memory structure 200B. The components of memory structure 300A use the same numbering system as memory structure 200B. For the sake of brevity, the discussion will focus on the parts of memory structure 300A that differ from memory structure 200B, rather than their similarities.

[0118] like Figure 3B As shown, in the ZY plane, the gate oxide structure GOX2 surrounds the semiconductor structure SI1, and the gate structure GS31 surrounds the gate oxide structure GOX2. In other words, the gate oxide structure GOX2 is located between the semiconductor structure SI1 and the gate structure GS31. In the Z direction, a portion of the gate structure GS31 is placed above the semiconductor structure SI1, and another portion of the gate structure GS31 is placed below the semiconductor structure SI1. Furthermore, in the X direction, the gate structure GS31 and the gate structure GS1 are separated from each other.

[0119] Figure 4A Illustrations based on some embodiments of the present invention Figure 1 The diagram illustrates a write operation on memory cell MC1. In some embodiments, the voltage level of storage node SN1 can determine the logic state of memory cell MC1. The current signal IR1 can be adjusted when storage node SN1 is charged or discharged. During a write operation, the voltage level VWWL1 of the write word line signal WWL1 is greater than the threshold voltage level VT1 of transistor TR1, thereby turning on transistor TR1 and allowing the write bit line signal WBL1 to charge or discharge storage node SN1.

[0120] In some embodiments, the write bit line signal WBL1 is used to carry the input bit IB1. In response to different logic values ​​of the input bit IB1, the write bit line signal WBL1 has a voltage level HVWBL or LVWBL, wherein the voltage level HVWBL is greater than the voltage level LVWBL.

[0121] exist Figure 4A In the illustrated embodiment, the write bit line signal WBL1 has a voltage level HVWBL. Correspondingly, during a write operation, the storage node SN1 is charged to a voltage level HVSN by the write bit line signal WBL1.

[0122] Figure 4B Illustrations based on some embodiments of the present invention Figure 1 The diagram shows a write operation performed on memory cell MC1. Please refer to... Figure 4B and Figure 4A , Figure 4B The situation is Figure 4A This is a variation of the situation. Therefore, for the sake of brevity, some parts of the description will not be repeated.

[0123] exist Figure 4B In the illustrated embodiment, the write bit line signal WBL1 has a voltage level LVWBL. Correspondingly, during a write operation, the storage node SN1 is discharged to a voltage level LVSN by the write bit line signal WBL1, where the voltage level LVSN is lower than the voltage level HVSN.

[0124] Figure 5A Illustrations based on some embodiments of the present invention Figure 1 The diagram illustrates a read operation performed on memory cell MC1. During a read operation, the voltage level VWWL1 of the write word line signal WWL1 is less than the threshold voltage level VT1. In some embodiments, the threshold voltage level VT1 may be greater than or equal to zero.

[0125] During a read operation, the voltage level VWWL1 is lower than the threshold voltage level VT1, causing transistor TR1 to turn off. At this time, the charge trap transistor CT1 turns on or off according to the voltage level of storage node SN1. Figure 5A In the embodiment shown, storage node SN1 has a voltage level HVSN that turns on charge trap transistor CT1.

[0126] Figure 5B Illustrations based on some embodiments of the present invention Figure 1 The diagram shows a write operation performed on memory cell MC1. Please refer to... Figure 5B and Figure 5A , Figure 5B The situation is Figure 5AThis is a variation of the situation. Therefore, for the sake of brevity, some parts of the description will not be repeated. Figure 5A In the illustrated embodiment, storage node SN1 has a voltage level LVSN that causes charge trap transistor CT1 to turn off. Details regarding voltage levels HVSN and LVSN are provided below. Figure 6B The embodiments are further illustrated below.

[0127] Figure 6A This is a schematic diagram 600A illustrating the relationship between the write word line signal WWL1 and the corresponding current level of the write transistor according to some embodiments of the present invention. The horizontal axis of schematic diagram 600A corresponds to the voltage level of the word line signal WWL1, that is, the gate voltage level of transistor TR1. The vertical axis of schematic diagram 600A corresponds to the current level of the current signal passing through transistor TR1.

[0128] Please refer to Figures 4A to 6A Transistor TR1 has a threshold voltage level VT1. Word line signal WWL1 can have a voltage level HVWWL greater than the threshold voltage level VT1 or a voltage level LVWWL less than the threshold voltage level VT1. When word line signal WWL1 has a voltage level HVWWL, transistor TR1 is turned on, allowing memory cell MC1 to perform write operations. When word line signal WWL1 has a voltage level LVWWL, transistor TR1 is completely turned off, allowing memory cell MC1 to maintain its logic state or perform read operations.

[0129] Figure 6B This is a schematic diagram 600B illustrating the relationship between the voltage level of storage node SN1 and the current level corresponding to the read transistor, according to some embodiments of the present invention. The horizontal axis of schematic diagram 600B corresponds to the voltage level of storage node SN1, i.e., the gate voltage level of charge trap transistor CT1. The vertical axis of schematic diagram 600B corresponds to the current level of the current signal IR1 passing through charge trap transistor CT1.

[0130] Please refer to Figures 5A to 6B When storage node SN1 has a voltage level LVSN, charge trap transistor CT1 is turned off, causing current signal IR1 to have a current level ILD0. In some embodiments, current level ILD0 is a zero current level. When storage node SN1 has a voltage level HVSN, charge trap transistor CT1 is turned on, causing current signal IR1 to have a current level ILD1, where current level ILD1 is greater than current level ILD0.

[0131] In some embodiments, the memory device 100 is further configured to compare the current level of the current signal IR1 with the sensed current level ISNS, wherein the sensed current level ISNS is greater than the current level ILD0 and less than the current level ILD1. When the current level of the current signal IR1 is greater than the sensed current level ISNS, the memory device 100 determines that the data in the storage node SN1 has a logic value of 1. When the current level of the current signal IR1 is less than the sensed current level ISNS, the memory device 100 determines that the data in the storage node SN1 has a logic value of 0.

[0132] Figure 7A This is a schematic diagram illustrating a memory device 700A according to some embodiments of the present invention. In some embodiments, the memory device 700A may be implemented as a 3D memory array. Please refer to... Figure 1 and Figure 7A The memory device 700A is a variation of the memory device 100. For the sake of brevity, the discussion will focus on the parts of the memory device 700A that differ from the memory device 100 rather than the parts that are the same.

[0133] like Figure 7A As shown, the memory device 700A includes memory cells MC1_1 to MCN_M. N and M at the end of the memory cell MCN_M are positive integers. Each of the memory cells MC1_1 to MCN_1 is used to receive a write bit line signal WBL1, a read word line signal RWL1, and a read bit line signal RBL1. Each of the memory cells MC1_2 to MCN_2 is used to receive a write bit line signal WBL2, a read word line signal RWL2, and a read bit line signal RBL2, and so on. Each of the memory cells MC1_M to MCN_M is used to receive a write bit line signal WBLM, a read word line signal RWLM, and a read bit line signal RBLM.

[0134] Similarly, each of the memory cells MC1_1 to MC1_M is used to receive the write word line signal WWL1. Each of the memory cells MC2_1 to MC2_M is used to receive the write word line signal WWL2, and so on. Each of the memory cells MCN_1 to MCN_M is used to receive the write word line signal WWLN.

[0135] In some embodiments, each of the memory cells MC1_1 to MCN_M includes two transistors. For example, memory cell MC1_1 includes transistor TR1_1 and charge-well transistor CT1_1. Memory cell MC1_2 includes transistor TR1_2 and charge-well transistor CT1_2. Memory cell MC2_1 includes transistor TR2_1 and charge-well transistor CT2_1. Memory cell MC2_2 includes transistor TR2_2 and charge-well transistor CT2_2.

[0136] like Figure 7A As shown, one end of transistor TR1_1 is used to receive the write bit line signal WBL1, and the other end of transistor TR1_1 is coupled to storage node SN1_1. The control terminal of transistor TR1_1 is used to receive the write word line signal WWL1. One end of charge trap transistor CT1_1 is used to receive the read word line signal RWL1, and the other end of charge trap transistor CT1_1 is used to receive the read bit line signal RBL1. The control terminal of charge trap transistor CT1_1 is coupled to storage node SN1_1.

[0137] Similarly, one end of transistor TR1_2 is used to receive the write bit line signal WBL2, and the other end of transistor TR1_2 is coupled to storage node SN1_2. The control terminal of transistor TR1_2 is used to receive the write word line signal WWL1. One end of charge trap transistor CT1_2 is used to receive the read word line signal RWL2, and the other end of charge trap transistor CT1_2 is used to receive the read bit line signal RBL2. The control terminal of charge trap transistor CT1_2 is coupled to storage node SN1_2.

[0138] Similarly, one end of transistor TR2_1 is used to receive the write bit line signal WBL1, and the other end of transistor TR2_1 is coupled to storage node SN2_1. The control terminal of transistor TR2_1 is used to receive the write word line signal WWL2. One end of charge trap transistor CT2_1 is used to receive the read word line signal RWL1, and the other end of charge trap transistor CT2_1 is used to receive the read bit line signal RBL1. The control terminal of charge trap transistor CT2_1 is coupled to storage node SN2_1.

[0139] Similarly, one end of transistor TR2_2 is used to receive the write bit line signal WBL2, and the other end of transistor TR2_2 is coupled to storage node SN2_2. The control terminal of transistor TR2_2 is used to receive the write word line signal WWL2. One end of charge trap transistor CT2_2 is used to receive the read word line signal RWL2, and the other end of charge trap transistor CT2_2 is used to receive the read bit line signal RBL2. The control terminal of charge trap transistor CT2_2 is coupled to storage node SN2_2.

[0140] Please refer to Figure 7A and Figure 3AThe memory device 700A can be implemented using the memory structure 300A. Specifically, the drain structure DS1 can operate as the drain terminal of charge trap transistors CT1_1 and CT2_1, and is used to receive the read bit line signal RBL1. The source structure SS1 can operate as the source terminal of charge trap transistors CT1_1 and CT2_1, and is used to receive the read word line signal RWL1. The gate structure GS1 can operate as the gate terminal of charge trap transistor CT1_1 and is coupled to the storage node SN1_1. The gate structure GS2 can operate as the gate terminal of charge trap transistor CT2_1 and is coupled to the storage node SN2_1.

[0141] On the other hand, gate structure GS31 can operate as the gate terminal of transistor TR1_1 and is used to receive the write word line signal WWL1. Gate structure GS32 can operate as the gate terminal of transistor TR2_1 and is used to receive the write word line signal WWL2. Drain portion DP1 can operate as the drain terminal of transistor TR1_1 and is coupled to storage node SN1_1. Drain portion DP2 can operate as the drain terminal of transistor TR2_1 and is coupled to storage node SN2_1. Source portion SP1 can operate as the source terminal of transistor TR1_1. Source portion SP2 can operate as the source terminal of transistor TR2_1. Conductor structure MS1 is used to receive the write bit line signal WBL1 and transmit the write bit line signal WBL1 to each of source portions SP1 and SP2.

[0142] Please refer to Figure 1 and Figure 7A The memory device 700A is a variation of the memory device 100. Memory cells MC1 to MCN can be implemented using memory cells MC1_1 to MCN_1. In other words, memory cells MC1_1 to MCN_1 can generate current signals IR1 to IRN respectively, and add the current signals IR1 to IRN together.

[0143] Figure 7B Illustrations based on some embodiments of the present invention Figure 7A Table 700B shows the voltage levels of the signals of the memory device 700A under various conditions. (See Table 700B for details.) Figure 7B As shown in Table 700B, the voltage levels of the selected write word line signal (WWL), the unselected write word line signal, the write bit line signal (WBL), the read word line signal (RWL), and the read bit line signal (RBL) under various conditions are displayed.

[0144] For illustrative purposes, the operation of memory cell MC1_1 is illustrated below. In this example, the selected WWL is the write word line signal WWL1. The unselected WWL is the write word line signal WWL2~WWLN. WBL is the write bit line signal WBL1. RWL is the read word line signal RWL1. RBL is the read bit line signal RBL1.

[0145] Please refer to Figure 7B and Figure 7A When a logic value of 0 is written to memory cell MC1_1, the selected write word line signal WWL1 has a voltage level of 3 volts (3V), causing transistor TR1_1 to turn on. In response to writing the logic value 0, the write bit line signal WBL1 has a voltage level of 3 volts. At this time, each of the unselected write word lines WWL2~WWLN, read word line signal RWL1, and read bit line signal RBL1 has a voltage level of 0 volts (0V).

[0146] Conversely, when a logic value of 1 is written to memory cell MC1_1, the selected write word line signal WWL1 has a voltage level of 3 volts, causing transistor TR1_1 to turn on. In response to writing the logic value 1, the write bit line signal WBL1 has a voltage level of 0 volts. At this time, each of the unselected write word lines WWL2~WWLN, read word line signal RWL1, and read bit line signal RBL1 has a voltage level of 0 volts.

[0147] While maintaining the logic state of memory cell MC1_1, the selected write word line signal WWL1 has a voltage level of 0 volts, causing transistor TR1_1 to turn off. Correspondingly, storage node SN1_1 can maintain the logic state of memory cell MC1_1. At this time, each of the unselected write word line signals WWL2~WWLN, write bit line signal WBL1, read word line signal RWL1, and read bit line signal RBL1 has a voltage level of 0 volts.

[0148] During a read operation on memory cell MC1_1, the read word line signal RWL1 has a voltage level of 1 volt (1V), and the read bit line signal RBL1 has a voltage level of 0 volts, resulting in a voltage difference across the charge trap transistor CT1_1. Correspondingly, the charge trap transistor CT1_1 generates a corresponding current signal based on the logic state of memory cell MC1_1. At this time, each of the write word lines WWL1~WWLN and the write bit line signal WBL1 has a voltage level of 0 volts.

[0149] Please refer to Figure 4A , Figure 4B and Figure 7BIn some embodiments, the memory cell MC1_1 can be implemented by the memory cell MC1, the transistor TR1_1 can be implemented by the transistor TR1, and the charge trap transistor CT1_1 can be implemented by the charge trap transistor CT1.

[0150] In the above embodiments, the voltage level HVWBL can be equal to a voltage level of 3 volts, the voltage level LVWBL can be equal to a voltage level of 0 volts, and the threshold voltage level VT1 can be between a voltage level of 0 volts and a voltage level of 3 volts.

[0151] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A memory device comprising a plurality of memory cells, the memory cells including a first memory cell, the first memory cell comprising: A first transistor, coupled to a first storage node, and used to transmit a first write bit line signal to the first storage node according to a first write word line signal; and A first charge trap transistor is used to generate a first current signal based on the threshold voltage level of the first charge trap transistor and the voltage level of the first storage node.

2. The memory device according to claim 1, wherein When the voltage level of the first write word line signal is greater than the threshold voltage level of the first transistor, the first transistor is turned on to perform a write operation. When the voltage level of the first write word line signal is less than the threshold voltage level of the first transistor, the first transistor is turned off to perform a read operation or maintain the logic state of the first memory cell.

3. The memory device of claim 2, wherein a first terminal of the first charge trap transistor is configured to receive a first read word line signal, and a second terminal of the first charge trap transistor is configured to receive a first read bit line signal. When the first memory cell maintains this logic state, the voltage level of the first read word line signal is equal to the voltage level of the first read bit line signal, and When the first memory cell performs the read operation, the voltage level of the first read word line signal is different from the voltage level of the first read bit line signal.

4. The memory device according to claim 2, wherein When a first logic value is written to the first memory cell, the voltage level of the first write bit line signal is equal to the voltage level of the first write word line signal. When a second logic value is written to the first memory cell, the voltage level of the first write bit line signal is different from the voltage level of the first write word line signal, and The first logical value is different from the second logical value.

5. The memory device of claim 1, wherein the memory cells further comprise a second memory cell, the second memory cell comprising: A second transistor, coupled to a second storage node, and used to transmit a second write bit line signal to the second storage node according to the first write word line signal; and A second charge trap transistor is used to generate a second current signal. The first memory unit and the second memory unit are also used to add the first current signal and the second current signal together.

6. The memory device of claim 5, further comprising: A first semiconductor structure extends in a first direction; A second semiconductor structure extends in the first direction and is separated from the first semiconductor structure in a second direction; and A first gate structure extends in the second direction and surrounds each of the first semiconductor structure and the second semiconductor structure. The first gate structure and the first semiconductor structure are used to operate as the first transistor, and The first gate structure and the second semiconductor structure are used to operate as the second transistor.

7. The memory device of claim 6, further comprising: A third semiconductor structure, coupled to the first semiconductor structure, and having a first length in the first direction; and A fourth semiconductor structure is coupled to the second semiconductor structure, has a second length greater than the first length in the first direction, and is isolated from the third semiconductor structure in the second direction. The third semiconductor structure and the fourth semiconductor structure are used to transmit the first write bit line signal and the second write bit line signal, respectively.

8. The memory device of claim 1, wherein the memory cells further comprise a second memory cell, the second memory cell comprising: A second transistor, coupled to a second storage node, and used to transmit the first write bit line signal to the second storage node according to a second write word line signal; and A second charge trap transistor is used to generate a second current signal. The first memory unit and the second memory unit are also used to add the first current signal and the second current signal together.

9. The memory device of claim 8, further comprising: A first semiconductor structure extends in a first direction; A second semiconductor structure extends in the first direction and is separated from the first semiconductor structure in a second direction; and A first gate structure extends upward on a third side and surrounds the first semiconductor structure; and A second gate structure extends upward from the third side, surrounds the second semiconductor structure, and is separated from the first gate structure in the second direction. The first gate structure and the first semiconductor structure are used to operate as the first transistor, and The second gate structure and the second semiconductor structure are used to operate as the second transistor.

10. The memory device of claim 9, further comprising: A conductive structure extends in the second direction and is used to transmit the first write bit line signal to each of the first semiconductor structure and the second semiconductor structure.

11. A memory structure comprising: A single-source pole structure extending in a first direction; A drain structure extends in the first direction and is separate from the source structure; A first gate structure surrounds each of the source structure and the drain structure, and is used to operate with the source structure and the drain structure as a first charge trap transistor. A first semiconductor structure extends in a second direction and is coupled to the first gate structure; and A second gate structure, separated from the first gate structure in the second direction, surrounds the first semiconductor structure and is used to operate with the first semiconductor structure as a first transistor.

12. The memory structure according to claim 11, further comprising: A third gate structure surrounds each of the source structure and the drain structure, and is configured to operate with the source structure and the drain structure as a second charge trap transistor; and A second semiconductor structure extends in the second direction, is separated from the first semiconductor structure in the first direction, and is coupled to the third gate structure.

13. The memory structure of claim 12, wherein the second gate structure further surrounds the second semiconductor structure and is configured to operate with the second semiconductor structure as a second transistor, and The drain terminal of the second transistor is coupled to the gate terminal of the second charge trap transistor.

14. The memory structure according to claim 13, further comprising: A third semiconductor structure, coupled to the first semiconductor structure, and having a first length in the second direction; and A fourth semiconductor structure is coupled to the second semiconductor structure and has a second length in the second direction. The first length is less than the second length.

15. The memory structure according to claim 14, further comprising: A first oxide structure having a third length in the second direction; and A second oxide structure having the first length in the second direction, and used to isolate the third semiconductor structure and the fourth semiconductor structure from each other. The first oxide structure, the third semiconductor structure, the second oxide structure, and the fourth semiconductor structure are arranged sequentially in the first direction.

16. The memory structure according to claim 12, further comprising: A fourth gate structure, separated from the second gate structure in the first direction, surrounds the second semiconductor structure and is used to operate with the second semiconductor structure as a second transistor. Each of the second gate structure and the fourth gate structure extends upward in a third direction, and The first direction, the second direction, and the third direction are perpendicular to each other.

17. The memory structure according to claim 16, further comprising: A conductive structure extends in the first direction and is used to transmit a write bit line signal to each of the first semiconductor structure and the second semiconductor structure.

18. A method of operating a memory device, comprising: Write a first input bit into a first storage node; A first weighted bit is stored by a first charge trap transistor coupled to the first storage node; and A first current signal is generated based on the first input bit and the first weight bit, and flows through the first charge trap transistor.

19. The operating method according to claim 18, further comprising: A first transistor is turned on by a write word line signal to transmit a first write bit line signal to the first storage node; and The write word line signal turns on a second transistor to transmit a second write bit line signal to a second storage node. The second storage node is different from the first storage node.

20. The operating method according to claim 18, further comprising: A first transistor is turned on by a first write word line signal to transmit a write bit line signal to the first storage node; and A second transistor is turned on by a second write word line signal to transmit the write bit line signal to a second storage node. The second storage node is different from the first storage node.

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