Memory device using high-level voltage and semiconductor device

Abstract

The present invention relates to a memory device, comprising: a switching unit configured to determine whether to transmit a high-level voltage of which a level is at least three times or more of a power supply voltage, and a control element configured to generate a first control signal which is switched between a first voltage level and a second voltage level to control the switching unit, the first voltage level being equal to a level of the power supply voltage, and the second voltage level being greater than 0 V and less than 10% of the high-level voltage level.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2025-0044468, filed on April 7, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure described herein relate to a memory system and a semiconductor device, and more specifically, to a memory system and a semiconductor device using a high-level voltage that is higher than the supply voltage. Background Technology

[0004] Data processing systems, including memory systems or data storage devices, have been developed to store more data in data storage devices, store data in data storage devices faster, and output data stored in data storage devices faster. Data storage devices may include non-volatile memory cells and / or volatile memory cells for storing data. Data storage devices can use high-level voltages (voltage levels higher than the supply voltage) to perform internal operations. Summary of the Invention

[0005] Embodiments of this disclosure may provide a memory device, a memory system including the memory device, a controller included in the memory system, or a data processing device including the memory system.

[0006] Embodiments of this disclosure may provide an apparatus and method for adjusting the level of a control signal for a switching device to reduce negative bias temperature instability (NBTI). NBTI is a degradation phenomenon of a switching device configured to transmit a high-level voltage at least three times or more than the supply voltage and used for internal operation in a semiconductor device or memory device.

[0007] Furthermore, embodiments of this disclosure may provide an apparatus and method for selectively adjusting the voltage level of a signal of a switching device included in a control memory device, thereby reducing degradation of the switching device and increasing the amount of current flowing through the switching device to obtain signal transmission gain, wherein the switching device is configured to transmit a high-level signal such as a pass voltage, a programming voltage, or an erase voltage.

[0008] Additionally, embodiments of this disclosure may provide an apparatus and method for reducing the degradation of switching devices included in a semiconductor device or memory device, thereby improving the lifespan and durability of the semiconductor device or memory device, wherein the switching device is configured to transmit a high-level voltage at a constant voltage level of at least three times the power supply voltage.

[0009] In one embodiment, a memory device may include: a switching unit configured to determine whether to transmit a high-level voltage that is at least three times or higher than the power supply voltage; and a control element configured to generate a first control signal that switches between a first voltage level and a second voltage level to control the switching unit. The first voltage level is equal to the power supply voltage level, and the second voltage level is greater than 0V and less than 10% of the high-level voltage level.

[0010] The memory device may further include: at least one memory cell configured to store data; a word line connected to the at least one memory cell and used to apply a high-level voltage transmitted through a switching unit; and a voltage generation circuit configured to output a high-level voltage.

[0011] The switching unit may include a PMOS transistor. A first control signal having a first voltage level or a second voltage level may be applied to the gate of the PMOS transistor.

[0012] A first control signal with a first voltage level can be used to turn on the PMOS transistor, and a first control signal with a second voltage level can be used to turn off the PMOS transistor.

[0013] The power supply voltage range is 2.5V to 5V, the high-level voltage is 20V or higher, and the second voltage is greater than 0V and less than 2V.

[0014] The second voltage level is adjustable based on the power supply voltage and the high-level voltage.

[0015] The control element can be connected to a switching element configured to transmit a second voltage level to the control element in response to a selection control signal.

[0016] Switching elements may include NMOS transistors.

[0017] The switching unit may include: a loop circuit including a plurality of transistors and activated in response to a first voltage level; and a switch configured to discharge the loop circuit in response to a second control signal.

[0018] The second control signal may have a logic value that is the opposite of the logic value of the first control signal. The voltage swing ranges of the first and second control signals may be different from each other.

[0019] In another embodiment, a semiconductor device may include: a switching unit configured to determine whether to transmit a high-level voltage that is at least three times or higher than the power supply voltage; a control device configured to generate a control signal that switches between a first voltage level and a second voltage level to control the switching unit; and a first switch configured to transmit a first low voltage level as a second voltage level to the control device in response to a first selection control signal, the first low voltage level being greater than a ground voltage level and less than the high-level voltage level.

[0020] The semiconductor device may further include: a second switch configured to transmit a ground voltage level as a second voltage level to the control device in response to a second selection control signal. Either the first selection signal or the second selection signal may be activated.

[0021] Each of the first switch and the second switch may include an NMOS transistor.

[0022] The first voltage level can be equal to the power supply voltage level.

[0023] The switching unit may include a PMOS transistor. A control signal having a first voltage level or a second voltage level may be applied to the gate of the PMOS transistor.

[0024] A first control signal with a first voltage level can be used to turn on the PMOS transistor, and a first control signal with a second voltage level can be used to turn off the PMOS transistor.

[0025] The power supply voltage range is 2.5V to 5V, the high-level voltage is 20V or higher, and the second voltage level is greater than 0V and less than 2V.

[0026] The second voltage level is adjustable based on the power supply voltage level and the high-level voltage level.

[0027] In another embodiment, a non-volatile memory device may include: a plurality of memory cells configured to store data; word lines connected to the plurality of memory cells; a voltage generator configured to generate at least one of a pass voltage, a programming voltage, and an erase voltage, wherein the level of each of the pass voltage, programming voltage, and erase voltage is at least three times higher than a power supply voltage; a switching unit configured to determine whether to transmit at least one of the pass voltage, programming voltage, and erase voltage to the word line; and a control element configured to generate a control signal controlling the switching unit, the control signal switching between a first voltage level and a second voltage level. The first voltage level may be equal to the level of the power supply voltage. The second voltage level may be greater than 0V and less than 10% of the level of the high voltage level.

[0028] The switching unit may include a PMOS transistor. A control signal having a first voltage level or a second voltage level may be applied to the gate of the PMOS transistor.

[0029] The second voltage level is adjustable based on the power supply voltage level and the high-level voltage level. Attached Figure Description

[0030] The description herein refers to the accompanying drawings, in which the same reference numerals denote the same parts throughout the drawings.

[0031] Figure 1 The negative bias temperature instability (NBTI) effect observed in a switching device according to an embodiment of the present disclosure is shown.

[0032] Figure 2 A memory system according to an embodiment of the present disclosure is shown.

[0033] Figure 3 A memory device according to an embodiment of the present disclosure is shown.

[0034] Figure 4 A semiconductor device according to an embodiment of the present disclosure is shown.

[0035] Figure 5 A memory device according to an embodiment of the present disclosure is shown.

[0036] Figure 6 Operation of a first switching device according to an embodiment of the present disclosure is shown.

[0037] Figure 7 The configurations of a second switching device and a third switching device according to embodiments of the present disclosure are shown.

[0038] Figure 8 It shows in Figure 7 The operation of the third switching device is shown in the figure.

[0039] Figure 9 Operation of a second and a third switching device according to embodiments of the present disclosure is shown.

[0040] Figure 10 A first simulation result of the variation of the output terminal of the switching device according to an embodiment of the present disclosure is shown.

[0041] Figure 11 A second simulation result showing the variation of the output terminal of the switching device according to an embodiment of the present disclosure is presented. Detailed Implementation

[0042] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The elements and features of the present disclosure may be configured or arranged in different ways to form other embodiments, which may be variations of any of the disclosed embodiments.

[0043] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may or need not be combined in the same embodiments.

[0044] In this disclosure, the terms “comprising,” “including,” “containing,” and “comprising” are open-ended. As used in the appended claims, these terms specify the presence of the said element but do not exclude the presence or addition of one or more other elements. Furthermore, the terms in the claims do not exclude the device from including additional components, such as interface units, circuitry, etc.

[0045] In this disclosure, various units, circuits, or other components may be described or declared as "configured to" perform one or more tasks. In such a context, "configured to" is used to indicate a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Therefore, even when a block / unit / circuit / component is not currently running, e.g., not turned on or activated, it can be said that the specified block / unit / circuit / component is configured to perform a task. Examples of blocks / units / circuits / components used with the "configured to" language include hardware, such as circuits, memory storing program instructions that can be executed to perform operations, etc. Furthermore, "configured to" may include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor running software) to operate in a manner capable of performing the relevant tasks. "Configured to" may also include adjusting manufacturing processes (e.g., semiconductor manufacturing facilities) to manufacture means (e.g., integrated circuits) suitable for performing or implementing one or more tasks.

[0046] As used in this disclosure, the terms “circuit” or “logic” refer to all of the following: (a) a purely hardware circuit implementation (e.g., an implementation of analog and / or digital circuitry only); and (b) a combination of circuitry and software (and / or firmware), such as (if applicable): (i) a combination of processors or (ii) a processor / software (including digital signal processors), software, and memory that work together to enable a device such as a mobile phone or server to perform various functions; and (c) a circuit, such as a microprocessor or a portion thereof, that requires software or firmware to function, even if the software or firmware is not physically present. The definition of “circuit” or “logic” applies to all uses of the term in this application, including in any claim. As a further example, as used in this application, the terms “circuit” or “logic” also cover implementations of only one or more processors or a portion thereof and their accompanying software and / or firmware. The terms “circuit” or “logic” also cover integrated circuits, for example, for storage devices, if applicable to a particular claim element.

[0047] As used herein, the terms “first,” “second,” “third,” etc., used as labels preceding nouns do not indicate any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily mean that the first value must precede the second. Furthermore, while these terms can be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element with the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0048] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude other factors that may influence the determination. That is, the determination may be based solely on these factors, or at least partially on them. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, such a phrase does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely based on B.

[0049] Here, a data entry, data item, or data term can be a bit sequence. For example, a data entry may include the contents of a file, a portion of a file, a page in memory, an object in object-oriented programming, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a bit sequence. According to an embodiment, a data entry may include discrete objects. According to another embodiment, a data entry may include units of information processed or disposed of for data input / output operations. According to yet another embodiment, a data entry may include units of information within a data packet transmitted between two different components.

[0050] The embodiments described herein can provide an apparatus and method for improving data input / output operations of a memory system or data processing system. Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals indicate like elements.

[0051] Figure 1 The negative bias temperature instability (NBTI) effect occurring in a switching device according to an embodiment of the present disclosure is illustrated.

[0052] Reference Figure 1 The image shows an example of a PMOS transistor (e.g., HVP) as a switching device. A PMOS transistor (e.g., HVP) can be used as a switch configured to selectively transmit a high-level voltage VPP that is several times or higher than the supply voltage VDD.

[0053] Negative bias temperature instability (NBTI) effects that can occur in switching devices can include an increase in the absolute value of the threshold voltage, a decrease in the mobility of p-channel MOSFETs, a decrease in drain current, and a decrease in transconductance. NBTI effects typically occur in PMOS transistors, but not NMOS transistors. When a PMOS transistor is reverse biased, silicon-hydrogen (Si-H) bonds may break along the silicon-oxide interface, creating interface traps. (See reference...) Figure 1 The graph shown illustrates that the rate at which this trap forms may vary depending on temperature ΔV. T The threshold voltage V of the PMOS transistor is accelerated by the applied stress time (i.e., Stress Time(s)). This trap may increase the threshold voltage V of the PMOS transistor. TH Threshold voltage V TH An increase in delay will exacerbate delays in circuits or components, including switching devices. If the increased delay causes the delay value of a circuit or component to exceed a certain amount, the circuit or component may be unable to meet the timing specifications of signals received from, transmitted by, or processed by another circuit or component.

[0054] The mechanism of negative bias temperature instability (NBTI) may begin with the degradation of the silicon-hydrogen (Si-H) bond, which breaks due to a chemical reaction with high-energy holes on the SiO2 / Si surface. For example, interface traps may occur when the voltage between the gate and source in a PMOS transistor (e.g., Vgs) is negative (e.g., -Vdd). If the voltage between the gate and source (e.g., Vgs) is "0", the interface traps may be reduced. Therefore, the negative bias temperature instability (NBTI) effect on a PMOS transistor may vary depending on the time it takes for the PMOS transistor to be stressed and released.

[0055] Generally, two types of traps are known to cause negative bias temperature instability (NBTI) effects. First, interface traps can occur when the voltage between the gate and source (e.g., Vgs) is negative. These interface traps may be difficult to recover from within a reasonable operating time, including when the voltage between the gate and source (e.g., Vgs) becomes "0". An electric field may disrupt the silicon-hydrogen (Si-H) bonds at the silicon-oxide interface. Hydrogen (e.g., H, H2) may be released from the moving substrate, and the remaining unsaturated bonds (e.g., dangling bonds at the Si-Pb center) may cause the threshold voltage Vgs to drop. TH The deterioration.

[0056] Furthermore, with the formation of more interface traps, hydrogen (e.g., H, H2) may diffuse from the source to the drain. Figure 1 As shown, a hydrogen density distribution from the source to the drain may be formed in a PMOS transistor.

[0057] Besides the formation of interface traps, existing traps in most dielectrics (e.g., nitrogen-related) can be filled by holes from the PMOS channel. These traps may be cleared when the stress voltage is removed. Threshold voltage V TH This degradation can recover over time.

[0058] As described above, when negative bias stress and temperature-dependent stress are applied to a PMOS transistor, negative bias temperature instability (NBTI) may occur due to interface degradation between the gate insulator (e.g., Gox) and the substrate. This degradation may increase the threshold voltage V. TH Specifically, when a negative bias is applied, holes may be injected into the Si / SiO2 interface. The silicon-hydrogen (Si-H) bonds may be broken by these holes, generating hydrogen ions (e.g., H+). As these hydrogen ions diffuse / drift, interface traps (positive charges) may form at their locations. These positively charged interface traps may further reduce the threshold voltage Vth of the PMOS transistor. TH The absolute value of . Furthermore, when the threshold voltage V TH When positive, the threshold voltage V TH The absolute value may increase.

[0059] Negative bias temperature instability (NBTI) effects that can occur in switching devices can adversely affect the normal operation of semiconductor devices, memory devices, or memory systems. This effect can be critical because PMOS transistors are frequently used as switching devices in semiconductor devices, memory devices, or memory systems. In particular, such as Figure 1The semiconductor device, memory device, or memory system may include a switching device configured to transmit a high-level voltage. Degradation, malfunction, or increased latency of the switching device may interfere with the normal operation of the semiconductor device, memory device, or memory system.

[0060] Figure 2 A memory system according to an embodiment of the present disclosure is shown.

[0061] Reference Figure 2 The data processing system 100 may include a host 102, which is coupled to or connected to a memory system (e.g., memory system 110). For example, the host 102 and the memory system 110 may be interconnected via a data bus, host cable, etc., to perform data communication.

[0062] Memory system 110 may include memory device 150 and controller 130. Memory device 150 and controller 130 in memory system 110 can be considered as physically separate components or elements. Memory device 150 and controller 130 can be connected via at least one data path. For example, a data path may include a channel and / or a path.

[0063] According to embodiments, the memory device 150 and the controller 130 may be functionally divided components or elements. Furthermore, according to embodiments, the memory device 150 and the controller 130 may be implemented using a single chip or multiple chips. The controller 130 may perform data input / output operations in response to a request input from an external device. For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0064] like Figure 2 As shown, memory device 150 may include multiple memory blocks 152, 154, and 156. Memory blocks 152, 154, and 156 can be understood as a group of non-volatile memory cells where data is erased together in a single erase operation. Although not shown, memory blocks 152, 154, and 156 may include pages, which are a group of non-volatile memory cells that store data together during a single programming operation or output data together during a single read operation. For example, a memory block may include multiple pages.

[0065] For example, memory device 150 may include multiple memory planes or multiple memory dies. According to an embodiment, a memory plane may be considered as a logical or physical partition, which includes at least one memory block, drive circuitry capable of controlling an array comprising multiple non-volatile memory cells, and a buffer capable of temporarily storing data input to or output from the non-volatile memory cells.

[0066] Furthermore, according to an embodiment, a memory die may include at least one memory plane. A memory die can be understood as a set of components implemented on a physically distinguishable substrate. Each memory die can be connected to the controller 130 via a data path. Each memory die may include an interface for exchanging data items and signals with the controller 130.

[0067] According to an embodiment, the memory device 150 may include at least one memory block 152, 154, 156, at least one memory plane, or at least one memory die. Figure 2 The internal configuration of the illustrated memory device 150 may vary depending on the configuration, performance, and / or design of the memory system 110. Embodiments of this disclosure are not limited to those described herein. Figure 2 The internal configuration shown.

[0068] Reference Figure 2 The memory device 150 may include a voltage supply circuit 170 capable of supplying at least a portion of the voltage to memory blocks 152, 154, and 156. The voltage supply circuit 170 may supply a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory blocks. For example, during a read operation to read data stored in the non-volatile memory cells included in memory blocks 152, 154, and 156, the voltage supply circuit 170 may supply the read voltage Vrd to the selected non-volatile memory cell. During a programming operation to store data in the non-volatile memory cells included in memory blocks 152, 154, and 156, the voltage supply circuit 170 may supply the programming voltage Vprog to the selected non-volatile memory cell. Furthermore, during a read or programming operation on a selected non-volatile memory cell, the voltage supply circuit 170 may supply the pass voltage Vpass to an unselected non-volatile memory cell. During the erase operation that erases data stored in the non-volatile memory cells included in memory blocks 152, 154, and 156, voltage supply circuit 170 can supply an erase voltage Vers to the memory blocks.

[0069] According to an embodiment, the voltage supply circuit 170 may apply a programming voltage Vprog, a voltage Vpass, or an erase voltage Vers to at least one memory block 152, 154, 156 via at least one word line. Figure 1 The high-level voltage VPP is shown in the diagram. The programming voltage Vprog, the pass voltage Vpass, or the erase voltage Vers can be several times higher than the power supply voltage.

[0070] Memory device 150 can store information about various voltages supplied to memory blocks 152, 154, and 156, and perform operations based on these voltages. For example, when the non-volatile memory cells in memory blocks 152, 154, and 156 can store multiple bits of data, multiple levels of read voltage Vrd may be needed to identify or read multiple data entries. Memory device 150 may include a table containing information corresponding to multiple levels of read voltage Vrd, each level corresponding to a multiple data entry. For example, the table may include bias values ​​stored in registers, each bias value corresponding to a specific level of read voltage Vrd. The number of bias values ​​of read voltage Vrd used for read operations may be limited to a preset range. Furthermore, the bias values ​​may be quantized.

[0071] The host 102 may include portable electronic devices, such as mobile phones, MP3 players, and laptops, or non-portable electronic devices, such as desktop computers, game consoles, televisions, and projectors.

[0072] Host 102 may further include at least one operating system (OS) that controls the functions and operations performed within host 102. The operating system can provide interoperability between host 102, which is operatively coupled to memory system 110, and a user intending to store data in memory system 110. The operating system can support functions and operations corresponding to user requests. By way of example and not limitation, operating systems can be classified as general-purpose operating systems and mobile operating systems based on the mobility of host 102. General-purpose operating systems can be further classified as personal operating systems and enterprise operating systems based on system requirements or user environment. Compared to personal operating systems, enterprise operating systems can be specifically designed to secure and support high-performance computing.

[0073] A mobile operating system can be used to support services or functions that enable mobility (e.g., power-saving features). Host 102 may include multiple operating systems. Host 102 can run multiple operating systems interlocked with memory system 110 in response to a user's request. Host 102 can transmit multiple commands corresponding to a user's request to memory system 110, thereby executing operations corresponding to the multiple commands within memory system 110.

[0074] The controller 130 in the memory system 110 can control the memory device 150 in response to requests or commands input from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102, and can perform a write operation (or programming operation) to store data input from the host 102 in the memory device 150. In order to perform data input / output (I / O) operations, the controller 130 can control and manage internal operations such as reading data, programming data, erasing data, etc.

[0075] According to an embodiment, the controller 130 may include a host interface 132, a processor 134, an error correction circuit (ECC) 138, a power management unit (PMU) 140, a memory interface (I / F) 142, and a memory 144. Figure 2 As shown, the components included in the controller 130 may vary depending on the structure, function, operational performance, etc., implemented (or associated with, configured) in the memory system 110.

[0076] For example, depending on the host interface protocol, the memory system 110 can be implemented using any of a variety of storage devices electrically connected to the host 102. Non-limiting examples of suitable storage devices include solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), miniature MMCs (RS-MMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, etc. Depending on the implementation of the memory system 110, components can be added to or omitted from the controller 130.

[0077] Both host 102 and memory system 110 may include a controller or interface for sending and receiving signals, data, etc., according to one or more predetermined protocols. For example, host interface 132 in memory system 110 may include devices capable of sending signals, data, etc. to host 102 or receiving signals, data, etc. from host 102.

[0078] The host interface 132 included in controller 130 can receive signals, commands (or requests), and / or data input from host 102 via a bus. For example, host 102 and memory system 110 can use a predetermined set of rules or procedures or a preset interface for data communication to send and receive data between host 102 and memory system 110. Examples of a set of rules or procedures for data communication standards or interfaces supported by host 102 and memory system 110 for sending and receiving data include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), High-Speed ​​Peripheral Component Interconnect (PCIe or PCI-e), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), etc. According to an embodiment, host interface 132 can be a layer for exchanging data with host 102 and can be implemented or driven by firmware such as Host Interface Layer (HIL). According to an embodiment, host interface 132 may include a command queue.

[0079] An Electronic Integrated Drive (IDE) interface or an Advanced Technology Accessory (ATA) interface can be used as one of the interfaces for transmitting and receiving data. For example, a cable comprising 40 parallel-connected wires can be used to support data transfer and reception between host 102 and memory system 110. When multiple memory systems 110 are connected to a single host 102, the multiple memory systems can be classified as master and slave devices using a position switch or DIP switch connected to the multiple memory systems. The memory system 110 configured as the master device can be used as the primary memory device. IDE (ATA) can include, for example, Fast-ATA, ATAPI, or Enhanced IDE (EIDE).

[0080] The Serial Advanced Technology Attachment (SATA) interface is a serial data communication interface compatible with various ATA standards for parallel data communication interfaces used by Integrated Electronic Drives (IDE) devices. The 40 wires in an IDE interface can be reduced to 6 wires in a SATA interface. For example, the 40 parallel signals of IDE can be converted to the 6 serial signals of a SATA interface. Due to its faster data transfer and reception rates and lower resource consumption for data transfer and reception in the host 102, the SATA interface is widely used. Up to 30 external devices can be connected to a single transceiver included in the host 102. Furthermore, the SATA interface supports hot-swapping, allowing external devices to be connected or disconnected from the host 102 even while data communication between the host 102 and another device is in progress. Therefore, even when the host 102 is powered on, the memory system 110 can be connected or disconnected as an auxiliary device (such as a device supported by Universal Serial Bus (USB)). For example, in a host 102 with an eSATA port, the memory system 110 can be freely connected to or disconnected from the host 102 like an external hard drive.

[0081] Small Computer System Interface (SCSI) is a serial data communication interface used to connect a computer or server to other peripheral devices. Compared to other interfaces such as IDE and SATA, SCSI can provide higher transfer speeds. In a SCSI-implemented (combined) system, host 102 and at least one peripheral device (e.g., memory system 110) are connected in series, but data transfer and reception between host 102 and each peripheral device can be performed through parallel data communication (or parallel data connections). In a SCSI-implemented system, it is relatively easy (e.g., stable and / or requiring minimal processing or adjustments) to connect or disconnect host 102 from devices such as memory system 110. SCSI can support connecting up to 15 other devices to a single transceiver included in host 102.

[0082] Serial SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, host 102 and multiple peripheral devices are connected in series, and data transmission and reception between host 102 and each peripheral device can be performed (or implemented) using a serial data communication scheme. SAS can support the connection between host 102 and peripheral devices via serial cables instead of parallel cables, making it easy (e.g., timely, and without additional processes, protocols, or devices) to manage devices using SAS, and enhancing operational reliability and communication performance. SAS can support connecting up to eight external devices to a single transceiver included in host 102.

[0083] High-speed non-volatile memory (NVMe) is an interface based at least on high-speed peripheral component interconnect (PCIe) designed to improve the performance and design flexibility of a host 102, server, computing device, etc., equipped with memory system 110. PCIe can use slots or specific cables to connect computing devices (e.g., host 102) and peripheral devices (e.g., memory system 110). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, 82 pins, etc.) and at least one wire (e.g., x1, x4, x8, x16, etc.) to achieve high-speed data communication of hundreds of MB / s or more (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, 1969 MB / s, etc.). According to embodiments, PCIe schemes can achieve bandwidths of tens to hundreds of gigabits per second. NVMe can support operating speeds of memory system 110 (e.g., SSD) higher than those of hard disks.

[0084] According to an embodiment, host 102 and memory system 110 can be connected via Universal Serial Bus (USB). Universal Serial Bus (USB) is a scalable, hot-swappable, plug-and-play serial interface that provides a cost-effective standard connection between host 102 and peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, cameras, etc. Multiple peripheral devices, such as memory system 110, can be coupled to a single transceiver included in host 102.

[0085] Reference Figure 2 Error correction circuit 138 can correct error bits in data read from memory device 150 and may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder performs error correction encoding on data to be programmed into memory device 150 to generate encoded data with parity bits added, and stores the encoded data in memory device 150. When controller 130 reads data stored in memory device 150, ECC decoder can detect and correct error bits contained in the data read from memory device 150. For example, after performing error correction decoding on data read from memory device 150, error correction circuit 138 determines whether error correction decoding was successful and outputs a command signal, such as a correction success signal or a correction failure signal, based on the result of error correction decoding. Error correction circuit 138 can use parity bits to correct error bits in the read data, which are generated during the ECC encoding process for the data stored in memory device 150. When the number of error bits is greater than or equal to the number of correctable error bits, the error correction circuit 138 may not correct the error bits, but may instead output a correction failure signal indicating that the correction of the error bits has failed.

[0086] According to embodiments, the error correction circuit 138 may perform error correction operations based on coding modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc. The error correction circuit 138 may include all circuits, modules, systems, and / or devices that perform error correction operations based on at least one of the above-described codes.

[0087] For example, an ECC decoder can perform hard-decision decoding or soft-decision decoding on data transmitted from memory device 150. Hard-decision decoding can be understood as one of two broadly classified methods for error correction. Hard-decision decoding may include the operation of correcting erroneous bits by reading digital data of "0" or "1" from non-volatile memory cells in memory device 150. Because hard-decision decoding processes binary logic signals, its circuit / algorithm design or configuration can be simpler than that of soft-decision decoding, and its processing speed can be faster.

[0088] Soft-decision decoding can quantize the threshold voltage of a non-volatile memory cell in memory device 150 into two or more quantized values, such as multi-bit data, approximations, analog values, etc., to correct error bits based on these two or more quantized values. Controller 130 can receive two or more letters or quantized values ​​from multiple non-volatile memory cells in memory device 150 and then perform decoding based on information generated by representing the quantized values ​​as a combination of information such as conditional probabilities or likelihoods.

[0089] According to an embodiment, the ECC decoder can use Low-Density Parity-Generation Matrix (LDPC-GM) codes in a method designed for soft-decision decoding. The algorithm used in LDPC codes reads the value of several bits of data from memory device 150 based on reliability, rather than simply reading 1 or 0 data as in hard-decision decoding, and iteratively repeats this process through message exchange to improve the reliability of the values. These values ​​are then ultimately determined to be 1 or 0 data. For example, the decoding algorithm using LDPC codes can be understood as probabilistic decoding. In hard-decision decoding, the value output from a non-volatile memory cell can be decoded as 0 or 1. Compared to hard-decision decoding, soft-decision decoding can determine the value stored in the non-volatile memory cell based on random information. Regarding bit flips that may be considered possible errors in memory device 150, soft-decision decoding can improve the probability of correcting errors and recovering data, and provide the reliability and stability of the corrected data. LDPC-GM codes can have a scheme where internal LDGM codes can be concatenated with high-speed LDPC codes.

[0090] According to embodiments, the ECC decoder can, for example, use low-density parity-check convolutional codes (LDPC-CCs) for soft-decision decoding. LDPC-CCs can have schemes that use linear-time encoding and pipeline decoding based on variable block lengths and shift registers.

[0091] According to an embodiment, the ECC decoder may, for example, use a log-likelihood ratio Turbo code (LLR-TC) for soft-decision decoding. The log-likelihood ratio (LLR) can be calculated as a non-linear function of the distance between the sampled value and the ideal value. Furthermore, the Turbo code (TC) may include simple codes, such as Hamming codes, in two or three dimensions, and be repeatedly decoded in both row and column directions to improve the reliability of the values.

[0092] The power management unit (PMU) 140 can control the power supplied to the controller 130. The PMU 140 can monitor the power supplied to the memory system 110, such as the voltage supplied to the controller 130, and supply power to components included in the controller 130. The PMU 140 can not only detect power on / off, but also generate a trigger signal when the power supply to the memory system 110 is unstable, enabling the memory system 110 to perform an emergency backup of its current state. According to embodiments, the PMU 140 may include means or components capable of accumulating power that can be used in emergency situations.

[0093] The memory interface (I / F) 142 can serve as an interface for handling commands and data transmitted between the controller 130 and the memory device 150, allowing the controller 130 to control the memory device 150 in response to commands or requests input from the host 102. In the case that the memory device 150 is flash memory, the memory interface 142 can generate control signals for the memory device 150 and process data input to or output from the memory device 150 under the control of the processor 134.

[0094] For example, when memory device 150 includes NAND flash memory, memory interface 142 includes a NAND flash controller (NFC). Memory interface 142 can provide an interface for handling commands and data between controller 130 and memory device 150. According to embodiments, memory interface 142 can be implemented or driven by firmware for exchanging data with memory device 150 and is referred to as the Flash Interface Layer (FIL).

[0095] According to an embodiment, the memory interface 142 may support an Open NAND Flash Interface (ONFi), switching modes, etc., for data input / output with the memory device 150. For example, ONFi may use a data path (e.g., channel, path, etc.) including at least one signal line capable of bidirectional transmission and reception in units of 8 bits or 16 bits of data. Data communication between the controller 130 and the memory device 150 may be implemented through at least one interface such as Asynchronous Single Data Rate (SDR), Synchronous Double Data Rate (DDR), and Switched Double Data Rate (DDR).

[0096] Memory 144 can be used as working memory for memory system 110 or controller 130, while also temporarily storing transactional data for operations performed in memory system 110 and controller 130. For example, memory 144 can temporarily store read data entries that are output from memory device 150 in response to a read request from host 102 before they are output to host 102. Furthermore, controller 130 can temporarily store write data entries that are input from host 102 into memory device 150 before they are programmed into memory device 150. When controller 130 controls operations such as data read operations, data write or programming operations, and data erase operations of memory device 150, data transferred between controller 130 and memory device 150 in memory system 110 can be temporarily stored in memory 144.

[0097] In addition to reading or writing data entries, memory 144 may also store information for inputting or outputting data between host 102 and memory device 150, such as mapped data, read requests, programming requests, etc. According to embodiments, memory 144 may include one or more of a command queue, program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, and mapping buffer / cache. Controller 130 may allocate some storage space in memory 144 for components created to perform data input / output operations. For example, a write buffer created in memory 144 may be used to temporarily store target data to be programmed.

[0098] In embodiments, memory 144 may be implemented using volatile memory. For example, memory 144 may be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 A memory 144 is shown, for example, located within the controller 130, but the embodiment is not limited thereto. The memory 144 may be located inside or outside the controller 130. For example, the memory 144 may be implemented by an external volatile memory having a memory interface for transferring data and / or signals between the memory 144 and the controller 130.

[0099] Processor 134 can control the overall operation of memory system 110. For example, processor 134 can control programming or reading operations of memory device 150 in response to a write or read request input from host 102. According to an embodiment, processor 134 can run firmware to control programming or reading operations in memory system 110. Here, firmware may be referred to as flash translation layer (FTL). (See also...) Figure 3 and Figure 4 Here is a detailed description of an example of FTL. According to an embodiment, processor 134 may be implemented using a microprocessor, a central processing unit (CPU), etc.

[0100] According to an embodiment, the memory system 110 may be implemented using at least one multi-core processor. A multi-core processor is a circuit or chip that integrates two or more cores that are considered different processing regions. For example, the data input / output speed (or performance) of the memory system 110 can be improved when multiple cores in the multi-core processor independently drive or run multiple flash translation layers (FTLs). According to an embodiment, data input / output (I / O) operations in the memory system 110 can be performed independently by different cores in the multi-core processor.

[0101] The processor 134 in the controller 130 can execute operations corresponding to requests or commands input from the host 102. Furthermore, the memory system 110 can execute operations independent of commands or requests input from the host 102. In one case, operations executed by the controller 130 in response to requests or commands input from the host 102 can be considered foreground operations, while operations executed by the controller 130 independently of requests or commands input from the host 102 can be considered background operations. The controller 130 can perform foreground or background operations to read, write, or erase data in the memory device 150. Additionally, parameter setting operations corresponding to setting parameter commands or setting feature commands that are set commands transmitted from the host 102 can be considered foreground operations. Background operations that can be executed by the controller 130 without commands transmitted from the host 102 include garbage collection (GC), wear leveling (WL), bad block management for identifying and handling bad blocks, etc.

[0102] According to embodiments, foreground and background operations can both perform substantially similar operations. For example, garbage collection can be considered a foreground operation when the memory system 110 performs garbage collection (e.g., manual GC) in response to a request or command input from the host 102. However, garbage collection can be considered a background operation when the memory system 110 performs garbage collection (e.g., automatic GC) independently of the host 102.

[0103] When the memory device 150 includes multiple dies (or multiple chips), each comprising multiple non-volatile memory cells, the controller 130 can perform parallel processing of multiple requests or commands from the host 102 to improve the performance of the memory system 110. For example, the transmitted requests or commands can be divided into multiple groups, which include at least some of the multiple planes, multiple dies, or multiple chips included in the memory device 150, and these multiple groups of requests or commands can be processed individually or in parallel in each plane, each die, or each chip.

[0104] The memory interface 142 in controller 130 can be connected to multiple dies or chips in memory device 150 via at least one channel and at least one path. When controller 130 distributes and stores data in multiple dies via the channels or paths in response to a request or command associated with multiple pages including non-volatile memory cells, multiple operations corresponding to the request or command can be executed simultaneously or in parallel. This processing method or scheme can be described as an interleaving method. Since operating via an interleaving method increases the data input / output speed of memory system 110, the data I / O performance of memory system 110 can be improved.

[0105] As an example and not a limitation, controller 130 can identify the status of multiple channels (or paths) associated with multiple dies included in memory device 150. Controller 130 can determine the status of each channel or path as, for example, a busy state, a ready state, an active state, an idle state, a normal state, and / or an abnormal state. Controller 130's determination of which channel (and / or data) is passed through can be associated with a physical block address. Controller 130 can reference descriptors passed from memory device 150. Descriptors may include block parameters or page parameters describing certain information about memory device 150. Descriptors may have a predetermined format or structure. For example, descriptors may include device descriptors, configuration descriptors, cell descriptors, etc. Controller 130 can refer to or use descriptors to determine which channel(s)(s)(s) are used to exchange instructions or data.

[0106] Reference Figure 2 The memory device 150 in the memory system 110 may include a plurality of memory blocks 152, 154, and 156. Each of the plurality of memory blocks 152, 154, and 156 includes a plurality of non-volatile memory cells. According to an embodiment, memory blocks 152, 154, and 156 may be a group of non-volatile memory cells that are erased together. Memory blocks 152, 154, and 156 may include a plurality of pages, which are a group of non-volatile memory cells that are read or programmed together.

[0107] According to an embodiment, each memory block 152, 154, 156 may have a highly integrated three-dimensional stacked structure. Furthermore, the memory device 150 may include multiple dies, each die including multiple planes, and each plane including multiple memory blocks 152, 154, 156. The configuration of the memory device 150 may vary depending on the performance of the memory system 110.

[0108] Figure 2 A memory device 150 comprising multiple memory blocks 152, 154, and 156 is shown. Depending on the number of bits that can be stored in a single memory cell, the multiple memory blocks 152, 154, and 156 can be any type of single-level cell (SLC) memory block, multi-level cell (MLC) memory block, etc. An SLC memory block comprises multiple pages implemented by memory cells, each memory cell storing one bit of data. Compared to MLC memory blocks, SLC memory blocks can have higher data I / O operation performance and higher endurance. An MLC memory block comprises multiple pages implemented by memory cells, each memory cell storing multiple bits of data, for example, two or more bits of data. Compared to SLC memory blocks, MLC memory blocks can have a larger storage capacity in the same space. From a storage capacity perspective, MLC memory blocks can be highly integrated.

[0109] According to an embodiment, the memory device 150 may be implemented using MLC memory blocks such as dual-cell (DLC) memory blocks, triple-cell (TLC) memory blocks, quad-cell (QLC) memory blocks, or combinations thereof. A DLC memory block may include multiple pages implemented by memory cells each capable of storing 2 bits of data. A TLC memory block may include multiple pages implemented by memory cells each capable of storing 3 bits of data. A QLC memory block may include multiple pages implemented by memory cells each capable of storing 4 bits of data. In another embodiment, the memory device 150 may be implemented using blocks comprising multiple pages implemented by memory cells each capable of storing five or more bits of data.

[0110] According to an embodiment, the controller 130 can use an MLC memory block included in the memory system 150 as an SLC memory block that stores one bit of data in a memory cell. The data input / output speed of a Multi-Level Cell (MLC) memory block can be slower than that of an SLC memory block. That is, when an MLC memory block is used as an SLC memory block, the margin for read or programmable operations can be reduced. For example, when an MLC memory block is used as an SLC memory block, the controller 130 can perform data input / output operations at a higher speed. Therefore, since MLC memory blocks may require high data input / output speeds to improve the performance of the memory system 110, the controller 130 can use the MLC memory block as an SLC buffer to temporarily store data.

[0111] Furthermore, according to an embodiment, the controller 130 can program data multiple times into a multi-level cell (MLC) without performing an erase operation on a specific MLC memory block included in the memory device 150. Generally, non-volatile memory cells do not support data rewriting. However, the controller 130 can utilize the MLC's ability to store multiple bits of data to program one bit of data into the MLC multiple times. For MLC rewrite operations, when one bit of data is programmed into the MLC, the controller 130 can store the number of programming operations as separate operation information. According to an embodiment, an operation for uniformly equalizing the threshold voltage of the MLC can be performed before programming other one-bit data into the same MLC, each of which already stores one bit of data.

[0112] According to an embodiment, the memory device 150 is implemented as a non-volatile memory such as flash memory, e.g., NAND flash memory, NOR flash memory, etc. In another embodiment, the memory device 150 may be implemented by at least one of the following: programmable ROM (PROM), erasable ROM (EPROM), electrically erasable ROM (EEPROM), phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), phase-change random access memory (PCRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), and spin-transfer torque magnetic random access memory (STT-MRAM), etc.

[0113] Figure 3 A memory device 300 according to an embodiment of the present disclosure is shown. Figure 3 The memory device 300 shown can be understood as being in Figure 2 An embodiment of the memory device 150 shown in the figure.

[0114] Reference Figure 3 The memory device 300 may include at least one memory die. The memory device 300 may receive or output multiple control signals, such as chip enable CE#, command latch enable CLE, address latch enable ALE, write enable WE#, read enable RE#, write protection WP#, and ready / busy R / B#, and receive or transmit data or operation information through channels I / O [7:0] and I / O [15:0]. For example, depending on the connection between the memory device 300 and such... Figure 2 The controller channels of the controller 130 shown (e.g., I / O[7:0], I / O[15:0]) can transmit and receive a predetermined amount of data (e.g., 1 byte (8 bits) or 2 bytes (16 bits)).

[0115] According to an embodiment, the memory device 300 may include multiple pins or pads. For example, multiple control signals CE#, CLE, ALE, WE#, RE#, WP#, and R / B# can be transmitted or received through specially assigned pins. Control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, a write protection signal WP#, and a status signal R / B# indicating a ready or busy state, etc. The control signals CE#, CLE, ALE, WE#, RE#, WP#, and R / B# can be controlled (transmitted and received) by the control circuitry 310 included in the memory device 300.

[0116] The control circuit 310 can perform preset operations in response to commands and addresses input to the memory device 300. For example, when a read command is received, the control circuit 310 can manage and control the components in the memory device 300 to sequentially execute operations or tasks corresponding to the read command. Furthermore, when... Figure 2 When the controller 130 shown transmits a command to check the operating state of the memory device 300, the control circuit 310 can check information about the operating state and output that information to the controller 130. The control circuit 310 can be configured to, in response to an input command or interrupt, execute an operation or task corresponding to a specific command or interrupt according to a preset program, and then transmit the result of the operation or task.

[0117] The memory device 300 may include input / output (I / O) control circuitry 320. The I / O control circuitry 320 may be connected to other devices or components (e.g., a controller) via channels I / O [7:0] and I / O [15:0]. The I / O control circuitry 320 in the memory device 300 may be connected to multiple registers 372, 374, 376 and a cache register 340 connected to the cell array 330.

[0118] According to an embodiment, the input / output control circuit 320 may include a chip selection decoder, while the memory device 300 may include multiple memory chips. The chip selection function can be used to activate one of the multiple memory chips included in or connected to the memory system or data processing system. According to an embodiment, the chip selection decoder can be implemented using combinational logic gates that activate a specific output line in response to an input binary code. The memory system or data processing system can use the activated output line to activate or "select" a specific chip or device among the multiple devices connected to the memory system or data processing system. For example, if multiple memory chips (e.g., flash memory chips in a solid-state drive (SSD)) exist on the same bus, it is impossible to communicate with all memory chips simultaneously for most operations, as data entries or commands sent via the bus may be routed to all memory chips. Instead, a chip selection signal can be used to select which chip to communicate with at any given time. The chip selection decoder can manage and control data communication between multiple devices (e.g., multiple memory chips) sharing the same bus or connection line in the system by activating a specific device based on an input selection code or signal.

[0119] According to an embodiment, the memory device 300 may include a cache register 340, an address register 372, a status information register 374, and a command register 376. The cache register 340 may temporarily store data. When the memory device 300 performs a read operation, the cache register 340 may store read data entries output from the cell array 330. When the memory device 300 performs a write operation or a programming operation, the cache register 340 may store write data entries. The address register 372 may store an address indicating the location in the cell array 330 where a read or write operation is to be performed. The command register 376 may store commands to be executed by the memory device 300. The status information register 374 may store status information, such as the result (failure / success) of an operation performed in the memory device 300 or the preparation status of the operation. For example, when the memory die in the memory device 300 includes multiple memory planes, the status information register 374 may store status information about each of the multiple memory planes. Data, commands, and information sent or received by the input / output control circuit 320 in the memory device 300 can be controlled by the control circuit 310 (e.g., sent, moved, or output).

[0120] During a read operation of memory device 300, row decoder 334 and column decoder 332 can select one or more memory cells in cell array 330 based on the address stored in address register 372 and control signals from control circuit 310. During the read operation, read data entries output from cell array 330 can be stored in data register 338 and then transferred from data register 338 to cache register 340. Read data entries stored in cache register 340 can be transferred to input / output control circuit 320 via input / output lines. Read data entries transferred to input / output control circuit 320 can be output to controller via channels I / O [7:0] and I / O [15:0].

[0121] During a write or programming operation of the memory device 300, the row decoder 334 and column decoder 332 can select one or more memory cells in the cell array 330 in response to an address stored in the address register 372 and a control signal from the control circuit 310. During a write operation, write data entries transferred from the controller to the input / output control circuit 320 via channels I / O [7:0] and I / O [15:0] can be stored in the cache register 340. Subsequently, the write data entry can be transferred from the cache register 340 to the data register 338. The write data entry stored in the data register 338 can be programmed by the control circuit 310 into the selected memory cell in the cell array 330.

[0122] Data register 338 and cache register 340 may be included in read / write circuitry including a sense amplifier, page buffer, etc. According to an embodiment, a page buffer or data latch included in the memory device 300 may correspond to data register 338 and / or cache register 340. Furthermore, cache register 340 is configured to temporarily store data transferred between data register 338 and input / output control circuitry 320. According to an embodiment, cache register 340 may have a pipe latch structure.

[0123] A pipelined (or pipelining) system including at least one pipe latch may include means capable of processing multiple data entries of serial input and output in parallel. According to an embodiment, the pipelined system is adapted to input / output control circuitry 320 or cache register 340. Further, according to an embodiment, the pipelined system can be used to compensate for latency and noise that occur during data transmission as the data transmission path in the memory device 300 within the memory system becomes longer.

[0124] Figure 3 The cell array 330 shown can have a two-dimensional or three-dimensional structure. The various structures of the cell array 330 and the operations of programming or verifying programmed data in the multiple memory cells included in the cell array 330 will be described in detail below.

[0125] Figure 4 A semiconductor device according to an embodiment of the present disclosure is shown.

[0126] Reference Figure 4 The semiconductor device may include a high-level voltage source circuit 210, a switching circuit 230, control logic 220, and a target circuit 240. Here, the target circuit 240, designed based on the semiconductor device, can perform internal operations using a high-level voltage VPP. Examples of the target circuit 240 capable of performing internal operations by receiving a high-level voltage VPP or a large current include memory devices, memory systems, charging devices, power supply devices, or drive devices included or used in household appliances, automobiles, communications, and industries.

[0127] The high-level voltage source circuit 210 can output a high-level voltage VPP that is several times (e.g., 3 to 4 times) or higher than the power supply voltage VCC. According to one embodiment, the high-level voltage source circuit 210 can receive the high-level voltage VPP from an external source (e.g., an external device) and transmit it to the switching circuit 230. In another embodiment, the power supply voltage VCC is input to the high-level voltage source circuit 210, which can utilize (e.g., pump) the power supply voltage VCC to generate the high-level voltage VPP.

[0128] Switching circuit 230 can determine whether to transmit the high-level voltage VPP from high-level voltage source circuit 210 to target circuit 240. Switching circuit 230 can determine whether to transmit the high-level voltage VPP in response to control signal CS output by control logic 220. According to an embodiment, switching circuit 230 may include... Figure 1 The PMOS transistor is shown in the figure. In another embodiment, the switching circuit 230 may include multiple transistors. See below for reference. Figure 7 Describe the internal configuration of the switching circuit 230.

[0129] Control logic 220 can output a control signal CS for controlling the switching circuit 230. According to an embodiment, control logic 220 can apply a power supply voltage VCC and a ground voltage GND. The level of the control signal CS output by control logic 220 can swing or switch between a first voltage level VLV and a second voltage level VHV. According to an embodiment, the level of the control signal CS can swing or switch between a ground voltage level GND and a second voltage level VHV. Control logic 220 can adaptively adjust the level of the control signal CS.

[0130] For example, the switching circuit 230 may include a PMOS transistor. The PMOS transistor can be turned off by a control signal CS having a second voltage level VHV. When the PMOS transistor is turned off, the switching circuit 230 may not transmit a high-level voltage VPP to the target circuit 240. Conversely, the PMOS transistor can be turned on by a control signal CS having a ground voltage level GND or a first voltage level VLV. When the PMOS transistor is turned on, the switching circuit 230 can transmit a high-level voltage VPP to the target circuit 240.

[0131] Reference Figure 1 and Figure 4When a PMOS transistor is turned on via ground voltage level GND and transmits a high-level voltage VPP, negative bias temperature instability (NBTI) may occur. Therefore, control logic 220 can use a first voltage level VLV instead of ground voltage level GND to turn on the PMOS transistor switched to the high-level voltage VPP. The first voltage level VLV can be lower than the second voltage level VHV. According to an embodiment, the first voltage level VLV can be greater than ground voltage level GND and less than 10% of the high-level voltage VPP level. For example, when the supply voltage VCC level is in the range of 2.5V to 5V, the high-level voltage VPP level can be 20V or higher. In this case, the second voltage level VHV can be substantially equal to the supply voltage VCC level, while the first voltage level VLV can be greater than 0V and less than 2V. By using the first voltage level VLV instead of ground voltage level GND, the voltage between the gate and source of the PMOS transistor (e.g., Vgs) can be reduced. This approach reduces the negative bias temperature instability (NBTI) effect that occurs in the PMOS transistor.

[0132] According to an embodiment, the first voltage level VLV can be adjusted based on the level of the power supply voltage VCC and the level of the high-level voltage VPP. Control logic 220 can adjust the first voltage level VLV in response to the level of the high-level voltage VPP output from the high-level voltage source circuit 210, and then output the first voltage level VLV to the switching circuit 230.

[0133] Figure 5 A memory device 150 comprising a memory cell array circuit formed in a memory die is shown according to an embodiment of the present disclosure.

[0134] Reference Figure 5 The memory device 150 may include at least one memory bank 330 having a plurality of cell strings 340. Each cell string 340 may include a plurality of non-volatile memory cells MC0 to MCn-1, which are connected to corresponding bit lines in a plurality of bit lines BL0 to BLm-1. The cell strings 340 are arranged in corresponding columns of the memory bank 330, and each cell string 340 may include at least one drain-select transistor (DST) and at least one source-select transistor (SST). The non-volatile memory cells MC0 to MCn-1 of each cell string 340 may be connected in series between the drain-select transistor DST and the source-select transistor SST. Each of the non-volatile memory cells MC0 to MCn-1 may be configured as a multi-level cell (MLC) storing a data item with multiple bits of data per cell. The cell string 340 may be electrically connected to corresponding bit lines in the bit lines BL0 to BLm-1.

[0135] In one embodiment, memory group 330 may include NAND flash memory cells MC0 to MCn-1. In another embodiment, memory group 330 may be implemented as NOR flash memory, a hybrid flash memory combining or mixing at least two different types of memory cells, or a monolithic NAND flash memory with the controller embedded in a single memory chip. In another embodiment, memory group 330 may include flash memory cells including charge-fed flash memory (CTF) layers with conductive floating gates or insulating layers.

[0136] According to an embodiment, Figure 5 The illustrated memory device 150 may include at least one memory block. The memory group 330 may have a two-dimensional (2D) or three-dimensional (3D) structure. For example, each of the memory blocks in the memory device 150 may be implemented as a three-dimensional structure, such as a vertical structure. Each of the memory blocks may have a three-dimensional structure extending along a first direction to a third direction (e.g., the x-axis, y-axis, and z-axis directions).

[0137] A memory bank 330, including at least one memory block, can be coupled to multiple bit lines BL, multiple string select lines SSL, multiple drain select lines DSL, multiple word lines WL, multiple virtual word lines DWL, and multiple common source lines CSL. In an embodiment, the memory bank 330 may include multiple NAND strings NS, for example, these NAND strings may each correspond to a cell string 340. Each NAND string NS may include multiple memory cells MC and may be connected to corresponding bit lines in the bit lines BL. Furthermore, the source select transistor SST of each NAND string NS may be connected to the common source line CSL, and the drain select transistor DST of each NAND string NS may be connected to the corresponding bit line BL. In each NAND string NS, the memory cells MC may be arranged between the source select transistor SST and the drain select transistor DST.

[0138] The memory device 150 may include a voltage supply circuit 170 that supplies word line voltages to individual word lines according to an operating mode, such as one or more predetermined voltages, including programming voltage, read voltage, and pass voltage, or it may supply voltage to a memory bank (e.g., a well region) forming each memory block including memory cells MC. In this case, the voltage generation operation of the voltage supply circuit 170 may be performed under the control of the control circuit 180. Furthermore, the voltage supply circuit 170 may generate multiple variable read voltages to distinguish multiple data items from each other.

[0139] In response to the control of the control circuit 180, one of the memory blocks (or sectors) of the memory cell array can be selected, and one of the word lines of the selected memory block can be selected. Word line voltages can be supplied to the selected and unselected word lines of the memory bank 330, respectively. The voltage supply circuit 170 may include a voltage generation circuit for generating target voltages of various levels suitable for the word lines of the memory bank 330.

[0140] Reference Figure 5 Between the voltage supply circuit 170 and at least one drain select line DSL, at least one source select line SSL, and multiple word lines WL0 to WLn-1 in the cell array 330, the memory device 150 may further include a switch 174. According to an embodiment, the switch 174 may be included in the voltage supply circuit 170.

[0141] Switch 174 can be operated based on a control signal that swings to different levels in response to voltage levels output from voltage supply circuit 170 to multiple word lines WL0 to WLn-1. According to an embodiment, switch 174 can correspond to... Figure 4 The switching circuit 230 is shown in the diagram. For example, when switch 174 transmits a high-level voltage, such as a programming voltage, erase voltage, or pass voltage, to multiple word lines WL0 to WLn-1, the control signal of switch 174 can swing between a first voltage level VLV and a second voltage level VHV. When switch 174 transmits a low-level read voltage to multiple word lines WL0 to WLn-1, the control signal of switch 174 can swing between a ground voltage level GND and a second voltage level VHV.

[0142] The memory device 150 may further include a read / write circuitry 320 controlled by control circuitry 180. The read / write circuitry 320 may operate as a sense amplifier or a write driver depending on the operating mode. For example, in verification and read operations, the read / write circuitry 320 may operate as a sense amplifier for reading data items from the memory cell array. In programming operations, the read / write circuitry 320 may operate as a write driver controlling the potential of bit lines based on the data items to be stored in the memory cell array. During programming operations, the read / write circuitry 320 may receive data items to be programmed into the cell array from page buffers. The read / write circuitry 320 may drive bit lines based on the input data items. For this purpose, the read / write circuitry 320 may include a plurality of page buffers (PB) 322, 324, 326, each page buffer corresponding to each column or each bit line, or each column pair or each bit line pair. According to an embodiment, each of the page buffers 322, 324, 326 may include a plurality of latches. According to an embodiment, the number of latches or page buffers connected to each bit line can be equal to or greater than the number of bits of data stored in the memory cell MC.

[0143] Page buffers 322, 324, and 326 can be connected to data input / output devices, such as serial circuits or serializers, via multiple buses. When each of page buffers 322, 324, and 326 is connected to a data input / output device via a different bus, potential latency during data transfer from page buffers 322, 324, and 326 can be reduced. For example, each page buffer 322, 324, and 326 can perform data transfer without waiting time.

[0144] According to an embodiment, the memory device 150 can receive a write command, write data, and information about the location (e.g., physical address) where the write data is to be stored. The control circuit 180 causes the voltage supply circuit 170 to generate programming pulses, pass voltages, etc., for a programming operation performed in response to the write command, and to generate one or more voltages for a verification operation performed after the programming operation.

[0145] When multiple data items are programmed into the non-volatile memory cells included in memory bank 330, the error rate may be higher than when a single data item is stored in a non-volatile memory cell. For example, errors in non-volatile memory cells may be caused by inter-cell interference (CCI). To reduce errors in non-volatile memory cells, the width (deviation) of the threshold voltage distribution corresponding to the data items stored between non-volatile memory cells should be reduced.

[0146] To this end, the memory device 150 can perform incremental step pulse programming (ISPP) operations to effectively narrow the threshold voltage distribution of the non-volatile memory cells. In embodiments, the memory device 150 can use the ISPP operation for multi-step programming operations. For example, the memory device 150 can divide the programming operation into least significant bit (LSB) programming operations and most significant bit (MSB) operations according to a predetermined order between non-volatile memory cells or pages.

[0147] Multi-bit values ​​programmed into memory cells of NAND flash memory (e.g., NAND flash memory cells MC0 to MCn-1 in memory bank 330) can be determined based on the threshold voltage window or threshold voltage distribution to which the cell's threshold voltage belongs. As the size of each memory cell shrinks and more bits of data are programmed into each memory cell (e.g., 3, 4, or 5 bits), the width of the threshold voltage window used to represent each multi-bit value becomes narrower, thus increasing the error rate in determining the multi-bit value stored in the memory cell. This is because as the amount of charge stored in each memory cell decreases with feature size, process variations become more prevalent, leading to significant differences in the threshold voltages of different memory cells storing the same value. Therefore, it becomes increasingly difficult to determine which value the threshold voltage of a memory cell corresponds to.

[0148] According to an embodiment, control circuitry 180 may include a read retry table (RRT). The RRT may be stored in memory device 150. Read errors may occur during the process of applying a read voltage to a non-volatile memory cell in memory device 150 via a word line and reading data stored in that non-volatile memory cell. Control circuitry 180 in memory device 150 may manage information related to a read retry mechanism for resolving read errors. One piece of information related to this read retry mechanism is the read RRT. The read retry mechanism utilizes the RRT value at the recorded location of the error so that memory device 150 can ensure data integrity upon rereading by applying an appropriate correction value (e.g., changing the read voltage level).

[0149] Figure 6 Operation of a first switching device according to an embodiment of the present disclosure is shown.

[0150] Reference Figure 6 The first switching device 230A may include a PMOS transistor. The first switching device 230A can transmit a high-level voltage VPP in response to a first inverting control signal ENH_N. Here, the level of the high-level voltage VPP can be several times higher than the supply voltage. For example, when the supply voltage is 3.5V, the high-level voltage VPP can be 28V.

[0151] The first control signal ENH for controlling the first switching device 230A can be switched or oscillated from the ground voltage level GND to the second voltage level VHV, or from the second voltage level VHV to the ground voltage level GND. The level of the second voltage level VHV can be approximately 3.5V. The first inverted control signal ENH_N, which is an inverted version of the first control signal ENH, can be applied to the gate of the PMOS transistor in the first switching device 230A.

[0152] The PMOS transistor in the first switching device 230A can be turned on by a first inverted control signal ENH_N with a ground voltage level GND, and turned off by a first inverted control signal ENH_N with a second voltage level VHV.

[0153] When a 0V ground voltage level GND is applied to the gate GATE of the PMOS transistor and the PMOS transistor is turned on, the performance of the first switching device 230A may be degraded due to the negative bias temperature instability (NBTI) effect because a high-level voltage VPP is applied or biased to the junction and well regions of the PMOS transistor for a long time. This effect cannot be ignored.

[0154] Figure 7 The configurations of a second and a third switching device according to embodiments of the present disclosure are shown. Specifically, Figure 7 The differences in negative bias temperature instability (NBTI) effects observed in a second switching device (first scheme) and a third switching device (second scheme) with different configurations are shown.

[0155] Reference Figure 7 The second switching device (first scheme) may include a second control circuit 220B and a second switching unit 230B.

[0156] The second control circuit 220B can output a first control signal ENH and a first inverted control signal ENH_N to the second switching unit 230B. The second switching unit 230B can determine whether to transmit a high-level voltage VPP in response to the first control signal ENH and the first inverted control signal ENH_N.

[0157] Here, the first control signal ENH and the first inverting control signal ENH_N can have logic states that are inverses of each other. Furthermore, the voltage level of the high-level voltage VPP can be several times the second voltage level VHV. The level of the second voltage level VHV can be... Figure 4 The power supply voltage levels VCC shown are basically the same.

[0158] The second switching unit 230B may include multiple transistors 232B, 234B, and 236B. The second switching unit 230B may include a loop circuit activated in response to a first inverting control signal ENH_N, and a switch 238B configured to discharge the loop circuit in response to the first control signal ENH. For example, the loop circuit may include one PMOS transistor 234B and two NMOS transistors 232B and 236B. According to an embodiment, the PMOS transistor 234B configured to determine whether to transmit a high-level voltage VPP in response to the first inverting control signal ENH_N may have a threshold voltage V of 2.57V. TH In the two NMOS transistors 232B and 236B, transistor 232B can operate at a threshold voltage V of 3.5V. TH To determine whether to transmit the high-level voltage VPP to the PMOS transistor, another transistor 236B may have an output terminal connected to the gate, allowing the high-level voltage VPP to be stably output through this output terminal. The second switching unit 230B may include a switch 238B configured to selectively connect the first control signal ENH and the loop circuit in response to a second voltage level VHV. Switch 238B may include a threshold voltage V with a threshold voltage V of 0.8V. TH The PMOS transistor. See below for reference. Figure 8 Describe the specific operation of the second switching unit 230B.

[0159] The second control circuit 220B may include at least one logic gate or at least one element. For example, the output of the second control circuit 220B may include a NAND gate 222B. Power supply voltage level VCC and ground voltage level GND can be applied to the output of the second control circuit 220B, and the level of the first inverted control signal ENH_N output by the second control circuit 220B can be either power supply voltage level VCC or ground voltage level GND. That is, the first inverted control signal ENH_N can be switched from power supply voltage level VCC to ground voltage level GND, or vice versa.

[0160] Reference Figure 7 The third switching device (second embodiment) can adopt a structure that improves upon the second switching device (first embodiment). The third switching device (second embodiment) may include a third control circuit 220C and a third switching unit 230C. The third switching unit 230C may include a configuration substantially the same as that of the second switching unit 230B. Reference will be made below. Figure 8 Describe the configuration and operation of the third switching unit 230C.

[0161] The third control circuit 220C may have a different structure than the second control circuit 220C. The third control circuit 230C may include at least one logic gate or at least one element. For example, the output of the third control circuit 220C may include a NAND gate 222C. The NAND gate 222C may be connected to the ground voltage switch 224C and the first voltage switch 226C.

[0162] Ground voltage switch 224C can transmit a ground voltage level GND to NAND gate 222C in response to a first selection signal OP1. First voltage switch 226C can transmit a first voltage level VLV to NAND gate 222C in response to a second selection signal OP2. According to an embodiment, each of ground voltage switch 224C and first voltage switch 226C can include an NMOS transistor. The ground voltage level GND can be applied to the body region of the NMOS transistor included in ground voltage switch 224C and first voltage switch 226C.

[0163] In response to the activation of the first selection signal OP1 and the second selection signal OP2, the swing range of the first inverting control signal ENH_N output from NAND gate 222C can change. For example, when the first selection signal OP1 is activated, the first inverting control signal ENH_N can switch from the power supply voltage level VCC to the ground voltage level GND, or from the ground voltage level GND to the power supply voltage level VCC. When the second selection signal OP1 is activated, the first inverting control signal ENH_N can switch from the power supply voltage level VCC to the first voltage level VLV, or from the first voltage level VLV to the power supply voltage level VCC.

[0164] According to the embodiment, only one of the first selection signal OP1 and the second selection signal OP2 can be activated. For example, the first selection signal OP1 and the second selection signal OP2 can be signals that are opposite in phase to each other.

[0165] Furthermore, according to the embodiment, the first selection signal OP1 or the second selection signal OP2 can only be activated when the third control circuit 230C outputs the first control signal ENH or the first inverted control signal ENH_N.

[0166] Figure 8 It shows in Figure 7 The operation of the third switching device is shown in the diagram. Specifically, Figure 8 The operation of the third switching unit 230C is shown when the first inverting control signal ENH_N changes from the second voltage level VHV to the ground voltage level GND (e.g., 0V) or from the ground voltage level GND (e.g., 0V) to the second voltage level VHV in response to the first selection signal OP1.

[0167] Reference Figure 8 When the first inverting control signal ENH_N is 0V, i.e., the same as the ground voltage level GND, the third switching unit 230C can be switched to the On state to transmit the high-level voltage VPP. Conversely, when the first inverting control signal ENH_N is the second voltage level VHV, the third switching unit 230C can be switched to the Off state, in which case it may not transmit the high-level voltage VPP. The operation of the third switching unit 230C can be controlled by the potential V of the loop circuit. G, DHVN The change is described by the voltage level. In the On Status, the first control signal ENH can be the second voltage level VHV. The switch 238C of the third switching unit 230C can be turned on by the second voltage level VHV, and the first control signal ENH of the second voltage level VHV can be connected to the loop circuit. The potential V of the loop circuit G, DHVN This can be achieved by subtracting the threshold voltage V of switch 238C from the second voltage level VHV. TH, HN_AS The obtained value (=VHV - V) TH, HN_AS (Operation 262). When the potential V of the loop circuit G, DHVN This becomes the difference (=VHV - V) TH, HN_AS When ), the NMOS transistor 232C is turned on, and the potential V of the loop circuit is... G, DHVN The value V transmitted by the NMOS transistor 232C can be increased. TH, DHVN (Operation 264). According to the embodiment, the high-level voltage VPP can be greater than 28.8V, the body voltage of the NMOS transistor 232C can be the internal ground voltage VSS, and the threshold voltage V of the NMOS transistor 232C is... TH It can be -3.5V.

[0168] As the potential V of the loop circuit... G, DHVN Increase the voltage V between the source and gate of the PMOS transistor 234C. GS, HVP It becomes greater than the threshold voltage V of the PMOS transistor 234C. TH, HVP The same voltage level can be applied to both the source and body regions of the PMOS transistor 234C. The breakdown voltage V of the PMOS transistor 234C... BVDSS It may be greater than 9V, and the threshold voltage V of the PMOS transistor 234C is... TH It can be -2.6V. When the voltage V between the gate and source of the PMOS transistor 234C... GS, HVP It becomes greater than the threshold voltage V of the PMOS transistor 234C. TH, HVP (For example, |V) GS, HVP |<|V TH, HVPWhen |), the PMOS transistor 234C can be turned on. Therefore, the potential V of the loop circuit. G, DHVN It can be further increased (operation 266).

[0169] The potential V of the loop circuit G, DHVN Further increase, and the potential V of the loop circuit G, DHVN It can reach a high-level voltage VPP (operation 268). This is because the breakdown voltage V of switch 238C... BVDSS The voltage is 28.8V or higher (e.g., greater than or equal to the high-level voltage VPP), so the potential V of the loop circuit is... G, DHVN It is unlikely to leak or discharge through the 238C switch. This scheme can support the loop circuit potential V during the On Status. G, DHVN Increase.

[0170] In the Off Status, the first inverting control signal ENH_N can transition to the second voltage level VHV. When the first inverting control signal ENH_N transitions from ground voltage (e.g., 0V) to the second voltage level VHV, the current flowing through the PMOS transistor 234C may decrease. When the voltage V between the gate and source of the PMOS transistor 234C... GS, HVP It becomes less than the threshold voltage V of the PMOS transistor 234C. TH, HVP (For example, |V) GS, HVP |<|V TH, HVP When |), the PMOS transistor 234C can be turned off.

[0171] In addition, the first control signal ENH, which has a ground voltage level (e.g., 0V), is transmitted through switch 238C (V S, HN_AS A voltage (VPP) is connected to the loop circuit, thereby forming a path (e.g., a discharge path) through which the potential of the loop circuit can be discharged. In this way, the potential of the loop circuit can be reduced from a high-level voltage VPP to a ground voltage level (e.g., 0V).

[0172] Figure 8 The diagram illustrates the transition of the first inverting control signal ENH_N from the second voltage level VHV to the ground voltage level GND or vice versa. The operation of the second switching device (first scheme) and the third switching device (second scheme) will be compared and described below as the swing range of the first inverting control signal ENH_N varies.

[0173] Figure 9 The operation of a second switching device and a third switching device according to embodiments of the present disclosure is illustrated. Specifically, Figure 9The operation of a second switching device (first scheme) based on a first inverting control signal ENH_N, which switches from a second voltage level VHV to a ground voltage level GND or from a ground voltage level GND to a second voltage level VHV, is compared and illustrated. The operation of a third switching device (second scheme) based on a first inverting control signal ENH_N, which switches from a second voltage level VHV to a first voltage level VLV or from a first voltage level VLV to a second voltage level VHV, is also compared and illustrated.

[0174] Reference Figure 9 The first inverting control signal ENH_N used in the second switching device (first scheme) can be switched from the second voltage level VHV to the ground voltage level GND, or from the ground voltage level GND to the second voltage level VHV. The first control signal ENH can have a logic value opposite to that of the first inverting control signal ENH_N. Similar to the first inverting control signal ENH_N, the first control signal ENH can be switched from the ground voltage level GND to the second voltage level VHV, or from the second voltage level VHV to the ground voltage level GND. Here, the second voltage level VHV can be equal to or less than 3.5V, and the high-level voltage VPP can be equal to or less than 28V.

[0175] Reference Figure 1 as well as Figures 7 to 9 The negative bias temperature instability (NBTI) effect may occur in the PMOS transistor 234B included in the second switching device (first scheme), which may degrade the operating performance of the second switching device (first scheme).

[0176] On the other hand, the first inverting control signal ENH_N used in the third switching device (second scheme) can be switched from the second voltage level VHV to the first voltage level VLV, or from the first voltage level VLV to the second voltage level VHV. Here, the first voltage level VLV can be at a level greater than 0V and less than 2V, relative to the ground voltage GND. Furthermore, the first control signal ENH can have a logic value opposite to that of the first inverting control signal ENH_N, but the first control signal ENH can be switched from the ground voltage level GND to the second voltage level VHV, or from the second voltage level VHV to the ground voltage level GND. That is, the first control signal ENH and the first inverting control signal ENH_N have opposite logic values, but their voltage swing ranges may be different. Here, the second voltage level VHV can be equal to or less than 3.5V, and the high-level voltage VPP can be equal to or less than 28V.

[0177] Reference Figure 1 as well as Figures 7 to 9The negative bias temperature instability (NBTI) effect in the PMOS transistor 234C included in the third switching device (second scheme) can be mitigated, reduced or avoided, thereby avoiding the deterioration of the operating performance of the third switching device (second scheme) or maintaining the operating performance of the third switching device (second scheme).

[0178] According to an embodiment, the first voltage level VLV may have a level that can be adaptively adjusted in response to the levels of the power supply voltage VCC and the high-level voltage VPP.

[0179] Figure 10 First simulation results of variations in the output of a switching device according to an embodiment of the present disclosure are shown. Specifically, Figure 10 The results of the operation (e.g., the switching / operating speed of the switching device) are shown when the output of the switching device (e.g., the drain of the PMOS transistor 234C included in the third switching unit 230C) rises from the ground voltage GND to the high-level voltage VPP.

[0180] Reference Figure 10 The diagram illustrates the operating speed at which the output of the switching device reaches the high-level voltage VPP from ground voltage GND when the voltage swing range of the first inverting control signal ENH_N applied to the gate of the PMOS transistor 234C included in the third switching unit 230C is different (e.g., estimated by adding three times the standard deviation to the average value (e.g., 3-sigma scan simulation)). Figure 10 Five examples are shown, including: a first case where the first inverting control signal ENH_N switches between ground voltage level GND and a second voltage level VHV; a second case where the first inverting control signal ENH_N switches between a first voltage level VLV and 1V, which is the second voltage level VHV; a third case where the first inverting control signal ENH_N switches between a first voltage level VLV and 1.2V, which is the second voltage level VHV; a fourth case where the first inverting control signal ENH_N switches between a first voltage level VLV and 1.5V, which is the second voltage level VHV; and a fifth case where the first inverting control signal ENH_N switches between a first voltage level VLV and 1.8V, which is the second voltage level VHV.

[0181] When the first inverting control signal ENH_N transitions between the ground voltage level GND and the second voltage level VHV, the operating margin of the switching device transmitting the high-level voltage VPP can be set from the first time point t0 to the second time point t1. For example, the duration from the first time point t0 to the second time point t1 is approximately 43.5 ns. In the five cases described above, the operating margin of the switching device can be satisfied when the first voltage level VLV is greater than 0V and less than 1.2V. However, when the first voltage level VLV is 1.5V or 1.8V, whether the operating margin of the switching device can be satisfied depends on the transition speed of the first inverting control signal ENH_N.

[0182] Figure 11 A second simulation result showing the variation of the output of the switching device according to an embodiment of the present disclosure is presented. Specifically, Figure 11 The operational result (e.g., the operating speed of the switching device) is shown as the process by which the output of the switching device (e.g., the drain region of the PMOS transistor 234C included in the third switching unit 230C) rises from a negative voltage level below ground voltage level GND to a high voltage level VPP.

[0183] Reference Figure 11 When the voltage swing range of the first inverted control signal ENH_N applied to the gate of the PMOS transistor 234C included in the third switching unit 230C is different, the operating speed of the drain region of the PMOS transistor 234C in the third switching unit 230C from the negative voltage level to the high voltage VPP may vary based on the different delays of the first inverted control signal ENH_N and the PMOS transistor 234C (e.g., estimated by adding three times the standard deviation to the average value (e.g., 3-sigma scan simulation)). Figure 10 Four scenarios are shown, including: the first scenario, where the first inverting control signal ENH_N switches between ground voltage level GND and second voltage level VHV; the second scenario, where the first inverting control signal ENH_N switches between a first voltage level VLV of 1.5V and a second voltage level VHV; the third scenario, where the first inverting control signal ENH_N switches between a first voltage level VLV of 1.8V and a second voltage level VHV; and the fourth scenario, where the first inverting control signal ENH_N switches between a first voltage level VLV and a second voltage level VHV of 2.0V.

[0184] When the first inverting control signal ENH_N switches between the ground voltage level GND and the second voltage level VHV, the operating margin of the switching device that transmits the high-level voltage VPP can be set from the first time point t0 to the second time point t1. For example, the duration from the first time point t0 to the second time point t1 is approximately 106 ns.

[0185] Of these four cases, compared to the case with ground voltage level GND, the operating margin of the switching device may not differ significantly when the first voltage level VLV is 1.5V. However, when the first voltage level VLV is 1.8V or 2.0V, whether the operating margin of the switching device can be satisfied depends on the switching speed of the first inverting control signal ENH_N.

[0186] Reference Figure 10 and Figure 11 By statistically estimating the delay in the third switching device (second scheme), the swing range of the first inverting control signal ENH_N, which satisfies the operating margin of the third switching device (second scheme) while mitigating the negative bias temperature instability (NBTI) effect, can be identified. According to an embodiment, the first voltage level VLV can be set to 10% or less of the high-level voltage VPP. Furthermore, in another embodiment, when the first voltage level VLV is set to less than 5-6% of the high-level voltage VPP, both the operating margin of the third switching device (second scheme) and the negative bias temperature instability (NBTI) effect can be satisfied.

[0187] As described above, according to embodiments of the present disclosure, a semiconductor device, memory device, or memory system can reduce the potential difference between the gate and the junction of a switching device by adjusting the signal potential of a switching device configured to transmit a high-level voltage at least three times or higher than the supply voltage, thereby reducing the negative bias temperature instability (NBTI) effect—a degradation phenomenon.

[0188] According to embodiments of this disclosure, semiconductor devices, memory devices, or memory systems can avoid or mitigate the negative bias temperature instability (NBTI) effect of switching devices, thereby having the advantage of reducing or avoiding performance degradation of switching devices.

[0189] The methods, processes, and / or operations described herein can be executed by code or instructions that run on a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be the apparatus described herein, or an element other than those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the methods can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0190] Furthermore, another embodiment may include a computer-readable medium, such as a non-transitory computer-readable medium, for storing the aforementioned code or instructions. The computer-readable medium may be volatile or non-volatile memory or other storage devices that may be removably or permanently coupled to a computer, processor, controller, or other signal processing device to execute code or instructions for performing the operations of the method or apparatus embodiments described herein.

[0191] The controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features disclosed herein can be implemented, for example, as non-transient logic, which may include hardware, software, or both. When at least partially implemented as hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features can be, for example, any of a variety of integrated circuits, including but not limited to application-specific integrated circuits, field-programmable gate arrays, combinations of logic gates, systems-on-a-chip, microprocessors, or other types of processing or control circuitry.

[0192] When implemented at least partially as software, controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be the device described herein or an element other than those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions used to implement the operations of the method embodiments can convert the computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods described herein.

[0193] While embodiments of the present disclosure have been shown and described with reference to specific examples, it will be apparent to those skilled in the art that various changes and modifications may be made to the embodiments without departing from the spirit and scope of the disclosure as defined in the claims. Furthermore, embodiments may be combined to form other embodiments.

Claims

1. A memory device, comprising: The switching unit determines whether to transmit a high-level voltage that is at least three times or higher than the power supply voltage; as well as The control element generates a first control signal that switches between a first voltage level and a second voltage level to control the switching unit. Wherein, the first voltage level is equal to the level of the power supply voltage, and The second voltage level is greater than 0V and less than 10% of the high voltage level.

2. The memory device according to claim 1, further comprising: At least one memory unit for storing data; A word line, connected to the at least one memory cell, is used to apply the high-level voltage transmitted through the switching unit; as well as The voltage generation circuit outputs the high-level voltage.

3. The memory device according to claim 1, wherein, The switching unit includes a PMOS transistor, and The first control signal, having either the first voltage level or the second voltage level, is applied to the gate of the PMOS transistor.

4. The memory device according to claim 3, wherein, A first control signal having the first voltage level is used to turn on the PMOS transistor, and a first control signal having the second voltage level is used to turn off the PMOS transistor.

5. The memory device according to claim 1, wherein, The power supply voltage range is 2.5V to 5V; The high-level voltage is 20V or higher; and The second voltage level is greater than 0V and less than 2V.

6. The memory device according to claim 1, wherein, The second voltage level can be adjusted based on the level of the power supply voltage and the level of the high-level voltage.

7. The memory device according to claim 1, wherein, The control element is connected to a switching element, which transmits the second voltage level to the control element in response to a selection control signal.

8. The memory device according to claim 7, wherein, The switching element includes an NMOS transistor.

9. The memory device according to claim 1, wherein, The switching unit includes: The loop circuit includes multiple transistors and is activated in response to the first voltage level; and A switch, in response to a second control signal, discharges the loop circuit.

10. The memory device according to claim 9, wherein, The second control signal has a logic value that is the opposite of the logic value of the first control signal, and The voltage swing ranges of the first control signal and the second control signal are different from each other.

11. A semiconductor device, comprising: The switching unit determines whether to transmit a high-level voltage that is at least three times or higher than the power supply voltage; The control device generates a control signal that switches between a first voltage level and a second voltage level to control the switching unit; as well as A first switch, in response to a first selection control signal, transmits a first low voltage level as the second voltage level to the control device, wherein the first low voltage level is greater than the ground voltage level and less than the high voltage level.

12. The semiconductor device of claim 11, further comprising: The second switch, in response to the second selection control signal, transmits the ground voltage level as the second voltage level to the control device. Either the first selection signal or the second selection signal is activated.

13. The semiconductor device according to claim 12, wherein, Each of the first switch and the second switch includes an NMOS transistor.

14. The semiconductor device according to claim 11, wherein, The first voltage level is equal to the level of the power supply voltage.

15. The semiconductor device according to claim 11, wherein, The switching unit includes a PMOS transistor, and The control signal having the first voltage level or the second voltage level is applied to the gate of the PMOS transistor.

16. The semiconductor device according to claim 15, wherein, A first control signal having the first voltage level is used to turn on the PMOS transistor, and a first control signal having the second voltage level is used to turn off the PMOS transistor.

17. The semiconductor device according to claim 11, wherein, The power supply voltage range is 2.5V to 5V; The high-level voltage is 20V or higher; and The second voltage level is greater than 0V and less than 2V.

18. The semiconductor device according to claim 11, wherein, The second voltage level can be adjusted based on the level of the power supply voltage and the level of the high-level voltage.

19. A non-volatile memory device, comprising: Multiple memory units store data; Word lines connect to the plurality of memory cells; A voltage generator generates at least one of a pass voltage, a programming voltage, and an erase voltage, wherein the level of each of the pass voltage, the programming voltage, and the erase voltage is at least three times or higher than the power supply voltage; A switching unit determines whether to transmit at least one of the through voltage, the programming voltage, and the erase voltage to the word line; as well as The control element generates a control signal that switches between a first voltage level and a second voltage level to control the switching unit. Wherein, the first voltage level is equal to the level of the power supply voltage, and Wherein, the second voltage level is greater than 0V and less than 10% of the level of the high voltage level.

20. The non-volatile memory device according to claim 19, wherein, The switching unit includes a PMOS transistor, and The control signal having the first voltage level or the second voltage level is applied to the gate of the PMOS transistor.

21. The non-volatile memory device according to claim 19, wherein, The second voltage level can be adjusted based on the level of the power supply voltage and the level of the high-level voltage.

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