Memory system, memory controller and method of operating a memory controller

Abstract

According to some example embodiments, a memory system includes a memory device and a memory controller configured to control the memory device, the memory controller including a training circuit configured to generate a plurality of reference pattern data, the plurality of reference pattern data including a plurality of pieces of reference pattern data, the plurality of pieces of reference pattern data being generated by cyclically shifting basic pattern data in units of unit intervals, generate a comparison result by comparing the plurality of reference pattern data with sampling data at the same time, and calculate a center of a window of a data signal based on the comparison result.

Description

[0001] Cross-reference to related applications

[0002] Related Application This application claims priority to Korean Patent Application No. 10-2025-0044275, filed on April 4, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor memory, and for example, to a memory system, a memory controller, and / or a method of operating the memory controller. Background Technology

[0004] Semiconductor memories are divided into volatile memory devices (such as static random access memory (RAM) (SRAM) and dynamic RAM (DRAM)) and non-volatile memory devices (such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM) and ferroelectric RAM (FRAM)). Non-volatile memory devices retain stored data even when the power supply to them is cut off.

[0005] The memory controller and the memory device communicate with each other using data signals. To increase the reliability of data transmission using data signals between the memory controller and the memory device, training can be performed. Training may include parallel data transmission using alignment of data signals and / or arrival timing.

[0006] The memory controller can perform training on the memory device after power-up to compensate for the timing of at least one of the data signals (or DQ signals) transmitted and / or sent via data lines and the data strobe signals (or DQS signals) transmitted and / or sent via data strobe lines to meet optimal alignment conditions and control memory operation. Summary of the Invention

[0007] The present invention provides a memory system, a memory controller, and / or a method for operating the memory controller with improved training speed.

[0008] According to some example embodiments, the memory system includes a memory device and a memory controller configured to control the memory device. The memory controller includes training circuitry configured to generate multiple reference pattern data, the multiple reference pattern data including multiple reference pattern data lines, the multiple reference pattern data being generated by cyclically shifting basic pattern data in units of unit intervals; generating a comparison result by simultaneously comparing the multiple reference pattern data with sampled data; and calculating the center of a window of data signals based on the comparison result.

[0009] According to some example embodiments, a method of operating a memory controller includes: generating a plurality of reference pattern data by cyclically shifting basic pattern data in unit intervals, generating a comparison result by comparing sampled data with the plurality of reference pattern data simultaneously by repeatedly performing sub-training operations, and calculating the center of a window of a data signal based on the comparison result.

[0010] According to some example embodiments, a memory controller is configured to control a memory device. The memory controller includes a training circuit, which includes a pattern generator and a comparator cluster. The pattern generator is configured to generate multiple reference pattern data by cyclically shifting basic pattern data in unit intervals. The comparator cluster includes multiple comparators, each of which is configured to receive sampled data, receive corresponding reference pattern data from the pattern generator, compare the sampled data with the corresponding reference pattern data, and generate a comparison result. Attached Figure Description

[0011] Some exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram illustrating a memory system according to some example embodiments;

[0013] Figure 2 Based on some example embodiments Figure 1 A flowchart of the operation of the memory system in the document;

[0014] Figure 3 Based on some example embodiments Figure 1 A more detailed block diagram of the training circuitry;

[0015] Figure 4 Based on some example embodiments Figure 1 A flowchart of the operation of the memory controller in the process;

[0016] Figure 5This is a diagram illustrating examples of multiple reference pattern data based on some example embodiments;

[0017] Figure 6 This is a diagram illustrating examples of the initial delay amounts of multiple reference mode data according to some example embodiments;

[0018] Figure 7 Based on some example embodiments Figure 1 A more detailed block diagram of the comparator cluster in the diagram;

[0019] Figure 8 Based on some example embodiments Figure 1 A flowchart of the operation of the memory system in the document;

[0020] Figure 9A , Figure 9B and Figure 9C It is used to describe according to some example embodiments. Figure 1 A diagram illustrating the operation of the memory controller in the diagram;

[0021] Figure 10 This is a diagram illustrating examples of reference pattern data and sampled data based on some example embodiments;

[0022] Figure 11 This is a graph showing the comparison results based on some example embodiments;

[0023] Figure 12 Based on some example embodiments Figure 1 A flowchart illustrating an example of the operation of the memory system in the diagram;

[0024] Figure 13 Based on some example embodiments Figure 1 A flowchart illustrating an example of the operation of the memory controller in the diagram;

[0025] Figure 14 Based on some example embodiments Figure 1 A more detailed block diagram of the training circuitry;

[0026] Figure 15 Based on some example embodiments Figure 1 A more detailed block diagram of the training circuitry;

[0027] Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E and Figure 16F It is a graph showing the effect of a memory system based on some example embodiments;

[0028] Figure 17 This is a block diagram illustrating a memory system according to some example embodiments; and

[0029] Figure 18 This is a block diagram of a storage system according to some example embodiments. Detailed Implementation

[0030] In the following, some exemplary embodiments of the inventive concept are clearly and in detail, enabling those skilled in the art to readily implement the inventive concept.

[0031] In some exemplary embodiments, the term "training" as used in this invention concept may refer to the operation of searching and adjusting the center of the window of the data signal DQ. In some exemplary embodiments, "left edge (LE)" may refer to the left (or earlier in time) closed interval of the unit interval (UI) constituting the window of the data signal DQ. "Right edge (RE)" may refer to the right (or, later in time) closed interval of the UI constituting the window of the data signal DQ. In some exemplary embodiments, expressions for the UI may be used in parallel with window items of the data signal DQ.

[0032] Figure 1 This is a block diagram illustrating a memory system 1000 according to some example embodiments.

[0033] Reference Figure 1 The memory system 1000 may include a memory controller 1100 and a memory device 1200. In some example embodiments, the memory system 1000 may include mass storage media used in computing devices, such as storage devices, solid-state drives (SSDs), and / or memory cards. In some example embodiments, the memory system 1000 may substantially include mobile systems, such as mobile phones, smartphones, tablet PCs, wearable devices, healthcare devices, and / or Internet of Things (IoT) devices. However, the example embodiments of the memory system 1000 are not necessarily limited thereto, and according to some example embodiments, the memory system 1000 may also include PCs, laptops, servers, media players, and / or automotive devices such as navigation devices.

[0034] The memory controller 1100 can be configured to control the memory device 1200 according to requests or controls from external devices (e.g., a host, a central processing unit (CPU), an application processor (AP), etc.). For example, in order to control the memory device 1200, the memory controller 1100 can exchange various signals using the control signal CTRL, the data signal DQ (or multiple data signals), and the data strobe signal DQS.

[0035] For example, the control signal CTRL, the data strobe signal DQS, and the data signal DQ can be provided to the memory device 1200 via different signal lines and / or different signal pins. The control signal CTRL and the data strobe signal DQS can include signals used to distinguish signals (e.g., command CMD, address ADDR, or data DATA) provided to the memory device 1200 via the data signal DQ. For example, the data signal DQ can be referred to as a signal transmitted and received via the data signal pin DQ pin or the data signal line, and the data strobe signal DQS can be referred to as a signal transmitted and received via the data strobe pin (DQS pin) and / or the data strobe line.

[0036] The memory device 1200 can store data DATA received from the memory controller 1100 or transmit and / or send the stored data DATA to the memory controller 1100 in response to various signals from the memory controller 1100. For example, the memory device 1200 can distinguish whether the signal provided via the data signal DQ is a command CMD, an address ADDR, or data DATA based on the control signal CTRL. In some example embodiments, various signals (such as the command latch enable signal CLE, the address latch enable signal ALE, the read enable signal RE / , and / or the write enable signal WE / ) can be provided to the memory device 1200 via the control signal CTRL.

[0037] The memory device 1200 can be configured to identify (or capture) data DATA provided via the data signal DQ based on the data strobe signal DQS. The memory device 1200 can store the identified data DATA based on the received command CMD and address ADDR.

[0038] For example, memory device 1200 may include NAND flash memory. However, exemplary embodiments of the present invention are not limited thereto, and in some exemplary embodiments, memory device 1200 may include at least one of a variety of memory devices, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), solid-state flash memory device, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and / or ferroelectric RAM (FRAM).

[0039] The memory controller 1100 can be configured to control the memory device 1200. For example, the memory controller 1100 can control the memory device 1200 to perform write, read, and / or erase operations. In some example embodiments, the memory controller 1100 can perform training on the memory device 1200.

[0040] The memory controller 1100 can perform training on the memory device 1200 in specific situations, such as the startup or initialization of the memory system 1000. For example, training can be performed after power is supplied to the memory system 1000 or after the memory system 1000 resumes from sleep mode. Training can also be performed before the memory controller 1100 generally controls the memory device 1200 (e.g., controls the memory device 1200 to perform write, read, and / or erase operations).

[0041] By using training, the memory controller 1100 can increase the reliability of data exchange with the memory device 1200. For example, the memory controller 1100 can detect the center of the window of the data signal DQ by writing a training pattern to or reading a training pattern from the memory device 1200 under various conditions. The memory controller 1100 can adjust the delay code or delay amount of the delay circuit to align with the center of the window of the detected multiple data signals DQ.

[0042] In some example embodiments, the memory controller 1100 may include training circuitry 1110. In some example embodiments, training circuitry 1110 may include hardware blocks comprising analog and / or digital circuitry. Training circuitry 1110 may include software blocks comprising a plurality of instructions to be executed by memory controller 1100.

[0043] Training circuit 1110 can perform training on memory device 1200. Training circuit 1110 can store information that is beneficial to training and / or information obtained through training (e.g., pattern data, final delay, etc.) in memory and / or registers. Training circuit 1110 can perform training on memory device 1200 using memory and / or registers.

[0044] The memory controller 1100 can calculate the difference between the data signal DQ and the data strobe signal DQS using a comparator while sequentially increasing the delay code. As the timing difference between the data signal DQ and the data strobe signal DQS increases, the training execution time can increase. Ensuring an effective window for the data signal DQ may be advantageous for improving the performance and reliability of the memory system 1000.

[0045] According to some example embodiments, the training circuit 1110 can perform parallel training operations. Parallel training operations can be referred to as training steps performed by simultaneously comparing multiple reference pattern data (or reference pattern data) with sampled data, based on multiple reference pattern data in which the basic pattern data has been cyclically shifted at unit intervals.

[0046] In some example embodiments, the training circuit 1110 can generate multiple reference mode data. The training circuit 1110 can simultaneously compare the multiple reference mode data with the sampled data and generate a comparison result. The training circuit 1110 can calculate the center of a window for the data signal DQ based on the comparison result.

[0047] For example, training circuit 1110 can detect the left and right edges of the window of data signal DQ based on the comparison result. Training circuit 1110 can determine the center of the window of data signal DQ based on the left and right edges of the window.

[0048] In some example embodiments, training circuitry 1110 may include comparator cluster 1111 and pattern generator 1112. Pattern generator 1112 may generate multiple reference pattern data based on basic pattern data. For example, the reference pattern data may include comparison pattern data. The reference pattern data may be used for comparison with sampled data received by the comparators. Pattern generator 1112 may provide multiple reference pattern data to comparator cluster 1111.

[0049] Comparator cluster 1111 may include multiple comparators. Comparator cluster 1111 can receive multiple reference mode data and sampled data. Comparator cluster 1111 can perform multiple comparison operations simultaneously by using multiple comparators. Comparator cluster 1111 can simultaneously compare sampled data with multiple reference mode data. Comparator cluster 1111 can generate comparison results.

[0050] As described above, the training circuit 1110 according to some example embodiments can generate multiple reference pattern data by cyclically shifting the basic pattern data in units of interval (UI). The training circuit 1110 can simultaneously compare the sampled data with the multiple reference pattern data using multiple comparators. The training circuit 1110 can improve the training speed by using a parallel structure. The operation of the memory controller 1100 according to some example embodiments of the present invention is described in more detail with reference to the following figures.

[0051] Figure 2 Based on some example embodiments Figure 1 A flowchart of the operation of the memory system 1000.

[0052] Reference Figure 1 and Figure 2 The memory system 1000 can perform training operations. In operation S110, the memory system 1000 can generate multiple reference pattern data based on the basic pattern data. For example, the pattern generator 1112 can generate multiple reference pattern data by cyclically shifting the basic pattern data in units of UI. (Refer to...) Figure 5 A more detailed explanation of the data from multiple reference models is provided.

[0053] In operation S120, the memory system 1000 can perform parallel training operations based on multiple reference pattern data. For example, the parallel training operation can be described as a training step performed by simultaneously comparing multiple reference pattern data with sampled data. The training circuit 1110 can compare the sampled data with multiple reference pattern data in parallel using multiple comparators.

[0054] In operation S130, the memory system 1000 can perform input / output operations based on training results. For example, the memory system 1000 can adjust the delay of the data signal DQ based on the training results. The memory system 1000 can compensate for the timing of the data signal DQ. The memory system 1000 can perform input / output operations with reference to the final delay of the data signal DQ or the data strobe signal DQS. Therefore, a memory system with improved reliability can be provided by reducing the skew between signals generated in high-frequency operation.

[0055] Figure 3 Based on some example embodiments Figure 1 A more detailed block diagram of the training circuit 1110 in the diagram.

[0056] Reference Figure 1 and Figure 3 The training circuit 1110 may include a comparator cluster 1111, a pattern generator 1112, a delay circuit 1113, a sampling circuit 1114, and a training control circuit 1115. The comparator cluster 1111 may include a first comparator C1 to an nth comparator Cn.

[0057] Pattern generator 1112 can generate pattern data. Pattern generator 1112 can generate multiple reference pattern data based on basic pattern data. Pattern generator 1112 can determine any one of the multiple reference pattern data as training pattern data. Pattern generator 1112 can provide multiple reference pattern data RPDs to comparator cluster 1111. Memory controller 1100 can send and / or transfer the training pattern data to memory device 1200.

[0058] In some example embodiments, the base pattern data may be predetermined, or alternatively, the base pattern data may be desired base pattern data. In some example embodiments, the base pattern data may be desired base pattern data. In some example embodiments, the base pattern data may be modified. The pattern generator 1112 may determine the base pattern data. In some example embodiments, the pattern generator 1112 (or memory controller 1100) may select low-cost pattern data as the base pattern data. The cost may be defined by Formula 1. In some example embodiments, t and i may be integers, N may indicate the maximum or total number of reference pattern data generated as the base pattern data, and B may indicate the length of the base pattern data. For example, in the case of 16-bit base pattern data, B may be '16'. The cost may increase as the base pattern data becomes more similar to the reference pattern data. The pattern generator 1112 may improve the reliability of the training steps by selecting base pattern data with low and / or minimum cost.

[0059] [Formula 1]

[0060] Cost =

[0061] The delay circuit 1113 may receive a delay code DCODE from the training control circuit 1115. For example, the delay code DCODE may indicate a delay control signal. The delay code DCODE may indicate a delay amount. In some example embodiments, the delay circuit 1113 may include multiple delay units for adjusting the timing of the data signal DQ. The delay circuit 1113 may control the delay amount of the data signal DQ by activating the multiple delay units based on the delay code DCODE.

[0062] In some example embodiments, delay circuit 1113 can receive mode data PD received via data signal DQ. Delay circuit 1113 can delay the received mode data PD based on delay code DCODE. Delay circuit 1113 can output the delayed mode data DPD to sampling circuit 1114.

[0063] In some example embodiments, the delay circuit 1113 can receive the data signal DQ. The delay circuit 1113 can delay the data signal DQ based on the delay code DCODE. The delay circuit 1113 can output the delayed data signal DQ to the sampling circuit 1114.

[0064] Sampling circuit 1114 can receive a clock signal. For example, the clock signal can be generated based on a data strobe signal DQS received from memory device 1200. Sampling circuit 1114 can receive the clock signal or the delayed data strobe signal DQS from a delay-locked loop (not shown). Sampling circuit 1114 can receive a data signal DQ from delay circuit 1113. Alternatively, in some example embodiments, sampling circuit 1114 can receive delayed mode data DPD from delay circuit 1113.

[0065] Sampling circuit 1114 can sample delayed mode data DPD based on a clock signal and generate sampled data SD. Sampling circuit 1114 can store the delayed mode data DPD received via data signal DQ as sampled data SD and output sampled data SD. Sampling circuit 1114 can provide sampled data SD to comparator cluster 1111.

[0066] Comparator cluster 1111 can receive multiple reference pattern data from pattern generator 1112. Comparator cluster 1111 can receive sampled data SD from sampling circuit 1114. Comparator cluster 1111 can send and / or transmit the comparison result CR to training control circuit 1115. Each of the first comparator C1 to the nth comparator Cn can receive sampled data SD. Each of the first comparator C1 to the nth comparator Cn can receive its corresponding reference pattern data. For example, the first comparator C1 can receive first reference pattern data, and the second comparator C2 can receive second reference pattern data.

[0067] Each of the first comparators C1 to the nth comparator Cn can compare the corresponding reference pattern data with the sampled data and generate a comparison result. For example, the first comparator C1 can generate a first sub-comparison result by comparing the first reference pattern data with the sampled data. The second comparator C2 can compare the second reference pattern data with the sampled data and generate a second sub-comparison result. For example, the second comparator C2 can generate a second sub-comparison result by comparing the second reference pattern data with the sampled data. The comparator cluster 1111 can provide the comparison results, including the first to nth sub-comparison results, to the training control circuit 1115.

[0068] In some example embodiments, each of the plurality of comparators C1 to Cn can determine whether the reference mode data is the same as the sampled data corresponding to the reference mode data. Each of the first comparators C1 to the nth comparator Cn can compare the reference mode data with the sampled data corresponding to the reference mode data and determine whether the reference mode data is the same as the sampled data. When the reference mode data is the same as the sampled data, each of the first comparators C1 to the nth comparator Cn can output a sub-comparison result indicating a first value (e.g., pass). When the reference mode data is different from the sampled data, each of the first comparators C1 to the nth comparator Cn can output a sub-comparison result indicating a second value (e.g., fail).

[0069] Training control circuit 1115 can generate a delay code DCODE. Training control circuit 1115 can generate delay codes corresponding to sub-training operations and send and / or transmit the generated delay codes to delay circuit 1113. For example, training control circuit 1115 can increase the delay code within a maximum or total of 1 UI. Training control circuit 1115 can provide the delay code DCODE to delay circuit 1113. Training control circuit 1115 can receive comparison results CR from comparator cluster 1111. Training control circuit 1115 can analyze the comparison results CR. Training control circuit 1115 can calculate the center of the window based on the comparison results CR.

[0070] In some example embodiments, the training control circuit 1115 may detect a comparator (e.g., at least one of the first comparators C1 to the nth comparator Cn) whose sub-comparison result (or sub-comparison result value) changes from a first value (e.g., pass) to a second value (e.g., fail) as a left-edge comparator (TPF) (hereinafter referred to as a "pass-fail (PF) comparator"). The training control circuit 1115 may also detect a comparator (e.g., at least one of the first comparators C1 to the nth comparator Cn and / or at least one of the first comparators C1 to the nth comparator Cn and / or at least one other comparator among the first comparators C1 to the nth comparator Cn) whose sub-comparison result (or sub-comparison result value) changes from a second value (e.g., fail) to a first value (e.g., pass) as a right-edge comparator (TFP) (hereinafter referred to as a "fail-pass (FP) comparator"). The training control circuit 1115 can detect a comparator (TFF) (hereinafter referred to as "FF comparator") in which a sub-comparison result (or sub-comparison result value) remains at a second value (e.g., failure). The training control circuit 1115 can also detect a comparator (TPP) (hereinafter referred to as "PP comparator") in which a comparator (TFF) is detected as passing (e.g., passing).

[0071] In some example embodiments, the training control circuit 1115 can turn multiple comparators C1 to Cn on or off. The training control circuit 1115 can deactivate unused comparators among the multiple comparators C1 to Cn (e.g., at least one comparator among the first comparators C1 to the nth comparator Cn). The training control circuit 1115 can generate multiple comparator control signals. These comparator control signals can indicate whether their corresponding comparators (e.g., at least one comparator among the first comparators C1 to the nth comparator Cn) are activated. The training control circuit 1115 can send and / or transmit the multiple comparator control signals to the comparator cluster 1111. The training control circuit 1115 can activate or deactivate comparators (e.g., at least one comparator among the first comparators C1 to the nth comparator Cn) by using the comparator control signals. For example, the training control circuit 1115 can deactivate unused comparators among the multiple comparators C1 to Cn by using the corresponding comparator control signals.

[0072] In some example embodiments, each of the first comparators C1 to the nth comparator Cn can receive a corresponding comparator control signal from the training control circuit 1115. Each of the first comparators C1 to the nth comparator Cn can be activated or deactivated in response to the comparator control signal. Each of the first comparators C1 to the nth comparator Cn can be turned on or off in response to the comparator control signal.

[0073] Figure 4 Based on some example embodiments Figure 1 A flowchart of the operation of the memory controller 1100.

[0074] Reference Figure 1 and Figure 4 The memory controller 1100 can perform parallel training operations. In operation S210, the memory controller 1100 can send and / or transfer training pattern data to the memory device 1200. The training pattern data may include any one of a plurality of reference pattern data. The training pattern data may be predetermined, or alternatively, the training pattern data may be desired training pattern data.

[0075] In operation S220, the memory controller 1100 can receive pattern data PD from the memory device 1200. The memory device 1200 can receive training pattern data. The memory controller 1100 can send and / or transmit training commands to the memory device 1200. The memory device 1200 can receive training commands. In response to the training commands, the memory device 1200 can send and / or transmit a signal generated by sampling the training pattern data as pattern data PD to the memory controller 1100. The memory controller 1100 can receive the pattern data PD via the data signal DQ.

[0076] In operation S230, the memory controller 1100 can compare multiple reference mode data with sampled data using first comparators C1 to nth comparators Cn, and generate a comparison result. Each of the first comparators C1 to nth comparators Cn can perform a comparison operation that compares the reference mode data with its corresponding sampled data. For example, sampled data can be generated based on the received mode data PD. The memory controller 1100 can compare the sampled data with multiple reference mode data in parallel. The first comparator C1 can perform a logical operation (e.g., XOR operation) on the first reference mode data and the sampled data. The first comparator C1 can output the logical operation result as a first sub-comparison result. While the first comparator C1 performs the logical operation, the second comparator C2 can perform a logical operation (e.g., XOR operation) on the second reference mode data and the sampled data. The second comparator C2 can output the logical operation result as a second sub-comparison result.

[0077] In operation S240, the memory controller 1100 can determine whether the FP comparator and the PF comparator are detected. When both the FP comparator and the PF comparator are detected, the memory controller 1100 can perform operation S260, and when neither the FP comparator nor the PF comparator is detected (e.g., when only one of the FP comparator and the PF comparator is detected, or when neither is detected), the memory controller 1100 can perform operation S250. For example, the memory controller 1100 can determine whether both the FP comparator and the PF comparator are detected, and in response to the detection of both the FP comparator and the PF comparator, the memory controller 1100 performs operation S260. The memory controller 1100 performs operation S250 in response to the detection of only one of the FP comparator and the PF comparator, and / or the memory controller 1100 performs operation S250 in response to the detection of neither the FP comparator nor the PF comparator.

[0078] In some example embodiments, the memory controller 1100 can identify reference mode data in the FP state and reference mode data in the PF state. According to some example embodiments, referring to... Figure 10 A more detailed description of the FP and PF states is provided. In some example embodiments, instead of detecting FP and PF comparators, the memory controller 1100 can detect reference mode data in the FP state and reference mode data in the PF state.

[0079] In operation S250, the memory controller 1100 can increase the delay code of the data signal DQ. For example, the memory controller 1100 can increase the delay amount of the data signal DQ. Afterwards, the memory controller 1100 can execute operation S220 again.

[0080] In operation S260, the memory controller 1100 can calculate the center of the window for the data signal DQ. The memory controller 1100 can find the center of the window for the data signal DQ based on the comparison result. The memory controller 1100 can determine the final delay of the data signal DQ. The memory controller 1100 can determine the final delay of the data signal DQ based on a first initial delay corresponding to the PF comparator and a second initial delay corresponding to the FP comparator.

[0081] As described above, according to some example embodiments, the memory controller 1100 can perform parallel training operations. The memory controller 1100 can generate multiple reference pattern data sets and repeatedly perform sub-training operations based on these multiple reference pattern data sets. The memory controller 1100 can determine the final delay amount of the data signal DQ based on the comparison results. Therefore, training latency can be reduced.

[0082] Figure 5 This is a diagram illustrating examples of multiple reference pattern data based on some example embodiments.

[0083] Reference Figure 1 , Figure 3 and Figure 5 The pattern generator 1112 can generate multiple reference pattern data. In some example embodiments, the multiple reference pattern data can be different from each other. The pattern generator 1112 can generate multiple reference pattern data used in parallel training operations. The pattern generator 1112 can generate multiple reference pattern data based on the basic pattern data.

[0084] For example, the number of reference pattern data can be equal to the total number of comparators. The number of reference pattern data can be predetermined. The number of reference pattern data can be adjusted. For example, with a basic pattern data length of '16', the maximum or total number of reference pattern data can be '9'. Hereinafter, we assume the basic pattern data length is '16' and the number of reference pattern data is '6'.

[0085] Pattern generator 1112 can generate first reference pattern data RPD1 through sixth reference pattern data RPD6. Pattern generator 1112 can obtain basic pattern data. For example, the basic pattern data can be the same as the first reference pattern data RPD1. For example, pattern generator 1112 can receive basic pattern data from a CPU (not shown) included in memory controller 1100. Alternatively, in some example embodiments, pattern generator 1112 can receive basic pattern data stored in registers included in training circuit 1110.

[0086] In some example embodiments, the pattern generator 1112 can generate multiple reference pattern data by cyclically shifting basic pattern data in units of UI. The first reference pattern data RPD1 may include first bit data BD1 to sixteenth bit data BD16. However, the example embodiments are not limited thereto, and in some example embodiments, the number of bits in the pattern data may be increased or decreased depending on the implementation. In some example embodiments, the basic pattern data (or pattern data, training pattern data, etc.) may include a basic pattern and auxiliary patterns. For example, the basic pattern data may include bit data corresponding to the basic pattern and bit data corresponding to the auxiliary pattern.

[0087] For example, the first bit data BD1 to the eighth bit data BD8 can constitute a basic mode, and the ninth bit data BD9 to the sixteenth bit data BD16 can constitute an auxiliary mode (or support mode). For example, the basic mode may include a mode that serves as the primary comparison reference in a comparison operation. The auxiliary mode may include modes used in conjunction with the basic mode, and may include modes that assist the basic mode.

[0088] For example, the first bit data BD1 to the sixteenth bit data BD16 can be arranged sequentially in the first reference mode data RPD1. In other words, in the first reference mode data RPD1, the first bit data BD1 to the sixteenth bit data BD16 can be arranged in ascending order from '1' to '16'. In the second reference mode data RPD2, the sixteenth bit data BD16 and the first bit data BD1 to the fifteenth bit data BD15 can be arranged sequentially. For example, the second reference mode data RPD2 can be arranged such that the sixteenth bit data BD16 is moved to the first position, and the remaining bits (BD1 to BD15) are arranged in the existing order. For example, the second reference mode data RPD2 may include first bits BD1 to sixteenth bits BD16, and the first bits BD1 to sixteenth bits BD16 may have an arrangement and / or order in which the sixteenth bit BD16 is located at the beginning (e.g., the start) of the second reference mode data RPD2, the first bits BD1 to fifteenth bits BD15 are sequentially arranged after the sixteenth bit BD16, and the fifteenth bit BD15 is located at the end of the second reference mode data RPD2. The third reference mode data RPD3 may be arranged in the order of fifteenth bit BD15, sixteenth bit BD16, and first bits BD1 to fourteenth bits BD14. For example, in the third reference mode data RPD3, after the fifteenth bit BD15 is moved to a first position and the sixteenth bit BD16 is moved to a second position, the remaining bits, or BD1 to BD14, may be arranged to maintain their existing order. In the fourth reference mode data RPD4, bits 14 through 16 (BD16) and bits 1 through 13 (BD13) can be arranged sequentially. In the fifth reference mode data RPD5, bits 13 through 16 (BD16) and bits 1 through 12 (BD12) can be arranged sequentially. In the sixth reference mode data RPD6, bits 12 through 16 (BD16) and bits 1 through 11 (BD11) can be arranged sequentially.For example, each reference pattern data (e.g., RPD2 to RPD6) following the first reference pattern data RPD1 involves left-rotating the first bit data BD1 to the sixteenth bit data BD16 by at least one position from the previous reference pattern data, such that each reference pattern data (e.g., RPD2 to RPD6) following the first reference pattern data RPD1 is a left-circular shift of the bit sequence of the first bit data BD1 to the sixteenth bit data BD16, wherein the bit data starting from the end of the reference pattern data is rotated to the beginning of the reference pattern data while maintaining the relative order of the remaining bit data. For example, each reference pattern data (e.g., RPD2 to RPD6) shifts the starting point of the order of bit data BD1 to BD16 at least one bit to the left.

[0089] For example, the first reference pattern data RPD1 may include pattern data obtained by shifting the basic pattern data by "0 UI". The second reference pattern data RPD2 may include pattern data obtained by shifting the basic pattern data by "1 UI". The third reference pattern data RPD3 may include pattern data obtained by shifting the basic pattern data by "2 UI". The fourth reference pattern data RPD4 may include pattern data obtained by shifting the basic pattern data by "3 UI". The fifth reference pattern data RPD5 may include pattern data obtained by shifting the basic pattern data by "4 UI". The sixth reference pattern data RPD6 may include pattern data obtained by shifting the basic pattern data by "5 UI".

[0090] In some example embodiments, the memory controller 1100 may determine the sixth reference mode data RPD6 as training mode data. The memory controller 1100 may send and / or transmit the sixth reference mode data RPD6 as training mode data to the memory device 1200. For example, the training mode data may include data in which the basic mode data is cyclically shifted by a predetermined or alternatively desired maximum or total UI.

[0091] Figure 6 This is a diagram illustrating examples of the initial delay amounts of multiple reference mode data based on some example embodiments.

[0092] Reference Figure 1 , Figure 5 and Figure 6In some example embodiments, the memory controller 1100 may determine the sixth reference mode data RPD6 as training mode data. The memory controller 1100 may send and / or transmit the sixth reference mode data RPD6 as training mode data to the memory device 1200. The memory device 1200 may send and / or transmit a signal generated by sampling the training mode data as mode data PD to the memory controller 1100.

[0093] In some example embodiments, the initial latency of each of the plurality of reference pattern data RPD1 to RPD6 can be the difference in UI from the training pattern data. For example, since the sixth reference pattern data RPD6 includes the training pattern data, the initial latency corresponding to the sixth reference pattern data RPD6 can be '0 UI'. Since the fifth reference pattern data RPD5 is the same as the training pattern data when shifted by '1 UI', the initial latency corresponding to the fifth reference pattern data RPD5 can be '1 UI'. Since the fourth reference pattern data RPD4 is the same as the training pattern data when shifted by '2 UI', the initial latency corresponding to the fourth reference pattern data RPD4 can be '2 UI'. Since the third reference pattern data RPD3 is the same as the training pattern data when shifted by '3 UI', the initial latency corresponding to the third reference pattern data RPD3 can be '3 UI'. Since the second reference pattern data RPD2 is the same as the training pattern data when shifted by '4 UI', the initial latency corresponding to the second reference pattern data RPD2 can be '4 UI'. Since the first reference mode data RPD1 is the same as the training mode data when shifted by '5 UI', the initial delay corresponding to the first reference mode data RPD1 can be '5 UI'.

[0094] Figure 7 Based on some example embodiments Figure 1 A more detailed block diagram of comparator cluster 1111 in the diagram. For example, Figure 7 The comparator cluster 1111a can correspond to Figure 1 The comparator cluster 1111.

[0095] Reference Figure 1 , Figure 3 , Figure 5 and Figure 7The comparator cluster 1111a may include a first comparator C1 to a sixth comparator C6. The comparator cluster 1111a may receive sampled data SD from the sampling circuit 1114. The comparator cluster 1111a may receive multiple reference pattern data RPD1 to RPD6 from the pattern generator 1112. The comparator cluster 1111a may send and / or transmit a comparison result CR, including the first sub-comparison result SCR1 to the sixth sub-comparison result SCR6, to the training control circuit 1115.

[0096] Each of the first comparators C1 to the sixth comparator C6 can receive sampled data SD and its corresponding reference mode data. Each of the first comparators C1 to the sixth comparator C6 can output its corresponding sub-comparison result. For example, the first comparator C1 can receive sampled data SD and first reference mode data RPD1. The first comparator C1 can output the first sub-comparison result SCR1 to the training control circuit 1115. The second comparator C2 can receive sampled data SD and second reference mode data RPD2. The second comparator C2 can output the second sub-comparison result SCR2 to the training control circuit 1115. The third comparator C3 can receive sampled data SD and third reference mode data RPD3. The third comparator C3 can output the third sub-comparison result SCR3 to the training control circuit 1115.

[0097] The fourth comparator C4 receives sampled data SD and fourth reference mode data RPD4. The fourth comparator C4 outputs the fourth sub-comparison result SCR4 to the training control circuit 1115. The fifth comparator C5 receives sampled data SD and fifth reference mode data RPD5. The fifth comparator C5 outputs the fifth sub-comparison result SCR5 to the training control circuit 1115. The sixth comparator C6 receives sampled data SD and sixth reference mode data RPD6. The sixth comparator C6 outputs the sixth sub-comparison result SCR6 to the training control circuit 1115.

[0098] Figure 8 Based on some example embodiments Figure 1 A flowchart of the operation of the memory system 1000.

[0099] Reference Figure 1 and Figure 8 The memory system 1000 can perform parallel training operations. A parallel training operation can include multiple sub-training operations. The memory system 1000 can repeatedly execute these sub-training operations.

[0100] In some example embodiments, training circuit 1110 may generate multiple reference pattern data and repeatedly perform sub-training operations based on the multiple reference pattern data. Training circuit 1110 may find the center of the window based on the comparison results generated in the sub-training operations. For example, a sub-training operation may be described as an operation that receives pattern data from memory device 1200, compares the sampled data with multiple reference pattern data, and generates comparison results. In other words, a sub-training operation may be described as an operation in which an operation of accessing memory device 1200 for training is combined with an operation of comparing the read pattern data with the reference data. Memory system 1000 may repeatedly perform sub-training operations while changing the delay code. In some example embodiments, training circuit 1110 may perform multiple sub-training operations within “1 UI”.

[0101] In operation S301, the memory controller 1100 can generate multiple reference pattern data. The memory controller 1100 can generate multiple reference pattern data based on the basic pattern data. In operation S302, the memory controller 1100 can send and / or transmit training pattern data to the memory device 1200. The memory controller 1100 can determine any one of the multiple reference pattern data as training pattern data. The memory controller 1100 can send and / or transmit the training pattern data to the memory device 1200. The memory device 1200 can receive the training pattern data.

[0102] In operation S303, variable k can be set to 1. In some example embodiments, variable k can be used to describe the repetition of sub-training operations, and this does not limit the scope of the inventive concept. Sub-training operations may include operations S304 to S310.

[0103] In operation S304, memory controller 1100 may send and / or transmit training commands to memory device 1200. For example, training commands may include a read data signal DQ training command. In some example embodiments, memory controller 1100 may send and / or transmit training mode data along with training commands to memory device 1200. Memory device 1200 may receive training commands.

[0104] In operation S305, memory device 1200 may send and / or transmit pattern data PD to memory controller 1100. Memory device 1200 may also send and / or transmit a signal generated by sampling training pattern data TPD as pattern data PD to memory controller 1100. Memory controller 1100 may receive pattern data PD.

[0105] In operation S306, the memory controller 1100 may delay the pattern data PD based on the k-th delay code. The memory controller 1100 may delay the pattern data PD by the delay amount corresponding to the k-th delay code. Alternatively, in some example embodiments, the memory controller 1100 may delay the data signal DQ by the delay amount corresponding to the k-th delay code. The memory controller 1100 may generate the k-th delayed pattern data DPD. For example, in operation S306, the memory controller 1100 generates the k-th delayed pattern data DPD by delaying the pattern data PD based on the k-th delay code. In operation S307, the memory controller 1100 may generate the k-th sampled data. The memory controller 1100 may generate the k-th sampled data based on a clock signal by sampling the k-th delayed pattern data.

[0106] In operation S308, the memory controller 1100 can compare the k-th sampled data with multiple reference mode data and generate a k-th comparison result. Each of the multiple comparators included in the memory controller 1100 can compare the k-th sampled data with its corresponding reference mode data. In other words, the memory controller 1100 can simultaneously compare the sampled data with multiple reference mode data. The memory controller 1100 can generate a k-th comparison result indicating whether the k-th sampled data is the same as the multiple reference mode data.

[0107] In operation S309, the memory controller 1100 can determine whether variable k is a maximum value or a total value. For example, the maximum value or the total value can be a predetermined value or, alternatively, a desired value. The memory controller 1100 can adjust the amount of delay in the data signal in units of delay steps. "1 UI" can be represented as the product of the maximum value or the total value and the delay step (1 UI = maximum value (or total value) * delay step). The maximum value or the total value can be determined based on the number of delay steps in 1 UI. For example, the delay step can indicate the amount (or value) of delay that increases as the delay code increases by '1'.

[0108] In some example embodiments, when variable k is not the maximum value or the total value, variable k can be incremented by "1" in operation S310. Afterwards, memory controller 1100 can execute operation S304. Memory controller 1100 can repeatedly execute the sub-training operation. When variable k is the maximum value or the total value, memory controller 1100 can execute operation S311.

[0109] In operation S311, the memory controller 1100 can detect the FP comparator TFP and PF comparator TPF by analyzing multiple comparison results. The memory controller 1100 can detect the left and right edges of the window based on the multiple comparison results. Alternatively, in some example embodiments, the memory controller 1100 can detect reference mode data in the FP state and reference mode data in the PF state.

[0110] In operation S312, the memory controller 1100 can calculate the center of the window based on the FP comparator TFP and the PF comparator TPF. Alternatively, in some example embodiments, the memory controller 1100 can calculate the center of the window based on reference mode data in the FP state and reference mode data in the PF state. Therefore, the memory controller 1100 can determine the final delay amount of the data signal DQ.

[0111] As described above, the memory controller 1100 can perform comparison operations on multiple reference pattern data and sample data in parallel using multiple comparators. Therefore, in some example embodiments, the memory controller 1100 can simultaneously perform training in units of delay steps and training in units of UI.

[0112] Figures 9A to 9C It is used to describe according to some example embodiments. Figure 1 A diagram illustrating the operation of the memory controller 1100.

[0113] Reference Figures 9A to 9C The training circuit 1110 may include a comparator cluster 1111a, a pattern generator 1112, a delay circuit 1113, a sampling circuit 1114, and a training control circuit 1115. The comparator cluster 1111a may include a first comparator C1 to a sixth comparator C6. The training circuit 1110 can repeatedly execute multiple sub-training operations while changing the delay code. The training circuit 1110 can perform parallel training operations while changing the delay code in "1UI".

[0114] For example, training circuit 1110 can perform the first to the third sub-training operations. However, the example embodiments are not limited thereto, and in some example embodiments, the number of sub-training operations in the parallel training operation can be increased or decreased depending on the implementation. See also... Figure 9A The delay code corresponding to the first sub-training operation may include a first delay code DCODE1. The first delay code DCODE1 may include an initial delay code. (See reference...) Figure 9B The delay code corresponding to the second sub-training operation may include the second delay code DCODE2. (See reference...) Figure 9CThe delay code corresponding to the third sub-training operation may include a third delay code DCODE3. The third delay code DCODE3 may include a final delay code. For example, the difference between the delay amount of the final delay code and the delay amount of the initial delay code may be a maximum of 1 UI' or a total of 1 UI'.

[0115] Training circuit 1110 can perform a first sub-training operation. Delay circuit 1113 can receive pattern data PD from memory device 1200. Delay circuit 1113 can receive a first delay code DCODE1 from training control circuit 1115. Delay circuit 1113 can delay the pattern data PD based on the first delay code DCODE1. Alternatively, in some example embodiments, delay circuit 1113 can delay the data signal DQ based on the first delay code DCODE1. Delay circuit 1113 can delay the pattern data PD by a delay amount corresponding to the first delay code DCODE1. Delay circuit 1113 can generate first delayed pattern data DPD1. Delay circuit 1113 can send and / or transmit the first delayed pattern data DPD1 to sampling circuit 1114.

[0116] Sampling circuit 1114 can receive first delayed mode data DPD1. Sampling circuit 1114 can receive a clock signal generated based on data strobe signal DQS. Sampling circuit 1114 can generate first sampled data SD1 by sampling the first delayed mode data DPD1 based on the clock signal. Sampling circuit 1114 can send and / or transmit the first sampled data SD1 to comparator cluster 1111a.

[0117] Comparator cluster 1111a can simultaneously compare first sampled data SD1 with multiple reference pattern data RPDs. For example, first comparator C1 can determine whether first sampled data SD1 is the same as first reference pattern data RPD1 during a first time period. First comparator C1 can generate a first sub-comparison result indicating whether first sampled data SD1 is the same as first reference pattern data RPD1. Second comparator C2 can determine whether first sampled data SD1 is the same as second reference pattern data RPD2 during the first time period. Second comparator C2 can generate a second sub-comparison result indicating whether first sampled data SD1 is the same as second reference pattern data RPD2. Comparator cluster 1111a can send and / or transmit a first comparison result CR1, including the first to sixth sub-comparison results, to training control circuit 1115.

[0118] The training control circuit 1115 can update the current delay code to the second delay code DCODE2. The training control circuit 1115 can send and / or transmit the second delay code DCODE2 to the delay circuit 1113.

[0119] Reference Figure 9B The training circuit 1110 can perform a second sub-training operation. The delay circuit 1113 can receive pattern data PD from the memory device 1200. The delay circuit 1113 can receive a second delay code DCODE2 from the training control circuit 1115. The delay circuit 1113 can delay the pattern data PD based on the second delay code DCODE2. The delay circuit 1113 can delay the pattern data PD by a delay amount corresponding to the second delay code DCODE2. The delay circuit 1113 can generate second delayed pattern data DPD2. The delay circuit 1113 can send and / or transmit the second delayed pattern data DPD2 to the sampling circuit 1114.

[0120] Sampling circuit 1114 can receive second delayed mode data DPD2. Sampling circuit 1114 can receive a clock signal. Sampling circuit 1114 can generate second sampled data SD2 based on the clock signal by sampling the second delayed mode data DPD2. Sampling circuit 1114 can send and / or transmit the second sampled data SD2 to comparator cluster 1111a.

[0121] Comparator cluster 1111a can simultaneously compare the second sampled data SD2 with multiple reference pattern data RPDs. For example, a first comparator C1 can determine whether the second sampled data SD2 is the same as the first reference pattern data RPD1 during a second time period. The first comparator C1 can generate a first sub-comparison result indicating whether the second sampled data SD2 is the same as the first reference pattern data RPD1. A second comparator C2 can determine whether the second sampled data SD2 is the same as the second reference pattern data RPD2 during the second time period. The second comparator C2 can generate a second sub-comparison result indicating whether the second sampled data SD2 is the same as the second reference pattern data RPD2. Comparator cluster 1111a can send and / or transmit a second comparison result CR2, including the first to sixth sub-comparison results, to the training control circuit 1115.

[0122] The training control circuit 1115 can update the current delay code to the third delay code DCODE3. The training control circuit 1115 can send and / or transmit the third delay code DCODE3 to the delay circuit 1113.

[0123] Reference Figure 9CThe training circuit 1110 can perform a third sub-training operation. The delay circuit 1113 can receive pattern data PD from the memory device 1200. The delay circuit 1113 can receive a third delay code DCODE3 from the training control circuit 1115. The delay circuit 1113 can delay the pattern data PD based on the third delay code DCODE3. The delay circuit 1113 can delay the pattern data PD by a delay amount corresponding to the third delay code DCODE3. The delay circuit 1113 can generate third delayed pattern data DPD3. The delay circuit 1113 can send and / or transmit the third delayed pattern data DPD3 to the sampling circuit 1114.

[0124] Sampling circuit 1114 can receive third delay mode data DPD3. Sampling circuit 1114 can receive a clock signal. Sampling circuit 1114 can generate third sampled data SD3 based on the clock signal by sampling the third delay mode data DPD3. Sampling circuit 1114 can send and / or transmit the third sampled data SD3 to comparator cluster 1111a.

[0125] Comparator cluster 1111a can simultaneously compare the third sampled data SD3 with multiple reference pattern data RPDs. For example, a first comparator C1 can determine whether the third sampled data SD3 is the same as the first reference pattern data RPD1 during a third time period. The first comparator C1 can generate a first sub-comparison result indicating whether the third sampled data SD3 is the same as the first reference pattern data RPD1. A second comparator C2 can determine whether the third sampled data SD3 is the same as the second reference pattern data RPD2 during the third time period. The second comparator C2 can generate a second sub-comparison result indicating whether the third sampled data SD3 is the same as the second reference pattern data RPD2. Comparator cluster 1111a can send and / or transmit a third comparison result CR3, including the first to sixth sub-comparison results, to the training control circuit 1115.

[0126] Figure 10 This is a diagram illustrating examples of reference pattern data and sampling data based on some example embodiments. Figure 11 This is a graph showing the comparison results based on some example embodiments.

[0127] Reference Figure 1 , Figure 9A , Figure 9B , Figure 9C , Figure 10 and Figure 11The comparator cluster 1111a can perform comparison operations on sampled data and multiple reference mode data. Each of the first comparators C1 to the sixth comparator C6 can perform the comparison operation by using different reference mode data. For example, the data signal DQ can precede the data strobe signal DQS. The memory controller 1100 may not be able to sample the twelfth bit data BD12 to the fourteenth bit data BD14 from the mode data PD. The memory controller 1100 can sample only the fifteenth bit data BD15, the sixteenth bit data BD16, and the first bit data BD1 to the eleventh bit data BD11 from the mode data PD. The first sampled data SD1 to the third sampled data SD3 may include only the fifteenth bit data BD15, the sixteenth bit data BD16, and the first bit data BD1 to the eleventh bit data BD11. However, the example embodiment is not limited to this.

[0128] During the first time period, the first comparator C1 can compare the first sampled data SD1 with the first reference mode data RPD1. Because the first sampled data SD1 is different from the first reference mode data RPD1, the first comparator C1 can output a sub-comparison result SCR11 indicating a second value (e.g., failure).

[0129] During the first time period, the second comparator C2 can compare the first sampled data SD1 with the second reference mode data RPD2. Because the first sampled data SD1 and the second reference mode data RPD2 are different, the second comparator C2 can output a sub-comparison result SCR21 indicating a second value (e.g., failure).

[0130] During the first time period, the third comparator C3 can compare the first sampled data SD1 with the third reference mode data RPD3. Because the first sampled data SD1 and the third reference mode data RPD3 are the same, the third comparator C3 can output a sub-comparison result SCR31 ​​indicating the first value (e.g., pass).

[0131] During the first time period, the fourth comparator C4 can compare the first sampled data SD1 with the fourth reference mode data RPD4. Because the first sampled data SD1 and the fourth reference mode data RPD4 are different, the fourth comparator C4 can output a sub-comparison result SCR41 indicating a second value (e.g., failure).

[0132] During the first time period, the fifth comparator C5 can compare the first sampled data SD1 with the fifth reference mode data RPD5. Because the first sampled data SD1 and the fifth reference mode data RPD5 are different, the fifth comparator C5 can output a sub-comparison result SCR51 indicating a second value (e.g., failure).

[0133] During the first time period, the sixth comparator C6 can compare the first sampled data SD1 with the sixth reference mode data RPD6. Because the first sampled data SD1 and the sixth reference mode data RPD6 are different, the sixth comparator C6 can output a sub-comparison result SCR61 indicating a second value (e.g., failure).

[0134] During the second time period, the first comparator C1 can compare the second sampled data SD2 with the first reference mode data RPD1. Because the second sampled data SD2 is different from the first reference mode data RPD1, the first comparator C1 can output a sub-comparison result SCR12 indicating a second value (e.g., failure).

[0135] During the second time period, the second comparator C2 can compare the second sampled data SD2 with the second reference mode data RPD2. Because the second sampled data SD2 is different from the second reference mode data RPD2, the second comparator C2 can output a sub-comparison result SCR22 indicating a second value (e.g., failure).

[0136] During the second time period, the third comparator C3 can compare the second sampled data SD2 with the third reference mode data RPD3. Because the second sampled data SD2 and the third reference mode data RPD3 are the same, the third comparator C3 can output a sub-comparison result SCR32 indicating the first value (e.g., pass).

[0137] During the second time period, the fourth comparator C4 can compare the second sampled data SD2 with the fourth reference mode data RPD4. Because the second sampled data SD2 and the fourth reference mode data RPD4 are different, the fourth comparator C4 can output a sub-comparison result SCR42 indicating a second value (e.g., failure).

[0138] During the second time period, the fifth comparator C5 can compare the second sampled data SD2 with the fifth reference mode data RPD5. Because the second sampled data SD2 and the fifth reference mode data RPD5 are different, the fifth comparator C5 can output a sub-comparison result SCR52 indicating a second value (e.g., failure).

[0139] During the second time period, the sixth comparator C6 can compare the second sampled data SD2 with the sixth reference mode data RPD6. Because the second sampled data SD2 is different from the sixth reference mode data RPD6, the sixth comparator C6 can output a sub-comparison result SCR62 indicating a second value (e.g., failure).

[0140] During the third time period, the first comparator C1 can compare the third sampled data SD3 with the first reference mode data RPD1. Because the third sampled data SD3 is different from the first reference mode data RPD1, the first comparator C1 can output a sub-comparison result SCR13 indicating a second value (e.g., failure).

[0141] During the third time period, the second comparator C2 can compare the third sampled data SD3 with the second reference mode data RPD2. Because the third sampled data SD3 is different from the second reference mode data RPD2, the second comparator C2 can output a sub-comparison result SCR23 indicating a second value (e.g., failure).

[0142] During the third time period, the third comparator C3 can compare the third sampled data SD3 with the third reference mode data RPD3. Because the third sampled data SD3 is different from the third reference mode data RPD3, the third comparator C3 can output a sub-comparison result SCR33 indicating a second value (e.g., failure).

[0143] During the third time period, the fourth comparator C4 can compare the third sampled data SD3 with the fourth reference mode data RPD4. Because the third sampled data SD3 and the fourth reference mode data RPD4 are the same, the fourth comparator C4 can output a sub-comparison result SCR43 indicating the first value (e.g., pass).

[0144] During the third time period, the fifth comparator C5 can compare the third sampled data SD3 with the fifth reference mode data RPD5. Because the third sampled data SD3 and the fifth reference mode data RPD5 are different, the fifth comparator C5 can output a sub-comparison result SCR53 indicating a second value (e.g., failure).

[0145] During the third time period, the sixth comparator C6 can compare the third sampled data SD3 with the sixth reference mode data RPD6. Because the third sampled data SD3 and the sixth reference mode data RPD6 are different, the sixth comparator C6 can output a sub-comparison result SCR63 indicating a second value (e.g., failure).

[0146] Comparator cluster 1111a can provide a first comparison result CR1 to training control circuit 1115. The first comparison result CR1 may include sub-comparison results SCR11, SCR21, SCR31, SCR41, SCR51, and SCR61. Comparator cluster 1111a can also provide a second comparison result CR2 to training control circuit 1115. The second comparison result CR2 may include sub-comparison results SCR12, SCR22, SCR32, SCR42, SCR52, and SCR62. Comparator cluster 1111a can further provide a third comparison result CR3 to training control circuit 1115. The third comparison result CR3 may include sub-comparison results SCR13, SCR23, SCR33, SCR43, SCR53, and SCR63.

[0147] In some example embodiments, the training circuit 1110 can determine the state of a comparator by analyzing multiple comparison results. Depending on the state of the comparator, the comparator can be classified as one of an FP comparator (TFP), a PF comparator (TPF), a failed comparator (TFF), and a passed comparator (TPP). For example, a failed comparator (TFF) may include a first comparator C1, a second comparator C2, a fifth comparator C5, and a sixth comparator C6. A PF comparator (TPF) may include a third comparator C3, and an FP comparator (TFP) may include a fourth comparator C4. For example, because each of the comparison results SCR11, SCR12, and SCR13 of the first comparator C1 indicates a second value (e.g., failure), the first comparator C1 can be classified as a failed comparator (TFF). Similarly, because the comparison results of each of the second comparators C2, the fifth comparator C5, and the sixth comparator C6 indicate a second value (e.g., failure), each of the second comparator C2, the fifth comparator C5, and the sixth comparator C6 can be classified as a failed comparator (TFF).

[0148] In some example embodiments, the training circuit 1110 can determine the state of the reference pattern data by analyzing the comparison results. The state of the reference pattern data can be the same as or similar to the state of the comparator. The state of the reference pattern data can include PF state, FP state, FF state, and PP state. Similar to the comparator state, reference pattern data whose comparison result changes from a first value (e.g., Pass) to a second value (e.g., Fail) can have a PF state. Reference pattern data whose comparison result changes from a second value (e.g., Fail) to a first value (e.g., Pass) can have an FP state. Reference pattern data whose comparison result remains at a second value (e.g., Fail) can have an FF state. Reference pattern data whose comparison result remains at a first value (e.g., Pass) can have a PP state.

[0149] For example, the first reference mode data RPD1, the second reference mode data RPD2, the fifth reference mode data RPD5, and the sixth reference mode data RPD6 can be in the FF state. The third reference mode data RPD3 can be in the PF state, and the fourth reference mode data RPD4 can be in the FP state.

[0150] The training circuit 1110 can determine the left edge of the reference mode data in the FP state as the left edge of the data signal DQ. The training circuit 1110 can also determine the right edge of the reference mode data in the PF state as the right edge of the data signal DQ. For example, the left edge of the fourth reference mode data RPD4 can be detected as the left edge of the data signal DQ. The right edge of the third reference mode data RPD3 can be detected as the right edge of the data signal DQ. The training circuit 1110 can calculate the final delay based on the initial delay of the reference mode data corresponding to the FP state (e.g., the fourth reference mode data RPD4). The training circuit 1110 can detect the center of the window.

[0151] In some example embodiments, training circuit 1110 can perform multiple sub-training operations while changing (or increasing) the delay code. For example, training circuit 1110 can determine reference pattern data in which the comparison result changes from a second value (e.g., failure) to a first value (e.g., pass).

[0152] For example, training circuit 1110 can determine that the comparison result of the fourth reference mode data RPD4 is a second value (e.g., failure). Training circuit 1110 can determine the time point at which the comparison result corresponding to the fourth reference mode data RPD4 changes from the second value (e.g., failure) to a first value (e.g., pass), or the delay code corresponding to that time point. Regarding the fourth reference mode data RPD4, training circuit 1110 can determine the delay code corresponding to the sub-training operation in which the comparison result first indicates the first value (e.g., pass) among a plurality of sub-training operations as the first delay code. Training circuit 1110 can add the delay amount corresponding to the first delay code to the initial delay amount of the fourth reference mode data RPD4 and determine the left detection time point indicating the left edge.

[0153] For example, training circuit 1110 can determine reference pattern data where the comparison result changes from a first value (e.g., pass) to a second value (e.g., fail). For example, training circuit 1110 can determine that the comparison result of third reference pattern data RPD3 is a first value (e.g., pass). Subsequently, training circuit 1110 can determine the time point or delay code at which the comparison result corresponding to the third reference pattern data RPD3 changes from the first value (e.g., pass) to the second value (e.g., fail). Regarding the third reference pattern data RPD3, training circuit 1110 can determine the delay code corresponding to the sub-training operation in which the comparison result first indicates a second value (e.g., fail) among a plurality of sub-training operations as a second delay code. Training circuit 1110 can add the delay amount corresponding to the second delay code to the initial delay amount of the third reference pattern data RPD3 and determine the right edge as the right detection time point.

[0154] For example, training circuit 1110 can detect the center of the window based on the left and right detection time points. For example, training circuit 1110 can determine the center time point of the window by averaging the left and right detection time points. Training circuit 1110 can determine the center time point of the window as the final delay of the data signal DQ.

[0155] The training circuit 1110 can simultaneously compare multiple reference pattern data with the sampled data using first comparators C1 to sixth comparators C6. Therefore, the training circuit 1110 can adjust the latency within a maximum of "1 UI" or a total of "1 UI," but by using first comparators C1 to sixth comparators C6, it can achieve the effect of performing as much training as "total number of comparators x UI." In other words, although the latency has already been adjusted within "1 UI," by using a parallel structure, it can achieve the effect of adjusting the latency within "6 UI." Therefore, according to some example embodiments, training time can be reduced, and the training range can be increased and / or improved.

[0156] Figure 12 Based on some example embodiments Figure 1 A flowchart illustrating an example of the operation of the memory system 1000.

[0157] Reference Figure 12 Describe the initialization and / or boot-up operations of the memory system 1000. (Refer to...) Figure 1 and Figure 12The memory system 1000 can perform a power-on operation in operation S410. In operation S420, the memory system 1000 can perform an initialization operation. The memory controller 1100 and the memory device 1200 can perform the initialization operation in a predetermined or alternatively desired manner. During the initialization operation, the memory controller 1100 can provide power supply voltage to the memory device 1200, perform various initial setup operations, and read necessary or alternatively desired information from the memory device 1200 and / or set necessary or alternatively desired information.

[0158] Initialization operations may include ZQ calibration operations. The memory system 1000 can perform ZQ calibration operations. ZQ calibration operations may be referred to as adjusting the strength of the output driver connected to the data signal DQ or other signal lines to provide high data integrity, or setting the on-chip termination (ODT) value.

[0159] In operation S430, the memory system 1000 can perform a duty cycle correction circuit (DCC) training operation. The memory device 1200 can output data via the data signal DQ in sync with the rising and falling edges of the data strobe signal DQS. The window of the data signal DQ can correspond to the logic high interval and logic low interval of the data strobe signal DQS, respectively. Because the data strobe signal is generated based on the read enable signal / RE, the window of the data signal DQ can be determined based on the ratio of the logic high interval to the logic low interval of the read enable signal / RE.

[0160] Duty cycle mismatch may occur. In other words, because the logic high and logic low intervals of the read enable signal / RE are different from each other, the window of the data signal DQ can be different from each other, and therefore, a valid window may not be guaranteed. Therefore, by performing a DCC training operation, duty cycle correction can be performed on clock signals such as the read enable signal / RE to ensure a valid data window.

[0161] In operation S440, the memory system 1000 can perform a read training operation. For example, the memory controller 1100 can adjust the settings of the memory device 1200 and the memory controller 1100 to optimize the signal integrity of data read from the center of the memory device 1200 or window (or data eye diagram). For example, the read training operation can be performed independently on each of the first data line DQ1 to the nth data line DQn.

[0162] In operation S450, the memory system 1000 may perform a write training operation. The write training operation may include transmit and / or transmitter (TX) side write training and receive and / or receiver (RX) side write training. TX side write training may be omitted. For example, the memory controller 1100 may transmit and / or transfer data to the memory device 1200 and adjust the settings of the memory controller 1100 and the memory device 1200 such that the signal integrity or centering of the window (or data eye diagram) of the transmitted and / or transferred data is optimized. For example, a write training operation may be performed independently on each of the first data lines DQ1 to the nth data line DQn. After performing the initialization or training operations in operations S410 to S450 as described above, in operation S460, the memory system 1000 may perform normal operation (or general operation) based on the training results.

[0163] The training performed in operations S430, S440, and S450 can be directed to data training (DQ training). References to some example embodiments are provided. Figures 1 to 11 The described parallel training operations can be applied to training performed in operations S430, S440, and S450.

[0164] In some example embodiments, the training performed in operations S430, S440, and S450 can reference each other's results. For example, when write training is performed in operation S450, the read operation can be performed based on the training results of the read operation performed in step S440, and data integrity can be ensured.

[0165] Figure 13 Based on some example embodiments Figure 1 A flowchart illustrating an example of the operation of the memory controller 1100.

[0166] Reference Figure 1 , Figure 12 and Figure 13 The memory controller 1100 can perform read training operations and write training operations. For a write training operation, the memory controller 1100 can write pattern data to the memory device 1200 and read the written pattern data. For a read training operation, the memory controller 1100 can read the pattern data stored in the memory device 1200. The memory controller 1100 can compare the read pattern data with multiple reference pattern data, and based on the comparison results, can determine the center position of the window.

[0167] In operation S510, the memory controller 1100 can generate multiple reference mode data. The memory controller 1100 can generate multiple reference mode data by cyclically shifting the basic mode data.

[0168] In operation S520, the memory controller 1100 can perform a read training operation. Operation S520 may include operations S521 to S523. In operation S521, the memory controller 1100 can send and / or transfer read training pattern data to the memory device 1200. The memory controller 1100 can send and / or transfer one of a plurality of reference pattern data as read training pattern data to the memory device 1200. In operation S522, the memory controller 1100 can repeatedly perform sub-training operations. The memory controller 1100 can perform sub-training operations while changing the delay code. The memory controller 1100 can generate a comparison result while simultaneously comparing the sampled data with multiple reference pattern data.

[0169] In operation S523, the memory controller 1100 can calculate the center of the window and determine a delay amount, such as a final delay amount. The memory controller 1100 can find the center of the window based on the comparison result. The memory controller 1100 can determine the final delay amount corresponding to the center of the window. The memory controller 1100 can apply the final delay amount to the data signal DQ. Alternatively, in some example embodiments, the memory controller 1100 can adjust the delay amount of the data strobe signal DQS based on the final delay amount.

[0170] The memory controller 1100 can determine the amount of latency in reading training operations as the final read latency. For example, the final read latency can be defined by Equation 2. Dfr can indicate the final read latency, Di can indicate the initial latency of the reference pattern data in the FP state, and Dc can indicate the fine latency. For example, the fine latency can be referred to as the latency in which the comparison result changes from a first value (e.g., pass) to a second value (e.g., fail) or from a second value (fail) to a first value (e.g., pass) in multiple sub-training operations.

[0171] [Formula 2]

[0172]

[0173] In operation S530, memory controller 1100 can perform a write training operation. Operation S530 may include operations S531 to S533. In operation S531, memory controller 1100 can send and / or transfer write training mode data to memory device 1200. Memory controller 1100 can send and / or transfer one of a plurality of reference mode data as write training mode data to memory device 1200. In operation S532, memory controller 1100 can repeatedly perform sub-training operations. Memory controller 1100 can perform sub-training operations while changing the delay code. Memory controller 1100 can generate a comparison result while simultaneously comparing sampled data with multiple reference mode data.

[0174] In operation S533, the memory controller 1100 can calculate the center of the window and determine the final delay amount. The memory controller 1100 can find the center of the window based on the comparison result. The memory controller 1100 can determine the final delay amount corresponding to the center of the window. The memory controller 1100 can apply the final delay amount to the data signal DQ. Alternatively, in some example embodiments, the memory controller 1100 can adjust the delay amount of the data strobe signal DQS based on the final delay amount.

[0175] The memory controller 1100 can determine the amount of latency in writing a training operation as the final write latency. For example, the final write latency can be defined by Equation 3. Dfw can indicate the final write latency, Di can indicate the initial latency of the reference pattern data in the FP state, and Dc can indicate the fine latency. For example, the fine latency can be referred to as the latency in which the comparison result changes from a first value (e.g., pass) to a second value (e.g., fail) or from a second value (e.g., fail) to a first value (e.g., pass) in multiple sub-training operations.

[0176] [Formula 3]

[0177]

[0178] Figure 14 Based on some example embodiments Figure 1 A more detailed block diagram of the training circuit 1110 in the diagram.

[0179] Reference Figure 1 and Figure 14The training circuit 1110a may include a comparator cluster 1111, a pattern generator 1112, a delay circuit 1113, a sampling circuit 1114, a training control circuit 1115, a pattern register 1116, and a delay register 1117. The comparator cluster 1111 may include a first comparator C1 to an nth comparator Cn. For ease of description, repeated descriptions of the components given above are omitted.

[0180] Pattern data can be stored in pattern register 1116. For example, at least one of basic pattern data, multiple reference pattern data, and training pattern data can be stored in pattern register 1116. In some example embodiments, pattern generator 1112 can generate multiple reference pattern data based on basic pattern data and store the multiple reference pattern data in pattern register 1116. Pattern generator 1112 can determine any one of the multiple reference pattern data as training pattern data. Pattern generator 1112 can store the determined training pattern data in pattern register 1116.

[0181] In some example embodiments, comparator cluster 1111 can perform comparison operations by referring to multiple reference pattern data stored in pattern register 1116. Memory controller 1100 can send and / or transfer training pattern data stored in pattern register 1116 to memory device 1200.

[0182] The final delay amount can be stored in delay register 1117. In some example embodiments, training control circuitry 1115 may store final delay information indicating the final delay amount of data signal DQ in delay register 1117. Alternatively, in some example embodiments, training control circuitry 1115 may store determined timing compensation information in delay register 1117. Timing compensation information may indicate the degree of timing compensation for data signal DQ and / or the degree of timing compensation for data strobe signal DQS. For example, delay register 1117 may store the final delay amount determined during a write training operation or during a read training operation. After the training operation is completed, memory controller 1100 may refer to the stored final delay information to perform input / output operations.

[0183] Figure 15 Based on some example embodiments Figure 1 A more detailed block diagram of the training circuit 1110 in the diagram.

[0184] Although data signals are Figures 1 to 14 The signal is represented as data signal DQ, but those skilled in the art will understand that this can include multiple data signals rather than a single signal. According to some example embodiments, see... Figure 15The parallel training operation on multiple data signals is described in more detail.

[0185] Training circuit 1110b can be configured to perform training operations. Training circuit 1110b can adjust the sampling time points of each of the first data signals DQ1 to the fourth data signals DQ4 provided by memory device 1200 to be centered by performing training. For example, in order to adjust the sampling time points of the first data signals DQ1 to the fourth data signals DQ4 to be centered, the operation of detecting the center of each of the first data signals DQ1 to the fourth data signals DQ4 can be pre-executed in training circuit 1110b.

[0186] The training circuit 1110b may include multiple data input / output pads (DQP), data strobe pads (DQSP), a delay-locked loop (DLL), a comparator cluster 1111, a pattern generator 1112, a delay circuit 1113, a sampling circuit 1114, and a training control circuit 1115. Although Figure 15 Multiple data input / output pads (DQPs), data strobe pads (DQSPs), and a delay-locked loop (DLL) are shown included in the training circuit 1110b, but the example embodiment is not limited thereto. In some example embodiments, the multiple data input / output pads (DQPs), data strobe pads (DQSPs), and delay-locked loop (DLL) may be configured externally to the training circuit 1110b.

[0187] The data strobe pad DQSP can receive a data strobe signal DQS from the memory device 1200. However, the example embodiments are not limited thereto, and in some example embodiments, the data strobe pad DQSP can output the data strobe signal DQS to the memory device 1200, and the component for outputting the data strobe signal DQS can be disposed in the memory controller 1100. The data strobe pad DQSP can send and / or transmit the received data strobe signal DQS to the delay-locked loop DLL.

[0188] Multiple data input / output pads (DQPs) can receive first data signals DQ1 through fourth data signals DQ4 from memory device 1200. However, the example embodiments are not limited thereto, and in some example embodiments, the data input / output pads (DQPs) can output the first data signals DQ1 through fourth data signals DQ4 to memory device 1200, and components for outputting the first data signals DQ1 through fourth data signals DQ4 can be disposed in memory controller 1100. The multiple data input / output pads (DQPs) can transmit and / or transfer pattern data received via the first data signals DQ1 through fourth data signals DQ4 to delay circuit 1113. Due to differences in noise or delay characteristics, the first data signals DQ1 through fourth data signals DQ4 can have different delays for each data signal. Therefore, it may be advantageous to perform alignment between the data strobe signal DQS and the first data signals DQ1 through fourth data signals DQ4 during training.

[0189] Delay circuit 1113 can receive pattern data (e.g., multiple bits of data) from multiple data input / output pads (DQP). Delay circuit 1113 can receive a delay control signal from training control circuit 1115. For example, the delay control signal can indicate a delay code. Delay circuit 1113 can delay and output the received pattern data in response to the delay control signal.

[0190] For example, each of the delay circuits 1113 may include a plurality of delay units for adjusting the timing of the data signal corresponding to each of the delay circuits 1113. The delay circuit 1113 may, in response to a delay control signal, individually control the timing (or delay amount) of sampling each of the first data signal DQ1 to the fourth data signal DQ4 by activating the plurality of delay units. The delay circuit 1113 may provide the delayed first data signal DQ1 to the fourth data signal DQ4 to the sampling circuit 1114.

[0191] Multiple data input / output pads DQP may include first data input / output pads DQP1 through fourth data input / output pads DQP4. Delay circuit 1113 may include first sub-delay circuits SDC1 through fourth sub-delay circuits SDC4. Multiple data signals DQ may include first data signal DQ1 through fourth data signal DQ4. Multiple delay control signals may include first input delay control signal through fourth input delay control signal.

[0192] The first sub-delay circuit SDC1 to the fourth sub-delay circuit SDC4 can be connected to the first data input / output pads DQP1 to DQP4, respectively. For example, the first sub-delay circuit SDC1 can be connected to the first data input / output pad DQP1, the second sub-delay circuit SDC2 can be connected to the second data input / output pad DQP2, the third sub-delay circuit SDC3 can be connected to the third data input / output pad DQP3, and the fourth sub-delay circuit SDC4 can be connected to the fourth data input / output pad DQP4.

[0193] Each of the first sub-delay circuits SDC1 to the fourth sub-delay circuit SDC4 can receive a corresponding input delay control signal. Each of the first sub-delay circuits SDC1 to the fourth sub-delay circuit SDC4 can individually control the timing of the data signal (e.g., the amount of delay) in response to its corresponding input delay control signal. For example, in response to the first input delay control signal, the first sub-delay circuit SDC1 can adjust the timing of transmitting and / or transmitting the first data signal DQ1 (e.g., the amount of delay). Similarly, the remaining second sub-delay circuits SDC2 to the fourth sub-delay circuit SDC4 can each receive corresponding second to fourth input delay control signals, and adjust the timing of the data signal accordingly, and therefore their detailed description is omitted.

[0194] Sampling circuit 1114 can receive clock or delayed data strobe signals from delay-locked loop DLL. Sampling circuit 1114 can receive first data signals DQ1 to fourth data signals DQ4 from delay circuit 1113. Sampling circuit 1114 can store the delayed pattern data received via first data signals DQ1 to fourth data signals DQ4 as sampled data and output the sampled data. Sampling circuit 1114 can provide the sampled data to comparator cluster 1111.

[0195] Comparator cluster 1111 may include a first sub-comparator group SCG1 through a fourth sub-comparator group SCG4. In some example embodiments, each of the first sub-comparator groups SCG1 through the fourth sub-comparator group SCG4 may include multiple comparators. For example, each of the multiple comparators included in the first sub-comparator group SCG1 may compare reference mode data with its corresponding first sub-sampled data. The first sub-sampled data may indicate sampled data generated based on mode data received via a first data signal DQ1. The first sub-comparator group SCG1 may simultaneously compare multiple reference mode data with the first sub-sampled data and generate a comparison result. The first sub-comparator group SCG1 may provide the comparison result corresponding to the first data signal DQ1 to the training control circuit 1115.

[0196] The training control circuit 1115 can receive comparison results from the comparator cluster 1111. Based on the comparison results, the training control circuit 1115 can detect the FP comparator and PF comparator of each of the first data signals DQ1 to the fourth data signals DQ4, and based on the detected FP and PF comparators, detect the center of each of the first data signals DQ1 to the fourth data signals DQ4. In other words, the training control circuit 1115 can detect the left edge LE and right edge RE of each of the first data signals DQ1 to the fourth data signals DQ4, and can detect the center of each of the first data signals DQ1 to the fourth data signals DQ4 based on the detected left edge LE and right edge RE.

[0197] The training control circuit 1115 can output a clock control signal and send and / or transmit the clock control signal to the delay-locked loop DLL. The training control circuit 1115 can output a delay control signal and send and / or transmit the delay control signal to the delay circuit 1113.

[0198] The training control circuit 1115 can control the delay-locked loop (DLL) using a clock control signal. The training control circuit 1115 can control the clock control signal and adjust the delay of the data strobe signal DQS.

[0199] In some example embodiments, the training control circuit 1115 can repeatedly perform sub-training operations while shifting each of the first data signals DQ1 to the fourth data signals DQ4 by a shift delay step (or tick time). The training control circuit 1115 can repeat the sub-training operation while shifting each of the first data signals DQ1 to the fourth data signals DQ4 by a shift delay step (or tick time) relative to '1 UI'.

[0200] For example, the delay step (or tick time) can be the smallest unit of delay of the data strobe signal DQS or data signal DQ shifted or delayed by the training circuit 1110. Alternatively, in some example embodiments, the delay step (or tick time) can be the smallest unit by which the training circuit 1110 shifts the data strobe signal DQS or data signal DQ.

[0201] The training control circuit 1115 can detect the FP comparator and PF comparator of each of the first data signals DQ1 to the fourth data signals DQ4. Alternatively, in some example embodiments, the training control circuit 1115 can detect the reference mode data in the FP state and the reference mode data in the PF state. Therefore, the training control circuit 1115 can detect the left edge LE and right edge RE of each of the first data signals DQ1 to the fourth data signals DQ4.

[0202] The training control circuit 1115 can adjust the timing or delay amount of each of the first data signals DQ1 to the fourth data signals DQ4 by using a delay control signal. The training control circuit 1115 can detect the center of the window of each of the first data signals DQ1 to the fourth data signals DQ4 based on the FP comparator and PF comparator of each of the detected first data signals DQ1 to the fourth data signals DQ4. The training control circuit 1115 can align the data signal DQ or the data strobe signal DQS based on the FP comparator and PF comparator of each of the detected first data signals DQ1 to the fourth data signals DQ4. The training control circuit 1115 can generate the delay control signal based on the FP comparator and PF comparator (or, left edge LE offset and right edge RE offset).

[0203] The Delay-Locked Loop (DLL) can receive a data strobe signal DQS from the data strobe pad DQSP. The DLL can receive a clock control signal from the training control circuit 1115. The DLL can delay and output the data strobe signal DQS based on the clock control signal. The DLL can provide the delayed data strobe signal DQS to the sampling circuit 1114. For example, the DLL may include multiple delay units for controlling the timing of the data strobe signal DQS. The DLL can adjust the timing of the data strobe signal DQS by activating the multiple delay units under the control of the clock control signal. However, the example embodiments are not limited thereto, and in some example embodiments, the memory controller 1100 may include a phase-locked loop (PLL) instead of a DLL.

[0204] Figures 16A to 16F This is a graph showing the effect of a memory system based on some example embodiments.

[0205] Figure 16A , Figure 16C and Figure 16E The results of general training operations according to some example embodiments are shown, and Figure 16B , Figure 16D and Figure 16F The results of parallel training operations according to some example embodiments are shown. (Refer to...) Figures 16A to 16F The horizontal axis can indicate the total number of sub-training operations (or the number of retries), and the vertical axis can indicate the comparison results. For example, the comparison results can indicate whether the reference pattern data is the same as the sampled data.

[0206] In some example embodiments, it is assumed that Figure 16A and Figure 16B The initial latency is approximately -0.9 UI. Figure 16C and Figure 16D The initial latency is approximately -2.7 UI, and Figure 16E and Figure 16F The initial latency is approximately -8.3 UI. (See reference...) Figure 16A , Figure 16C and Figure 16E Assume that each of the first interval T1 to the ninth interval T9 indicates 1 UI. (Refer to...) Figure 16B , Figure 16D , Figure 16F Solid lines indicate reference mode data in PF state, and dashed lines indicate reference mode data in FP state.

[0207] Reference Figure 16A When the number of sub-training operations is less than the first step number v1, the comparison result can be a second value (e.g., failure). When the number of sub-training operations is the first step number v1 (e.g., equal to the first step number v1), the comparison result can change from a second value (e.g., failure) to a first value (e.g., pass). When the number of sub-training operations is greater than the first step number v1 and less than the second step number v2, the comparison result can be a first value (e.g., pass). When the number of sub-training operations is the second step number v2 (e.g., equal to the second step number v2), the comparison result can change from a first value (e.g., pass) to a second value (e.g., failure). When the number of sub-training operations is greater than the second step number v2, the comparison result can indicate a second value (e.g., failure).

[0208] The training circuit can repeatedly perform sub-training operations while changing the delay code (or increasing the delay amount) until the left and right edges are detected. For example, when the initial delay amount is approximately -0.9 UI, the training circuit can repeat the sub-training operation approximately 25 times. The training circuit can detect the left edge LE in the first interval T1 and the right edge RE in the second interval T2. For example, the training circuit can detect the center of the window by increasing the delay amount to a maximum of 2 UI or a total of 2 UI.

[0209] Reference Figure 16BWhen the number of sub-training operations is less than the third step number v3, the comparison result of the reference pattern data with the PF state can include a first value (e.g., pass), and the comparison result of the reference pattern data with the FP state can include a second value (e.g., fail). When the number of sub-training operations is the third step number v3, the comparison result of the reference pattern data with the PF state can change from the first value (e.g., pass) to the second value (e.g., fail), and the comparison result of the reference pattern data with the FP state can change from the second value (e.g., fail) to the first value (e.g., pass). When the number of sub-training operations is greater than the third step number v3, the comparison result of the reference pattern data with the PF state can include a second value (e.g., fail), and the comparison result of the reference pattern data with the FP state can include a first value (e.g., pass).

[0210] The training circuit 1110 can repeatedly perform sub-training operations while changing the delay code (or increasing the delay amount) until reference pattern data with FP state and reference pattern data with PF state are detected. For example, when the initial delay amount is about -0.9 UI, the training circuit 1110 can repeat the sub-training operation about 8 times. For example, the training circuit 1110 can detect the center of the window by increasing the delay amount to the maximum or a total of 1 UI.

[0211] Reference Figure 16C When the number of sub-training operations is less than the fourth step number v4, the comparison result can be a second value (e.g., failure). When the number of sub-training operations is the fourth step number v4 (e.g., equal to the fourth step number v4), the comparison result can change from a second value (e.g., failure) to a first value (e.g., pass). When the number of sub-training operations is greater than the fourth step number v4 and less than the fifth step number v5, the comparison result can be a first value (e.g., pass). When the number of sub-training operations is the fifth step number v5 (e.g., equal to the fifth step number v5), the comparison result can change from a first value (e.g., pass) to a second value (e.g., failure). When the number of sub-training operations is greater than the fifth step number v5, the comparison result can indicate a second value (e.g., failure).

[0212] For example, with an initial latency of approximately -2.7 UI, the training circuit can repeat the sub-training operation approximately 60 times. The training circuit can detect the left edge (LE) in the third interval T3 and the right edge (RE) in the fourth interval T4. For example, the training circuit can detect the center of the window by increasing the latency to the maximum or a total of 4 UI.

[0213] Reference Figure 16DWhen the number of sub-training operations is less than step number v6, the comparison result of the reference pattern data with PF state can include a first value (e.g., pass), and the comparison result of the reference pattern data with FP state can include a second value (e.g., fail). When the number of sub-training operations is step number v6, the comparison result of the reference pattern data with PF state can change from the first value (e.g., pass) to the second value (e.g., fail), and the comparison result of the reference pattern data with FP state can change from the second value (e.g., fail) to the first value (e.g., pass). When the number of sub-training operations is greater than step number v6, the comparison result of the reference pattern data with PF state can include a second value (e.g., fail), and the comparison result of the reference pattern data with FP state can include a first value (e.g., pass).

[0214] For example, when the initial latency is approximately -2.7 UI, the training circuit 1110 can repeat the sub-training operation approximately 4 times. For example, the training circuit 1110 can detect the center of the window by increasing the latency to a maximum or a total of 1 UI.

[0215] Reference Figure 16E When the number of sub-training operations is less than the seventh step number v7, the comparison result can be a second value (e.g., failure). When the number of sub-training operations is the seventh step number v7 (e.g., equal to the seventh step number v7), the comparison result can change from a second value (e.g., failure) to a first value (e.g., pass). When the number of sub-training operations is greater than the seventh step number v7 and less than the eighth step number v8, the comparison result can be a first value (e.g., pass). When the number of sub-training operations is the eighth step number v8 (e.g., equal to the eighth step number v8), the comparison result can change from a first value (e.g., pass) to a second value (e.g., failure). When the number of sub-training operations is greater than the eighth step number v8, the comparison result can indicate a second value (e.g., failure).

[0216] For example, with an initial latency of approximately -8.3 UI, the training circuit can repeat the sub-training operation approximately 170 times. The training circuit can detect the left edge (LE) in the eighth interval T8 and the right edge (RE) in the ninth interval T9. For example, the training circuit can detect the center of the window by increasing the latency to the maximum or a total of 9 UI.

[0217] Reference Figure 16FWhen the number of sub-training operations is less than the ninth step number v9, the comparison result of the reference pattern data with the PF state can include a first value (e.g., pass), and the comparison result of the reference pattern data with the FP state can include a second value (e.g., fail). When the number of sub-training operations is the ninth step number v9 (e.g., equal to the ninth step number v9), the comparison result of the reference pattern data with the PF state can change from the first value (e.g., pass) to the second value (e.g., fail), and the comparison result of the reference pattern data with the FP state can change from the second value (e.g., fail) to the first value (e.g., pass). When the number of sub-training operations is greater than the ninth step number v9, the comparison result of the reference pattern data with the PF state can include a second value (e.g., fail), and the comparison result of the reference pattern data with the FP state can include a first value (e.g., pass).

[0218] For example, when the initial latency is approximately -8.3 UI, the training circuit 1110 can repeat the sub-training operation approximately 15 times. For example, the training circuit 1110 can detect the center of the window by increasing the latency to a maximum or a total of 1 UI.

[0219] As described above, the number of sub-training operations performed in a typical training circuit can increase rapidly with an increase in the initial delay. However, the training circuit 1110 according to some example embodiments can detect the center of the window by increasing the delay of the data signal DQ by up to 1 UI. Therefore, training execution time can be reduced and training speed can be improved.

[0220] Figure 17 This is a block diagram illustrating a memory system 2000 according to some example embodiments.

[0221] Reference Figure 17 The memory system 2000 may include a memory controller 2100 and a memory module 2200. The memory module 2200 may include a buffer device 2210 (or a buffer chip) and a plurality of memory devices 2221 to 222n (or memory chips). For example, each of the plurality of memory devices 2221 to 222n may be implemented as a separate chip or a separate package. The buffer device 2210 may be connected between the memory controller 2100 and the plurality of memory devices 2221 to 222n.

[0222] The memory controller 2100 can control memory operations on multiple memory devices 2221 to 222n. The memory controller 2100 can send and / or transmit control signals CTRL, data signals DQ, and data strobe signals DQS. The buffer device 2210 can receive address ADDR, command CMD, and data DATA. The buffer device 2210 can route address ADDR, command CMD, and data DATA to the multiple memory devices 2221 to 222n. The buffer device 2210 can send and / or transmit address ADDR, command CMD, and data DATA to the memory device corresponding to address ADDR or control signal CTRL.

[0223] Multiple memory devices 2221 to 222n can receive address ADDR, command CMD and data DATA from buffer device 2210, and perform memory operations (or input / output operations) including write operations and read operations based on the received address ADDR, command CMD and data DATA.

[0224] The plurality of memory devices 2221 to 222n may include a memory cell array (not shown), and the memory cell array may include a plurality of memory cells arranged in a region where a plurality of word lines and a plurality of bit lines intersect each other.

[0225] In some example embodiments, the plurality of memory cells included in each of the plurality of memory devices 2221 to 222n may include volatile memory cells or non-volatile memory cells. For example, the plurality of memory cells may include non-volatile memory cells such as flash memory, resistive random access memory (RAM) (RRAM), phase-change RAM (PRAM) and MRAM, and / or additionally, volatile memory cells such as DRAM.

[0226] The memory controller 2100 may include training circuitry 2110. Training circuitry 2110 can generate multiple reference pattern data. Training circuitry 2110 can control the parallel training operation of buffer device 2210. Training circuitry 2110 can execute the parallel training operation of buffer device 2210. Memory controller 2100 can determine the amount (or degree of delay) of signals sent and / or transmitted to buffer device 2210 and the amount of delay of signals received from buffer device 2210.

[0227] Buffer device 2210 may include training circuitry 2211. Training circuitry 2211 can generate multiple reference pattern data. Training circuitry 2211 can control parallel training operations on multiple memory devices 2221 to 222n. Training circuitry 2211 can perform parallel training operations on multiple memory devices 2221 to 222n. Memory controller 2100 can determine the amount (or degree of) delay of signals sent and / or transmitted to each of the multiple memory devices 2221 to 222n and the amount of delay of signals received from each of the multiple memory devices 2221 to 222n.

[0228] Figure 18 This is a block diagram of a storage system 3000 according to some example embodiments.

[0229] Reference Figure 18 The storage system 3000 may include a host device 10 and a storage device 3100. The host device 10 can control data processing operations on the storage device 3100, such as data read operations, data write operations, etc. The host device 10 may be referred to as a data processing device capable of processing data, such as a CPU, processor, microprocessor, and / or application processor (AP). The host device 10 may execute an operating system (OS) and / or various applications.

[0230] The host device 10 may include a host controller 11 and a host memory 12. The host controller 11 may include means configured to control the overall operation of the host device 10 and / or control the storage device 3100 from the host device 10 side. The host memory 12 may include buffer memory, cache memory, and / or operational memory used by the host device 10. The host memory 12 may load various software and / or data driven by the host device 10.

[0231] Storage device 3100 can operate under the control of host device 10. Storage device 3100 may include storage controller 3200 and non-volatile memory device 3300. Storage controller 3200 can manage non-volatile memory device 3300. Storage controller 3200 can perform various management operations for the efficient use of non-volatile memory device 3300. Non-volatile memory device 3300 may include multiple non-volatile memories.

[0232] When the non-volatile memory device 3300 includes flash memory, the flash memory may include a two-dimensional (2D) NAND array and / or a three-dimensional (3D) (or vertical) NAND memory array. In some example embodiments, the memory device 3100 may also include a variety of other types of non-volatile memory. For example, the memory device 3100 may include MRAM, spin-torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), RRAM, and / or other various types of memory.

[0233] The storage controller 3200 may include a CPU 3210, a flash translation layer (FTL) 3220, a buffer memory 3230, an error correction code (ECC) engine 3240, a host interface circuit 3250, and a non-volatile memory interface circuit 3260. The storage controller 3200 may also include a working memory (not shown) in which the FTL 3220 is loaded, and data write and read operations on the non-volatile memory device 3300 can be controlled by the CPU 3210 through the execution of the flash translation layer.

[0234] In some example embodiments, CPU 3210 may be implemented as a multi-core processor, such as a dual-core processor and / or a quad-core processor. FTL 3220 may be loaded into the operational memory of memory controller 3200. For example, the operational memory may be implemented as volatile memory, such as SRAM and DRAM, or as non-volatile memory, such as flash memory and PRAM.

[0235] The FTL 3220 can perform various functions, such as address mapping, wear leveling, and garbage collection. Address mapping operations can include translating logical addresses received from host device 10 into physical addresses for actually storing data in non-volatile memory device 3300. Wear leveling operations can be techniques for preventing and / or reducing excessive degradation of specific blocks or alternatively desired blocks by using blocks in non-volatile memory device 3300 evenly, and can be implemented using firmware techniques that balance the erase counts of physical blocks. Garbage collection operations can be techniques for ensuring available capacity in non-volatile memory device 3300 by copying valid data from a block to a new block and then erasing the block.

[0236] The buffer memory 3230 can be configured to temporarily store write data received from the host device 10 and / or data read from the non-volatile memory device 3300 under the control of the memory controller 3200. Hereinafter, it is assumed that the buffer memory 3230 includes SRAM. However, the example embodiment is not limited thereto.

[0237] The ECC engine 3240 can perform error detection and correction operations on read data read from the non-volatile memory device 3300. The ECC engine 3240 can generate parity bits for the write data to be written into the non-volatile memory device 3300, and the generated parity bits can be stored in the non-volatile memory device 3300 along with the write data. When reading data from the non-volatile memory device 3300, the ECC engine 3240 can correct errors in the read data using the parity bits read from the non-volatile memory device 3300 and the read data itself, and output the error-corrected read data.

[0238] The host interface circuit 3250 can send and receive packets to and from the host device 10. Packets sent from and / or transmitted to the host interface circuit 3250 may include commands, request RQs, and / or data to be recorded in the non-volatile memory device 3300, and packets sent from and / or transmitted to the host device 10 may include responses to commands and / or data read from the non-volatile memory device 3300.

[0239] The non-volatile memory interface circuit 3260 can send and / or transfer data to be recorded in the non-volatile memory device 3300, or receive data read from the non-volatile memory device 3300. The non-volatile memory interface circuit 3260 can be implemented in accordance with standard conventions, such as toggle and / or open NAND flash interface (ONFI).

[0240] In some example embodiments, the non-volatile memory interface circuit 3260 may include a training circuit 3261. (Based on reference...) Figures 1 to 17 According to the methods described in some example embodiments, training circuit 3261 can perform parallel training operations on non-volatile memory device 3300. Training circuit 3261 can simultaneously compare multiple reference pattern data with sampled data using multiple comparators. Training circuit 3261 can simultaneously train delays in units of delay steps and delays in units of unit intervals. Therefore, training time can be reduced and training speed can be increased.

[0241] According to some example embodiments, the memory system can generate multiple reference pattern data in which basic pattern data is cyclically shifted in unit intervals, and a comparison result can be generated by comparing sampled data and multiple reference pattern data in parallel. The memory system can determine the final delay of the data signal based on the comparison result. Therefore, a memory system with improved training speed, a memory controller, and / or a method of operating the memory controller is provided.

[0242] Some example embodiments provide a method for operating a memory system including a memory device and a memory controller configured to control the memory device. The method of operating the memory system includes: generating a plurality of reference pattern data by the memory controller through cyclically shifting basic pattern data in unit intervals; generating a comparison result by the memory controller by repeatedly performing sub-training operations to simultaneously compare sampled data with the plurality of reference pattern data; and calculating the center of a window of a data signal by the memory controller based on the comparison result.

[0243] In some example embodiments, the sub-training operation includes: receiving pattern data from a memory device via a data signal by a memory controller; generating delayed pattern data by the memory controller by delaying the pattern data based on a delay code; generating sampled data by the memory controller by sampling the delayed pattern data based on a clock signal generated based on a data strobe signal received from the memory device; and generating a comparison result by the memory controller by simultaneously comparing the sampled data with multiple reference pattern data.

[0244] In some example embodiments, in response to the sampled data being the same as the corresponding reference mode data in a plurality of reference mode data, the comparison result indicates a first value, and in response to the sampled data being different from the corresponding reference mode data in a plurality of reference mode data, the comparison result indicates a second value.

[0245] In some example embodiments, the method of operating the memory system further includes: detecting a pass-fail (PF) comparator by a memory controller based on a comparison result, the PF comparator including a comparison result value that changes from a first value to a second value; and detecting a fail-pass (FP) comparator by the memory controller based on the comparison result, the FP comparator including a comparison result value that changes from a second value to a first value.

[0246] Additionally, some example embodiments provide a non-transitory computer-readable medium including instructions that, when executed by a memory system including a memory device and a memory controller configured to control the memory device, cause the memory system to at least: generate a plurality of reference pattern data by cyclically shifting basic pattern data in unit intervals; generate a comparison result by repeatedly performing sub-training operations to simultaneously compare sampled data with the plurality of reference pattern data; and calculate the center of a window of the data signal based on the comparison result.

[0247] It should be understood that elements and / or properties described herein as "identical" or "equal" to other elements, and / or properties described herein as "identical," "identical," or "equal" to other elements, may be "identical," "identical," or "equal" to other elements and / or properties, or "substantially identical," "substantially identical," or "substantially equal." Elements and / or properties that are identical or substantially identical to other elements and / or properties may be structurally identical or substantially identical, functionally identical or substantially identical, and / or compositionally identical or substantially identical.

[0248] As described herein, any device, electronic device, module, unit, and / or part thereof and / or any portion thereof according to any example embodiment may include one or more instances of processing circuitry, may be included in one or more instances of processing circuitry, and / or may be implemented by one or more instances of processing circuitry, such as hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field-programmable gate array (FPGA) and programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, processing circuitry may include a non-transitory computer-readable storage device (e.g., memory), such as a solid-state drive (SSD), storing instruction programs, and a processor (e.g., a CPU) configured to execute instruction programs to implement functions and / or methods performed by some or all of any device, electronic device, module, unit, and / or part thereof according to any example embodiment.

[0249] Furthermore, any or all elements described with reference to the accompanying drawings may communicate with any or all other elements described with reference to the accompanying drawings. For example, any element may communicate unidirectionally and / or bidirectionally and / or broadcastly with any or all other elements in the drawings to transmit and / or exchange and / or receive information such as, but not limited to, data and / or commands in a manner such as serial and / or parallel via a bus such as a wireless and / or wired bus (not shown). The information may be encoded in various formats, such as analog and / or digital formats.

[0250] The above description provides some exemplary embodiments for implementing the inventive concept. The inventive concept includes the above exemplary embodiments, as well as exemplary embodiments whose design is simply modified and / or easily modified. Furthermore, the inventive concept includes techniques that can be readily modified and implemented using the exemplary embodiments. Therefore, the scope of the inventive concept should not be construed as limited to the above exemplary embodiments, but can be defined by the claims of the inventive concept and their equivalents.

Claims

1. A memory system, comprising: Memory devices; and A memory controller, configured to control the memory device, includes a training circuit configured to... Multiple reference pattern data are generated, the multiple reference pattern data including multiple reference pattern data, which are generated by cyclically shifting basic pattern data in units of interval; A comparison result is generated by simultaneously comparing the multiple reference mode data with the sampled data. as well as The center of the window for the data signal is calculated based on the comparison result.

2. The memory system according to claim 1, wherein, The training circuit includes, A pattern generator is configured to generate the plurality of reference pattern data based on the basic pattern data; and A comparator cluster, comprising multiple comparators, and Each of the plurality of comparators is configured to, Receive the sampled data; Receive the corresponding reference pattern data from the pattern generator; The sampled data is compared with the corresponding reference mode data; as well as Generate the comparison results.

3. The memory system according to claim 2, wherein, The training circuit also includes, The delay circuit is configured to receive a delay code from the training control circuit, receive pattern data from the memory device via a data signal, and delay the pattern data based on the delay code. The sampling circuit is configured to receive delay mode data output by the delay circuit, receive a clock signal, and generate the sampled data by sampling the delay mode data based on the clock signal. and The training control circuit is configured to generate the delay code, receive the comparison result from the comparator cluster, and calculate the center of the window of the data signal based on the comparison result. The clock signal is generated based on a data strobe signal received from the memory device.

4. The memory system according to claim 3, wherein, The basic mode data includes bit data corresponding to the basic mode and bit data corresponding to the auxiliary mode.

5. The memory system according to claim 3, wherein, The training control circuit is configured to activate an unused comparator among the plurality of comparators by using a comparator control signal.

6. The memory system according to claim 3, wherein, In response to the sampled data being identical to the corresponding reference mode data, the comparison result indicates a first value, and In response to the fact that the sampled data is different from the corresponding reference mode data, the comparison result indicates a second value.

7. The memory system according to claim 6, wherein, The training control circuit is configured to detect, based on the comparison result, a pass-fail PF comparator and a fail-pass FP comparator among the plurality of comparators, wherein the pass-fail PF comparator includes a comparison result value that changes from the first value to the second value, and the fail-pass FP comparator includes a comparison result value that changes from the second value to the first value.

8. The memory system according to claim 7, wherein, The training control circuit is configured to determine the final delay of the data signal based on a first initial delay corresponding to the pass-fail PF comparator and a second initial delay corresponding to the fail-pass FP comparator.

9. The memory system according to claim 8, wherein, The training circuit also includes a delay register configured to store the final delay amount.

10. The memory system according to claim 3, wherein, The training circuit further includes a mode register configured to store at least one of the basic mode data, the plurality of reference mode data, and training mode data.

11. The memory system according to claim 3, wherein, The training circuit is configured to repeatedly perform sub-training operations while increasing the delay code to 1 unit interval UI, and The sub-training operation indicates the operation of receiving the pattern data, comparing the sampled data with the plurality of reference pattern data, and generating the comparison result.

12. The memory system according to claim 1, wherein, The memory controller is configured to determine any one of the plurality of reference mode data as training mode data and send the training mode data to the memory device.

13. The memory system according to claim 12, wherein, The memory device is configured to receive the training pattern data and send a signal generated by sampling the training pattern data as pattern data to the memory controller.

14. The memory system according to claim 12, wherein, The training pattern data includes data in which the basic pattern data has been cyclically shifted by the maximum unit interval.

15. A method of operating a memory controller, the method comprising: Multiple reference pattern data are generated by cyclically shifting the basic pattern data in unit intervals. The comparison results are generated by simultaneously comparing the sampled data with the multiple reference pattern data through repeated execution of sub-training operations; as well as The center of the window for the data signal is calculated based on the comparison result.

16. The method according to claim 15, wherein, The sub-training operation includes: Pattern data is received from an external memory device via the data signal; Delayed pattern data is generated by delaying the pattern data based on a delay code; The sampled data is generated by sampling the delay mode data based on a clock signal, wherein the clock signal is generated based on a data strobe signal received from the external memory device; and The comparison result is generated by simultaneously comparing the sampled data with the plurality of reference pattern data.

17. The method according to claim 15, wherein, In response to the sampled data being identical to a corresponding reference mode data among the plurality of reference mode data, the comparison result indicates a first value, and In response to the sampled data being different from the corresponding reference mode data among the plurality of reference mode data, the comparison result indicates a second value.

18. The method of claim 17, further comprising: Based on the comparison result, a pass-fail PF comparator is detected, wherein the pass-fail PF comparator includes a comparison result value that has changed from the first value to the second value; as well as The failure-through-FP comparator is based on the comparison result, and the failure-through-FP comparator includes a comparison result value that has changed from the second value to the first value.

19. The method of claim 18, further comprising: The final delay of the data signal is determined based on a first initial delay corresponding to the pass-fail PF comparator and a second initial delay corresponding to the fail-pass FP comparator.

20. A memory controller configured to control a memory device, the memory controller comprising: Training circuit, the training circuit includes, The pattern generator is configured to generate multiple reference pattern data by cyclically shifting the basic pattern data in unit intervals; and A comparator cluster includes multiple comparators, each of which is configured to receive sampled data, receive corresponding reference pattern data from the pattern generator, compare the sampled data with the corresponding reference pattern data, and generate a comparison result.

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