Storage device and method of operating the same

Abstract

A storage device is provided, comprising: a first sense amplifier circuit connected to a first pair of input and output lines, a pre-charge circuit connected to a second pair of input and output lines, and a first switch circuit, wherein the pre-charge circuit is configured to pre-charge the second pair of input and output lines with a pre-charge voltage after the first switch circuit disconnects the first pair of input and output lines from the second pair of input and output lines, and wherein the first switch circuit is configured to connect the first pair of input and output lines with the second pair of input and output lines in a read operation to transfer a voltage of the first pair of input and output lines amplified by the first sense amplifier circuit to the pre-charged second pair of input and output lines.

Description

Technical Field

[0001] The example embodiments relate to storage devices, and more specifically, to storage devices and methods of operating thereof. Background Technology

[0002] Storage devices can be used to store data in various applications and can update or output the stored data according to received commands. For example, a storage device can store data in response to a write command and output the stored data in response to a read command. Storage devices may consume power when performing write and read operations, and this power consumption may increase if write and read operations are performed frequently. In particular, power consumption of storage devices can be critical in applications such as battery-powered mobile devices or systems that include large-capacity storage devices. Summary of the Invention

[0003] Various aspects provide a storage device that reduces power consumption and its operation method.

[0004] According to various aspects, a storage device is provided, the storage device comprising: a first readout amplifier circuit connected to a first input and output pair; a precharge circuit connected to a second input and output pair; and a first switch circuit located between the first input and output pair and the second input and output pair, wherein the precharge circuit is configured to precharge the second input and output pair with a precharge voltage after the first switch circuit disconnects the first input and output pair from the second input and output pair, and wherein the first switch circuit is configured to connect the first input and output pair and the second input and output pair during a read operation to transfer the voltage of the first input and output pair amplified by the first readout amplifier circuit to the precharged second input and output pair.

[0005] According to various aspects, a method of operating a storage device is provided, the method comprising: in a read operation, disconnecting a first input and output pair and a second input and output pair; in the read operation, pre-charging the second input and output pair with a pre-charging voltage; in the read operation, amplifying the voltage of the first input and output pair; and in the read operation, connecting the first input and output pair and the second input and output pair in order to transfer the amplified voltage of the first input and output pair to the pre-charged second input and output pair.

[0006] According to various aspects, a storage device is provided, the storage device comprising: a first input and output line pair; a readout amplification circuit configured to amplify the voltage of the first input and output line pair to output it to the first input and output line pair; a second input and output line pair; a pre-charge circuit configured to pre-charge the second input and output line pair with a pre-charge voltage; and a first switching circuit that connects or disconnects the first input and output line pair and the second input and output line pair according to a first control signal. Attached Figure Description

[0007] These and / or other aspects, features, and advantages of the present invention will become apparent and more readily understood from the following description of exemplary embodiments taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 This is a block diagram illustrating a system according to an exemplary embodiment of the present disclosure; Figure 2 This is a block diagram illustrating a storage device according to an exemplary embodiment of the present disclosure; Figure 3 This is a block diagram illustrating a storage device according to an exemplary embodiment of the present disclosure; Figure 4 This is a circuit diagram illustrating a storage device according to an exemplary embodiment of the present disclosure; Figure 5 This is a timing diagram illustrating the operation of a storage device according to an exemplary embodiment of the present disclosure; Figure 6A and Figure 6B This is a circuit diagram illustrating an example of a write driver according to an exemplary embodiment of the present disclosure; Figure 7 This is a timing diagram illustrating the operation of a storage device according to an exemplary embodiment of the present disclosure; Figure 8A and Figure 8B This is a timing diagram illustrating an example of the operation of a storage device according to an exemplary embodiment of the present disclosure; Figure 9 This is a circuit diagram illustrating a storage device according to an exemplary embodiment of the present disclosure; Figure 10 This is a block diagram illustrating a storage device according to an exemplary embodiment of the present disclosure; Figure 11 This is a flowchart illustrating an operation method of a storage device according to an exemplary embodiment of the present disclosure; Figure 12 This is a flowchart illustrating an operation method of a storage device according to an exemplary embodiment of the present disclosure; Figure 13This is a diagram illustrating the layout of an integrated circuit device according to an exemplary embodiment of the present disclosure; Figure 14 This is a perspective view illustrating an integrated circuit device according to an exemplary embodiment of the present disclosure; and Figure 15 It is according to the exemplary embodiments of this disclosure along Figure 13 Cross-sectional view of an integrated circuit device cut by X1-X1' and Y1-Y1' lines. Detailed Implementation

[0009] Figure 1 This is a block diagram illustrating a system 10 according to an exemplary embodiment of the present disclosure. Figure 1 As shown, system 10 may include a storage controller 11 and a storage device 12, and may be referred to as a storage system. In some example embodiments, the storage controller 11 and the storage device 12 may be manufactured using semiconductor processes and may be included in a single package or in two separate packages.

[0010] Storage controller 11 can communicate with the host and storage device 12, and can control data exchange between the host and storage device 12. As an example, storage controller 11 can write data to storage device 12 or read data stored in storage device 12 according to a request received by the host. Figure 1 As shown, the storage controller 11 can provide the storage device 12 with commands CMD, addresses ADDR, and data DQ, and can receive data DQ from the storage device 12.

[0011] Storage device 12 can receive commands CMD, address ADDR, and data DQ from storage controller 11, and can provide data DQ to storage controller 11. Storage device 12 may include storage cells, and each storage cell may store at least one bit.

[0012] In some example embodiments, storage device 12 may include volatile memory cells. For example, storage device 12 may be a dynamic random access memory (DRAM) device, such as Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, Low Power Double Data Rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR4X SDRAM, LPDDR5 SDRAM, Graphics Double Data Rate (GDDR) Synchronous Graphics Random Access Memory (SGRAM), GDDR2 SGRAM, GDDR3 SGRAM, GDDR4 SGRAM, GDDR5 SGRAM, GDDR6 SGRAM, and so on. In some example embodiments, DRAM dies may be stacked in storage device 12, such as High Bandwidth Memory (HBM), HBM2, HBM3, and so on. In some example embodiments, storage device 12 may be a storage module such as a single in-line memory module (SIMM), a dual in-line memory module (DIMM), and so on. For example, storage device 12 may be a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), and a small outline DIMM (SO-DIMM). In some example embodiments, storage device 12 may include the following references. Figure 13 Vertical channel transistors (VCTs) as described above.

[0013] In some example embodiments, storage device 12 is a non-volatile storage device and may include non-volatile storage cells. For example, storage device 12 may be a non-volatile storage device such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), etc. In the following, DRAM devices will be described primarily as volatile storage devices, but it should be noted that the example embodiments of this disclosure are not limited thereto.

[0014] Storage device 12 may include circuitry for reading data stored in the storage cells (which may be referred to herein as reading data) or writing data (which may be referred to herein as writing data) into the storage cells. For example, see the following reference. Figure 3As described above, the storage device 12 may include a sense amplifier, which can be used to read data from or write data to the storage cells. Due to advancements in semiconductor technology, the number of storage cells included in the storage device 12 can be increased, and the size of the cell array including the storage cells can be increased. Therefore, the circuitry for reading or writing data can be layered. For example, the storage cells can be accessed not only via bit line pairs but also via additional input and output line pairs. The input and output line pairs can be connected to another input and output line pair via switching circuitry and can be connected to a sense amplifier and / or a precharger.

[0015] When storage device 12 performs write and read operations according to commands CMD provided by storage controller 11, power consumption may occur, and the more frequent the write and read operations, the greater the power consumption may be. As described below with reference to the accompanying drawings, in storage device 12, the swing voltage of input and output line pairs with high parasitic capacitance can be reduced, and charge can be reused to precharge the input and output line pairs. Furthermore, the timing of control signals can be adjusted according to the position of the storage cells in the cell array of storage device 12, and unnecessary precharging of input and output line pairs can be omitted. Therefore, storage device 12 can consume less power, and thus, the power consumption of system 10 can be reduced.

[0016] Figure 2 This is a block diagram illustrating a storage device 20 according to an exemplary embodiment of the present disclosure. Figure 2 The storage device 20 may be Figure 1 An example of storage device 12, but it should be noted that Figure 1 The storage device 12 is not limited to Figure 2 Storage device 20. For example... Figure 2 As shown, the storage device 20 may include an address buffer 21, a row decoder 22, a column decoder 23, a cell array 24, a read / write circuit 25, an input and output buffer (I / O buffer) 26, and a control circuit 27.

[0017] Address buffer 21 can receive address ADDR and can extract row address RA and column address CA from address ADDR. For example... Figure 2 As shown, address buffer 21 can provide row address RA to row decoder 22 and column address CA to column decoder 23.

[0018] Row decoder 22 can be connected to cell array 24 via multiple word lines WL. Row decoder 22 can select one word line WL from the multiple word lines WL based on row address RA and can activate the selected word line. For example, row decoder 22 can apply a word line drive voltage to the selected word line. Column decoder 23 can be connected to read / write circuitry 25. In some example embodiments, column decoder 23 can enable sub-circuits (e.g., sense amplifiers) included in read / write circuitry 25 based on column address CA.

[0019] Cell array 24 may include multiple storage cells. For example... Figure 2 As shown, a memory cell MC can be connected to a word line WL and a bit line BL. As a DRAM cell, the memory cell MC can include a cell transistor CT and a capacitor C. In some example embodiments, the cell transistor CT can be a field-effect transistor (FET). The cell transistor CT can be connected between the bit line BL and the capacitor C, and can have a gate connected to the word line WL. The capacitor C can have one end connected to the cell transistor CT, and can have the other end to which a constant potential (e.g., a negative supply voltage VSS) is applied. The cell transistor CT can connect the capacitor C to the bit line BL in response to an activated word line WL. Through the cell transistor CT, during a read operation, the charge stored in the capacitor C can be transferred to the bit line BL, while during a write operation, the charge on the bit line BL can be transferred to the capacitor C.

[0020] The read / write circuit 25 can write data to or read data from at least one memory cell included in the cell array 24. For example, in a read operation, the read / write circuit 25 can output a data signal DTA by sensing a signal (e.g., voltage and / or current) received from the memory cell MC via the bit line BL. Furthermore, in a write operation, the read / write circuit 25 can apply a signal to the bit line BL based on the data signal DTA to write data to the memory cell MC. In some example embodiments, the read / write circuit 25 may include a sense amplifier, and the sense amplifier selected by the column decoder 23 can be enabled in both read and write operations. Examples of the read / write circuit 25 will be described below with reference to the accompanying drawings.

[0021] Input and output buffers 26 can be connected to read / write circuitry 25. During a read operation, input and output buffers 26 can store a value corresponding to the data signal DTA received from read / write circuitry 25, and can output data DQ corresponding to at least a portion of the stored value according to the control of control circuitry 27. Furthermore, during a write operation, input and output buffers 26 can store a value corresponding to the received data DQ, and can provide the read / write circuitry 25 with a data signal DTA corresponding to at least a portion of the stored value according to the control of control circuitry 27. In some example embodiments, storage device 20 may further include an error correction code (ECC) engine between read / write circuitry 25 and input and output buffers 26, and the storage cells included in cell array 24 may store codewords generated by the ECC engine.

[0022] Control circuit 27 can receive command CMD and control the operation of storage device 20. For example, control circuit 27 can generate control signals for read operations, write operations, and refresh operations. In some example embodiments, control circuit 27 may include a command decoder for decoding command CMD and can generate control signals based on the decoded command. For example, control circuit 27 can identify a read operation or a write operation based on the decoded command and generate control signals based on the identified operation. In some example embodiments, control circuit 27 may include a mode register and can store values ​​in the mode register based on command CMD, address ADDR, and / or data DQ. Control circuit 27 can identify one of a plurality of modes based on the values ​​stored in the mode register and generate control signals based on the identified mode.

[0023] Figure 3 This is a block diagram illustrating a storage device 30 according to an exemplary embodiment of the present disclosure. For example, Figure 3 The block diagram illustrates an example of read / write circuitry included in storage device 30. (Reference) Figure 3The storage device 30 may include first-line sense amplifiers BLSA1 to n-line sense amplifiers BLSAn, first-line switches BLSW1 to n-line switches BLSWn, first-partial sense amplifiers LSA1 to n-partial sense amplifiers LSAn, first-partial switches LSW1 to n-partial switches LSWn, a precharger PRE, a write driver WD, a global switch GSW, and input and output sense amplifiers IOSA (n is an integer greater than 1). Furthermore, the storage device 30 may include first-line lines BL1 to n-line lines BLn, first complementary bit lines BLB1 to n-line complementary bit lines BLBn, first-partial input and output lines LIO1 to n-line local input and output lines LIOn, first-complementary local input and output lines LIOB1 to n-line complementary local input and output lines LIOBn, global input and output lines GIO, complementary global input and output lines GIOB, input and output lines IO, and complementary input and output lines IOB.

[0024] Here, a local input and output line pair including local input and output lines and complementary local input and output lines can be referred to as a first input and output line pair, and a global input and output line pair including global input and output line GIO and complementary global input and output line GIOB can be referred to as a second input and output line pair, and an input and output line pair including input and output line IO and complementary input and output line IOB can be referred to as a third input and output line pair. Here, bit line switches, local switches, and global switches can be referred to as a first switching circuit, a second switching circuit, and a third switching circuit, respectively. Furthermore, a local sense amplifier and an input and output sense amplifier IOSA can be referred to as a first sense amplifier circuit and a second sense amplifier circuit. Additionally, in this document, the connection or disconnection of two components can mean being electrically connected or electrically disconnected, unless otherwise described.

[0025] The first line sense amplifier BLSA1 can be connected to the first line pair and amplifies the voltage of the first line pair when enabled. The first line switch BLSW1 can connect the first line pair to the first local input and output pair according to a control signal between the first line pair and the first local input and output pair. The first local sense amplifier LSA1 can be connected to the first local input and output pair and amplifies the voltage of the first local input and output pair when enabled. The first local switch LSW1 can connect the first local input and output pair to the global input and output pair according to a control signal between the first local input and output pair and the global input and output pair.

[0026] A precharger PRE can be connected to the global input and output pairs and can precharge the global input and output pairs with a precharge voltage according to a control signal. A write driver WD can be connected to the global input and output pairs and can apply a voltage and / or current corresponding to the written data to the global input and output pairs during a write operation. Here, the precharger PRE and the write driver WD can be referred to as a precharge circuit and a write drive circuit, respectively. A global switch GSW can connect the global input and output pairs to the input and output pairs according to a control signal between the global input and output pairs and the input and output pairs. An input and output sense amplifier IOSA can be connected to the input and output pairs and can amplify the voltage of the input and output pairs when enabled. In some example embodiments, the storage device 30 may also include additional prechargers. For example, the storage device 30 may also include prechargers connected to bit line pairs and / or prechargers connected to local input and output pairs.

[0027] like Figure 3 As shown, the global input and output pairs can be connected to the first local switches LSW1 through the nth local switches LSWn, and the global input and output pairs can have a length greater than that of the local input and output pairs. Therefore, the global input and output pairs can have a parasitic capacitance greater than that of the local input and output pairs, and may require a larger current when operating at the same voltage than the local input and output pairs. As described above with reference to the accompanying drawings, the global input and output pairs can be precharged with a precharge voltage PRE, and the precharge voltage can be between the negative supply voltage and the positive supply voltage (e.g., provided to the sense amplifier). The global input and output pairs can be controlled to have a small swing voltage, and therefore, the current consumed by the global input and output pairs can be reduced.

[0028] Figure 4 This is a circuit diagram illustrating a storage device 40 according to an exemplary embodiment of the present disclosure. For example, Figure 4 The circuit diagram shows Figure 3 Examples of elements in storage device 30 corresponding to a bit line pair and a local input and output line pair. In the following text, Figure 4 Description and Figure 3 Duplicate descriptions between items will be omitted.

[0029] refer to Figure 4The storage device 40 may include a bit line switch 41, a local sense amplifier 42, a local switch 43, a precharger 44, a global switch 45, and an input and output sense amplifier 46. The bit line switch 41 may be connected between the bit line pair and the input and output line pairs, and may include a first transistor M11 and a second transistor M12 as n-channel field-effect transistors (NFETs). The first transistor M11 and the second transistor M12 may receive a column select signal CSL, and may connect the bit line BL and the complementary bit line BLB to the local input and output line LIO and the complementary local input and output line LIOB, respectively, in response to the activated (in other words, high-level) column select signal CSL.

[0030] The local sense amplifier 42 can be connected to the local input and output line pair (in other words, the local input and output line LIO and the complementary local input and output line LIOB), and can include first transistors M21 to M23 as NFETs, and fourth transistors M24 to M26 as p-channel field-effect transistors (PFETs). The first transistor M21, second transistor M22, fourth transistor M24, and fifth transistor M25 can correspond to two inverters cross-coupled between the local input and output line LIO and the complementary local input and output line LIOB. Furthermore, the third transistor M23 can be connected between the two inverters and a node to which a negative supply voltage VSS is applied, and the sixth transistor M26 can be connected between the two inverters and a node to which a positive supply voltage VLSA is applied. Figure 4 As shown, the local sense amplifier 42 (in other words, two inverters) can be enabled in response to an active (in other words, high-level) local sense amplifier enable signal LSAEN and an active (in other words, low-level) complementary local sense amplifier enable signal LSAENB. The enabled local sense amplifier 42 can amplify the voltages of the local input and output pairs by using power supplied by the negative supply voltage VSS and the positive supply voltage VLSA.

[0031] A local switch 43 can be connected between the local input and output line pairs and the global input and output line pairs, and can include a first transistor M31 and a second transistor M32 as n-channel field-effect transistors (NFETs). The first transistor M31 and the second transistor M32 can receive a first control signal SW1, and can connect the local input and output line LIO and the complementary local input and output line LIOB to the global input and output line GIO and the complementary global input and output line GIOB, respectively, in response to the activated (in other words, high-level) first control signal SW1.

[0032] The precharger 44 can be connected to the global input and output line pair (in other words, the global input and output line GIO and the complementary global input and output line GIOB) and can include first transistors M41 to third transistors M43 as NFETs. First transistor M41 and second transistor M42 can be connected in series between the global input and output line GIO and the complementary global input and output line GIOB, and can receive a precharge voltage VPRE. Therefore, first transistor M41 and second transistor M42 can precharge the global input and output line GIO and the complementary global input and output line GIOB with the precharge voltage VPRE in response to an activated (in other words, high-level) precharge signal GIOPR. Third transistor M43 can be connected between the global input and output line GIO and the complementary global input and output line GIOB, and can make the potential of the global input and output line GIO and the potential of the complementary global input and output line GIOB the same in response to an activated (in other words, high-level) precharge signal GIOPR.

[0033] In some example embodiments, the precharge voltage VPRE can be a voltage within the supply voltage. For example, the precharge voltage VPRE can be the voltage between the negative supply voltage VSS and the positive supply voltage VLSA provided to the local sense amplifier 42, and can be approximately an intermediate voltage between the positive supply voltage VLSA and the negative supply voltage VSS. If the precharge voltage VPRE is approximately the supply voltage, and the voltage of one of the global input and output lines GIO and the complementary global input and output line GIOB is pulled up or down from the supply voltage during a read or write operation, charge can be concentrated on one of the global input and output lines GIO and GIOB for precharge. However, as referenced below... Figure 5 and Figure 7 As described, when precharging is performed using a precharge voltage VPRE as an intermediate voltage, during read or write operations, the voltages of the global input / output lines GIO and GIOB can move away from the precharge voltage VPRE in opposite directions. Furthermore, when the voltages of the global input / output lines GIO and GIOB subsequently return to the precharge voltage VPRE for further precharging, the charge can be reused. As a result, current consumption during read or write operations can be reduced, and power consumption of the storage device 40 can be reduced.

[0034] A global switch 45 can be connected between the global input and output line pairs and the input and output line pairs, and can include a first transistor M51 and a second transistor M52 as NFETs. The first transistor M51 and the second transistor M52 can receive a second control signal SW2, and can connect the global input and output line GIO and the complementary global input and output line GIOB to the input and output line IO and the complementary input and output line IOB, respectively, in response to the activated (in other words, high-level) second control signal SW2.

[0035] The input and output sense amplifier 46 can be connected to the input and output line pairs (in other words, the input and output line IO and the complementary input and output line IOB). The voltage of the input and output line pairs can be amplified in response to the activated input and output sense amplifier enable signal IOSAEN.

[0036] Figure 5 This is a timing diagram illustrating the operation of a storage device according to an example embodiment of the present disclosure. For example, Figure 5 The timing diagram shows that in Figure 4 An example of a read operation performed in storage device 40. Reference will be made below. Figure 4 describe Figure 5 .

[0037] refer to Figure 5 The column select signal CSL can be activated before time t1. Therefore, the voltage of the bit line pair, which varies according to the voltage of the memory cell, can be transmitted to the local input and output line pairs. At time t1, the local sense amplifier enable signal LSAEN can be activated. Local sense amplifier 42 can be enabled, and the amplification of the voltage of the local input and output line pairs can be initiated by local sense amplifier 42. Input and output sense amplifier 46 can amplify the voltage of the input and output line pairs for output to the input and output line pairs. Therefore, as... Figure 5 As shown, the voltages of the local input and output lines LIO and the complementary local input and output lines LIOB can be increased or decreased.

[0038] At time t2, the first control signal SW1 can be activated. The first control signal SW1 can be activated to allow the amplified voltage of the input and output line pairs to be transmitted to the global input and output line pairs. For example, to facilitate the transmission of the amplified voltage of the input and output line pairs to the global input and output line pairs, the local switch 43 can connect the local input and output line pairs and the global input and output line pairs in response to the activated first control signal SW1. Therefore, as... Figure 5As shown, the voltages of the global input and output lines GIO and the complementary global input and output lines GIOB can be increased or decreased. Due to the activation of the second control signal SW2, the voltages of the global input and output line pairs can be transferred to the input and output line pairs via the global switch 45.

[0039] At time t3, the second control signal SW2 can be deactivated, and the input and output sense amplifier enable signal IOSAEN can be activated. Therefore, the input and output line pairs can be disconnected from the global input and output line pairs. At time t3, the voltages of the input and output line pairs transmitted from the global input and output line pairs (in other words, the voltages between input and output line GIO and complementary input and output line GIOB) can be sufficiently amplified by the input and output sense amplifier 46. Therefore, after the local sense amplifier 42 is enabled, the input and output sense amplifier 46 can be enabled, and the global switch 45 can disconnect the global input and output line pairs from the input and output line pairs.

[0040] At time t4, the precharge signal GIOPR can be activated. Therefore, the global input and output pairs can be precharged at the precharge voltage VPRE. Figure 5 As shown, after the voltage of the local input and output line pair is transferred to the global input and output line pair at time t2, the global input and output line pair can have a swing voltage VX until the global input and output line pair is precharged at time t4. Time t3 can be determined so that the voltage of the input and output line pair has a magnitude sufficient to be amplified by the input and output sense amplifier 46, and therefore, the magnitude of the swing voltage VX can be determined. Due to the precharge voltage VPRE as an intermediate voltage, the swing voltage VX can be smaller than the voltage of the global input and output line pair even if only one line in the global input and output line pair is pulled up or pulled down. Furthermore, at time t4, the charge of the complementary global input and output line GIOB can be used for the precharge of the global input and output line GIO, and therefore, the current and power consumed for its precharge can be reduced. (Refer to the above...) Figure 3 As described, the global input and output pairs can have relatively high parasitic capacitance, and therefore, small swing voltage VX and charge reuse can significantly reduce the power consumption of the storage device.

[0041] Figure 6A and Figure 6B This is a circuit diagram illustrating an example of a write driver WD according to an exemplary embodiment of this disclosure. (Refer to the above...) Figure 3As described, the write driver WD can be connected to the global input and output pairs and can apply a voltage corresponding to the written data to the global input and output pairs during a write operation. The precharge voltage VPRE of the global input and output pairs can be an intermediate voltage as described above with reference to the accompanying drawings, and the write driver WD can operate the global input and output pairs so that the voltage of the global input and output pairs has a small swing voltage around the precharge voltage VPRE during a write operation.

[0042] refer to Figure 6A The write driver 60a may include first transistors M61 to M66 as NFETs. First transistors M61 to M63 may be connected in series between a first positive power supply voltage VDD1 and a negative power supply voltage VSS. First transistors M61 and M62 may be connected to the global input and output lines GIO and may receive complementary global input and output line drive signals GIOB_DRV and GIO_DRV, respectively. The gate and drain of the third transistor M63 may be connected to each other, and therefore, the third transistor M63 may function as a diode.

[0043] Transistors M64 through M66 can be connected in series between the first positive power supply voltage VDD1 and the negative power supply voltage VSS. Transistor M64 and transistor M65 can be connected to the complementary global input and output line GIOB, and can receive the global input and output line drive signal GIO_DRV and the complementary global input and output line drive signal GIOB_DRV, respectively. The gate and drain of transistor M66 can be connected to each other, and therefore, transistor M66 can function as a diode.

[0044] The first positive supply voltage VDD1 applied to the first transistor M61 and the fourth transistor M64 can be lower than that applied to the sense amplifier (e.g., Figure 4 The local sense amplifier 42) provides the positive supply voltage VLSA. Furthermore, the voltage applied to the second transistor M62 and the fifth transistor M65 can be higher than the negative supply voltage VSS than the diode's forward voltage. Therefore, the pull-up and pull-down voltages of the global input and output lines GIO and the complementary global input and output line GIOB can be limited during write operations, as described below. Figure 7 As described, the global input and output line pairs can have a small voltage swing relative to the precharge voltage VPRE during write operations.

[0045] refer to Figure 6BThe write driver 60b may include first transistors M61 to sixth transistors M66 as NFETs. First transistors M61 to third transistors M63 may be connected in series between the second positive supply voltage VDD2 and the negative supply voltage VSS. First transistors M61 and second transistors M62 may be connected to the global input and output lines GIO and may receive the bias voltage VB and the global input and output line drive signal GIO_DRV, respectively. The gate and drain of the third transistor M63 may be connected to each other, and therefore, the third transistor M63 may function as a diode.

[0046] Transistors M64 through M66 can be connected in series between the second positive power supply voltage VDD2 and the negative power supply voltage VSS. Transistor M64 and transistor M65 can be connected to the complementary global input and output line GIOB, and can receive the bias voltage VB and the complementary global input and output line drive signal GIOB_DRV, respectively. The gate and drain of transistor M66 can be connected to each other, and therefore, transistor M66 can function as a diode.

[0047] The bias voltage VB applied to the first transistor M61 and the fourth transistor M64 can be lower than that applied to the sense amplifier (e.g., Figure 4 The local sense amplifier 42) provides a positive supply voltage VLSA. Therefore, the voltages of the global input and output lines GIO and the complementary global input and output line GIOB can be limited to be equal to or less than the bias voltage VB. Furthermore, the voltages applied to the second transistor M62 and the fifth transistor M65 can be higher than the negative supply voltage VSS by the forward voltage of the diodes. Therefore, the pull-up and pull-down voltages of the global input and output lines GIO and the complementary global input and output line GIOB can be limited during write operations, as described below. Figure 7 As described, the global input and output line pairs can have a small voltage swing relative to the precharge voltage VPRE during write operations.

[0048] Figure 7 This is a timing diagram illustrating the operation of a storage device according to an example embodiment of the present disclosure. For example, Figure 7 The timing diagram shows that in Figure 4 An example of a write operation performed in storage device 40. Referring below... Figure 4 describe Figure 7 .

[0049] refer to Figure 7At time t5, the first control signal SW1 can be activated. The local switch 43 can connect the local input and output pairs to the global input and output pairs in response to the activated first control signal SW1. Furthermore, the write driver WD can apply a voltage corresponding to the written data to the global input and output pairs. Therefore, as... Figure 7 As shown, the voltages of the global input and output pairs can gradually move away from the pre-charge voltage VPRE. Furthermore, the voltages of the local input and output pairs can also vary depending on the voltages of the global input and output pairs.

[0050] At time t6, the first control signal SW1 can be deactivated. Therefore, the local switch 43 can disconnect the local input and output pairs from the global input and output pairs in response to the deactivated first control signal SW1.

[0051] At time t7, the local sense amplifier enable signal LSAEN can be activated. The enabled local sense amplifier 42 can amplify the voltages of the local input and output line pairs, and therefore, as... Figure 7 As shown, the voltages of the local input and output line pairs can be amplified. After time t7, as the voltage of the column select signal CSL increases, the bit line switch 41 can connect the bit line pairs to the local input and output line pairs, and thus, the amplified voltages of the local input and output line pairs can be applied to the bit line pairs, and the voltages of the bit line pairs can be transmitted through the bit line sense amplifier (e.g., ...). Figure 3 BLSA1 in the image is magnified.

[0052] As shown in the attached diagram above, the pre-charge voltage VPRE can be an intermediate voltage, and the swing voltage VY of the global input and output pairs can be less than the voltage of the global input and output pairs if only one line in the global input and output pairs is pulled up or pulled down. Furthermore, as shown in the attached diagram above... Figure 6A and Figure 6B As shown, the write driver WD can limit the pull-up and pull-down voltages of the global input and output line pairs during write operations. Therefore, as Figure 7 As shown, the global input and output line pairs can have a small swing voltage VY. The charge of the complementary global input and output line GIOB can be used for the pre-charging of the global input and output line GIO, and thus, the current and power consumed for their pre-charging can be reduced.

[0053] Figure 8A and Figure 8B This is a timing diagram illustrating an example of the operation of a storage device according to an exemplary embodiment of the present disclosure. For example, Figure 8A and Figure 8B The timing diagram illustrates an example of a write operation performed in a storage device. (See the reference above.) Figure 7As described, the global input and output line pairs can have a swing voltage VY during a write operation. In some example embodiments, Figure 8A and Figure 8B Write operations can be performed by Figure 4 The storage device 40 performs the operation. Reference will be made below. Figure 4 describe Figure 8A and Figure 8B .

[0054] In some example embodiments, the storage device 40 may selectively precharge the global input and output line pairs after data is written and before the next data is written. For example, such as Figure 8A and Figure 8B As shown, the global input and output line pairs can have a swing voltage VY by writing to the driver WD. Figure 8A As shown, due to the precharge signal GIOPR activated at time t0, the global input and output pairs can be precharged with the precharge voltage VPRE. Meanwhile, as... Figure 8B As shown, the global input and output pairs can maintain the swing voltage VY because the precharge signal GIOPR remains in the deactivated state at time t0.

[0055] In some example embodiments, storage device 40 may support burst writes. When the write data turnover rate is high, storage device 40 can, as... Figure 8A The diagram shows that the global input and output pairs are precharged with a precharge voltage VPRE, and the storage device 40 can perform operations such as... when the write data toggle rate is low. Figure 8B The diagram shows the skipping of pre-charging of global input and output pairs. Therefore, power consumption in storage device 40 caused by unnecessary pre-charging can be reduced. In some example embodiments, the storage controller (or host) can set the value of the mode register of storage device 40 based on the write data toggle rate. Storage device 40 can identify a mode based on the value of the mode register and can execute in a first mode. Figure 8A The operation can be performed in the second mode. Figure 8B The operation. In some example embodiments, the storage device 40 can compare the first written data and the subsequent second written data in a burst write, and can perform operations if the second written data is different from the first written data. Figure 8A The operation can be performed when the second written data is the same as the first written data. Figure 8B The operation.

[0056] Figure 9 This is a circuit diagram illustrating a storage device 90 according to an exemplary embodiment of the present disclosure. For example, Figure 9 The circuit diagram shows Figure 3 Examples of elements in storage device 30 corresponding to a bit line pair and a local input and output line pair. These will be omitted in the following text. Figure 9 Description and Figure 4 The descriptions are repetitive.

[0057] refer to Figure 9 The storage device 90 may include a bit line switch 91, a first local sense amplifier 92, a second local sense amplifier 93, and a local switch 94. The bit line switch 91 may include a first transistor M11 and a second transistor M12 that receive a column select signal CSL. The local switch 94 may include a first transistor M41 and a second transistor M42 that receive a first control signal SW11, and a third transistor M43 and a fourth transistor M44 that receive the first control signal SW12.

[0058] In some example embodiments, the local sense amplifiers may have a cascaded structure. For example, such as Figure 9 As shown, the first local sense amplifier 92 is responsive to two inverters cross-coupled at the local input and output line pairs, and the second local sense amplifier 93 is responsive to two inverters whose inputs are connected to the local input and output line pairs. During a read operation, the first control signal SW11 can be deactivated, and the first control signal SW12 can be activated. Therefore, the voltages of the local input and output line pairs can be amplified by the first local sense amplifier 92 and the second local sense amplifier 93, and the read rate can be increased. During a write operation, the first control signal SW11 can be activated, the first control signal SW12 can be deactivated, and the second local sense amplifier 93 can be unused.

[0059] Figure 10 This is a block diagram illustrating a storage device 100 according to an exemplary embodiment of the present disclosure. Figure 10 As shown, the storage device 100 may include a cell array 101 and control circuitry 102. Global input and output lines (GIOs) can extend from the cell array 101 in the Y-axis direction, and multiple local switches (such as first local switches LSW1 to third local switches LSW3) connected to the global input and output lines GIOs can be arranged in the Y-axis direction. Figure 10 As shown, the first local switch LSW1 is closer to the control circuit 102 than the second local switch LSW2 and the third local switch LSW3, and the third local switch LSW3 is farther away from the control circuit 102 than the first local switch LSW1 and the second local switch LSW2.

[0060] In some example embodiments, the control circuit 102 may generate a control signal provided to the switch that varies depending on the distance from the control circuit 102. For example, such as Figure 10 As shown, the first control signal SW1_NEAR provided to the first local switch LSW1 adjacent to the control circuit 102 can have a first activation pulse width PW1, and the first control signal SW1_FAR provided to the third local switch LSW3 which is further away from the control circuit 102 can have a third activation pulse width PW3, and the first control signal SW1_MID provided at the second local switch LSW2 between the first local switch LSW1 and the third local switch LSW3 can have a second activation pulse width PW2. Figure 10 As shown, the second activation pulse width PW2 can be greater than the first activation pulse width PW1 and less than the third activation pulse width PW3 (PW1). <PW2<PW3)。

[0061] The time required for the first control signal generated by control circuit 102 to reach the third local switch LSW3 can be longer than the time required for it to reach the first local switch LSW1. Furthermore, the parasitic resistance and / or capacitance of the path traversed by the first control signal SW1_FAR provided to the third local switch LSW3 can be relatively high. Therefore, control circuit 102 can generate a first control signal SW1_FAR with a sufficient pulse width (in other words, a third activation pulse width PW3) to provide to the third switch circuit LSW3. However, if the first control signal SW1_NEAR provided to the first local switch LSW1 has a third activation pulse width PW3 in the same manner as the first control signal SW1_FAR, while consuming unnecessary power, the local input and output pairs can be connected to the global input and output pairs for a time equal to or greater than the time required for writing or reading. Therefore, as Figure 10 As shown, the first control signal SW1_NEAR can have a shortened activation pulse width (in other words, the first activation pulse width PW1), and therefore the power consumption of the storage device 100 can be reduced during read and write operations.

[0062] Figure 11 This is a flowchart illustrating an operation method of a storage device according to an example embodiment of the present disclosure. For example, Figure 11 The flowchart illustrates a read operation performed by a storage device. For example... Figure 11 As shown, the operation method of the storage device may include multiple operations (e.g., operations S11 to S14). In some example embodiments, Figure 11 The method can be derived from Figure 4 The storage device 40 performs the operation. Reference will be made below. Figure 4 describe Figure 11 .

[0063] refer to Figure 11In operation S11, local input and output pairs and global input and output pairs can be disconnected. For example, local switch 43 can disconnect local input and output pairs and global input and output pairs in response to a deactivated first control signal SW1.

[0064] In operation S12, the global input and output pairs can be pre-charged. For example, the precharger 44 can pre-charge the global input and output pairs with a pre-charge voltage VPRE in response to an activated pre-charge signal GIOPR. As described above with reference to the accompanying drawings, the pre-charge voltage VPRE can be an intermediate voltage, and the global input and output pairs can have a small voltage swing around the pre-charge voltage VPRE. In some example embodiments, operation S12 can be performed after operation S11 is performed. In some example embodiments, operation S12 can be completed before operation S13, described below, is started.

[0065] In operation S13, the voltage of the local input and output pairs can be amplified, and in operation S14, the local input and output pairs and the global input and output pairs can be connected. In some example embodiments, when the local sense amplifier 42 is enabled, the local input and output pairs and the global input and output pairs can be connected. For example, the local sense amplifier 42 can be enabled in response to an activated local sense amplifier enable signal LSAEN, and the local switch 43 can connect the local input and output pairs and the global input and output pairs in response to an activated first control signal SW1. Therefore, the voltage of the local input and output pairs amplified by the local sense amplifier 42 can be transferred to the pre-charged global input and output pairs.

[0066] Figure 12 This is a flowchart illustrating an operation method of a storage device according to an example embodiment of the present disclosure. For example, Figure 12 The flowchart illustrates a write operation performed by a storage device. For example... Figure 12 As shown, the operation method of the storage device may include multiple operations (e.g., operations S21 to S24). In some example embodiments, Figure 12 The method can be derived from Figure 4 The storage device will execute. In the following text, reference will be made to... Figure 4 describe Figure 12 .

[0067] refer to Figure 12In operation S21, a drive voltage can be applied to the global input and output pairs, and in operation S22, the local input and output pairs and the global input and output pairs can be connected. For example, the write driver WD can apply a voltage corresponding to the written data to the global input and output pairs. Furthermore, the local switch 43 can connect the local input and output pairs and the global input and output pairs in response to the activated first control signal SW1. Therefore, the voltage applied to the global input and output pairs can be transferred to the local input and output pairs.

[0068] In operation S23, the connection between the local input and output pairs and the global input and output pairs can be disconnected. For example, local switch 43 can disconnect the connection between the local input and output pairs and the global input and output pairs in response to the deactivated first control signal SW1.

[0069] In operation S24, the voltage of the local input and output line pairs can be amplified. For example, the local sense amplifier 42 can be enabled in response to the activated local sense amplifier enable signal LSAEN, and can amplify the voltage of the local input and output line pairs.

[0070] Figure 13 This is a diagram illustrating the layout of an integrated circuit device 200 according to an exemplary embodiment of the present disclosure, and Figure 14 This is a perspective view showing an integrated circuit device 200 according to an exemplary embodiment of the present disclosure, and Figure 15 It is according to the exemplary embodiments of this disclosure along Figure 13 A cross-sectional view of the integrated circuit device 200 cut by X1-X1' and Y1-Y1' lines.

[0071] refer to Figures 13 to 15 The integrated circuit device 200 may include a substrate 210, multiple first conductive lines 220, a channel layer 230, a gate electrode 240, a gate insulating layer 250, and a capacitor structure 280. The integrated circuit device 200 may be a memory device including a vertical channel transistor (VCT). A VCT may refer to a structure in which the channel length of the channel layer 230 extends vertically from the substrate 210.

[0072] A lower insulating layer 212 can be disposed on a substrate 210, and a plurality of first conductive lines 220 can be spaced apart from each other in a first direction (X-axis direction) and can extend on the lower insulating layer 212 in a second direction (Y-axis direction). On the lower insulating layer 212, a plurality of first insulating patterns 222 can be disposed to fill the spaces between the plurality of first conductive lines 220. The plurality of first insulating patterns 222 can extend in the second direction (Y-axis direction), and the upper surfaces of the plurality of first insulating patterns 222 can be disposed at the same horizontal level as the upper surfaces of the plurality of first conductive lines 220. The plurality of first conductive lines 220 can be used as bit lines of an integrated circuit device 200.

[0073] In some example embodiments, the plurality of first conductive lines 220 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. The plurality of first conductive lines 220 may comprise a single layer or multiple layers of the aforementioned materials. In example embodiments, the plurality of first conductive lines 220 may comprise a two-dimensional semiconductor material, and for example, the two-dimensional semiconductor material may comprise graphene, carbon nanotubes, or combinations thereof.

[0074] The channel layer 230 can be arranged in a matrix shape, which is achieved by spacing multiple first conductive lines 220 along a first direction (X-axis direction) and a second direction (Y-axis direction). The channel layer 230 can have a first width in the first direction (X-axis direction) and a first height in the third direction (Z-axis direction), and the first height can be greater than the first width. For example, the first height can be approximately two to ten times the first width, but is not limited thereto. The bottom portion of the channel layer 230 can be used as a first source / drain region (not shown), and the upper portion of the channel layer 230 can be used as a second source / drain region (not shown), and the portion of the channel layer 230 located between the first source / drain region and the second source / drain region can be used as a channel region (not shown).

[0075] In some example embodiments, the channel layer 230 may include an oxide semiconductor. The channel layer 230 may comprise a single layer or multiple layers of oxide semiconductor. In some example embodiments, the channel layer 230 may have a bandgap energy greater than that of silicon. The channel layer 230 may be polycrystalline or amorphous, but is not limited thereto. In some example embodiments, the channel layer 230 may include a two-dimensional semiconductor material, and for example, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or combinations thereof.

[0076] The gate electrode 240 may extend along a first direction (X-axis direction) on both sidewalls of the channel layer 230. The gate electrode 240 may include a first sub-gate electrode 240P1 facing the first sidewall of the channel layer 230, and a second sub-gate electrode 240P2 facing the second sidewall of the channel layer 230 opposite to the first sidewall. Since a single channel layer 230 is arranged between the first sub-gate electrode 240P1 and the second sub-gate electrode 240P2, the integrated circuit device 200 may have a dual-gate transistor structure. However, the example embodiment is not limited to this, and a single-gate transistor structure can be achieved by omitting the second sub-gate electrode 240P2 and forming only the first sub-gate electrode 240P1 on the channel layer 230 facing the first sidewall. The gate electrode 240 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof.

[0077] The gate insulating layer 250 may surround the sidewalls of the channel layer 230 and may be located between the channel layer 230 and the gate electrode 240. For example, as Figure 13 As shown, the entire sidewall of the channel layer 230 may be surrounded by the gate insulating layer 250, and a portion of the sidewall of the gate electrode 240 may contact the gate insulating layer 250. In an example embodiment, the gate insulating layer 250 may extend in the extension direction of the gate electrode 240 (in other words, in a first direction (X-axis direction)), and only two sidewalls of the channel layer 230 facing the gate electrode 240 may contact the gate insulating layer 250. In some example embodiments, the gate insulating layer 250 may be composed of a silicon oxide film, a silicon oxynitride film, a high dielectric constant film having a higher dielectric constant than a silicon oxide film, or a combination thereof. The high dielectric constant film may be composed of a metal oxide or a metal oxynitride.

[0078] On a plurality of first insulating patterns 222, a plurality of second insulating patterns 232 may extend in a second direction (Y-axis direction), and a channel layer 230 may be disposed between two adjacent second insulating patterns among the plurality of second insulating patterns 232. Furthermore, between two adjacent second insulating patterns, a first buried layer 234 and a second buried layer 236 may be disposed in the space between two adjacent channel layers. The first buried layer 234 may be disposed at the bottom portion of the space between two adjacent channel layers 230, and the second buried layer 236 may be formed to fill the remaining portion of the space between two adjacent channel layers on the first buried layer 234. The upper surface of the second buried layer 236 may be disposed at the same horizontal level as the upper surface of the channel layer 230, and the second buried layer 236 may cover the upper surface of the gate electrode 240. On the other hand, the plurality of second insulating patterns 232 may be composed of a material layer continuous with the plurality of first insulating patterns 222, or the second buried layer 236 may be composed of a material layer continuous with the first buried layer 234.

[0079] Capacitor contacts 260 can be disposed on channel layer 230. The capacitor contacts 260 can be arranged to overlap perpendicularly with channel layer 230 and can be arranged in a matrix shape spaced apart in a first direction (X-axis direction) and a second direction (Y-axis direction). An upper insulating layer 262 can surround the sidewalls of the capacitor contacts 260 on a plurality of second insulating patterns 232 and a second buried layer 236.

[0080] An etch stop film 270 may be disposed on the upper insulating layer 262, and a capacitor structure 280 may be disposed on the etch stop film 270. The capacitor structure 280 may include a lower electrode 282, a capacitor dielectric layer 284, and an upper electrode 286. The lower electrode 282 may penetrate the etch stop film 270 to be electrically connected to the upper surface of the capacitor contact 260. The lower electrode 282 may be formed as a column extending in a third direction (Z-axis direction), but is not limited thereto. In some example embodiments, the lower electrode 282 may be arranged to overlap perpendicularly with the capacitor contact 260, and may be arranged in a matrix shape spaced apart in a first direction (X-axis direction) and a second direction (Y-axis direction). Alternatively, in order to arrange the lower electrode 282 in a hexagonal shape, positioning pads (not shown) may be further disposed between the capacitor contact 260 and the lower electrode 282.

[0081] As described above, exemplary embodiments have been disclosed in the accompanying drawings and specification. Although specific terminology has been used to describe exemplary embodiments in this specification, this is for the purpose of describing the technical spirit of this disclosure only and is not intended to limit the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent exemplary embodiments can be made therefrom.

Claims

1. A storage device, the storage device comprising: A first readout amplifier circuit is configured to amplify the voltage of a first input and output line pair; A pre-charge circuit is connected to a second input and output line pair; as well as A first switching circuit is located between the first input and output line pair and the second input and output line pair. The pre-charge circuit is configured to pre-charge the second input and output pair with a pre-charge voltage after the first switching circuit disconnects the first input and output pair from the second input and output pair. The first switching circuit is configured to connect the first input and output pair to the second input and output pair during a read operation, so as to transfer the voltage of the first input and output pair amplified by the first readout amplifier circuit to the pre-charged second input and output pair.

2. The storage device according to claim 1, further comprising: Second readout amplifier circuit; as well as The second switching circuit is located between the second input and output line pair and the second readout amplifier circuit.

3. The storage device according to claim 2, wherein, The second readout amplifier circuit is configured to be enabled during the read operation after the first readout amplifier circuit is enabled.

4. The storage device according to claim 2, wherein, The second switching circuit is configured to disconnect the second input and output pairs from the second read amplifier circuit in response to a deactivation second control signal during the read operation after the first read amplifier circuit is enabled.

5. The storage device according to claim 2, wherein, The pre-charge circuit is further configured to pre-charge the second input and output pairs with the pre-charge voltage after the second switching circuit disconnects the second input and output pairs from the second readout amplifier circuit.

6. The storage device according to claim 5, wherein, The pre-charge voltage is the voltage between the first power supply voltage and the second power supply voltage provided to the first readout amplifier circuit.

7. The storage device according to claim 1, further comprising: Multiple storage cells, each of which is connected to multiple bit line pairs; as well as A plurality of third switching circuits are located between the plurality of bit line pairs and the first input and output line pairs.

8. The storage device according to claim 7, wherein, Each of the plurality of memory cells includes a capacitor and a vertical channel transistor connected to the capacitor.

9. The storage device according to claim 1, further comprising: A plurality of first switching circuits, wherein the plurality of first switching circuits includes the first switching circuit; as well as A control circuit, configured to generate a plurality of first control signals in each of the plurality of first switching circuits, The activation pulse width of the first control signal provided to the first switch circuit closer to the control circuit among the plurality of first switch circuits is shorter than the activation pulse width of the first control signal provided to the first switch circuit farther away from the control circuit among the plurality of first switch circuits.

10. The storage device of claim 1, further comprising a write drive circuit connected to the second input and output line pair. in, The write drive circuit is configured to be enabled when the first switch circuit connects the first input and output line pair to the second input and output line pair during a write operation.

11. The storage device according to claim 10, wherein, The first readout amplifier circuit is further configured to be enabled during the write operation after the first switching circuit disconnects the second input and output line pair from the first input and output line pair.

12. The storage device according to claim 10, wherein, The write drive circuit includes a first transistor to a third transistor connected in series between the positive power supply voltage node and the negative power supply voltage node.

13. The storage device according to claim 12, wherein, The third transistor includes: The source, which is connected to the negative power supply voltage node; and A drain and a gate, wherein the drain and the gate are connected to each other.

14. The storage device according to claim 12, wherein, The precharge circuit is further configured to precharge the second input and output line pair with the precharge voltage in a first mode after the write drive circuit is disabled during the write operation. In the second mode, the second input and output line pair is not precharged.

15. A method of operating a storage device, the method comprising: During the read operation, disconnect the first input and output line pair from the second input and output line pair; In the read operation, the second input and output line pair is precharged with a precharge voltage; In the read operation, the voltage of the first input and output line pair is amplified; as well as In the read operation, the first input and output pair is connected to the second input and output pair in order to transfer the amplified voltage of the first input and output pair to the pre-charged second input and output pair.

16. The method of operating the storage device according to claim 15, wherein, The pre-charging of the second input and output pair is performed after the disconnection of the first input and output pair from the second input and output pair is executed.

17. The method of operating a storage device according to claim 15, the method further comprising: During a write operation, the first input and output line pair is connected to the second input and output line pair; as well as In the write operation, a drive voltage is applied to the second input and output line pair.

18. The method of operating a storage device according to claim 17, the method further comprising: During the write operation, the connection between the first input and output line pair and the second input and output line pair is disconnected; as well as In the write operation, the voltage of the first input and output line pair is amplified.

19. A storage device, the storage device comprising: First input and output line pair; A readout amplifier circuit is configured to amplify the voltage of the first input and output line pair to output it to the first input and output line pair; Second input and output line pair; A pre-charge circuit configured to pre-charge the second input and output line pair with a pre-charge voltage; as well as A first switching circuit connects or disconnects the first input and output line pair from the second input and output line pair according to a first control signal.

20. The storage device according to claim 19, wherein, The readout amplifier circuit includes: Two inverters, which are cross-coupled between the lines of the first input and output line pairs; A first transistor, located between the two inverters and a node to which a positive power supply voltage is applied; and The second transistor is located between the two inverters and the node to which a negative power supply voltage is applied.

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