Memory device and driving method thereof, memory system

Abstract

The embodiment of the present application discloses a memory device and a driving method thereof, and a memory system, relates to semiconductor technology, and is favorable for realizing flexible adjustment of line layout of a storage circuit connected with a memory bank, and reducing process cost and product size. A storage unit array in the memory device comprises a plurality of memory banks. A peripheral circuit is coupled with the plurality of memory banks. The peripheral circuit comprises a first storage circuit and a plurality of second storage circuits. The first storage circuit is configured to store address information of a defective word line in a word line coupled with the plurality of memory banks. The plurality of second storage circuits are all coupled with the first storage circuit, one second storage circuit is configured to acquire information in the first storage circuit; and is configured to couple a redundant word line corresponding to the defective word line in response to a first control signal. Wherein, the data transmission path between the plurality of second storage circuits and the first storage circuit is shorter than the data transmission path between the plurality of second storage circuits and the plurality of memory banks.

Description

Technical Field

[0001] This application relates to semiconductor technology, and to, but is not limited to, a memory device and its driving method, and a memory system. Background Technology

[0002] A memory device includes an array of memory cells and peripheral circuitry. The peripheral circuitry comprises various integrated circuit structures with different functions, distributed across different spatial regions of the memory device. The location of these integrated circuit structures is related to the effectiveness of their functions and the overall performance of the product. Summary of the Invention

[0003] In view of this, the present application provides a memory device and its driving method and memory system to solve at least one problem existing in the prior art, which can realize flexible adjustment of the circuit layout connecting the memory body, reduce process cost and product size.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] In a first aspect, embodiments of this application provide a memory device. The memory device includes a memory cell array and peripheral circuitry. The memory cell array includes a plurality of memory banks. The peripheral circuitry is coupled to the plurality of memory banks.

[0006] The peripheral circuitry includes a first storage circuit and a plurality of second storage circuits. The first storage circuit is configured to store address information of damaged word lines among word lines coupled to the plurality of memory banks. Each of the plurality of second storage circuits is coupled to the first storage circuit, and one of the plurality of second storage circuits is configured to couple to a redundant word line corresponding to the damaged word line in response to a first control signal. The data transmission paths between the plurality of second storage circuits and the first storage circuit are all shorter than the data transmission paths between the plurality of second storage circuits and the plurality of memory banks.

[0007] In some examples, the peripheral circuitry further includes a first multiplexer circuit, wherein multiple inputs of the first multiplexer circuit are coupled to multiple second storage circuits, and the output of the first multiplexer circuit is coupled to the storage bank.

[0008] The first multiplexing circuit is configured to couple the redundant word line corresponding to the damaged word line to the target memory in response to a second control signal, and to transmit data in the second memory circuit to the target memory. The memory coupled to the damaged word line is different from the target memory coupled to the redundant word line corresponding to the damaged word line.

[0009] In some examples, a plurality of the second storage circuits are configured to be coupled to at least one of the redundant word lines or at least one word line in response to a plurality of the first control signals.

[0010] In some examples, the second storage circuitry includes content-addressable storage units.

[0011] In some examples, the content-addressable storage unit includes a second storage element and a comparison circuit. The second storage element is configured to store identification and address information of the corrupted word line obtained from the first storage circuit, and identification information and address information of a redundant word line corresponding to one corrupted word line. The comparison circuit is configured to compare user data with the address information of the corrupted word line stored in the second storage element, wherein the user data and the address information of the corrupted word line are identical, and are coupled to the redundant word line corresponding to the corrupted word line.

[0012] In some examples, the second storage element also stores the address information of the memory bank coupled to the damaged word line, and the address information of the memory bank coupled to the redundant word line corresponding to one damaged word line. The address information of the memory bank coupled to the word line is different from the address information of the memory bank coupled to the redundant word line.

[0013] In some examples, the first storage circuitry includes a one-time programmable memory cell. The one-time programmable memory cell includes a first storage element and at least one transistor; the first storage element stores the address information of the corrupted word line.

[0014] In some examples, the corrupted word line is coupled to the second memory circuit. The redundant word line is coupled to both the memory bank and the second memory circuit. One redundant word line corresponds to one corrupted word line. Multiple redundant word lines are arranged sequentially adjacent to each other and coupled to one memory bank on one side of the memory bank.

[0015] In some examples, the peripheral circuitry further includes a buffer circuit. The buffer circuitry is coupled to the plurality of second storage circuits, the first storage circuit, and the data transmission interface, and is configured to transfer user data transmitted via the data transmission interface to the second storage circuit in response to a third control signal; it is also configured to transfer data in the first storage circuit to the plurality of second storage circuits in response to a fourth control signal.

[0016] In some examples, the buffer circuit includes a buffer and a second multiplexer circuit coupled to the buffer. A first input of the second multiplexer circuit is coupled to the data transmission interface, a second input of the second multiplexer circuit is coupled to the first storage circuit, and the output of the second multiplexer circuit is coupled to the plurality of second storage circuits through the buffer.

[0017] In some examples, the peripheral circuitry further includes input / output circuitry. The input / output circuitry is coupled to the data transmission interface and configured to receive user data and output it to the data transmission interface.

[0018] In the aforementioned memory device, the second memory circuit, in response to a first control signal, can disconnect from the damaged word line and then connect to the redundant word line corresponding to the damaged word line, enabling data transmission from the second memory circuit to the memory bank. Considering the large amount of data transmitted between the first and second memory circuits, and the significant differences in data transmission path lengths between different second memory circuits and the first memory circuit, which can easily lead to data transmission delays, the layout of multiple second memory circuits within the memory device is adjusted to ensure that the data transmission paths between each of the multiple second memory circuits and the first memory circuit are all shorter than the data transmission paths between the multiple second memory circuits and the multiple memory banks. This not only reduces the delay in transmitting data from the first memory circuit to different second memory circuits but also facilitates flexible adjustment of the wiring layout between the second memory circuits and the memory bank, thus reducing product size and manufacturing costs.

[0019] Secondly, embodiments of this application provide a memory system. The memory system includes a memory device and a memory controller. The memory device includes a first storage circuit and a second storage circuit. The memory controller is coupled to the memory device and configured to transfer address information of a corrupted word line stored in the first storage circuit to the second storage circuit; and to transmit user data to the second storage circuit; and is further configured to output a first control signal, instructing the second storage circuit to couple a redundant word line corresponding to the corrupted word line if the user data is found to be the same as the address information of the corrupted word line.

[0020] In some examples, the memory device further includes a first multiplexing circuit. The memory controller is also configured to output a second control signal instructing the first multiplexing circuit to transfer data within the second memory circuit to a target memory coupled to the redundant word line. The memory coupled to the corrupted word line is different from the target memory coupled to the redundant word line corresponding to the corrupted word line.

[0021] The memory system described above includes the memory device provided in any of the above examples. The beneficial effects of the memory system are the same as those of the memory device provided in any of the above examples, and will not be repeated here.

[0022] Thirdly, embodiments of this application provide a driving method for a memory device. The driving method includes: in response to a power-on reset signal, transferring address information of a damaged word line stored in a first storage circuit and coupled to a plurality of memory banks to a second storage circuit. In response to a first control signal, comparing user data and data stored in the second storage circuit, determining and coupling a redundant word line corresponding to the damaged word line. The data transmission path between the second storage circuit and the first storage circuit is shorter than the path from the second storage circuit to the memory bank via the coupled redundant word line.

[0023] In some examples, determining and coupling the redundant word line corresponding to the damaged word line includes: determining the identification information and address information of the redundant word line corresponding to the damaged word line based on the address information and identification information of the damaged word line, and determining a target redundant word line. Determining a target memory bank based on the address information of the memory bank coupled to the target redundant word line; wherein the memory bank coupled to the damaged word line is different from the target memory bank. The second memory circuit is coupled to the target memory bank via the target redundant word line.

[0024] In some examples, determining and coupling the redundant word line corresponding to the damaged word line includes: determining the identification information and address information of the redundant word line corresponding to the damaged word line, and the address information of the memory bank coupled to the redundant word line, based on the address information and identification information of the damaged word line, and determining the target redundant word line. The second memory circuit and the target memory bank are coupled through the target redundant word line.

[0025] In some examples, the method further includes: in response to a second control signal, coupling the target redundant word line to a target memory bank, and transmitting data within the second memory circuit to the target memory bank. The memory bank coupled to the word line is different from the target memory bank coupled to the target redundant word line.

[0026] In some examples, transmitting the data within the second storage circuit to the target memory includes: decoding the data transmitted by the redundant word line and then transmitting it to the target memory.

[0027] In some examples, the method further includes: transmitting the user data to the second storage circuit in response to a third control signal; and transferring data in the first storage circuit to the plurality of second storage circuits in response to a fourth control signal.

[0028] In some examples, the method further includes updating the address information of the corrupted word line stored in the first storage circuit in response to a refresh signal.

[0029] The above-described driving method is used to drive the memory device provided in any of the above examples. The beneficial effects of the driving method for the memory device are the same as those of the memory devices provided in any of the above examples, and will not be repeated here. Attached Figure Description

[0030] In the accompanying drawings, similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0031] Figure 1 Schematic diagram of the memory device provided for implementation of this application Figure 1 ;

[0032] Figure 2 Schematic diagram of different structural layouts of the memory cell array and peripheral circuits of the memory device provided for implementation of this application Figure 1 ;

[0033] Figure 3 Schematic diagram of different structural layouts of the memory cell array and peripheral circuits of the memory device provided for implementation of this application Figure 2 ;

[0034] Figure 4 Schematic diagram of the memory device provided for implementation of this application Figure 2 ;

[0035] Figure 5 Schematic diagram of the storage device provided for the implementation of this application Figure 1 ;

[0036] Figure 6 Schematic diagram of the storage device provided for the implementation of this application Figure 2 ;

[0037] Figure 7 Schematic diagram of the structure of the second storage circuit provided for implementation of this application Figure 1 ;

[0038] Figure 8 Schematic diagram of the structure of the second storage circuit provided for implementation of this application Figure 2 ;

[0039] Figure 9A Type 1 of data information for damaged and redundant word lines provided for the implementation of this application;

[0040] Figure 9BData information type two for damaged word lines and redundant word lines provided for the implementation of this application;

[0041] Figure 10 Schematic diagram of different structural layouts of the memory cell array and peripheral circuits of the memory device provided for implementation of this application Figure 3 ;

[0042] Figure 11 A schematic diagram of the structure of the first and second storage circuits provided for the implementation of this application;

[0043] Figure 12 Schematic diagram of the memory device provided for implementation of this application Figure 3 ;

[0044] Figure 13 Schematic diagram of the memory device provided for implementation of this application Figure 4 ;

[0045] Figure 14 Schematic diagram of the memory system provided for implementation of this application Figure 1 ;

[0046] Figure 15 Schematic diagram of the electronic system provided for the implementation of this application Figure 1 ;

[0047] Figure 16 Schematic diagram of the electronic system provided for the implementation of this application Figure 2 ;

[0048] Figure 17 Flowchart of the driving method for the memory device provided in this application Figure 1 ;

[0049] Figure 18 Flowchart of the driving method for the memory device provided in this application Figure 2 ;

[0050] Figure 19 Flowchart of the driving method for the memory device provided in this application Figure 3 ;

[0051] Figure 20 Flowchart of the driving method for the memory device provided in this application Figure 4 ;

[0052] Figure 21 Flowchart of the driving method for the memory device provided in this application Figure 5 ;

[0053] Figure 22 Flowchart of the driving method for the memory device provided in this application Figure 6;

[0054] Figure 23 Flowchart of the driving method for the memory device provided in this application Figure 7 . Detailed Implementation

[0055] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] In the embodiments of this application, the terms "first," "second," etc., are used to distinguish similar objects, and not to describe a specific order or sequence.

[0057] In the embodiments of this application, the term "A in contact with B" includes the case where A and B are in direct contact, or the case where there are other components between A and B and A is indirectly in contact with B.

[0058] It should be understood that the phrases "some embodiments" or "some examples" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "some embodiments" or "some examples" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0059] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0060] It is understood that the meanings of “on”, “above” and “above” in this application should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intermediary feature or layer (i.e., directly on something), but also that it is “on” something with an intermediary feature or layer.

[0061] It should be noted that although this specification describes the embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0062] In some example memory devices, such as dynamic random access memory (DRAM), redundant row circuitry can be added to the DRAM's cell array, along with a backup decoder in the peripheral circuitry. The redundant row circuitry is connected to the backup decoder via a programmable connector. When a defect is detected in a row of the DRAM's cell array, the standard decoder connection for that row can be disconnected via a programmable connector (e.g., One-Time Programmable, OTP), and the backup row circuitry and backup decoder can be activated to replace the defective row. This masks row defects during manufacturing, improving DRAM yield and reliability.

[0063] Furthermore, rows can be located using Content-Addressable Memory (CAM). CAM is a special storage structure that allows direct access to addresses through data content, rather than through traditional address indexing. For example, in a row CAM, each storage location contains a data item and an associated tag. The data item is the actual stored data, while the tag is used for quick identification and retrieval of the data item.

[0064] For example, the array of memory cells in a memory device can be divided into multiple banks, which can operate in parallel. One bank corresponds to one row CAM.

[0065] During the power-on reset of the memory device, the memory controller writes the data in the OTP into the row CAM corresponding to each Bank.

[0066] The system compares the input row address with the data stored in the latch to determine if they match. If they don't match, the corresponding row is accessed directly via the CAM. If they match, the row address is identified as bad, and a corresponding redundant row address is matched, allowing direct access to the redundant row address.

[0067] It is understandable that the row CAM is coupled to the row decoder in the memory device. The row decoder can activate the corresponding word line according to the address given by the row CAM, so as to directly access the address according to the data.

[0068] However, in some examples employing a CAM and OTP circuit structure, multiple CAMs are positioned near their respective coupled banks. For example, a bank and its coupled CAM may be located in one physical area, with multiple sets of banks and CAMs arranged sequentially within the same physical area. The OTP is located on one side of a unified area comprised of these physical areas. Thus, based on the arrangement of different physical areas (banks and CAMs), the OTP requires relatively long lines to connect to multiple CAMs. The varying transmission path lengths between different CAMs and the OTP can easily lead to significant differences in the time it takes for the CAMs to store data, causing latency issues. Furthermore, the layout design of the lines between the CAMs and the OTP is constrained by their positional relationship, resulting in high complexity and hindering flexible adjustments for different application scenarios.

[0069] To address at least one of the aforementioned problems, embodiments of this application provide a memory device and its driving method, as well as a memory system, which facilitates flexible adjustment of the circuit layout connecting the memory bank, reducing process costs and product size.

[0070] For example, the memory device may include, but is not limited to, one or more of the following: NAND flash memory (e.g., vertical NAND flash memory), NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), and nano random access memory (NRAM). The subsequent examples in this application do not limit the specific internal structure of the memory device.

[0071] In some embodiments, such as Figure 1 As shown, the memory device 100 includes a memory cell array 110 and peripheral circuitry 120.

[0072] The storage cell array 110 includes multiple storage banks 111. For example, the storage cell array 110 includes multiple storage cells, which can be divided into multiple storage banks 111. For instance, one storage bank 111 can correspond to an independent row address space and column address space. Each storage bank 111 can perform read and write operations independently, and multiple storage banks 111 can work in parallel, improving access efficiency.

[0073] Peripheral circuitry 120 is coupled to multiple memory banks 111. For example, peripheral circuitry 120 can be coupled to multiple memory banks 111 via lines such as bit lines (BL), word lines (WL) to apply voltage and / or current signals to memory cells in each memory bank 111 and to sense voltage and / or current signals from memory cells in each memory bank 111 to perform logical operations (e.g., programming, reading, or writing operations) on the memory cells in the multiple memory banks 111.

[0074] Continue reading Figure 1 The aforementioned peripheral circuit 120 includes: a first storage circuit 121 and a plurality of second storage circuits 122.

[0075] The first storage circuit 121 is configured to store address information of a damaged word line WL_d in a word line WL coupled to a plurality of memory banks 111. For example, the first storage circuit 121 may include a one-time programmable memory cell (e.g., an OTP cell).

[0076] Multiple second storage circuits 122 are coupled to the first storage circuit 121 and configured to couple a redundant word line RWL corresponding to a corrupted word line WL_d in response to a first control signal Ctrl1. For example, the second storage circuits 122 may include content-addressable memory cells (e.g., CAM cells). It is understood that the word line WL includes the corrupted word line WL_d.

[0077] In this embodiment, the data transmission paths between the multiple second storage circuits 122 and the first storage circuit 121 are all shorter than the data transmission paths between the multiple second storage circuits 122 and the multiple memory banks 111. For example, one second storage circuit 122 is coupled to one memory bank 111 via a word line WL. The data transmission path between one second storage circuit 122 and the first storage circuit 121 is shorter than the data transmission path between this second storage circuit 122 and the memory bank 111. The example provided in this application does not limit the number of multiple second storage circuits 122, which can be adjusted according to the number of memory banks 111 in the actual memory device 100.

[0078] For example, such as Figure 2 and Figure 3The diagram illustrates the positional relationship of the first storage circuit 121, the second storage circuit 122, and the storage-related circuit 1110 in the peripheral circuit 120, as well as their connection to the multiple memories 111 in the storage cell array 110. Each storage-related circuit 1110 is coupled to a single memory cell 111. For example, the storage cell array 110 is housed in one semiconductor structure, and the peripheral circuit 120 is housed in another semiconductor structure; the two semiconductor structures can be stacked. Within the semiconductor structure containing the peripheral circuit 120, multiple second storage circuits 122 can be centrally located in a vacant space near the first storage circuit 121 (e.g., ...). Figure 2 (As shown), instead of being dispersed near each memory-related circuit 1110. Alternatively, multiple second memory circuits 122 can be centrally located on the side of the memory-related circuit 1110 closest to the first memory circuit 121, and situated around the first memory circuit 121. For example, as Figure 3 As shown, all the second storage circuits 122 can be positioned between all the storage-related circuits 1110 and the first storage circuit 121, which can reduce the line length between multiple second storage circuits 122 and the first storage circuit 121.

[0079] It is understandable that, due to the large size of the row address field, the data transmission from the first storage circuit 121 to the second storage circuit 122 takes a long time. In particular, when the transmission path between the two is long or the transmission paths between the first storage circuit 121 and different second storage circuits 122 are significantly different, delay problems are likely to occur.

[0080] In the aforementioned memory device 100, the second storage circuit 122, in response to the first control signal Ctrl1, can disconnect from the damaged word line WL_d and then connect to the redundant word line RWL corresponding to the damaged word line WL_d. This allows data in the second storage circuit 122 to be transmitted to the memory bank 111 via the redundant word line RWL. Considering the large amount of data transmitted between the first storage circuit 121 and the second storage circuit 122, the positional layout of the multiple second storage circuits 122 within the memory device 100 is adjusted relative to the first storage circuit 121. The data transmission paths between the multiple second storage circuits 122 and the first storage circuit 121 are all set to be shorter than the data transmission paths between the multiple second storage circuits 122 and the multiple memory banks 111. This not only reduces the delay in transmitting data from the first storage circuit 121 to the second storage circuit 122 but also facilitates flexible adjustment of the wiring layout between the second storage circuits 122 and the memory bank 111, thereby reducing the manufacturing cost and product size of the memory device 100.

[0081] In addition, such as Figure 2 and Figure 3As shown, memory bank 111 and second memory circuit 122 are coupled via a row decoder (XDEC) to decode the address signal and convert it into a specific row selection signal, thereby controlling the activation and access of a specific row in the memory bank. The example provided in this application does not impose specific limitations on the structure and location of the row decoder. Considering that the row decoder only needs to decode a specific row address, the amount of decoded data is small, and its impact on data transmission delay is minimal, it can be placed near the memory bank 111 to which it is coupled.

[0082] In some examples, such as Figure 4 As shown, the peripheral circuitry 120 also includes a first multiplexer circuitry 123. For example, the first multiplexer circuitry 123 may include a multiplexer (e.g., a MUX).

[0083] The multiple input terminals of the first multiplexing circuit 123 are respectively coupled to multiple second storage circuits 122, and the output terminal of the first multiplexing circuit 123 is coupled to the storage bank 111. For example, the first multiplexing circuit 123 may include at least two input terminals, and the number of input terminals is related to its circuit logic and can be set according to actual needs.

[0084] For example, peripheral circuitry 120 may include one or more first multiplexer circuits 123. When peripheral circuitry 120 includes a first multiplexer circuit 123, the number of inputs to the first multiplexer circuit 123 may be the same as the number of second storage circuits 122.

[0085] Alternatively, when the peripheral circuit 120 includes multiple first multiplexing circuits 123, each first multiplexing circuit 123 may have at least two input terminals, and each first multiplexing circuit 123 may be coupled to two second storage circuits 122. Furthermore, the number of second storage circuits 122 coupled to different first multiplexing circuits 123 may vary. For example, multiple input terminals of some first multiplexing circuits 123 may be coupled to three second storage circuits 122. Multiple input terminals of some first multiplexing circuits 123 may be coupled to two second storage circuits 122. The examples provided in this application do not impose specific limitations on the number of first multiplexing circuits 123 or the number of second storage circuits 122 coupled to each first multiplexing circuit 123; these can be adjusted according to actual needs.

[0086] Furthermore, the output of the first multiplexing circuit 123 is coupled to the memory bank 111, enabling selective connection of different second memory circuits 122 to a single memory bank 111. For example, the outputs of at least two first multiplexing circuits 123 coupled to different second memory circuits 122 can be coupled to the same memory bank 111. Alternatively, the outputs of different first multiplexing circuits 123 can be coupled to different memory banks 111. The examples provided in this application are not limiting and can be adjusted according to actual needs.

[0087] The first multiplexing circuit 123 is configured to couple the redundant word line RWL corresponding to the damaged word line WL_d to the target memory bank 111 in response to the second control signal Ctrl2, and to transfer the data in the second storage circuit 122 to the target memory bank 111.

[0088] The memory bank 111 coupled to the damaged word line WL_d can be the same as or different from the target memory bank 111 coupled to the redundant word line RWL corresponding to the damaged word line WL_d.

[0089] For example, the memory bank 111 coupled to the damaged word line WL_d is the same as the target memory bank 111 coupled to the redundant word line RWL corresponding to the damaged word line WL_d. The target memory bank 111 can be quickly selected to store data, and the corresponding circuit structure is simple.

[0090] For example, the memory bank 111 coupled to the damaged word line WL_d is different from the target memory bank 111 coupled to the redundant word line RWL corresponding to the damaged word line WL_d. Different memory banks 111 can be selected to store data according to requirements (e.g., the information carried by the first control signal Ctrl1), which can reduce the number of times the memory bank 111 that has been erased many times and improve the service life of the memory device 100.

[0091] In this way, the first multiplexing circuit 123, in response to the second control signal Ctrl2, connects the redundant word line RWL to the target memory 111, and transmits the data in the second storage circuit 122 to the target memory 111.

[0092] In some examples, the peripheral circuitry 120 may include multiple first multiplexing circuits 123, each of which may operate in parallel in response to a second control signal Ctrl2. These different first multiplexing circuits 123 may connect to different target memory banks 111 in response to the second control signal Ctrl2.

[0093] Furthermore, the memory bank 111 coupled to the damaged word line WL_d can be the same as or different from the target memory bank 111 coupled to the redundant word line RWL corresponding to the damaged word line WL_d. The effect achieved in this example can be seen in the explanation of the functional effect of a first multiplexer circuit 123 in the above example, and will not be repeated here.

[0094] In some examples, such as Figure 5 and Figure 6 In the positional relationship of the circuit layout of a memory bank 111 and its coupled redundant word lines RWL (and row decoder), a memory bank 111 can divide multiple memory cells into multiple sub-sections, each sub-section being arranged adjacent to the corresponding redundant word line RWL (e.g., ...). Figure 5 (As shown). This reduces the transmission path length between the second storage circuit 122 and the redundant word line RWL.

[0095] Alternatively, multiple memory cells of a memory bank 111 can be grouped together in one area, and redundant word lines (RWL) can be grouped together in one area, and coupled to (a row decoder or) a second memory circuit 122 via different leads (e.g., Figure 6 (As shown).

[0096] In this application, the connection relationship between each memory bank 111 (e.g., memory cell) and each word line WL or redundant word line RWL is not specifically limited and can be set according to actual needs.

[0097] For example, such as Figure 6 As shown, word line WL is coupled to the second storage circuit 122. Redundant word line RWL is coupled to the memory bank 111 and the second storage circuit 122. One redundant word line RWL corresponds to one word line WL.

[0098] Multiple redundant word lines RWL are sequentially adjacent and coupled to a memory bank 111. The multiple redundant word lines RWL are located on the same side of the memory bank 111.

[0099] This simplifies the circuit design between memory bank 111, redundant word line RWL, and second memory circuit 122, improving the flexibility of the circuit design; moreover, based on such Figure 2 and Figure 3 The layout and positional relationship between the second storage circuit 122 and the storage bank 111 shown are designed as follows: Figure 6 The layout of a memory bank 111 and its coupled redundant word line RWL, as shown, also helps to reduce the transmission path length between the second memory circuit and the redundant word line.

[0100] In some examples, multiple second storage circuits 122 are configured to be coupled to at least one redundant word line RWL or at least one word line WL in response to multiple first control signals Ctrl1.

[0101] For example, the memory cell array 110 includes multiple memory banks 111. Each memory bank 111 can correspond to an independent row address space and column address space (e.g., ...). Figure 5 and Figure 6 (As shown). A second storage circuit is configured to connect a memory bank 111 to a second storage circuit 122 in response to a first control signal Ctrl1 coupled to at least one redundant word line RWL or at least one word line WL.

[0102] In other words, different first control signals Ctrl1 can indicate that different second storage circuits 122 are connected to the corresponding storage bank 111.

[0103] In the event of a detected damaged word line WL_d, memory bank 111 can be connected to the second storage circuit 122 via a redundant word line RWL, or memory bank 111 can be connected to the second storage circuit 122 via a word line WL other than the damaged word line WL_d. This allows each memory bank 111 to perform read and write operations independently. When read and write operations are performed on different memory banks, multiple second storage circuits 122 can respond to multiple first control signals Ctrl1 respectively, allowing multiple memory banks 111 to operate in parallel, thus improving access efficiency.

[0104] In some examples, such as Figure 7 and Figure 8 As shown, the second storage circuit 122 includes a content-addressable storage unit 1221.

[0105] For example, the second storage circuit 122 includes a content-addressable memory. The content-addressable memory cell 1221 includes a CAM. <n>For example, such as Figure 7 As shown, the second storage circuit 122 includes CAM <0> CAM <1> CAM <2> ……CAM <7> .

[0106] Continue reading Figure 7 The peripheral circuitry 120 also includes a shift register 125 and a multiplexer 126. For example, during the power-on (POR) process of the memory device 100, the second storage circuitry 122 can acquire information about the corrupted word line WL_d stored in the first storage circuitry 121. For instance, the multiplexer 126 can sequentially select content-addressable memory cells CAM. <0> CAM <1> CAM <2> ……CAM <7> When a content-addressable memory cell 1221 is selected, the information of the corresponding damaged word line WL_d can be transferred from the first storage circuit 121 to the shift register 125, and then written from the shift register 125 to the selected content-addressable memory cell 1221.

[0107] Next, another content-addressable memory cell 1221 can be selected, the shift register 125 can be reset, and the above operation steps can be repeated until the second storage circuit 122 acquires the information of all damaged word lines WL_d. In this way, the information of damaged word lines WL_d stored in the first storage circuit 121 can be sequentially transferred to multiple content-addressable memory cells 1221.

[0108] There is no long data transmission line between the multiplexer 126 and the shift register 125, and they can be integrated into one structure. The example provided in this application does not limit this.

[0109] In some examples, such as Figure 8 As shown, the content-addressable memory unit 1221 includes a second memory element 1222 and a comparison circuit 1223.

[0110] The second storage element 1222 is configured to store the identification information and address information of the damaged word line WL_d obtained from the first storage circuit 121, and the identification information and address information of the redundant word line RWL corresponding to one damaged word line WL_d. For example, the second storage element 1222 may include multiple second storage elements 1222, and the second storage element 1222 may include a latch. For example, as... Figure 8 As shown, the content-addressable storage unit 1221 includes 16 latches. <0> Latch <1> Latch <2> ...Latch <15> .

[0111] The comparator circuit 1223 is configured to compare user data with the address information of the damaged word line WL_d stored in the second storage element 1222. The user data and the address information of the damaged word line WL_d are the same, and the redundant word line RWL corresponding to the damaged word line WL_d is coupled.

[0112] For example, comparator circuit 1223 is coupled to data path 1224 (e.g., ...). Figure 8 The comparison circuit 1223, between the data path 1224 (as shown) and the content-addressable memory unit 1221, is configured to compare user data with the address information of the corrupted word line WL_d stored in the second memory element 1222, and output the comparison result. For example, the comparison circuit 1223 may include multiple comparators. One comparator can compare a data path 1224 (such as...). Figure 8 The data carried by the data (as shown) is compared with the data in the corresponding latch. When the bit value stored in each latch is equal to the bit value carried by the corresponding data line of the data path, the comparison result can be a logic value "1" (e.g., a higher voltage), which can be characterized as the user data being the same as the address information of the corrupted word line WL_d, coupled to the redundant word line RWL corresponding to the corrupted word line WL_d.

[0113] In this way, the content addressable storage unit 1221 achieves the connection between the second storage circuit 122 and the redundant word line RWL through the second storage element 1222 and the comparator circuit 1223.

[0114] Furthermore, the comparator circuit 1223 can also be located outside the content-addressable memory cell 1221. For example, the comparator circuit 1223 can be coupled between the data path and the content-addressable memory cell 1221 (e.g., the second storage element 1222 of the content-addressable memory cell 1221). In this way, during the power-on POR process, the peripheral circuit can be configured to write data from the data path to the content-addressable memory cell 1221, that is, the data path can be connected to the content-addressable memory cell 1221, bypassing the comparator circuit 1223, or ignoring the comparison result.

[0115] The number of addressable memory cells 1221, the number of data paths 1224, and the number of corresponding latches in the second storage circuit 122 described above can be set according to actual conditions, for example, such as Figure 7 The content-addressable memory unit 1221 shown includes eight CAMs. For example... Figure 8 The data path 1224 shown includes 16 data lines (the corresponding latches include 16 latches). The examples provided in this application are not limiting.

[0116] In some examples, such as Figure 9A As shown, the second storage element 1222 stores the address information of the damaged word line WL_d and the identification information RED (e.g., "0") of the damaged word line WL_d, as well as the address information of the redundant word line RWL corresponding to a damaged word line WL_d and the identification information RED (e.g., "1") of the redundant word line RWL (e.g., "1").

[0117] Or, such as Figure 9B As shown, the second storage element 1222 stores the address information of the damaged word line WL_d, the identification information RED (e.g., "0") of the damaged word line WL_d, and the address information of the storage bank 111 coupled to the damaged word line WL_d, as well as the address information of the redundant word line RWL corresponding to a damaged word line WL_d, the identification information RED (e.g., "1") of the redundant word line RWL, and the address information of the storage bank 111 coupled to the redundant word line RWL.

[0118] The address information of the memory bank 111 coupled to the damaged word line WL_d can be the same as or different from the address information of the memory bank 111 coupled to the redundant word line RWL.

[0119] For example, the address information of memory bank 111 coupled to the damaged word line WL_d is the same as the address information of memory bank 111 coupled to the redundant word line RWL, which can quickly select the target memory bank 111 to store data, and the corresponding circuit structure is simple.

[0120] Alternatively, the address information of the memory bank 111 coupled to the damaged word line WL_d may be different from the address information of the memory bank 111 coupled to the redundant word line RWL. Different memory banks 111 can be selected to store data according to requirements (e.g., the information carried by the first control signal Ctrl1), which can reduce the number of times the memory bank 111 that has been erased more often and improve the service life of the memory device.

[0121] For example, the address information of memory bank 111 may contain data consisting of 4 bits (1 square in the figure represents 1 bit of data). The example provided in this application does not impose specific restrictions on the address information of memory bank 111.

[0122] In some examples, the peripheral circuitry 120 may include a plurality of first storage circuits 121. For example, such as... Figure 10 The peripheral circuit 120 is shown to have a first storage circuit 121, a second storage circuit 122, and a storage bank-related circuit 1110, with their positional relationship and connection to multiple memories 111 in the storage cell array 110. Each storage bank-related circuit 1110 is coupled to one memory bank 111. The peripheral circuit 120 may include two first storage circuits 121. One first storage circuit 121 may be coupled to a portion of the second storage circuit 122, and another first storage circuit 121 may be coupled to another portion of the second storage circuit 122. Alternatively, one first storage circuit 121 may be coupled to all of the second storage circuits 122, and another first storage circuit 121 may also be coupled to all of the second storage circuits 122.

[0123] The examples provided in this application do not limit the number of first storage circuits 121 or the number of second storage circuits 122 coupled to one first storage circuit 121, and can be set according to actual needs.

[0124] In some examples, the first storage circuit 121 may include a one-time programmable memory. For example, the first storage circuit 121 may be a fuse-proof OTP memory.

[0125] like Figure 11 As shown, the first storage circuit 121 includes a one-time programmable storage unit 1211 (e.g., an OTP unit). For example, the first storage circuit 121 may include multiple OTP storage units.

[0126] As is understandable, one-time programmable memory (OTP) is a special type of non-volatile memory characterized by the fact that it can only be programmed once; once the data is written, it cannot be changed or deleted. OTP memory can be used to store fixed configuration information, unique device identifiers, encryption keys, authentication token seeds, and other content that will not be modified during the device's lifespan. Because it cannot be erased or rewritten, OTP memory offers high security, preventing malicious or unauthorized data tampering.

[0127] The one-time programmable memory cell 1211 includes a first memory element and at least one transistor (not shown). For example, the first memory element may include a register. The first memory element stores address information for a corrupted word line WL_d.

[0128] In some examples, such as Figure 11 and Figure 12 As shown, the peripheral circuit 120 also includes a buffer circuit 124.

[0129] The buffer circuit 124 is coupled to a plurality of second storage circuits 122, a first storage circuit 121 and a data transmission interface, and is configured to transmit user data transmitted through the data transmission interface to the second storage circuits 122 in response to a third control signal Ctrl3.

[0130] In this way, the buffer circuit 124 temporarily stores the user data, transmits the user data to the second storage circuit 122 in response to the third control signal Ctrl3, and then compares the user data with the information of the damaged word line WL_d.

[0131] Furthermore, the buffer circuit 124 is also configured to transfer data in the first storage circuit 121 to a plurality of second storage circuits 122 in response to the fourth control signal Ctrl4.

[0132] In this way, considering that the field information of the damaged word line WL_d is large, the buffer circuit 124 temporarily stores the field information of the damaged word line WL_d. In the process of transferring the data in the first storage circuit 121 to the multiple second storage circuits 122 in response to the fourth control signal Ctrl4, the buffer circuit 124 plays a buffering role, thereby improving the data transmission performance between the first storage circuit 121 and the multiple second storage circuits 122.

[0133] In some examples, such as Figure 13 As shown, the buffer circuit 124 includes a buffer 1241 and a second multiplexer circuit 1242 coupled to the buffer 1241.

[0134] For example, the second multiplexer circuit 1242 may have at least two inputs. For instance, the second multiplexer circuit 1242 includes a first input, a second input, and an output (not shown). The first input of the second multiplexer circuit 1242 is coupled to the data transmission interface DADAT, the second input of the second multiplexer circuit 1242 is coupled to the first storage circuit 121, and the output of the second multiplexer circuit 1242 is coupled to the buffer 1241.

[0135] Additionally, buffer 1241 is coupled to a plurality of second storage circuits 122 via a data path (e.g., a data line).

[0136] In some examples, such as Figure 13 As shown, the peripheral circuit 120 also includes an input / output circuit 127. The input / output circuit 127 is coupled to the data transmission interface DADAT and is configured to receive user data and output it to the data transmission interface DADAT.

[0137] For example, the input / output circuit 127 may include circuit structures (e.g., Input / Output Circuit, or I / O circuit for short) that enable signal transmission and interaction between the memory device 100 and external devices. For example, the input / output circuit 127 may include buffers, level shifters, and overvoltage and overcurrent protection circuits, etc. The example provided in this application does not impose specific limitations on this, and its main purpose is to receive user data and output it to the data transmission interface DADAT.

[0138] like Figure 14 and Figure 15 As shown, this application embodiment provides a memory system 200. The memory system 200 includes a memory device 100 and a memory controller 210.

[0139] For example, memory controller 210 can manage data in memory device 100 and communicate with host 310 (such as...). Figure 16 (As shown) Communication. The memory controller 210 can be configured to control operations such as reading, erasing, and programming of the memory device 100; it can also be configured to manage various functions regarding data stored or to be stored in the memory device 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; it can also be configured to process error checking and correction (ECC) codes regarding data read from or written to the memory device 100.

[0140] In some examples, such as Figure 14 As shown, the memory device 100 includes a first storage circuit 121 and a second storage circuit 122.

[0141] Additionally, the memory controller 210 is coupled to the memory device 100 and configured to transfer the address information of the damaged word line WL_d stored in the first storage circuit 121 to the second storage circuit 122; and to transfer user data to the second storage circuit 122; and is also configured to output a first control signal Ctrl1, instructing the second storage circuit 122 to couple the redundant word line RWL corresponding to the damaged word line WL_d if the user data and the address information of the damaged word line WL_d are the same.

[0142] For example, during the power-on (POR) process of the memory device 100, the second memory circuit 122 can acquire information about the damaged word line WL_d stored in the first memory circuit 121. Where the first memory circuit 121 is coupled to the second memory circuit 122 via a buffer circuit 124, the buffer circuit 124 buffers the information about the damaged word line WL_d stored in the first memory circuit 121 and, in response to a fourth control signal, transfers the information about the damaged word line WL_d to multiple second memory circuits 122. It is understood that the power-on reset signal can be output by the memory controller 210 or by the host 310 (e.g., […]). Figure 16 The output shown in this application is not limited to this example.

[0143] Additionally, the buffer circuit 124 temporarily stores user data and transmits the user data to the second storage circuit 122 in response to the third control signal Ctrl3.

[0144] Then, the memory controller 210 outputs the first control signal Ctrl1, and the second storage circuit 122 couples the redundant word line RWL corresponding to the damaged word line WL_d if the user data and the address information of the damaged word line WL_d are the same.

[0145] In some examples, such as Figure 15 As shown, the memory device 100 also includes a first multiplexing circuit 123.

[0146] The memory controller 210 is also configured to output a second control signal Ctrl2, instructing the first multiplexer circuit 123 to transfer data from the second storage circuit 122 to the target memory bank 111 coupled to the redundant word line RWL. The memory bank 111 coupled to the damaged word line WL_d may be the same as or different from the target memory bank 111 coupled to the redundant word line RWL corresponding to the damaged word line WL_d.

[0147] For example, the memory bank 111 coupled to the damaged word line WL_d is the same as the target memory bank 111 coupled to the redundant word line RWL corresponding to the damaged word line WL_d. The target memory bank 111 can be quickly selected to store data, and the corresponding circuit structure is simple.

[0148] For example, the memory bank 111 coupled to the damaged word line WL_d is different from the target memory bank 111 coupled to the redundant word line RWL corresponding to the damaged word line WL_d. By using information carried by different second control signals Ctrl2, data within the second storage circuit 122 can be transferred to different target memory banks 111. For instance, the target memory bank 111 can be selected based on factors such as the number of times it has been erased, reducing the number of times memory banks 111 with a high number of erase cycles are used and increasing the lifespan of the memory device 100.

[0149] In this way, the first multiplexing circuit 123, in response to the second control signal Ctrl2, connects the redundant word line RWL to the target memory 111, and transmits the data in the second storage circuit 122 to the target memory 111.

[0150] like Figure 16 As shown in the illustration, an embodiment of this application illustrates an electronic system 300. For example, the electronic system 300 may include, but is not limited to, a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device 100 therein.

[0151] Please continue reading. Figure 16 The electronic system 300 may include a host 310 and a memory system 200.

[0152] The host 310 may be a processor of an electronic device (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)). The host 310 may be configured to send data to or receive data from the memory system 200.

[0153] The memory system 200 includes a memory controller 210 and one or more memory devices 100, as well as other integrated circuit structures for signal transmission. The memory controller 210 and the one or more memory devices 100 can be integrated and packaged in the same memory device. This facilitates the application of the memory system 200 in different types of terminal electronic products.

[0154] For example, such as Figure 17 As shown, this application provides a readable storage medium 400. The readable storage medium 400 includes a stored computer program or instructions; when the computer program or instructions are executed, a driving method is used to control the device where the computer-readable storage medium is located to implement the memory device 100 as provided in any of the following examples.

[0155] For example, the types of readable storage media 400 include: storage devices with integrated memory controller 210 and one or more memory devices 100, including: Universal Flash Storage (UFS) or Embedded Multi Media Card (eMMC) and other types of storage devices.

[0156] The integrated circuit of this storage device can be implemented in various ways. For example, it can be a memory card that integrates a single memory device 100 and a memory controller 210, or an SSD that integrates multiple memory devices 100 and memory controller 210. It is understood that the storage capacity and / or operating speed of an SSD is greater than that of a memory card.

[0157] For examples, please continue reading. Figure 17 The readable storage medium 400 also includes a connector 410. The connector 410 is configured to connect the readable storage medium 400 to a host (e.g., Figure 16 The host 310 is coupled to it. For example, connector 410 includes gold fingers.

[0158] like Figures 18-23 As shown, this application embodiment provides a driving method for a memory device 100, which is capable of responding to a control signal to instruct a second storage circuit 122 in the memory device 100 to couple with a redundant word line RWL corresponding to a damaged word line WL_d, and writing data to a target memory bank 111 via the redundant word line RWL.

[0159] In some examples, such as Figure 18 As shown, the driving method includes S100 and S200.

[0160] S100: In response to the power-on reset signal POR, the address information of the damaged word line WL_d in the word line WL coupled to the multiple memory banks 111 stored in the first storage circuit 121 is transferred to the second storage circuit 122.

[0161] It is understandable that the power-on reset signal can be output by the memory controller 210 or by the host 310 (e.g., Figure 16 The output shown in this application is not limited to this example.

[0162] For example, the first storage circuit 121 stores the address information of the corrupted word line WL_d. In response to the power-on reset signal POR, the first storage circuit 121 transfers the information of the corrupted word line WL_d to the buffer circuit 124 (e.g., ...). Figure 12 (as shown), and is transmitted to the second storage circuit 122 via the buffer circuit 124.

[0163] Additionally, the buffer circuit 124 temporarily stores user data and transmits the user data to the second storage circuit 122 in response to the third control signal Ctrl3.

[0164] S200: In response to the first control signal Ctrl1, compare the user data and the data stored in the second storage circuit 122, determine the redundant word line RWL corresponding to the damaged word line WL_d, and couple it.

[0165] The data transmission path between the second storage circuit 122 and the first storage circuit 121 is shorter than the path from the second storage circuit 122 to the storage bank 111 via the coupled redundant word line RWL.

[0166] For example, such as Figure 1 As shown, the second storage circuit 122 is coupled to the first storage circuit 121. When the address information of the damaged word line WL_d is obtained, the second storage circuit 122 responds to the first control signal Ctrl1, compares the user data and the data stored in the second storage circuit 122, determines the redundant word line RWL corresponding to the damaged word line WL_d and couples it, and then writes the data to the target memory bank 111 through the redundant word line RWL.

[0167] Considering the large amount of data transmitted between the first storage circuit 121 and the second storage circuit 122, the positional layout of the multiple second storage circuits 122 in the memory device 100 relative to the first storage circuit 121 is adjusted. The data transmission paths between the multiple second storage circuits 122 and the first storage circuit 121 are all shorter than the data transmission paths between the multiple second storage circuits 122 and the multiple memory banks 111. This not only reduces the delay in transmitting data from the first storage circuit 121 to the second storage circuit 122, but also facilitates flexible adjustment of the wiring layout between the second storage circuits 122 and the memory banks 111, and helps reduce the product size and manufacturing costs.

[0168] Depending on the information stored in the first storage circuit 121, for example, the first storage circuit 121 can store the address information and identification information of the damaged word line WL_d, as well as the identification information and address information of the redundant word line RWL corresponding to the damaged word line WL_d, and the address information of the storage bank 111 coupled to the redundant word line RWL (such as...). Figure 19 The logic of the method steps shown); or, the first storage circuit 121 can also store the address information and identification information of the damaged word line WL_d, as well as the identification information and address information of the redundant word line RWL corresponding to the damaged word line WL_d (such as...). Figure 20 (Logic of the steps shown). The following example demonstrates a control method for the second storage circuit 122 based on two different types of information.

[0169] In some examples, such as Figure 19 As shown, the above step S200: Determine and couple the redundant word line RWL corresponding to the damaged word line WL_d, including: S210~S230.

[0170] S210: Based on the address and identification information of the damaged word line WL_d, determine the identification and address information of the redundant word line RWL corresponding to the damaged word line WL_d, and determine the target redundant word line RWL.

[0171] It is understandable that "target redundant word line RWL" refers to a redundant word line RWL selected during data transmission, and does not mean that it is the only redundant word line RWL.

[0172] For example, such as Figure 8 As shown, the second storage circuit 122 includes a second storage element 1222 and a comparison circuit 1223. The second storage element 1222 is configured to store the identification information and address information of the damaged word line WL_d obtained from the first storage circuit 121, as well as the identification information and address information of the redundant word line RWL corresponding to the damaged word line WL_d. The comparison circuit 1223 is configured to compare user data with the address information of the damaged word line WL_d stored in the second storage element 1222. The user data and the address information of the damaged word line WL_d are identical, and the user data is coupled to the redundant word line RWL corresponding to the damaged word line WL_d.

[0173] S220: Determine the target memory bank 111 based on the address information of the memory bank 111 coupled to the target redundant word line RWL. The memory bank 111 coupled to the damaged word line WL_d is different from the target memory bank 111.

[0174] It is understandable that "target memory 111" refers to a memory 111 selected during data transmission, and does not mean that it is the only memory 111.

[0175] For example, a redundant word line RWL can correspond to a preset memory bank 111. Through the address information of the memory bank 111, in response to the second control signal Ctrl2, the redundant word line RWL is connected to its corresponding memory bank 111.

[0176] Understandably, the memory controller 210 is also configured to output a second control signal Ctrl2, which carries information pointing to the target memory bank 111, coupling the target redundant word line RWL to the target memory bank 111. This target memory bank 111 can be the same memory bank 111 as the memory bank 111 coupled to the damaged word line WL_d, or it can be a different memory bank 111. For example, the target memory bank 111 can be selected based on factors such as the number of times the memory bank 111 has been erased, which helps to improve the service life of the memory device 100.

[0177] S230: The second storage circuit 122 is coupled to the target memory bank 111 via the target redundant word line RWL.

[0178] For example, such as Figure 15 As shown, after coupling the second storage circuit 122 to the target redundant word line RWL, the first multiplexer circuit 123 can select which memory bank 111 the target redundant word line RWL is coupled to, thereby connecting the second storage circuit 122 to the target memory bank 111. The memory bank 111 coupled to the damaged word line WL_d can be the same as or different from the target memory bank 111 coupled to the redundant word line RWL corresponding to the damaged word line WL_d.

[0179] Understandably, the memory controller 210 is also configured to output a second control signal Ctrl2, which can carry information pointing to the target memory bank 111, and couple the target redundant word line RWL to the target memory bank 111. This target memory bank 111 can be the same memory bank 111 as the memory bank 111 coupled to the damaged word line WL_d, or it can be a different memory bank 111.

[0180] For example, the memory bank 111 coupled to the damaged word line WL_d is the same as the target memory bank 111 coupled to the redundant word line RWL corresponding to the damaged word line WL_d. The target memory bank 111 can be quickly selected to store data, and the corresponding circuit structure is simple.

[0181] Alternatively, the memory bank 111 coupled to the damaged word line WL_d may be different from the target memory bank 111 coupled to the redundant word line RWL corresponding to the damaged word line WL_d. Different memory banks 111 can be selected to store data according to requirements (e.g., the information carried by the first control signal Ctrl1), which can reduce the number of times the memory bank 111 that has been erased many times and improve the service life of the memory device 100.

[0182] In other examples, such as Figure 20 As shown, the above step S200: determining and coupling the redundant word line RWL corresponding to the damaged word line WL_d, includes: S240 and S250.

[0183] S240: Based on the address information and identification information of the damaged word line WL_d, determine the identification information and address information of the redundant word line RWL corresponding to the damaged word line WL_d, and the address information of the memory bank 111 coupled to the redundant word line RWL, and determine the target redundant word line RWL.

[0184] For example, the second storage circuit 122 includes a second storage element 1222 and a comparator circuit 1223. The second storage element 1222 is configured to store the identification information and address information of the damaged word line WL_d obtained from the first storage circuit 121, and to store the identification information and address information of the redundant word line RWL corresponding to a damaged word line WL_d.

[0185] The comparator circuit 1223 is configured to compare user data with the address information of the damaged word line WL_d stored in the second storage element 1222. The user data and the address information of the damaged word line WL_d are the same, and the redundant word line RWL corresponding to the damaged word line WL_d is coupled.

[0186] S250: The second storage circuit 122 is coupled to the target memory bank 111 via the target redundant word line RWL.

[0187] For example, a redundant word line RWL can correspond to a preset memory bank 111. Through the address information of the memory bank 111, in response to the second control signal Ctrl2, the redundant word line RWL is connected to its corresponding memory bank 111.

[0188] In some examples, such as Figure 21 As shown, the method further includes: S300.

[0189] S300: In response to the second control signal Ctrl2, the target redundant word line RWL is coupled to the target memory bank 111, and the data in the second storage circuit 122 is transmitted to the target memory bank 111. The memory bank 111 coupled to the damaged word line WL_d is different from the target memory bank 111 coupled to the target redundant word line RWL.

[0190] For example, in response to the second control signal Ctrl2, the first multiplexer circuit 123 connects the target redundant word line RWL to the target memory bank 111. Through the information carried by different second control signals Ctrl2, the data in the second storage circuit 122 can be transmitted to different target memory banks 111.

[0191] In some examples, such as Figure 22 As shown, step S300 above: transmitting data from the second storage circuit 122 to the target storage 111 includes: S310.

[0192] S310: After decoding the data transmitted by the redundant word line RWL, transmit it to the target memory 111.

[0193] For example, the second storage circuit 122 is connected via a line decoder (e.g., Figure 2 and Figure 3 The XDEC shown is coupled to memory bank 111. After the line decoder decodes the data transmitted by the redundant word line RWL, it is transmitted to the target memory bank 111.

[0194] In some examples, such as Figure 23 As shown, the method also includes S400 and S500.

[0195] S400: In response to the third control signal Ctrl3, the user data is transmitted to the second storage circuit 122.

[0196] S500: In response to the fourth control signal Ctrl4, the data in the first storage circuit 121 is transferred to multiple second storage circuits 122.

[0197] For example, such as Figure 12 As shown, the buffer circuit 124 temporarily stores the user data. In response to the third control signal Ctrl3, the buffer circuit 124 transmits the user data to the second storage circuit 122 for subsequent comparison of the user data with the information of the damaged word line WL_d.

[0198] Additionally, the buffer circuit 124 temporarily stores the information in the first storage circuit 121, and in response to the fourth control signal Ctrl4, transfers the data in the first storage circuit 121 to a plurality of second storage circuits 122.

[0199] Furthermore, considering that the field information of the damaged word line WL_d is relatively large, the buffer circuit 124 plays a buffering role in the process of transferring the data in the first storage circuit 121 to the multiple second storage circuits 122 in response to the fourth control signal Ctrl4, thereby improving the performance of data transmission between the first storage circuit 121 and the multiple second storage circuits 122.

[0200] In some examples, such as Figure 23 As shown, the method also includes: S600.

[0201] S600: In response to the refresh signal Ref, update the address information of the corrupted word line stored in the first storage circuit 121.

[0202] For example, the first storage circuit 121 may include non-volatile memory (e.g., a register). If the information of the damaged word line WL_d determined based on actual data statistics is incorrect, or if the damaged word line WL_d needs to be replaced, the first storage circuit 121 may update the address information of the damaged word line WL_d stored in the first storage circuit 121 in response to the refresh signal Ref. This expands the applicable scenarios for the first storage circuit 121.

[0203] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.< / n>

Claims

1. A memory device, characterized in that, include: A storage cell array, comprising multiple storage units; Peripheral circuitry, coupled to the plurality of memory cells; The peripheral circuit includes: The first storage circuit is configured to store address information of damaged word lines among the word lines coupled to the plurality of storage banks; A plurality of second storage circuits are coupled to the first storage circuit, and one of the plurality of second storage circuits is configured to couple to a redundant word line corresponding to the damaged word line in response to a first control signal; wherein the data transmission paths between the plurality of second storage circuits and the first storage circuit are all shorter than the data transmission paths between the plurality of second storage circuits and the plurality of memory banks.

2. The memory device according to claim 1, characterized in that, The peripheral circuit also includes a first multiplexer circuit, wherein multiple input terminals of the first multiplexer circuit are respectively coupled to multiple second storage circuits, and the output terminal of the first multiplexer circuit is coupled to the storage body. The first multiplexing circuit is configured to couple the redundant word line corresponding to the damaged word line to the target memory in response to a second control signal, and transmit the data in the second memory circuit to the target memory. The memory bank coupled to the damaged word line is different from the target memory bank coupled to the redundant word line corresponding to the damaged word line.

3. The memory device according to claim 2, characterized in that, The plurality of second storage circuits are configured to be coupled to at least one of the redundant word lines or at least one of the word lines in response to the plurality of the first control signals.

4. The memory device according to claim 1, characterized in that, The second storage circuit includes a content-addressable storage unit.

5. The memory device according to claim 4, characterized in that, The content-addressable storage unit includes a second storage element and a comparison circuit; The second storage element is configured to store the identification information and address information of the damaged word line obtained from the first storage circuit, and the identification information of the redundant word line corresponding to a damaged word line, and the address information of the redundant word line; The comparison circuit is configured to compare user data with the address information of the corrupted word line stored in the second storage element, wherein the user data and the address information of the corrupted word line are the same, and the redundant word line corresponding to the corrupted word line is coupled.

6. The memory device according to claim 5, characterized in that, The second storage element also stores the address information of the storage bank coupled to the damaged word line, and the address information of the storage bank coupled to the redundant word line corresponding to one damaged word line; The address information of the memory bank coupled to the damaged word line is different from the address information of the memory bank coupled to the redundant word line.

7. The memory device according to claim 1, characterized in that, The first storage circuit includes a one-time programmable storage unit; The one-time programmable memory unit includes a first memory element and at least one transistor; the first memory element stores the address information of the damaged word line.

8. The memory device according to claim 1, characterized in that, The word line is coupled to the second storage circuit; The redundant word line is coupled to the memory bank and the second memory circuit; One of the redundant word lines corresponds to one of the damaged word lines among the word lines; Multiple redundant word lines are arranged adjacent to each other and coupled to one of the memory banks on one side of the memory bank.

9. The memory device according to claim 1, characterized in that, The peripheral circuit also includes: A buffer circuit, coupled to the plurality of second storage circuits, the first storage circuit, and the data transmission interface, is configured to transmit user data transmitted through the data transmission interface to the second storage circuit in response to a third control signal; and is further configured to transfer data in the first storage circuit to the plurality of second storage circuits in response to a fourth control signal.

10. The memory device according to claim 9, characterized in that, The buffer circuit includes a buffer and a second multiplexer circuit coupled to the buffer; The first input terminal of the second multiplexing circuit is coupled to the data transmission interface, the second input terminal of the second multiplexing circuit is coupled to the first storage circuit, and the output terminal of the second multiplexing circuit is coupled to the plurality of second storage circuits through the buffer.

11. The memory device according to claim 1, characterized in that, The peripheral circuit also includes: An input / output circuit, coupled to the data transmission interface, is configured to receive user data and output it to the data transmission interface.

12. A memory system, characterized in that, include: Memory devices; The memory device includes a first memory circuit and a second memory circuit; A memory controller, coupled to the memory device, is configured to transfer the address information of the damaged word line stored in the first memory circuit to the second memory circuit; It is configured to transmit user data to the second storage circuit; and is also configured to output a first control signal, instructing the second storage circuit to couple a redundant word line corresponding to the damaged word line if the user data is found to be the same as the address information of the damaged word line.

13. The memory system according to claim 12, characterized in that, The memory device further includes a first multiplexing circuit; The memory controller is also configured to output a second control signal, instructing the first multiplexing circuit to transmit data in the second memory circuit to a target memory coupled to the redundant word line; The memory bank coupled to the damaged word line is different from the target memory bank coupled to the redundant word line corresponding to the damaged word line.

14. A method for driving a memory device, characterized in that, include: In response to the power-on reset signal, the address information of the damaged word line in the word line coupled to multiple memory banks stored in the first storage circuit is transferred to the second storage circuit; In response to the first control signal, the user data and the data stored in the second storage circuit are compared to determine the redundant word line corresponding to the damaged word line and couple it. The data transmission path between the second storage circuit and the first storage circuit is shorter than the path from the second storage circuit to the storage bank via the coupled redundant word line.

15. The method according to claim 14, characterized in that, The step of determining and coupling the redundant word line corresponding to the damaged word line includes: Based on the address information and identification information of the damaged word line, determine the identification information and address information of the redundant word line corresponding to the damaged word line, and determine the target redundant word line; The target memory bank is determined based on the address information of the memory bank coupled to the target redundant word line; wherein the memory bank coupled to the damaged word line is different from the target memory bank; The second storage circuit is coupled to the target storage bank via the target redundant word line.

16. The method according to claim 14, characterized in that, The step of determining and coupling the redundant word line corresponding to the damaged word line includes: Based on the address information and identification information of the damaged word line, determine the identification information and address information of the redundant word line corresponding to the damaged word line, as well as the address information of the memory cell coupled to the redundant word line, and determine the target redundant word line; The second storage circuit is coupled to the target storage bank via the target redundant word line.

17. The method according to claim 14, characterized in that, The method further includes: In response to a second control signal, the target redundant word line is coupled to the target memory bank, and the data in the second memory circuit is transmitted to the target memory bank; The memory bank coupled to the damaged word line is different from the target memory bank coupled to the target redundant word line.

18. The method according to claim 14, characterized in that, The step of transmitting data from the second storage circuit to the target storage includes: After decoding the data transmitted via the redundant word line, it is transmitted to the target storage.

19. The method according to claim 14, characterized in that, The method further includes: In response to a third control signal, the user data is transmitted to the second storage circuit; In response to a fourth control signal, the data in the first storage circuit is transferred to the plurality of second storage circuits.

20. The method according to claim 14, characterized in that, The method further includes: The address information of the damaged word line stored in the first storage circuit is updated in response to the refresh signal.

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