A fast write circuit and method for ferroelectric capacitor memory cells FeRAM

Abstract

A kind of fast write circuit and method for ferroelectric capacitor storage unit FeRAM, including plate line clamping unit, bit line driving circuit and negative pressure generation unit;The plate line clamping unit is used to clamp the plate line end of ferroelectric capacitor at constant common-mode voltage;The bit line driving circuit is connected with bit line and plate line respectively, for controlling bit line potential according to write data;The negative pressure generation unit is connected with bit line driving circuit, for generating transient negative voltage when writing logic "0";The present application realizes single-cycle parallel write using constant plate line architecture, greatly improves write speed and reduces power consumption;At the same time, by transient negative pressure, the write voltage swing is widened, the write margin problem under low-voltage process is solved, and high-voltage isolation circuit is not needed, easy to integrate.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor memory technology, and specifically relates to a fast write circuit and method for ferroelectric capacitor memory cells (FeRAM). Background Technology

[0002] FeRAM utilizes the hysteresis loop characteristic of ferroelectric capacitors to store information. Standard memory cells mainly include two types: 1T1C and 2T2C. 1T1C offers high density and is suitable for large-capacity storage, while 2T2C offers high reliability and is suitable for high-stability scenarios. The core mechanism for writing data is to apply an electric field exceeding the coercive voltage Vc to the ferroelectric capacitor to forcibly reverse the polarization direction of the domains.

[0003] On the one hand, existing FeRAM architectures generally employ pulsed board-line driving, where the board line can only switch between the power supply voltage VDD and ground VSS. Since ferroelectric polarization switching depends on the relative voltage difference across a capacitor, a single-potential board line cannot simultaneously meet the bidirectional writing requirements of different data ("0" and "1") in the array. The controller is forced to adopt a time-division multiplexing strategy, i.e., first pulling the board line high to write logic "0", then pulling it low to write logic "1" (or vice versa). This two-step serial writing mechanism doubles the write cycle, resulting in limited data throughput. On the other hand, the board line connects to the entire row of memory cells and has extremely high parasitic capacitance. In traditional solutions, each write operation requires charging and discharging the board line across the entire power supply swing (0V to VDD), which not only generates huge dynamic power consumption but also causes significant power supply bounce noise, affecting circuit stability.

[0004] To overcome the slow speed and high power consumption caused by step-by-step serial writing in traditional pulsed board-line (PBL) schemes, a constant board-line architecture has emerged in existing technologies. In this architecture, the board line (PL) of the memory cell no longer undergoes voltage switching but is fixedly connected to 1 / 2 VDD. When writing a "1", the bit line voltage is driven to VDD; when writing a "0", the bit line voltage is driven to VSS. However, this architecture has the following drawbacks: First, insufficient write margin: Because the board line is fixed at 1 / 2 VDD, the effective write voltage available across the ferroelectric capacitor is only half of the power supply voltage. In modern low-power processes, the power supply voltage is already low, and the halved voltage often approaches or even falls below the coercivity voltage of the ferroelectric material. This leads to incomplete domain polarization reversal, making data writing very fragile. Second, poor data retention: Due to the weak write field strength, the ferroelectric domains are in a "soft write" state, making them highly susceptible to external interference or depolarization over time, resulting in data loss or insufficient induced charge during reading, leading to "read errors". US Patent Publication No. 20020126522A1 discloses a non-volatile memory and control method aimed at improving reliability under low power supply voltage. To overcome the problem of insufficient write margin under low voltage, a dedicated negative voltage generation circuit is introduced into its board line drive circuit. During write operations, the board line (PL) is driven to a negative voltage below ground potential, thereby increasing the voltage difference across the ferroelectric capacitor. The technical solution has the following drawbacks: First, during operation, the PL, which connects to the entire row of memory cells and has a large parasitic capacitance, must be repeatedly switched between positive voltage, ground potential, and negative voltage to charge and discharge the capacitive load. This not only increases dynamic power consumption but also causes power / ground bounce noise. Second, this solution still relies on voltage switching of the board line; during operation, it must wait for the level transition of the large capacitor board line, failing to solve the speed bottleneck caused by serial writing.

[0005] Patent CN101777377A discloses a bit-line-board-line merging structure for ferroelectric memory arrays. This scheme combines the functions of bit lines and board lines, utilizing the voltage signals of bit lines and complementary bit lines to complete the write operation, thus eliminating the need for dedicated pulse board line operations and improving write speed. However, this scheme has drawbacks: its bit line driving is entirely limited to the standard positive power supply voltage (VDD) and ground potential (VSS), failing to overcome the limitations of the power rails. Furthermore, with the trend of continuously decreasing power supply voltages in modern advanced processes, this scheme cannot solve the problems of incomplete polarization switching and poor data retention caused by the decreasing absolute voltage difference. Summary of the Invention

[0006] To overcome the problems existing in the prior art, the present invention aims to propose a fast write circuit and method for ferroelectric capacitor memory cells (FeRAM). By clamping the board line to a constant common-mode voltage and cooperating with the bidirectional driving mechanism of positive high voltage and negative transient voltage of bit line BL, the writing of logic "1" and logic "0" can be completed simultaneously in a single write operation phase. The voltage swing of reverse write is artificially increased, significantly improving the write margin and ensuring that saturation polarization of ferroelectric capacitors can be achieved even under low-voltage processes, thus balancing high-speed parallel writing and high-reliability data storage.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows: A fast write circuit for ferroelectric capacitor memory cells (FeRAM) includes a memory array, a board line clamping circuit, and a bit line driving circuit. The memory array includes at least one memory cell, which includes an access transistor and a ferroelectric capacitor. The gate of the transistor is connected to a word line to control gating, and the drain is connected to a bit line. One end of the plate of the ferroelectric capacitor is connected to a plate line, and the other end of the plate is connected to the source of the transistor. The board line clamping circuit is used to maintain the board line at a constant common-mode voltage; The bit line driving circuit includes a negative voltage generation unit and a push-pull driving unit; the negative voltage generation unit is used to generate a transient negative voltage below ground potential during the write pulse; the push-pull driving unit is used to bidirectionally drive the bit line according to the logic level of the written data: when writing first logic level data, the bit line is driven to the first level; when writing second logic level data, the bit line is driven to a transient negative voltage below ground potential.

[0008] The storage unit adopts a 1T1C structure or a 2T2C structure; When it is a 1T1C structure, each bit line performs level driving independently; In the 2T2C structure, complementary bit lines are simultaneously written with opposite data. One bit line is driven to the power supply voltage to write logic "1", and the other complementary bit line is driven to the transient negative voltage to write logic "0".

[0009] During the write phase, the board line PL remains at a constant common-mode voltage without the need for traditional pulse switching. After the word line WL is enabled, the bit line drive circuit synchronously performs opposite polarity drive actions on BL and BLB within a single timing sequence. To overcome the issues of insufficient differential voltage and unreliable writing that may occur when writing "0" using only ground potential (0V) in constant board line mode, a transient negative voltage mechanism is introduced and parallel driving is implemented. Specifically, when writing logic "1", the bit line driver synchronously performs bidirectional driving actions within a single timing phase, that is, rapidly pulling the data bit line BL to VDD to establish a positive polarization differential, while simultaneously driving the reference bit line BLB to a negative voltage - To establish a reverse polarization voltage difference, complementary data writing of BL (block BL) storing "1" and BLB (block BL) storing "0" is completed in a single operation; when writing logic "0", the bit line drive circuit synchronously executes bidirectional complementary drive actions, with the drive logic being the opposite of that when writing logic "1": the data bit line BL is pulled down to a transient negative voltage - The complementary bit line BLB is pulled up to the power supply voltage VDD, thereby establishing a polarization electric field with the opposite direction and equivalent amplitude to the writing "1" across the ferroelectric capacitor.

[0010] The bit line driving circuit includes a negative voltage generating unit and a push-pull driving unit; The negative voltage generation unit is used to generate the transient negative voltage during the write pulse through capacitive coupling effect, and to restore the virtual ground node in the negative voltage generation unit to ground potential when not writing. The push-pull drive unit includes a pull-up transistor and a pull-down transistor. The source of the pull-up transistor is connected to a power supply, and the source of the pull-down transistor is connected to the output terminal of the negative voltage generation unit. The gates of the pull-up transistor and the pull-down transistor respectively receive a write control signal, which is generated by the write data latch result.

[0011] The negative pressure generating unit is a capacitor bootstrap negative pressure generating circuit based on timing delay control, including a pre-charge switching transistor, a bootstrap capacitor, and a delay drive unit. The control terminal of the precharge switch is connected to the precharge control signal, the source is connected to the virtual ground node, and the drain is grounded. The input terminal of the delay drive unit is connected to the precharge control signal, and the output terminal is connected to the first terminal of the bootstrap capacitor. The second terminal of the bootstrap capacitor is connected to the virtual ground node. The precharge control signal is delayed by the delay drive unit to generate a delay signal, which drives the first terminal of the bootstrap capacitor to pull the virtual ground node to a negative voltage after the precharge switch is turned off.

[0012] During the precharge phase, the precharge control signal is inactive, the precharge switch is turned on, and the virtual ground node is precharged to ground potential. Simultaneously, the bootstrap capacitor is precharged to establish an initial voltage difference. When the write operation begins, the precharge control signal flips, first quickly turning off the precharge switch to cut off the NVSS's path to ground, causing it to immediately enter a floating state. Subsequently, this flip signal undergoes delayed processing by the delay drive unit before reaching the drive terminal of the bootstrap capacitor, causing its potential to jump. This timing design ensures that the NVSS is completely isolated from ground when the capacitor operates, thereby using capacitive coupling to forcibly pull the floating NVSS node below ground potential without loss.

[0013] The common-mode voltage is V CM ; When writing logic "1", the bit line voltage is VDD, and the voltage difference across the ferroelectric capacitor is VDD-V. CM When writing logic "0", the bit line voltage is -V. NEG The voltage difference across the ferroelectric capacitor is V. CM +V NEG V NEG It represents the absolute value of the transient negative voltage.

[0014] A memory chip, including the fast write circuit described above, as well as an address decoder, a sensitive amplifier, and an input / output interface.

[0015] An electronic device, comprising the memory chip and a central processing unit communicatively connected to the memory chip.

[0016] A fast write method for ferroelectric capacitor memory cells, applied to the aforementioned fast write circuit, the method comprising the following steps: Receive external write data signals; The data latch unit samples and latches the level state of the written data signal; If the latch result is high, the corresponding first control signal is generated to control the pull-up transistor to turn on and pull the bit line voltage up to the power supply voltage. If the latch result is low, a corresponding second control signal is generated to control the negative voltage generation unit to start, and the bit line voltage is driven to transient negative voltage through the pull-down transistor; The write operations of logic "1" and logic "0" are completed in parallel within a single time sequence, without the need for time-division multiplexing.

[0017] The negative pressure generation unit specifically includes: First, turn off the precharge switch to disconnect the virtual ground node from the ground; After a preset delay, the pump signal level is changed, and the floating virtual ground node is forcibly pulled down to a transient negative voltage by utilizing the coupling effect of the bootstrap capacitor, thereby driving the pull-down transistor to pull the bit line low.

[0018] Compared with the prior art, the present invention has the following advantages: 1. Significantly improved write speed In traditional FeRAM architectures, board lines (PLs) must pulse-switch between VDD and VSS. Since the polarization switching of ferroelectric capacitors depends on voltage differences, a single-potential board line cannot simultaneously satisfy the write requirements of logic "0" and logic "1". Therefore, the controller is forced to adopt a time-division multiplexing strategy of "write 0 first, then write 1" (or vice versa). This serial mechanism doubles the write cycle time and limits throughput.

[0019] This invention features a parallel write mechanism: the board line (PL) is clamped at a constant common-mode voltage, eliminating potential switching. During the write operation, the bit line drive circuit utilizes complementary drive logic to simultaneously pull one bit line up to VDD (write "1") and pull another complementary bit line down to a transient negative voltage (write "0"). This mechanism physically eliminates the time interval between writing "0" and writing "1" in traditional schemes, achieving single-cycle parallel writing and theoretically doubling the write rate, greatly satisfying the high-speed memory access requirements of high-performance computing. Compared to the prior art US20020126522A1, this invention employs a constant board line architecture, keeping the board line potential fixed at all times, eliminating the need for charging and discharging large capacitor board lines, thus offering advantages in dynamic power consumption; furthermore, the constant board line architecture combined with bidirectional push-pull bit line drive enables single-cycle parallel writing.

[0020] 2. Significantly enhanced write reliability and margin While existing constant line-of-sight solutions offer high speed, they typically fix the line-of-sight at 1 / 2 VDD. This means that when writing logic "0", the voltage difference across the capacitor is only 1 / 2 VDD. In modern low-voltage processes (e.g., VDD < 1.2V), this voltage often approaches or even falls below the coercivity voltage (Vc) of ferroelectric materials, resulting in incomplete polarization switching, poor data retention, and a high susceptibility to read errors.

[0021] This invention introduces a transient negative voltage: when writing logic "0", the bit line is not driven to ground potential (0V), but is driven to below ground potential (-V) through a capacitor bootstrap circuit. NEG The voltage swing multiplication design artificially and significantly widens the voltage swing for reverse writing. For example, when PL = 1 / 2 VDD, the bit line BL = -V. NEG At that time, the voltage difference across the ferroelectric capacitor becomes 1 / 2 VDD + V NEGTherefore, even at extremely low supply voltages, this invention ensures the generation of a strong write electric field sufficient to overcome coercive voltage, achieving saturation polarization of ferroelectric capacitors. This not only solves the inherent defects of existing constant board-line architectures at low voltages but also significantly improves data retention and interference immunity.

[0022] 3. Reduced power consumption and noise suppression In traditional solutions, the board line (PL) connects the entire row of memory cells and has extremely high parasitic capacitance. Each write operation requires charging and discharging the board line with its full power swing (0V to VDD), which not only consumes a huge amount of dynamic power but also causes severe power supply bounce noise due to high current switching, affecting the stability of the sensitive amplifier.

[0023] In this invention, the board line remains at a constant potential, eliminating the need for charge / discharge switching. Only the bit line (BL) experiences voltage fluctuations, and the capacitive load of the bit line is typically much smaller than that of the board line. This invention eliminates the charging and discharging power consumption of the large capacitance of the board line, significantly reducing the dynamic power consumption of write operations. Simultaneously, since there is no large current instantaneously flowing into the ground line, power supply bounce noise is effectively suppressed, improving the stability of the circuit operation.

[0024] 4. High circuit integration and no need for high-voltage processes. Directly introducing a continuous external negative high-voltage power supply to solve the voltage margin problem not only requires an additional off-chip negative voltage source but also introduces a serious risk of charge leakage. To prevent transistor breakdown, high-voltage devices with thick gate oxide layers and complex level conversion interfaces must be used, which significantly increases the layout area and process cost.

[0025] This invention utilizes the principle of capacitive bootstrapping to generate a negative voltage at the moment of writing, rather than continuously supplying it. The timing protection design of this invention, through the cooperation of a pre-charged switching transistor and a delay drive unit, ensures the reliability of the negative voltage generation process. This negative voltage exists only during the write pulse, and the node automatically returns to a safe potential when not writing. This allows the circuit to be compatible with standard low-voltage CMOS processes without the need for additional high-voltage isolation circuits or complex level shifters, minimizing the complexity of peripheral circuits and chip area overhead while ensuring high performance. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the FeRAM memory cell structure; Figure 2 Schematic diagram of board wire clamping circuit Figure 3 Write the timing diagram in parallel; Figure 4 This is a schematic diagram of a capacitor bootstrap negative voltage generation circuit. Figure 5This is a schematic diagram of a bit-line complementary drive and voltage selection circuit. Detailed Implementation

[0027] The embodiments and effects of the present invention will be further described in detail below with reference to the accompanying drawings.

[0028] A fast write scheme for FeRAM (FeMetal RAM) memory cells. The core of this scheme is to break the limitation of traditional board line PL (Power Line Point) requiring pulse switching. By clamping the board line to a constant common-mode voltage and cooperating with the bidirectional driving mechanism of positive high voltage and negative transient voltage of bit line BL (Power Line BL), the writing of logic "1" and logic "0" can be completed simultaneously in a single write operation phase.

[0029] 1. Basic Unit Structure of Memory Array The fast write scheme based on negative voltage bit lines proposed in this invention has universal architectural adaptability and can be applied to 1T1C high-density cells or 2T2C high-reliability cells. For example... Figure 1 The diagram shows the structural schematics of two types of memory cells. Regardless of the structure, the core of the memory cell consists of access transistors and ferroelectric capacitors. The gate of the transistor is connected to the word line WL to control selection, the plate terminals of the ferroelectric capacitor are uniformly connected to a constant common-mode voltage, and the drain of the transistor is connected to the bit line. Specifically, for the 1T1C structure, data is written to only a single bit line BL during writing; for the 2T2C structure, complementary bit lines BL and BLB are used to simultaneously write opposite data.

[0030] 2. Board wire clamping circuit In one embodiment, such as Figure 2 As shown, the board line clamping circuit includes a common-mode voltage input terminal V. CM The system includes a buffer, a clamping switch, and a decoupling capacitor. The input terminal of the buffer is connected to the common-mode voltage V. CM The output terminal is connected to the board line PL via a clamping switch. The control terminal of the clamping switch receives the board line clamping enable signal PL_EN. When PL_EN is valid, the clamping switch is turned on, and the board line PL is clamped to the common-mode voltage V. CM When PL_EN is invalid, the board line PL can be in a high-impedance state. A decoupling capacitor is connected between the board line PL and VSS or the common-mode reference node to suppress board line voltage disturbances. Therefore, the input to the board line clamping circuit includes the common-mode voltage VSS. CM And the board line clamping enable signal PL_EN, the output is the board line voltage V. PL During the write phase, V PL ≈V CM The bit line BL is driven to VDD or a transient negative voltage -V based on the written data. NEG This creates the required writing voltage difference across the ferroelectric capacitor.

[0031] 3. Parallel write timing like Figure 3 The parallel write timing diagram clearly illustrates the complete workflow of this mechanism in a 2T2C architecture: During the write phase, the board line PL remains at a constant common-mode voltage without the need for traditional pulse switching. After the word line WL is enabled, the bit line drive circuit synchronously performs opposite polarity drive actions on BL and BLB within a single timing sequence. To overcome the potential issues of insufficient differential voltage and unreliable writing caused by using only ground potential (0V) to write "0" in constant board line mode, this invention introduces a transient negative voltage mechanism and implements parallel drive.

[0032] Specifically, when writing a logic "1", the bit line driver synchronously performs bidirectional drive actions within a single timing phase, that is, rapidly pulling the data bit line BL to VDD to establish a positive polarization voltage difference, while simultaneously driving the reference bit line BLB to a negative voltage. To establish a reverse polarization voltage difference, complementary data writing of BL (blocking logic) storing "1" and BLB (blocking logic) storing "0" is completed in a single operation; when writing logic "0", the driving logic is reversed but also executed concurrently, i.e., BL drives to - The BLB driver is driven to the VDD. This mechanism not only utilizes... This significantly improves the write margin under low-voltage processes, ensuring a precise differential reference for the sensitive amplifier during subsequent reads. More importantly, it eliminates the redundant steps of traditional solutions that require time-division multiplexing of "writing 1" and "writing 0," achieving instantaneous parallel writing of positive and negative polarity data. This doubles the theoretical write speed while maintaining high reliability. Since the 2T2C structure is essentially composed of two complementary 1T1C units, this write mechanism is universal; the 1T1C structure only requires unilateral execution of the corresponding level drive.

[0033] 4. Negative voltage generation circuit based on capacitor bootstrapping like Figure 4As shown, in order to generate a stable transient negative voltage while avoiding charge leakage caused by timing races, this invention designs a capacitor bootstrap negative voltage generation circuit based on timing delay control. This circuit mainly consists of an input buffer stage, a pre-charge switch, a delay drive unit, and a bootstrap capacitor C_Boost. Its core working logic lies in using the delay unit to construct a timing protection mechanism. During the pre-charge stage, the control signal Pump_En is inactive, the pre-charge switch is turned on, pre-charging the virtual ground node NVSS to ground potential VSS, and simultaneously the bootstrap capacitor is pre-charged to establish an initial voltage difference. When the write operation begins, the Pump_En signal flips, first quickly turning off the pre-charge switch, cutting off the path of NVSS to ground and causing it to immediately enter a floating state. Subsequently, this flip signal is processed by the delay drive unit before reaching the drive terminal of the bootstrap capacitor and causing its potential to jump. This timing design ensures that NVSS is completely isolated from ground when the capacitor operates, thereby using the capacitive coupling effect to forcibly pull the floating NVSS node below ground potential without loss.

[0034] Because this negative voltage is generated transiently through capacitive coupling only during the write pulse, rather than being continuously supplied by an external power source, the node automatically returns to a safe potential when the circuit is in a non-write state. This mechanism naturally avoids the need for high-voltage isolation circuits and complex level conversion interfaces that would otherwise require a continuous negative high-voltage power supply, significantly simplifying peripheral circuit design and reducing layout area overhead.

[0035] 5. Bit line drive logic and selection circuit like Figure 5 As shown, this invention designs a universal bit line driving circuit that supports negative voltage output. The circuit mainly consists of two symmetrical push-pull driving units, each including a pull-up PMOS transistor and a pull-down NMOS transistor. The pull-up PMOS transistor is connected between the positive power supply VDD and the corresponding bit line, and the pull-down NMOS transistor is connected between the corresponding bit line and the negative voltage node NVSS. The input of each push-pull driving unit includes a write data signal Write_Data or its inverted signal and the negative voltage node NVSS, and the output is the corresponding bit line voltage. Specifically, the write data signal Write_Data directly controls the left push-pull driving unit to drive bit line BL, and after being inverted, controls the right push-pull driving unit to drive the complementary bit line BLB, thus keeping the driving logic of the two bit lines complementary. During the write operation, depending on the level state of Write_Data, the pull-up PMOS transistor of one push-pull driving unit is turned on, pulling the corresponding bit line up to the power supply voltage VDD; the pull-down NMOS transistor of the other push-pull driving unit is turned on, pulling the corresponding complementary bit line down to the transient negative voltage -V generated by the capacitor bootstrap circuit. NEG The above structure can operate independently as a single circuit to adapt to a 1T1C architecture, or it can be used as... Figure 5 The diagram illustrates a complementary drive structure to adapt to the 2T2C architecture. Thus, under a constant bias of board line PL, bit line BL and the complementary bit line BLB can be driven to VDD and -V respectively within the same write timing. NEG This establishes writing electric fields in opposite directions, enabling the parallel writing of complementary data.

[0036] In one embodiment, the transistors described in this invention can be implemented using MOS transistors in CMOS technology, including NMOS transistors, PMOS transistors, or a transmission gate structure composed of NMOS transistors and PMOS transistors. The pull-up transistor can be a PMOS transistor, while the pull-down transistor, precharge switch, clamping switch, and access transistor can be implemented using NMOS transistors or PMOS transistors depending on the specific circuit connection. For transistors connected to the transient negative voltage node NVSS, methods such as body-source connection, isolation trap devices, voltage-enhanced devices, or limiting the negative voltage amplitude can be used to suppress parasitic PN junction forward conduction and improve reliability during negative voltage driving, depending on the negative voltage amplitude and process conditions. The ferroelectric capacitors described in this invention are preferably hafnium-based ferroelectric capacitors, and their ferroelectric materials can be HfO2-based ferroelectric materials, HfZrO2 ferroelectric materials, or other doped hafnium oxide ferroelectric materials. The ferroelectric capacitors have ferroelectric polarization hysteresis characteristics and can form different polarization states under the action of an external write electric field for storing logic data. The ferroelectric capacitor can be used as a single-ended storage capacitor in a 1T1C storage unit, or as a complementary storage capacitor in a 2T2C storage unit.

[0037] To verify the technical effectiveness of this invention, circuit simulation was performed using the SMIC 180 nm process library. The simulation was set with a power supply voltage VDD = 1.8V and a board-level common-mode voltage clamp at V... CM =0.4V. In a traditional constant board-line architecture, the board-line voltage is VDD / 2 = 0.9V. When writing data, the voltage difference across the capacitor is only 0.9V, lower than the typical coercive voltage of ferroelectric materials, leading to incomplete polarization reversal. With the circuit of this invention, the negative voltage generation unit generates a transient negative voltage within 1ns through bootstrap capacitor coupling. The bit line is driven to -V. NEG = The 1V voltage increases the effective write voltage difference across the ferroelectric capacitor to 1.4V, achieving saturation polarization and reducing the risk of write failure under low voltage conditions.

Claims

1. A fast write circuit for ferroelectric capacitor memory cells (FeRAM), characterized in that, This includes the memory array, board line clamping circuit, and bit line driving circuit; The memory array includes at least one memory cell, which includes at least one access transistor and a ferroelectric capacitor. The gate of the transistor is connected to a word line to control gating, and the drain is connected to a bit line. One end of the plate of the ferroelectric capacitor is connected to a plate line, and the other end of the plate is connected to the source of the transistor. The board line clamping circuit is used to maintain the board line at a constant common-mode voltage; The bit line driving circuit includes a negative voltage generation unit and a push-pull driving unit; the negative voltage generation unit is used to generate a transient negative voltage below ground potential during the write pulse; the push-pull driving unit is used to bidirectionally drive the bit line according to the logic level of the written data: when writing first logic level data, the bit line is driven to the first level; When writing data at the second logic level, the bit line is driven to a transient negative voltage below ground potential.

2. The fast write circuit according to claim 1, characterized in that, The storage unit adopts a 1T1C structure or a 2T2C structure; When it is a 1T1C structure, each bit line performs level driving independently; When it is a 2T2C structure, the complementary pair of bit lines simultaneously write opposite data, one bit line is driven to the power supply voltage to write logic "1", and the other complementary bit line is driven to the transient negative voltage to write logic "0". When it is a 2T2C structure, during the write phase, the board line PL is always kept at a constant common-mode voltage. After the word line WL is turned on, the bit line drive circuit synchronously performs opposite polarity drive actions on BL and BLB within a single timing sequence.

3. The fast write circuit according to claim 2, characterized in that, During the writing phase, a transient negative pressure mechanism is introduced and parallel driving is implemented, as follows: When writing a logic "1", the bit line driver synchronously performs bidirectional drive actions within a single timing phase, that is, pulling the data bit line BL to VDD to establish a positive polarization voltage difference, while simultaneously driving the reference bit line BLB to a negative voltage. To establish a reverse polarization pressure difference, thus completing the complementary data writing of BL storing "1" and BLB storing "0" in one operation; When writing logic "0", the bit line driving circuit synchronously executes bidirectional complementary driving actions, and the driving logic is the opposite of that when writing logic "1": the data bit line BL is pulled down to the transient negative voltage -V. NEG The complementary bit line BLB is pulled up to the power supply voltage VDD, thereby establishing a polarization electric field with the opposite direction and equivalent amplitude to the writing "1" across the ferroelectric capacitor.

4. The fast write circuit according to claim 1, characterized in that, The bit line driving circuit includes a negative voltage generating unit and a push-pull driving unit; The negative voltage generation unit is used to generate the transient negative voltage during the write pulse through capacitive coupling effect, and to restore the virtual ground node in the negative voltage generation unit to ground potential when not writing. The push-pull drive unit includes a pull-up transistor and a pull-down transistor. The source of the pull-up transistor is connected to a power supply, and the source of the pull-down transistor is connected to the output terminal of the negative voltage generation unit. The gates of the pull-up transistor and the pull-down transistor respectively receive a write control signal, which is generated by the write data latch result.

5. The fast write circuit according to claim 4, characterized in that, The negative pressure generating unit is a capacitor bootstrap negative pressure generating circuit based on timing delay control, including a pre-charge switching transistor, a bootstrap capacitor, and a delay drive unit. The control terminal of the precharge switch is connected to the precharge control signal, the source is connected to the virtual ground node, and the drain is grounded. The input terminal of the delay drive unit is connected to the precharge control signal, the output terminal is connected to the first terminal of the bootstrap capacitor, and the second terminal of the bootstrap capacitor is connected to the virtual ground node; wherein, the precharge control signal is delayed by the delay drive unit to generate a delay signal, and the delay signal drives the bootstrap capacitor to pull the virtual ground node to a negative voltage after the precharge switch is turned off.

6. The fast write circuit according to claim 3, characterized in that, During the precharge phase, the precharge control signal is inactive, the precharge switch is turned on, and the virtual ground node is precharged to ground potential. At the same time, the bootstrap capacitor is precharged to establish the initial voltage difference. When the write operation begins, the precharge control signal flips, and the precharge switch is quickly turned off first, cutting off the path of NVSS to ground so that it immediately enters the floating state. Subsequently, the flip signal is processed by the delay drive unit and reaches the drive terminal of the bootstrap capacitor, causing its potential to jump.

7. The fast write circuit according to claim 1, characterized in that, The common-mode voltage is V CM When writing logic "1", the bit line voltage is VDD, and the voltage difference across the ferroelectric capacitor is VDD-V. CM When writing logic "0", the bit line voltage is -V. NEG The voltage difference across the ferroelectric capacitor is V. CM +V NEG V NEG It represents the absolute value of the transient negative voltage.

8. A memory chip, characterized in that, It includes the fast write circuit as described in any one of claims 1 to 7, as well as an address decoder, a sensitive amplifier, and an input / output interface.

9. An electronic device, characterized in that, It includes the memory chip of claim 8, and a central processing unit that is communicatively connected to the memory chip.

10. A fast writing method for ferroelectric capacitor memory cells, characterized in that, Applied to the fast write circuit as described in any one of claims 1-7, the method includes the following steps: Receive external write data signals; The data latch unit samples and latches the level state of the written data signal; If the latch result is high, the corresponding first control signal is generated to control the pull-up transistor to turn on and pull the bit line voltage up to the power supply voltage. If the latch result is low, a corresponding second control signal is generated to control the negative voltage generation unit to start, and the bit line voltage is driven to transient negative voltage through the pull-down transistor; The write operations of logic "1" and logic "0" are completed in parallel within a single time sequence, without the need for time-division multiplexing; First, turn off the precharge switch to disconnect the virtual ground node from the ground; After a preset delay, the pump signal level is changed, and the floating virtual ground node is forcibly pulled down to a transient negative voltage by utilizing the coupling effect of the bootstrap capacitor, thereby driving the pull-down transistor to pull the bit line low.

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