Memory device, memory control method and storage system

Abstract

The present disclosure provides a memory device, a memory control method and a memory system. The memory device comprises: a memory cell array; a peripheral circuit connected with corresponding memory cell rows through word lines, comprising a first power supply circuit and a second power supply circuit, the first power supply circuit is used for outputting a first negative voltage to one end of a first transistor, the second power supply circuit is used for outputting a second negative voltage to one end of a second transistor, the first transistor is a transistor in a first word line driving circuit coupled with a first unselected word line, and the second transistor is a transistor in a second word line driving circuit coupled with a second unselected word line; the absolute value of the first negative voltage is smaller than the absolute value of the second negative voltage; the first power supply circuit comprises a first negative voltage pull-up module, and the first negative voltage pull-up module is used for pulling up the first negative voltage when the first negative voltage is lower than a first reference voltage. The embodiments of the present disclosure can improve the reliability and operation efficiency of the memory.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and more specifically, to a memory device, a memory control method, a storage system, and a computer system. Background Technology

[0002] Memory devices are widely used in various electronic devices such as computers, wireless communication devices, cameras, and digital displays to store relevant data, especially dynamic random access memory (DRAM). To improve circuit reliability, related technologies incorporate one or more negative voltages in DRAM memory.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a memory device, a memory control method, a storage system, and a computer system.

[0005] According to a first aspect of the present disclosure, a memory device is provided, comprising: a memory cell array including a plurality of memory cell rows and a word line coupled to each memory cell row; peripheral circuitry connected to the corresponding memory cell row via the word line, including a first power supply circuit and a second power supply circuit, the first power supply circuit being configured to output a first negative voltage to one end of a first transistor, the second power supply circuit being configured to output a second negative voltage to one end of a second transistor, the first transistor being a transistor in a first word line driving circuit coupled to a first unselected word line, and the second transistor being a transistor in a second word line driving circuit coupled to a second unselected word line; the absolute value of the first negative voltage being less than the absolute value of the second negative voltage; the first power supply circuit including a first negative voltage pull-up module, the first negative voltage pull-up module being configured to pull up the first negative voltage when the first negative voltage is lower than a first reference voltage.

[0006] According to a second aspect of the present disclosure, a memory control method is provided, applied to a memory device, the memory device including a memory cell array and peripheral circuitry, the memory cell array including a plurality of memory cell rows and word lines coupled to each memory cell row; the peripheral circuitry is connected to the corresponding memory cell row through the word lines, including a first power supply circuit and a second power supply circuit, the first power supply circuit being used to output a first negative voltage to one end of a first transistor, the second power supply circuit being used to output a second negative voltage to one end of a second transistor, the first transistor being a transistor in a first word line driving circuit coupled to a first unselected word line, and the second transistor being a transistor in a second word line driving circuit coupled to a second unselected word line; the absolute value of the first negative voltage is less than the absolute value of the second negative voltage; the memory control method includes: responding to a memory activation signal, outputting a first power supply signal to the first power supply circuit, and outputting a second power supply signal to the second power supply circuit, so that the first power supply circuit outputs the first negative voltage to the first transistor, and the second power supply circuit outputs the second negative voltage to the second transistor; outputting a third power supply signal to the first power supply circuit to set a first reference voltage, so that the first power supply circuit detects the first negative voltage, and pulls up the first negative voltage when the first negative voltage is lower than the first reference voltage.

[0007] According to a third aspect of the present disclosure, a storage system is provided, including a memory device and a memory controller coupled to the memory device, wherein the memory device includes: a memory cell array, the memory cell array including a plurality of memory cell rows and a word line coupled to each memory cell row; peripheral circuitry, the peripheral circuitry being connected to the corresponding memory cell row via the word line, including a first power supply circuit and a second power supply circuit, the first power supply circuit being used to output a first negative voltage to one end of a first transistor, the second power supply circuit being used to output a second negative voltage to one end of a second transistor, the first transistor being a transistor in a first word line driving circuit coupled to a first unselected word line, and the second transistor being a transistor in a second word line driving circuit coupled to a second unselected word line; the absolute value of the first negative voltage is less than the absolute value of the second negative voltage; the first power supply circuit includes a first negative voltage pull-up module, the first negative voltage pull-up module being used to pull up the first negative voltage when the first negative voltage is lower than a first reference voltage.

[0008] According to a fourth aspect of the present disclosure, a computer system is provided, including the storage system described above.

[0009] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0011] Figure 1 This is a schematic diagram of the structure of a memory device in an exemplary embodiment of this disclosure.

[0012] Figure 2 This is a schematic diagram of a memory device according to an exemplary embodiment of the present disclosure.

[0013] Figure 3 This is a schematic diagram showing the distribution of the memory cell array and peripheral circuits in the memory in an embodiment of this disclosure.

[0014] Figure 4 This is a circuit diagram of the word line driving circuit in an embodiment of this disclosure.

[0015] Figure 5 This is a schematic diagram of the first negative voltage pull-up module in an embodiment of this disclosure.

[0016] Figure 6 This is a schematic diagram of the clamping unit in an exemplary embodiment of this disclosure.

[0017] Figure 7 This is a circuit diagram of the clamping unit in an exemplary embodiment of this disclosure.

[0018] Figure 8 This is a schematic diagram of the first negative voltage pull-up module in an embodiment of this disclosure.

[0019] Figure 9 This is a schematic diagram of the control unit in an exemplary embodiment of this disclosure.

[0020] Figure 10 This is a schematic diagram of the circuit for generating the first feedback voltage in an embodiment of this disclosure.

[0021] Figure 11 This is a circuit diagram of the first sampling unit in an exemplary embodiment of this disclosure.

[0022] Figure 12 This is a schematic diagram of the first negative voltage pull-up module 211 and charge pump unit 210 multiplexing the first sampling unit in an exemplary embodiment of this disclosure.

[0023] Figure 13 In the exemplary embodiment Figure 12 The circuit example diagram corresponding to the structure shown is shown.

[0024] Figure 14 This is a schematic diagram of the second negative voltage pull-up module in an exemplary embodiment of this disclosure.

[0025] Figure 15 This is a flowchart of a memory control method provided in an embodiment of this disclosure.

[0026] Figure 16 This is a schematic diagram of a storage system provided in an embodiment of this disclosure.

[0027] Figure 17 A block diagram of an exemplary system with a memory is shown in an embodiment of this disclosure.

[0028] Figure 18 A block diagram of a storage system is shown as an example.

[0029] Figure 19 A block diagram of another storage system is shown as an example. Detailed Implementation

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0031] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0032] Figure 1 This is a schematic diagram of the structure of a memory device in an exemplary embodiment of this disclosure.

[0033] refer to Figure 1 The memory device 100 may include:

[0034] Storage cell array 1; Storage cell array 1 includes multiple rows of storage cells and word lines WL coupled to each row of storage cells;

[0035] Peripheral circuit 2 is connected to the corresponding memory cell row via word lines (including selected word line, first unselected word line, and second unselected word line). Peripheral circuit 2 includes a first power supply circuit 21 and a second power supply circuit 22. The first power supply circuit 21 is used to output a first negative voltage to one end of the first transistor, and the second power supply circuit 22 is used to output a second negative voltage to one end of the second transistor. The first transistor is the transistor in the first word line driving circuit 23 coupled to the first unselected word line, and the second transistor is the transistor in the second word line driving circuit 24 coupled to the second unselected word line. The absolute value of the first negative voltage is less than the absolute value of the second negative voltage.

[0036] The first power supply circuit 21 includes a first negative voltage pull-up module 211, which is used to pull up the first negative voltage when the first negative voltage is lower than the first reference voltage.

[0037] It should be noted that, Figure 1 The selected word line, the first unselected word line, and the second unselected word line in the text are merely examples to illustrate that word lines in these three states exist in memory.

[0038] This embodiment of the disclosure, by providing a pull-up circuit for the negative voltage with the smaller absolute value in a memory device with two negative voltages, can avoid the problem of decreased circuit stability caused by the negative voltage falling below its set value. Furthermore, by providing a pull-up module for the negative voltage, the negative voltage can be clamped in a timely manner when temperature changes cause it to change below its set value, thereby preventing a decrease in circuit reliability and memory operating efficiency caused by the reduction in negative voltage due to temperature changes when the memory is set with a negative voltage.

[0039] In memory, a negative voltage is set in a specific control circuit or bias circuit section of the memory cell (the negative voltage is below 0V, generated by a charge pump; the charge pump with the ability to generate negative voltage also has the ability to reduce voltage, ensuring that its output negative voltage is below a certain set value). For example, the source voltage of the transistor in the word line drive circuit of the unselected word line is set to a negative voltage to avoid abnormal voltage changes in the unselected word line caused by voltage changes in the selected word line. This suppresses noise interference, reduces the probability of erroneous operation, improves the overall performance and stability of the memory, and enhances the reliability of stored data.

[0040] Introducing a negative voltage, while suppressing abnormal word line voltage fluctuations and resolving noise interference to some extent, also introduces anomalies such as increased power consumption and slower memory response speed. After investigation and analysis, it was determined that the negative voltage was lower than its set value. To maintain word line stability, it is typically necessary to reduce the bias voltage of transistors (e.g., transistors in word line driver circuits). The lower the voltage, the lower the likelihood of noise interference. Therefore, when power allows, it is preferable to set the negative voltage lower; there is no need to increase it—if a higher voltage is required, a positive voltage can be set directly, or the output voltage of the negative voltage charge pump can be increased.

[0041] However, in the process of troubleshooting the anomaly, the inventors discovered that simply setting the negative voltage higher (but the absolute value lower) could not solve the problem caused by the negative voltage.

[0042] In some implementations, to further prevent noise interference, two negative voltages are applied to the word line driver circuits. The word line driver circuit connected to the unselected word line belonging to the same memory block as the selected word line uses a lower negative voltage, resulting in stronger noise immunity. The word line driver circuits connected to other unselected word lines use a higher negative voltage to reduce power consumption. However, when both negative voltages are present simultaneously, in active mode, charge sharing occurs. The higher negative voltage is pulled down by the lower negative voltage, causing the higher negative voltage to fall below its set value, leading to system failure. Furthermore, it also causes a slower rise in the word line voltage of the word line driver circuit connected to the higher negative voltage, reducing the memory's response speed.

[0043] In some implementations, when the circuit uses components, voltages, or currents with a negative temperature coefficient (CTAT), the voltage decreases as the temperature rises. During high-temperature code burning (e.g., trimming) at chip power-on, the generated negative voltage is even lower. As the chip begins normal operation and the temperature decreases, the negative voltage needs to recover to its set value. However, the negative voltage charge pump can only reduce the voltage, and its ability to increase the negative voltage is limited, leading to abnormal negative voltage and reduced memory response speed. Conversely, when the circuit uses components, voltages, or currents with a positive temperature coefficient (PTAT), the voltage increases as the temperature rises. After prolonged chip operation, the chip temperature rises, requiring the negative voltage to increase with the temperature. However, since the negative voltage charge pump can only reduce the voltage, its ability to increase the negative voltage is limited, further reducing memory response speed.

[0044] Based on this, the present disclosure provides a memory device 100 to solve the problems caused by negative voltage. To more clearly understand the technical solutions of the embodiments of the present disclosure, firstly... Figure 2 and Figure 3 The storage cell array and peripheral circuits using embodiments of this disclosure will be introduced below. Figure 4 Let me introduce the word line driving circuit and the unselected word line.

[0045] Figure 2 This is a schematic diagram of a memory device according to an exemplary embodiment of the present disclosure.

[0046] refer to Figure 2 The DRAM memory device 100 may include a memory cell array 1 and peripheral circuitry 2.

[0047] The memory cell array 1 includes multiple memory cells 10 arranged in an array. Each memory cell 10 includes a storage transistor T and a storage capacitor C. The storage capacitor C is used to store charge, and the storage transistor T is used to control the bit line BL to store or discharge charge to the capacitor C. The switching of the transistor T is controlled by the voltage of the word line WL. The amount of charge stored in the capacitor C of the memory cell 10 represents whether a binary bit (1 or 0) stored in the memory cell is 1 or 0.

[0048] The storage cells 10 are arranged in an array to form a storage cell array 1. The storage cell array may include multiple banks, each bank may be divided into multiple blocks or storage volumes, each block includes multiple rows of storage cells and multiple columns of storage cells, each row of storage cells is coupled to a corresponding word line WL, and each column of storage cells is coupled to a corresponding bit line BL.

[0049] Memory cell arrays use rows and columns to specify addresses. By specifying the intersection of the rows and columns (by specifying the row and column addresses of the DRAM), the memory controller (such as those described later)... Figure 16 The memory controller can independently access each memory cell in the DRAM chip and perform read or write operations on the data stored therein.

[0050] Peripheral circuit 2 may include a series of complementary metal-oxide-semiconductor (CMOS) control circuits, such as: control circuits corresponding to each memory block, such as sensing amplifier circuits (SA) and word-line driver circuits (WLD); control circuits corresponding to each memory repository, such as row decoders and column decoders; and control circuits corresponding to all memory repositories, such as command buffers, command decoders, address buffers, data buffers, mode registers, input / output buffers, etc. For ease of understanding, Figure 2 Not all of them are shown in the image.

[0051] Figure 3 This is a schematic diagram showing the distribution of the memory cell array and peripheral circuits in the memory in an embodiment of this disclosure.

[0052] refer to Figure 3 The storage unit array 1 includes M banks 101, each bank 101 includes N blocks 111, and each block 111 has a control circuit on at least one side. Similarly, each bank 11 has a control circuit on at least one side. Every K banks in the M banks form a bank row, and the M banks form M / K bank rows. Peripheral circuits corresponding to all banks are located between the two middle bank rows. It should be noted that M, N, and K are all positive integers, and M is an integer multiple of K.

[0053] For example, refer to Figure 3 M=16. Each memory block 111 is surrounded by a word line driver circuit 2111 and a sensing amplifier 2112 corresponding to that memory block. Each storage block 111 has a column decoder 21 and a row decoder 22 corresponding to that storage block on both sides. Every four storage blocks 101 form a storage block row, and 16 storage blocks form four storage block rows. A control circuit 22 is located between the two middle storage block rows. It should be noted that... Figure 3 The number of storage repositories is for illustrative purposes only and is not intended to limit the number of storage repositories in the memory device of this disclosure. The focus of this disclosure is not on the layout of the memory cell array and peripheral circuitry, and therefore will not be detailed here. The circuitry provided in this disclosure is applicable to memory cell arrays and peripheral circuitry with various layouts.

[0054] Figure 4 This is a circuit diagram of the word line driving circuit in an embodiment of this disclosure.

[0055] refer to Figure 4The word line driving circuit WLD may include an inverter 41 and a pull-down transistor 42, wherein the source of the P-type transistor in the inverter 41 is connected to the power supply circuit XPP_INV to obtain the first voltage XPP output by the power supply circuit XPP_INV according to the voltage XPP\. <1> The input of inverter 41 is connected to the main word line signal MWL, and the output is connected to the word line WL (referred to as word line WL in the diagram). <1> For example, the source of the N-type transistor in inverter 41 is connected to the first negative voltage VWLN1.

[0056] Pull-down transistor 42 is an N-type transistor, with its drain connected to the word line WL and its control terminal connected to the word line drive signal WLD. <1> (The text in the image is marked with the letter WL) <1> For example, the source is connected to the second negative voltage VWLN2.

[0057] By controlling MLL and WLD <1> It can be 0 or 1, which can realize the signal change of word line WL.

[0058] When the word line WL <1> When selected, MWL is low, and WLD is low. <1> When in a low-level state, word line WL <1> Connect the first voltage XPP <1> .

[0059] When the word line WL <1> There are two possibilities when it is not selected.

[0060] One type is the word line WL <1> The word lines corresponding to the memory block are not selected. That is, when the entire memory block is not active, since the word lines connected to a memory block use the same main word line signal MWL\, and MWL\ is in a high-level state, WLD... <1> When in a low-level state, word line WL <1> Connect the first negative voltage VWLN1. Similarly, at this time, all WLs in this memory block are connected to VWLN1.

[0061] Another type is the letter line WL. <1> When a selected word line exists in the word line corresponding to a memory block, meaning a portion of the memory block is activated, the main word line signal MWL is low. The selected word line is then connected to the word line driver circuit via WLD. <1> When the selected word line is in a low-level state, it is connected to the first voltage XPP. <1> Unselected text lines (e.g., text line WL) <1> WLD in the connected word line driver circuit <1> The word line WL is in a high-level state. <1> Connect a second, more negative voltage, VWLN2.

[0062] Therefore, both the first negative voltage VWLN1 and the second negative voltage VWLN2 are provided to the word line drive circuit connected to the unselected word line. Next, refer to the above principle to understand the following definitions.

[0063] When there is no selected word line in the memory block containing an unselected word line, that word line is the first unselected word line. The word line driving circuit connected to the first unselected word line is the first word line driving circuit. The N-type transistor of the inverter 41 in the first word line driving circuit is the first transistor. One end of the first transistor (e.g.) Figure 4 As shown, the first negative voltage VWLN1 is connected, and the first power supply circuit 21 is used to output the first negative voltage VWLN1 to the first transistor in the first word line drive circuit.

[0064] When a selected word line exists within the memory block containing an unselected word line, that word line is designated as the second unselected word line. The word line driver circuit connected to the second unselected word line is called the second word line driver circuit. The pull-down transistor in the second word line driver circuit is called the second transistor. One end of the second transistor (e.g., ...) Figure 4 (As shown) The second negative voltage VWLN2 is connected, and the second power supply circuit 22 is used to output the second negative voltage VWLN2 to the second transistor in the second word line drive circuit.

[0065] In an exemplary embodiment, the second unselected word line includes word lines belonging to the same memory block as the selected word line, or the second unselected word line includes word lines belonging to the same memory block as the selected word line and at least a portion of word lines contained in a memory block adjacent to the memory block where the selected word line is located; the first unselected word line includes other unselected word lines besides the second unselected word line.

[0066] It is understandable that when the memory is active, the selected word line changes continuously. The same word line can be the selected word line, the first unselected word line, and the second unselected word line at different times. Correspondingly, the word line driver circuit it is connected to will also be in different states and have different names. Therefore, the first word line driver circuit and the second word line driver circuit are names of the word line driver circuit in different states, not based on their position.

[0067] In practical applications, during power-on operations such as read, write, and refresh operations on memory devices, as described above, significant voltage overshoot can occur due to coupling effects between word lines and bit lines coupled to unselected memory cells, and between the substrate and source terminals of transistors in word line drive circuits. To address this, related technologies apply a negative voltage to the transistors in unselected word line drive circuits. As mentioned above, the second negative voltage VWLN2 is lower than the first negative voltage VWLN1, used to reduce the coupling effect between word lines connected to the same main word line signal MWL\; that is, the absolute value of the first negative voltage VWLN1 is less than the absolute value of the second negative voltage VWLN2.

[0068] In this scenario, because two different negative voltages exist simultaneously, the first negative voltage VWLN1 may be pulled low by the second negative voltage VWLN2. Since the sources of all NMOS transistors in WLD are connected to either VWLN1 or VWLN2, if one of the negative voltages falls below the first value, it will cause increased transistor leakage current, thereby increasing the overall chip power consumption. Furthermore, an excessively large voltage difference between the negative voltages will also affect transistor performance, thus impacting chip functionality.

[0069] Based on this, the present embodiment provides a first negative voltage pull-up module 211 in the first power supply circuit 21. The first negative voltage pull-up module 211 is used to pull up the first negative voltage VWLN when the first negative voltage VWLN is lower than the first reference voltage.

[0070] Figure 5 This is a schematic diagram of the first negative voltage pull-up module in an embodiment of this disclosure.

[0071] refer to Figure 5 In an exemplary embodiment, the first negative voltage pull-up module 211 may include a comparator 51, a control unit 52, and a clamping unit 53.

[0072] The first terminal of comparator 51 is connected to the first feedback voltage VWLN_FB corresponding to the first negative voltage VWLN1, the second terminal is connected to the first conversion voltage VREF_FB corresponding to the first reference voltage VREF1, and the output terminal is connected to the control unit 52 and the clamping unit 53.

[0073] The control unit 52 includes a first input terminal, a second output terminal, and a second output terminal. The first input terminal is connected to the output terminal of the comparator 51 to receive the comparison signal S0 from the comparator 51. The first output terminal outputs a first control signal S1. The second output terminal is connected to the clamping unit 53 to output a second control signal S2, wherein the second control signal S2 is generated based on the comparison signal S0 and the first control signal S1.

[0074] The input terminal of the clamping unit 53 is connected to the second output terminal of the control unit 52 and the output terminal of the comparator 51. The output terminal is connected to the first negative voltage VWLN. When the comparison signal S0 is the first value, the first negative voltage VWLN is pulled up according to the second control signal S2.

[0075] Wherein, the first negative voltage VWLN1 and the first reference voltage VREF1 are both negative voltages. The first reference voltage VREF1 is the minimum voltage threshold set for the first negative voltage VWLN1, that is, to control the first negative voltage VWLN1 to be no lower than the first reference voltage VREF1.

[0076] The first feedback voltage VWLN_FB is a positive voltage, obtained by converting the first negative voltage VWLN1; the first conversion voltage VREF_FB is also a positive voltage, obtained by converting the first reference voltage VREF1. By converting the first negative voltage VWLN1 and the first reference voltage VREF1 to obtain a positive voltage, the corresponding conversion voltages can be compared in the comparator.

[0077] When the first negative voltage VWLN1 is lower than the first reference voltage VREF1, the comparison signal S0 output by comparator 51 is a first value; when the first negative voltage VWLN1 is not lower than the first reference voltage VREF1, the comparison signal S0 output by comparator 51 is a second value. When the comparison signal S0 is the first value, the clamping unit 53 pulls up the first negative voltage VWLN1.

[0078] The second control signal S2 is used to control the pull-up degree of the clamping unit 53 on the first negative voltage. The second control signal S2 can be generated based on the first control signal S1. When the comparison signal S9 is the first value, the control unit 52 generates and outputs the second control signal S2.

[0079] Figure 6 This is a schematic diagram of the clamping unit in an exemplary embodiment of this disclosure.

[0080] refer to Figure 6 In an exemplary embodiment, the clamping unit 53 may include:

[0081] The current generation unit 531 is used to output a first current I1 through the first node N1 when the comparison signal S0 is a first value;

[0082] There are P current mirror units 532, each of which is connected to the first node N1 and the first negative voltage VWLN1. The k-th current mirror unit is turned on by the k-th bit data control of the second control signal S2 to output a first current I1 to the first negative voltage VWLN1, where 1≤k≤P.

[0083] exist Figure 6 In the illustrated embodiment, the clamping unit 53 adjusts the pull-up amplitude of the first negative voltage VWLN1 via a current mirror method. Exemplarily, a multiplexed circuit mirroring unit 532 outputs a pull-up current to the first negative voltage VWLN1, with different circuit mirroring units 532 outputting different pull-up currents. Each circuit mirroring unit 532 can be enabled by a specific bit of the second control signal S2. Therefore, the number of circuit mirroring units 532 can be the same as the number of bits in the second control signal S2.

[0084] Therefore, different circuit mirror units 532 can be enabled by the second control signal S2 to output different pull-up currents, and different numbers of circuit mirror units 532 can be enabled by the second control signal S2 to output different pull-up currents. As long as the pull-up current output by each circuit mirror unit 532 is configured reasonably, various values ​​of pull-up current can be achieved by adjusting the bits of the second control signal S2 through permutations and combinations.

[0085] Figure 7 This is a circuit diagram of the clamping unit in an exemplary embodiment of this disclosure.

[0086] refer to Figure 7 In some embodiments, the current generating unit 531 may include:

[0087] The first transistor M1 has its first terminal grounded, and its control terminal connected to the output of the comparator.

[0088] The second transistor M2 has its first terminal connected to the second terminal of the first transistor M1, and its second terminal connected to the first node N1. Its control terminal receives a bias signal SS, which is used to control the magnitude of the first current I1.

[0089] The third transistor M3 has its first terminal connected to the power supply voltage, and its second terminal and control terminal connected to the first node.

[0090] The current mirror unit 532 may include:

[0091] The fourth transistor group M4×n includes n mirror transistors connected in parallel. The first terminal of each mirror transistor is connected to the power supply voltage, the control terminal is connected to the first node N1, and the second terminal is connected to the third node N3, where n≥1.

[0092] The fifth transistor M5 has its first terminal connected to the third node N3, and its control terminal is used to receive one bit of data from the second control signal S2.

[0093] The sixth transistor M6 has its first terminal and control terminal connected to the second terminal of the fifth transistor M5, and the second terminal is connected to the first negative voltage VWLN1.

[0094] The n value may not be the same for different current mirror units 532.

[0095] exist Figure 7In the illustrated embodiment, the bias signal SS is used to control the magnitude of the first current I1 output by the first node N1. The current mirror unit 532 determines the magnitude of its output pull-up current based on the value of n in its fourth transistor group M4×n. When n=1, the pull-up current output by the current mirror unit 532 is I1; when n=3, the pull-up current output by the current mirror unit 532 is 3×I1, and so on. By setting different n values ​​for different current mirror units 532, the pull-up current output by each circuit mirror unit 532 can be configured.

[0096] There are many other methods to configure the pull-up current output of each circuit mirror unit 532, such as setting resistor units with different resistance values ​​in each circuit mirror unit 532. Those skilled in the art can set these methods according to actual conditions, and this disclosure will not elaborate further here.

[0097] In addition to pulling up the first negative voltage VWLN1 by outputting pull-up current through a current mirror, the first negative voltage VWLN1 can also be pulled up in other ways, such as setting pull-up branches with different resistance values ​​and enabling different pull-up branches to achieve different degrees of pull-up on the first negative voltage VWLN1.

[0098] The pull-up degree of the first negative voltage VWLN1 can be controlled by the second control signal S2. The pull-up degree of the first negative voltage VWLN1 can be determined by the drop amplitude of the first negative voltage VWLN1, i.e., the first reference voltage VREF1.

[0099] In this embodiment of the disclosure, the first reference voltage VREF1 can be selected by the first control signal S1.

[0100] Figure 8 This is a schematic diagram of the first negative voltage pull-up module in an embodiment of this disclosure.

[0101] refer to Figure 8 The first negative voltage pull-up module 211 also includes:

[0102] Signal conversion unit 54 receives a first control signal S1 at its input terminal and outputs a third control signal S3 at its output terminal. Signal conversion unit 54 is used to output the third control signal S3 according to the first control signal S1.

[0103] The first conversion voltage selection unit 55 receives the third control signal S3 at its input terminal and is connected to the second terminal of the comparator at its output terminal. Based on the third control signal S3, the first conversion voltage selection unit 55 outputs the first conversion voltage VREF_FB from multiple candidate conversion voltages.

[0104] For example, the first conversion voltage selection unit 55 may include M switching elements K1 to KM and N series-connected reference resistors R1 to RN, and the third control signal S3 has at least M bits, wherein,

[0105] The first terminal of the first reference resistor R1 is grounded, the second terminal of the Nth reference resistor RN is connected to the reference voltage, and the second terminal of the i-th reference resistor Ri and the first terminal of the (i+1)-th reference resistor Ri+1 are connected to the i-th node.

[0106] The first terminals of M switching elements K1 to KM are all connected to the second terminal of comparator 51. The second terminal of each switching element Kj is connected to a node. The control terminal of the j-th switching element Kj is used to receive the j-th bit of the third control signal S3. <j>, 1<M≤N, 1≤i≤N, 1≤j≤M.

[0107] By using multiple reference resistors for voltage division, various first conversion voltages VREF_FB can be generated based on the reference voltage, thus corresponding to multiple different first reference voltages VREF1. The first conversion voltage VREF_FB is used to limit the drop amplitude of the first feedback voltage VWLN1_FB, which is equivalent to the first reference voltage VREF1 being used to limit the drop amplitude of the first negative voltage VWLN1.

[0108] The greater the difference between the first conversion voltage VREF_FB and the first feedback voltage VWLN1_FB, the greater the pull-up amplitude required by the clamping unit 53 for the first negative voltage VWLN1, for example, the greater the pull-up current output by the clamping unit 53. Therefore, the third control signal S3 controlling the first conversion voltage VREF_FB is related to the second control signal S2 controlling the pull-up amplitude of the pull-up current 53.

[0109] Therefore, in some embodiments of this disclosure, the first control signal S1 is configured to simultaneously control the generation of the second control signal S2 and the third control signal S3, thereby reducing the signal generation circuit and saving circuit area.

[0110] Figure 9 This is a schematic diagram of the control unit in an exemplary embodiment of this disclosure.

[0111] refer to Figure 9 In this embodiment of the disclosure, the control unit 52 may include an AND logic unit 521. The first input terminal of the AND logic unit 521 is used to receive a comparison signal S0, and the second input terminal is used to receive a first control signal S1. The AND logic unit 521 is used to output a second control signal S2 according to the first control signal S1 when the comparison signal S0 is a first value.

[0112] exist Figure 9 In the illustrated embodiment, the first value is, for example, 1.

[0113] When the comparison signal S0 is 1, the second control signal S2 is equal to the first control signal S1; when the comparison signal S0 is 0, the control unit 52 does not output the second control signal S2, or outputs the second control signal S2 with a default value (e.g., all bits are 0), and the clamping unit 53 does not output the pull-up current.

[0114] Therefore, by using the first control signal S1, the second control signal S2 and the third control signal S3 can be generated simultaneously.

[0115] Table 1 shows an exemplary correspondence between the first control signal S1, the second control signal S2, and the third control signal S3. In the example in Table 1, both the first control signal S1 and the second control signal S2 are 3 bits, and there are 3 current mirroring units 532 in the clamping unit 53; the third control signal S3 is 8 bits. In this case, the signal conversion unit 54 can be implemented by a 3-to-8 decoder.

[0116] Table 1

[0117] First control signal S1 Second control signal S2 Third control signal S3 000 000 00000001 001 001 00000010 010 010 00000100 011 011 00001000 100 100 00010000 101 101 00100000 110 110 01000000 111 111 10000000

[0118] Among them, the third control signal S3 is independent of the state of the comparison signal S0, and the second control signal S2 only reflects the above correspondence when the comparison signal S0 is the first value.

[0119] In conjunction with the aforementioned embodiments, let the n values ​​corresponding to the three current mirror units 532 in the clamping unit 53 be 8, 16, and 32, respectively. That is, when the three current mirror units 532 are enabled, the pull-up currents output are 8I1, 16I1, and 32I1, respectively. Then, according to the control signal relationship in Table 1, the pull-up current correspondence table shown in Table 2 is obtained.

[0120] Table 2

[0121] First control signal S1 Comparison signal S0 Second control signal S2 Pull-up current any value 0 \ 0 000 1 000 0 001 1 001 8I1 010 1 010 16I1 011 1 011 24I1 100 1 100 32I1 101 1 101 40I1 110 1 110 48I1 111 1 111 56I1

[0122] The above correspondence is only an example. Those skilled in the art can choose their own method to implement the signal conversion, as long as the second control signal S2 and the third control signal S3 can be generated simultaneously based on the first control signal S1.

[0123] The following describes the circuit for generating the first feedback voltage VWLN1_FB corresponding to the first negative voltage VWN1.

[0124] Figure 10 This is a schematic diagram of the circuit for generating the first feedback voltage in an embodiment of this disclosure.

[0125] refer to Figure 10 In an exemplary embodiment, the first negative voltage pull-up module 211 further includes:

[0126] The first sampling unit 56 has its input terminal connected to the first negative voltage VWLN1 and its output terminal connected to the first terminal of the comparator 511, and is used to output the first feedback voltage VWLN1_FB corresponding to the first negative voltage VWLN1.

[0127] Figure 11 This is a circuit diagram of the first sampling unit in an exemplary embodiment of this disclosure.

[0128] refer to Figure 11 In some embodiments, the first sampling unit 56 may include

[0129] The first enable switch EN1 has a first terminal connected to a first negative voltage, and a control terminal receiving a detection control signal SEN. The detection control signal SEN is used to control the start or stop of detecting the first negative voltage.

[0130] The first voltage divider resistor unit RZX1 has its first end connected to the second end of the first enable switch EN1, and its second end connected to the second node N2. The second node N2 is the output terminal of the first sampling unit.

[0131] The second voltage divider resistor unit RZX2 has its first end connected to the second node N2, and its second end used to connect to the reference voltage.

[0132] There are various circuit structures that can implement the first sampling unit 56, i.e., the circuit structure that converts negative voltage into positive voltage for sampling. Figure 11 This is merely an example; those skilled in the art can design specific circuits according to their actual needs.

[0133] In some embodiments, the first sampling unit 56 can reuse the original circuit for sampling the first negative voltage VWLN1 by the charge pump, thereby saving circuit area.

[0134] Figure 12 This is a schematic diagram of the first negative voltage pull-up module 211 and charge pump unit 210 multiplexing the first sampling unit in an exemplary embodiment of this disclosure.

[0135] refer to Figure 12 In an exemplary embodiment, the output terminal of the first sampling unit 56 is also connected to a charge pump unit 210. The charge pump unit 210 is used to pull down the first negative voltage VWLN1 according to the comparison result of the first feedback voltage VWLN1_FB and the second conversion voltage VREF2_FB. The second conversion voltage VREF2_FB corresponds to the target voltage value of the first negative voltage VWLN1.

[0136] The first sampling unit 56 can simultaneously output the first feedback voltage VWLN1_FB of the first negative voltage VWLN1 to the charge pump unit 210 and the first negative voltage pull-up module 211.

[0137] In the charge pump unit 210, if the first feedback voltage VWLN1_FB is higher than the second conversion voltage VREF2_FB, the charge pump unit 210 pulls down the first negative voltage VWLN1 until the first feedback voltage VWLN1_FB is not higher than the second conversion voltage VREF2_FB.

[0138] In the first negative voltage pull-up module 211, if the first feedback voltage VWLN1_FB is lower than the first conversion voltage VREF_FB, the first negative voltage pull-up module 211 pulls up the first negative voltage VWLN1 until the first feedback voltage VWLN1_FB is not higher than the first conversion voltage VREF_FB.

[0139] Therefore, the value of the first negative voltage VWLN1 is always maintained within a certain range, thus achieving clamping. This prevents the negative voltage from rising or falling, avoiding various problems caused by negative voltage entering the circuit.

[0140] Figure 13 In the exemplary embodiment Figure 12 The circuit example diagram corresponding to the structure shown is shown.

[0141] refer to Figure 13 In an exemplary embodiment, the charge pump unit 210 may include a charge pump comparator 2101, a clock circuit 2102, and a plurality of charge pumps 2103.

[0142] When the charge pump unit 210 and the first negative voltage pull-up module 211 share the first sampling unit 56, the second conversion voltage VREF2_FB can also be selected from the first conversion voltage selection unit 55. For example, the voltage between two reference resistors of the first conversion voltage selection unit 55 can be received as the second conversion voltage VREF2_FB.

[0143] Meanwhile, the first conversion voltage selection unit 55 and the first sampling unit 56 can share a reference voltage by controlling the switching element M0. The first end of the switching element M0 is connected to the reference voltage, and the second end is connected to the first conversion voltage selection unit 55 and the first sampling unit 56. The control end receives the voltage enable signal EN0.

[0144] In addition, the first conversion voltage selection unit 55 may also be provided with a second enable switch EN2 at the ground terminal. The first terminal of the second enable switch EN2 is grounded, the second terminal is connected to a reference resistor, and the control terminal is used to receive a preset control signal. The preset control signal can be either the detection control signal SEN or other control signals. The preset control signal can be used to control whether the first conversion voltage selection unit 55 outputs the first conversion voltage VREF1_FB and the second conversion voltage VREF2_FB.

[0145] pass Figure 13 The circuit shown incorporates both pull-down and pull-up circuits for the first negative voltage VWLN1, which can maintain the stability of the first negative voltage VWLN1 and improve the reliability of the memory.

[0146] The above example of the first negative voltage pull-up module 211 is used to pull up the first negative voltage VWLN1. In practical applications, pull-up circuits for other negative voltages can also be set up according to the form of the first negative voltage pull-up module 211.

[0147] Figure 14 This is a schematic diagram of the second negative voltage pull-up module in an exemplary embodiment of this disclosure.

[0148] refer to Figure 14 In this embodiment of the disclosure, the second power supply circuit 22 includes a second negative voltage pull-up module 221, which is used to pull up the second negative voltage VWLN2 when the second negative voltage VWLN2 is lower than the second reference voltage.

[0149] The structure of the second negative voltage pull-up module 221 can be exactly the same as that of the first negative voltage pull-up module 211, the difference being that the connected negative voltage is different (from the first negative voltage VWLN1 to the second negative voltage VWLN2), and it can also be connected to the charge pump unit corresponding to the second negative voltage, such as... Figure 12 and Figure 13 The combination shown.

[0150] In addition to setting up negative voltage pull-up circuits for the first and second negative voltages, negative voltage pull-up circuits can also be set up for other negative voltages to prevent the risk of negative voltage drop caused by positive temperature coefficient operation and negative temperature coefficient operation, as mentioned above, thereby improving the response efficiency of the memory.

[0151] It is important to note that the negative voltage pull-up modules corresponding to different negative voltages cannot be the same. In some embodiments, different negative voltage pull-up modules can share the first conversion voltage selection unit 55 and draw conversion voltages from different nodes to save circuit area. However, it is best not to share the same circuit structure in other parts to prevent coupling between negative voltages and unpredictable circuit risks.

[0152] Figure 15 This is a flowchart of a memory control method provided in an embodiment of this disclosure.

[0153] refer to Figure 15 The memory control method 1500 is applied to the memory device 100 shown in any of the above embodiments. The memory device 100 includes a memory cell array and peripheral circuitry. The memory cell array includes multiple rows of memory cells and word lines coupled to each row. The peripheral circuitry is connected to the corresponding rows of memory cells via word lines and includes a first power supply circuit and a second power supply circuit. The first power supply circuit outputs a first negative voltage to one end of a first transistor, and the second power supply circuit outputs a second negative voltage to one end of a second transistor. The first transistor is a transistor in a first word line driving circuit coupled to a first unselected word line, and the second transistor is a transistor in a second word line driving circuit coupled to a second unselected word line. The absolute value of the first negative voltage is less than the absolute value of the second negative voltage. The memory control method 1500 can be implemented by the peripheral circuitry.

[0154] Memory control method 1500 may include:

[0155] Step S1: In response to the memory activation signal, output a first power supply signal to the first power supply circuit and output a second power supply signal to the second power supply circuit, so that the first power supply circuit outputs a first negative voltage to the first transistor and the second power supply circuit outputs a second negative voltage to the second transistor.

[0156] Step S2: Output a third power supply signal to the first power supply circuit to set a first reference voltage, so that the first power supply circuit can detect the first negative voltage and pull up the first negative voltage when the first negative voltage is lower than the first reference voltage.

[0157] You can refer to this. Figure 4 The following is an explanation of the word line driving circuit: Method 1500.

[0158] The memory activation signal is a signal sent by the memory controller to the peripheral circuitry to control the memory to switch from an IDLE state to an Active state, enabling operations such as refreshing, reading, and writing. When the memory controller sends the memory activation signal and the row address to the memory, the row address decoder in the peripheral circuitry receives this address signal, decodes it, and converts it into a control signal for a specific word line. That is, it determines the word line to be activated, i.e., selects the word line, based on the combination of address bits.

[0159] Therefore, when the memory controller sends a memory activation signal, the row address decoder in the peripheral circuit responds to the memory activation signal to determine the memory block where the selected word line is located, and then determines the other unselected word lines in the memory block as the second unselected word lines. Then, it can also select the second unselected word line in the adjacent memory block, and finally set all the unselected word lines except the second unselected word line as the first unselected word line.

[0160] Next, the peripheral circuit outputs a first power supply signal to the first power supply circuit and a second power supply signal to the second power supply circuit, so as to supply power to the word line driving circuit connected to the first unselected word line and the second unselected word line respectively, so as to set the first unselected word line and the second unselected word line to a first negative voltage and a second negative voltage respectively.

[0161] Finally, the peripheral circuit outputs a third power supply signal to the first power supply circuit to set the first reference voltage, so that the first power supply circuit can detect the first negative voltage and pull up the first negative voltage when the first negative voltage is lower than the first reference voltage.

[0162] In some embodiments, the peripheral circuit may also output a fourth power supply signal to the second power supply circuit to set a second reference voltage, so that the second power supply circuit can detect the second negative voltage and pull up the second negative voltage when the second negative voltage is lower than the second reference voltage.

[0163] If there are other negative voltages and their corresponding negative voltage pull-up circuits in the circuit, they can be controlled according to the above logic.

[0164] The principle and circuit implementation of Method 1500 have been described above and will not be repeated here.

[0165] Figure 16 This is a schematic diagram of a storage system provided in an embodiment of this disclosure.

[0166] refer to Figure 16 The storage system 1600 includes a memory device 100 as shown in any of the above embodiments and a memory controller 161 coupled to the memory device 100.

[0167] In some embodiments, the memory device 100 includes: a memory cell array, the memory cell array including a plurality of memory cell rows and a word line coupled to each memory cell row; peripheral circuitry, the peripheral circuitry being connected to the corresponding memory cell row via word lines, including a first power supply circuit and a second power supply circuit, the first power supply circuit being used to output a first negative voltage to one end of a first transistor, the second power supply circuit being used to output a second negative voltage to one end of a second transistor, the first transistor being a transistor in a first word line driving circuit coupled to a first unselected word line, and the second transistor being a transistor in a second word line driving circuit coupled to a second unselected word line; the absolute value of the first negative voltage is less than the absolute value of the second negative voltage; the first power supply circuit includes a first negative voltage pull-up module, the first negative voltage pull-up module being used to pull up the first negative voltage when the first negative voltage is lower than a first reference voltage.

[0168] The reliability of the storage system has been improved and power consumption has been reduced by the inclusion of a negative voltage pull-up module.

[0169] Figure 17 A block diagram of an exemplary system with a memory is shown in an embodiment of this disclosure.

[0170] System 1700 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, or any other suitable electronic device having memory therein.

[0171] like Figure 17 As shown, system 700 may include host 170 and, for example, Figure 16 The storage system 1600 shown has one or more memory devices 100 and a memory controller 161. The host 170 can be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor) of an electronic device. The host 170 can be configured to send data to or receive data from the memory 100.

[0172] The memory device 100 can be any memory device disclosed herein, such as a non-volatile memory. The non-volatile memory can be a NAND flash memory (e.g., a three-dimensional (3D) NAND flash memory).

[0173] In some embodiments, memory controller 161 is coupled to memory device 100 and host 170 and is configured to control memory device 100. Memory controller 161 can manage data stored in memory device 100 and communicate with host 170.

[0174] In some embodiments, the memory controller 61 is configured to send commands to the memory device 100.

[0175] In some embodiments, the memory controller 61 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0176] In some embodiments, the memory controller 61 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which can be used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 61 can be configured to send commands to the memory device 100 to cause the memory device 100 to perform operations, such as read, erase, and program operations.

[0177] The memory controller 61 can also be configured to manage various functions related to data stored or to be stored in the memory device 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0178] In some embodiments, the memory controller 61 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 100. The memory controller 61 may also perform any other suitable function, such as formatting the memory device 100. The memory controller 61 may communicate with an external device (e.g., host 170) according to a specific communication protocol. For example, the memory controller 61 may communicate with the external device via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0179] The memory controller 61 and one or more memory devices 100 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 702 can be implemented and packaged into different types of end electronic products.

[0180] Figure 18 A block diagram of a storage system is shown as an example.

[0181] like Figure 18 As shown, the memory controller 61 and the single memory device 100 can be integrated into the memory card 180. The memory card 180 may include a PC card (also known as a PCMCIA card, Personal Computer Memory Card International Association card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., MMC card, RS-MMC card, MMCmicro card, etc.), an SD card (e.g., SD card, miniSD card, microSD card, SDHC card, etc.), a UFS card, etc. The memory card 180 may also include a connector for connecting the memory card 180 to a host computer (e.g., ...). Figure 17 The memory card connector 181 is coupled to the host 170.

[0182] Figure 19 A block diagram of another storage system is shown as an example.

[0183] like Figure 9 As shown, the memory controller 61 and multiple memory devices 100 can be integrated into the SSD 190. The SSD 190 may also include components for connecting the SSD 190 to a host computer (e.g., ...). Figure 17 The SSD 190 is coupled to the host 170 in the host system. In some embodiments, the storage capacity and / or operating speed of the SSD 190 is greater than that of the memory card 180.

[0184] This disclosure also provides a computer system including a storage system as shown in any of the preceding embodiments.

[0185] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0186] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.< / j>

Claims

1. A memory device, characterized in that, include: A storage cell array, the storage cell array comprising a plurality of storage cell rows and word lines coupled to each storage cell row; The peripheral circuit, connected to the corresponding memory cell row via the word line, includes a first power supply circuit and a second power supply circuit. The first power supply circuit outputs a first negative voltage to one end of a first transistor, and the second power supply circuit outputs a second negative voltage to one end of a second transistor. The first transistor is a transistor in a first word line driving circuit coupled to a first unselected word line, and the second transistor is a transistor in a second word line driving circuit coupled to a second unselected word line. The absolute value of the first negative voltage is less than the absolute value of the second negative voltage. The first power supply circuit includes a first negative voltage pull-up module, which is used to pull up the first negative voltage when the first negative voltage is lower than the first reference voltage.

2. The memory device as claimed in claim 1, characterized in that, The second power supply circuit includes a second negative voltage pull-up module, which is used to pull up the second negative voltage when the second negative voltage is lower than the second reference voltage.

3. The memory device as claimed in claim 1, characterized in that, The storage cell array includes multiple storage blocks; each storage block includes the multiple storage cell rows and word lines coupled to each storage cell row; Wherein, the second unselected word line includes word lines belonging to the same storage block as the selected word line, or the second unselected word line includes word lines belonging to the same storage block as the selected word line and at least a portion of word lines contained in a storage block adjacent to the storage block where the selected word line is located; The first unselected character line includes all other unselected character lines except the second unselected character line.

4. The memory device as claimed in claim 1, characterized in that, The first negative voltage pull-up module includes: The comparator has a first terminal connected to the first feedback voltage corresponding to the first negative voltage, a second terminal connected to the first conversion voltage corresponding to the first reference voltage, and an output terminal connected to the control unit and the clamping unit to output a comparison signal. The control unit includes a first input terminal, a second output terminal, and a second output terminal. The first input terminal is connected to the output terminal of the comparator to receive the comparison signal, the first output terminal outputs a first control signal, and the second output terminal is connected to a clamping unit to output a second control signal. The clamping unit has its input terminal connected to the second output terminal of the control unit and the output terminal of the comparator, and its output terminal connected to the first negative voltage.

5. The memory device as claimed in claim 4, characterized in that, The control unit outputs the second control signal based on the comparison signal and the first control signal; when the comparison signal is a first value, the clamping unit pulls up the first negative voltage based on the second control signal.

6. The memory device as claimed in claim 5, characterized in that, The control unit includes an AND logic unit. The first input terminal of the AND logic unit is used to receive the comparison signal, and the second input terminal is used to receive the first control signal. When the comparison signal is a first value, the AND logic unit is used to output the second control signal according to the first control signal.

7. The memory device as claimed in claim 4 or 5, characterized in that, The first negative voltage pull-up module also includes: The signal conversion unit receives the first control signal at its input terminal and outputs a third control signal at its output terminal. The signal conversion unit outputs the third control signal according to the first control signal. The first conversion voltage selection unit receives the third control signal at its input terminal and is connected to the second terminal of the comparator at its output terminal. The first conversion voltage selection unit outputs the first conversion voltage from a plurality of candidate conversion voltages based on the third control signal.

8. The memory device as claimed in claim 7, characterized in that, The first conversion voltage selection unit includes M switching elements and N series-connected reference resistors, and the third control signal has at least M bits, wherein... The first terminal of the first reference resistor is grounded, the second terminal of the Nth reference resistor is connected to the reference voltage, and the second terminal of the i-th reference resistor and the first terminal of the (i+1)-th reference resistor are connected to the i-th node. The first terminals of the M switching elements are all connected to the second terminals of the comparator. The second terminal of each switching element is connected to a node. The control terminal of the j-th switching element is used to receive the j-th bit of the third control signal, where 1 < M ≤ N, 1 ≤ i ≤ N, and 1 ≤ j ≤ M.

9. The memory device as claimed in claim 4 or 5, characterized in that, The clamping unit includes: A current generation unit is used to output a first current through a first node when the comparison signal is a first value; There are P current mirror units, each of which is connected to the first node and the first negative voltage. The kth current mirror unit is turned on by the kth bit of the second control signal to output the first current to the first negative voltage, where 1≤k≤P.

10. The memory device as claimed in claim 9, characterized in that, The current generating unit includes: The first transistor has its first terminal grounded, and its control terminal connected to the output terminal of the comparator. The second transistor has a first terminal connected to the second terminal of the first transistor, and the second terminal connected to the first node. The control terminal receives a bias signal, which is used to control the magnitude of the first current. The third transistor has its first terminal connected to the power supply voltage, and its second terminal and control terminal connected to the first node.

11. The memory device as claimed in claim 9, characterized in that, The current mirror unit includes: The fourth transistor group includes n mirror transistors connected in parallel. The first terminal of each mirror transistor is connected to the power supply voltage, the control terminal is connected to the first node, and the second terminal is connected to the third node, where n≥1. The fifth transistor has its first terminal connected to the third node, and its control terminal used to receive one bit of data from the second control signal. The sixth transistor has its first terminal and control terminal connected to the second terminal of the fifth transistor, and the second terminal is connected to the first negative voltage.

12. The memory device as claimed in claim 4 or 5, characterized in that, The first negative voltage pull-up module also includes: The first sampling unit has its input terminal connected to the first negative voltage and its output terminal connected to the first terminal of the comparator, and is used to output the first feedback voltage corresponding to the first negative voltage.

13. The memory device as claimed in claim 12, characterized in that, The first sampling unit includes: A first enable switch has a first terminal connected to the first negative voltage and a control terminal receiving a detection control signal, which is used to control the start or stop of detecting the first negative voltage. The first voltage divider resistor unit has a first end connected to the second end of the first enable switch, and a second end connected to a second node, the second node being the output end of the first sampling unit; The second voltage divider resistor unit has its first end connected to the second node and its second end used to connect to the reference voltage.

14. The memory device as claimed in claim 12, characterized in that, The output of the first sampling unit is also connected to a charge pump unit, which is used to pull down the first negative voltage according to the comparison result of the first feedback voltage and the second conversion voltage, wherein the second conversion voltage corresponds to the target voltage value of the first negative voltage.

15. A memory control method, characterized in that, Applied to a memory device, the memory device including a memory cell array and peripheral circuitry, the memory cell array including a plurality of memory cell rows and word lines coupled to each memory cell row; The peripheral circuit is connected to the corresponding memory cell row through the word line, including a first power supply circuit and a second power supply circuit. The first power supply circuit is used to output a first negative voltage to one end of the first transistor, and the second power supply circuit is used to output a second negative voltage to one end of the second transistor. The first transistor is a transistor in the first word line driving circuit coupled to the first unselected word line, and the second transistor is a transistor in the second word line driving circuit coupled to the second unselected word line. The absolute value of the first negative voltage is less than the absolute value of the second negative voltage; The memory control method includes: In response to the memory activation signal, a first power supply signal is output to the first power supply circuit and a second power supply signal is output to the second power supply circuit, so that the first power supply circuit outputs the first negative voltage to the first transistor and the second power supply circuit outputs the second negative voltage to the second transistor; A third power supply signal is output to the first power supply circuit to set a first reference voltage, so that the first power supply circuit can detect the first negative voltage and pull up the first negative voltage when the first negative voltage is lower than the first reference voltage.

16. The memory control method as described in claim 15, characterized in that, Also includes: The second power supply circuit outputs a fourth power supply signal to set a second reference voltage, so that the second power supply circuit can detect the second negative voltage and pull up the second negative voltage when the second negative voltage is lower than the second reference voltage.

17. A storage system, characterized in that, Includes a memory device and a memory controller coupled to the memory device, wherein the memory device includes: A storage cell array, the storage cell array comprising a plurality of storage cell rows and word lines coupled to each storage cell row; The peripheral circuit, connected to the corresponding memory cell row via the word line, includes a first power supply circuit and a second power supply circuit. The first power supply circuit outputs a first negative voltage to one end of a first transistor, and the second power supply circuit outputs a second negative voltage to one end of a second transistor. The first transistor is a transistor in a first word line driving circuit coupled to a first unselected word line, and the second transistor is a transistor in a second word line driving circuit coupled to a second unselected word line. The absolute value of the first negative voltage is less than the absolute value of the second negative voltage. The first power supply circuit includes a first negative voltage pull-up module, which is used to pull up the first negative voltage when the first negative voltage is lower than the first reference voltage.

18. A computer system, characterized in that, Including the storage system as described in claim 17.

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