Peripheral circuit and memory device including the same

Abstract

Peripheral circuits and memory devices including the same are provided. The memory device includes a cell array having a first sub-cell array and a second sub-cell array, and a first bit line sense amplifier and a second bit line sense amplifier connected to the first sub-cell array and the second sub-cell array, respectively. The memory device further includes a first local I / O line pair and a second local I / O line pair electrically connected to a first bit line pair connected with the first bit line sense amplifier and a second bit line pair connected with the second bit line sense amplifier, respectively. The memory device further includes a common local I / O line pair connected to the first local I / O line pair and the second local I / O line pair, a common local sense amplifier configured to amplify a voltage level transferred from the common local I / O line pair, a global I / O line pair connected to the common local sense amplifier, and an I / O sense amplifier electrically connected to the global I / O line pair.

Description

Technical Field

[0001] This disclosure relates to peripheral circuits and memory devices including peripheral circuits. Background Technology

[0002] Dynamic Random Access Memory (DRAM) operates by writing and reading data based on the charge stored in the cell capacitors of the memory cells. In DRAM, the memory cell array can be connected to bit lines and complementary bit lines. When a read operation is performed, a bit line sense amplifier senses and amplifies the voltage difference between the bit line and the complementary bit line (i.e., between bit line pairs). The data of the bit line pair sensed by the bit line sense amplifier is selectively transferred to local input / output (I / O) line pairs via column select transistors, and the local sense amplifier amplifies the data of the local I / O line pairs. The data of the local I / O line pairs amplified by the local sense amplifier can be transferred to global I / O line pairs, and the global I / O line sense amplifier amplifies the data of the global I / O line pairs, and the amplified data is output as read data to the outside via a data pad. Summary of the Invention

[0003] Embodiments of this disclosure relate to peripheral circuitry that reduces data bottlenecks within a memory device and increases data transfer speeds, and to a memory device including such peripheral circuitry.

[0004] The purposes achieved by this disclosure are not limited to those described above, and other purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0005] In some embodiments, a memory device may include: a cell array including a first sub-cell array and a second sub-cell array; a first bit line sense amplifier connected to the first sub-cell array; a second bit line sense amplifier connected to the second sub-cell array; a first local input / output (I / O) line pair electrically connected to the first bit line pair connected to the first bit line sense amplifier; a second local I / O line pair electrically connected to the second bit line pair connected to the second bit line sense amplifier; a common local I / O line pair connected to the first local I / O line pair and the second local I / O line pair; a common local sense amplifier configured to amplify voltage levels transmitted from the common local I / O line pair; a global I / O line pair connected to the common local sense amplifier; and an I / O sense amplifier electrically connected to the global I / O line pair.

[0006] In some embodiments, a memory device may include: a cell array, including a first sub-cell array and a second sub-cell array; a first bit line sense amplifier connected to the first sub-cell array; a second bit line sense amplifier connected to the second sub-cell array; a first local I / O line pair electrically connected to the first bit line pair connected to the first bit line sense amplifier; a second local I / O line pair electrically connected to the second bit line pair connected to the second bit line sense amplifier; and a common local I / O line pair connected to the first local I / O line pair and the second local I / O line pair, the common local I / O line pair including... Includes a common local I / O line and complementary common local I / O lines; a plurality of transmission gates configured to: electrically connect the common local I / O line pair to one of the first local I / O line pairs or the second local I / O line pairs, and electrically isolate the common local I / O line pair from the other of the first local I / O line pairs or the second local I / O line pairs; a common local sense amplifier configured to amplify the voltage level transmitted from the common local I / O line pair; a global I / O line pair connected to the common local sense amplifier; and an I / O sense amplifier electrically connected to the global I / O line pair.

[0007] In some embodiments, a memory device may include: a cell array including a first sub-cell array and a second sub-cell array; a first bit line sense amplifier connected to the first sub-cell array; a second bit line sense amplifier connected to the second sub-cell array; a first local I / O line pair electrically connected to the first bit line pair connected to the first bit line sense amplifier; a second local I / O line pair electrically connected to the second bit line pair connected to the second bit line sense amplifier; a common local I / O line pair connected to the first local I / O line pair and the second local I / O line pair, the common local I / O line pair including a common local I / O line and a complementary common local I / O line; and a plurality of transmission gates configured to: A common local I / O line pair is electrically connected to one of the first or second local I / O line pairs, and the common local I / O line pair is electrically isolated from the other of the first or second local I / O line pairs; a common local sense amplifier is disposed between the first and second sets of bit line sense amplifiers and is configured to amplify the voltage level transmitted from the common local I / O line pair, the first set of bit line sense amplifiers including a first bit line sense amplifier and connected to the first sub-cell array, and the second set of bit line sense amplifiers including a second bit line sense amplifier and connected to the second sub-cell array; a global I / O line pair is connected to the common local I / O line pair. A sense amplifier; and an I / O sense amplifier electrically connected to a global I / O line pair, wherein the common local sense amplifier may include: a first NMOS transistor having a first terminal connected to a common local I / O line and a gate connected to a complementary common local I / O line; a second NMOS transistor having a first terminal connected to the complementary common local I / O line, a second terminal connected to a second terminal of the first NMOS transistor, and a gate connected to the common local I / O line; a third NMOS transistor being turned on in response to a first activation signal applied to the gate of the third NMOS transistor, having a first terminal connected to a ground voltage line and a second terminal connected to the second terminals of the first NMOS transistor and the second NMOS transistor; a first PMOS transistor having a first terminal connected to a common local I / O line and a gate connected to the complementary common local I / O line; a second PMOS transistor having a first terminal connected to the complementary common local I / O line, a second terminal connected to the second terminal of the first NMOS transistor, and a gate connected to the common local I / O line; and a third PMOS transistor being turned on in response to a second activation signal applied to the gate of the third PMOS transistor, having a first terminal connected to an internal power line and a second terminal connected to the second terminals of the first PMOS transistor and the second PMOS transistor.In some embodiments, the peripheral circuitry may include: a first bit-line sense amplifier connected to a first sub-cell array of the cell array; a second bit-line sense amplifier connected to a second sub-cell array of the cell array; a first local I / O line pair electrically connected to the first bit-line pair connected to the first bit-line sense amplifier; a second local I / O line pair electrically connected to the second bit-line pair connected to the second bit-line sense amplifier; a first common local I / O line pair connected to the first local I / O line pair and the second local I / O line pair; a first common local sense amplifier configured to amplify the voltage level transmitted from the first common local I / O line pair; a global I / O line pair connected to the first common local sense amplifier; and an I / O sense amplifier electrically connected to the global I / O line pair, wherein the peripheral circuitry is disposed below or above the cell array. According to various embodiments of this disclosure, the parasitic resistance and / or parasitic capacitance associated with the global I / O line pair are effectively reduced, and a stable voltage level can be rapidly established during read and write operations.

[0008] According to various embodiments of this disclosure, bottlenecks in data transmission using global I / O pairs can be reduced, and data transmission speed can be increased by reducing the load on global I / O pairs.

[0009] According to various embodiments of this disclosure, by integrating multiple local sense amplifiers into a single common local sense amplifier, the transistor size in the common local sense amplifier and / or switching circuit can be enlarged in the same device layout area, thereby further improving data transmission speed.

[0010] According to various embodiments of this disclosure, sufficient sensing amplification can be ensured without arranging local sensing amplifiers for each local I / O line, thereby achieving a memory core structure that supports high-speed operation while reducing the overall memory chip size increase.

[0011] The technical effects obtainable from this disclosure are not limited to those described above. Other technical effects not mentioned will be clearly understood by those skilled in the art from the following description. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0013] Figure 2 and Figure 3 It is shown Figure 1 A diagram illustrating the connection structure of the bit line sense amplifier and the local sense amplifier.

[0014] Figure 4 This is a perspective view showing the memory core circuitry according to an embodiment of the present disclosure.

[0015] Figure 5 It is shown Figure 1 A block diagram showing the detailed structure of the line decoder.

[0016] Figure 6 It is used to explain sub-cell arrays and Figure 5 A diagram illustrating an example of the operation of a sub-row decoder.

[0017] Figure 7 It is shown as Figure 4 A diagram illustrating an example of a sub-peripheral circuit, which is a part of the peripheral circuitry.

[0018] Figure 8 It shows a more detailed diagram of the circuit structure set in the sub-peripheral circuit and the sub-peripheral circuit itself.

[0019] Figure 9 This shows further arrangements. Figure 7 A diagram illustrating an example of a peripheral circuit.

[0020] Figure 10 To show in more detail Figure 9 A diagram showing a portion of the peripheral circuitry.

[0021] Figure 11 It is used for explanation Figure 8 A diagram illustrating an example implementation of multiple switching elements.

[0022] Figure 12 It is shown Figure 8 A diagram illustrating an example of the detailed structure of a common local sensing amplifier and switching circuit.

[0023] Figure 13 This is a diagram illustrating an example of an amplified voltage level transmitted from a common local I / O line pair according to another disclosed embodiment.

[0024] Figure 14 It is a circuit diagram used to explain the data flow during a read or write operation on a memory cell.

[0025] Figure 15 This is a waveform diagram schematically illustrating the level changes and timing relationships of the main control signal during a read operation in a circuit according to an embodiment of the present disclosure.

[0026] Figure 16 This is an exemplary waveform diagram showing the level changes and timing relationships of the master control signal during a write operation in a circuit according to an embodiment of the present disclosure.

[0027] Figure 17 It is shown as Figure 4A diagram illustrating an example of a sub-peripheral circuit, which is a part of the peripheral circuitry.

[0028] Figure 18 This is a diagram showing the circuit structure set in the sub-peripheral circuit in more detail. Detailed Implementation

[0029] In the following text, reference will be made to Figures 1 to 18 Various embodiments of this disclosure are described. Throughout the specification, the same reference numerals may denote the same components.

[0030] Figure 1 This is a block diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0031] Reference Figure 1 The memory device 100 may include a cell array (e.g., a memory cell array) 110, a row decoder 112, a bit line sense amplifier (BLSA) array 120, a column decoder 130, an input / output (I / O) gate circuit 140, a control logic circuit 150, and a data input / output circuit 180.

[0032] The memory cell array 110 may include a plurality of memory cells 111 arranged in a matrix of rows and columns. The memory cell array 110 may include multiple word lines WL1 to WLn (where n is an integer of 2 or greater) connected to the rows of the memory cells and multiple bit lines BL1 to BLm (where m is an integer of 2 or greater) connected to the columns of the memory cells. Data connected to the memory cells on the active word lines WL can be sensed and amplified by a bit line sensing amplifier connected to the bit lines BL.

[0033] The row decoder 112 can decode the row address XADD and activate the word line WL corresponding to the row address XADD, from word line WL1 to WLn. When the word line is activated (e.g., when a word line enable operation is performed), a high voltage VPP higher than the power supply voltage VDD can be applied to the gate of the access transistor of the memory cell.

[0034] Bit line sense amplifier array 120 may include bit line sense amplifiers 120-1 to 120-m implemented in array form. Each of the bit line sense amplifiers 120-1 to 120-m can sense and amplify data output from a corresponding memory cell 111. Bit line sense amplifier 120-1 may be connected to a bit line pair including a bit line and a complementary bit line to sense and amplify voltages appearing on the bit line. In this embodiment, bit line BL may indicate a bit line pair of the folded bit line sense amplifier type. Each of the bit line sense amplifiers 120-1 to 120-m may be a cross-coupled differential sense amplifier implemented using P-type sense amplifiers and N-type sense amplifiers.

[0035] Column decoder 130 decodes column address YADD and generates column selection signals CSL1 to CSLk (where k is an integer of 2 or greater). In burst mode, column decoder 130 generates column selection signals CSL1 to CSLk by decoding a burst address that increments by 1 based on column address YADD, and the bit line BL selected by column selection signals CSL1 to CSLk can be connected to I / O gating circuitry 140. The burst address can represent the address of a column location that can be accessed with respect to a burst length of read and / or write commands.

[0036] The column select transistor in the I / O gate circuit 140 can transmit the voltage level of the selected bit line output "sensed and amplified by bit line sense amplifiers 120-1 to 120-m" from the bit lines BL1 to BLm to the local sense amplifier (LSA) block 160 in response to the column select signals CSL1 to CSLk.

[0037] Control logic circuitry 150 can control the circuitry of memory device 100 to perform operations according to control parameters stored in the mode register of memory device 100. Control logic circuitry 150 can receive command / address (CA) signals from a processor or memory controller. Control logic circuitry 150 can receive CA signals from the memory controller indicating read and / or write commands, and can control operations according to the read and / or write commands. Control logic circuitry 150 can generate control signals (e.g., XADD, YADD, PSW, PLSA_EQ, PLSA_EN1, PLSA_EN2) controlling the operating timing and / or memory operations of memory device 100 in response to the CA signals. According to an embodiment, commands and addresses may be provided as separate signals.

[0038] The control logic circuit 150 can control the following (refer to...). Figures 7 to 18 The level of the described signal (e.g., activation signal, block select signal, column select signal, drive signal, and similar signals).

[0039] The data input / output circuit 180 can be divided into a write data path 182 and a read data path 184. The write data path 182 may include a data input buffer that receives write data DQ. The read data path 184 may include a data output buffer that transmits read data DQ. The read data path 184 may include an I / O sense amplifier (IOSA) 170 and a local sense amplifier block 160 that outputs read data DQ. The local sense amplifier block 160 may include one or more local sense amplifiers that amplify the voltage levels transmitted to LIO and LIOB via local I / O lines, and the I / O sense amplifier 170 amplifies the voltage levels transmitted to GIO and GIOB via global I / O lines.

[0040] Figure 2 and Figure 3 It is shown Figure 1 A diagram showing the connection structure of the bit line sense amplifier (BLSA) and the local sense amplifier (LSA). Figure 2 The connection structure of the bit line sense amplifier is shown, and Figure 3 The connection structure between the bit line sense amplifier and the local sense amplifier can be shown. Figure 2 Bit line sensing amplifiers 120-1 to 120-4 and Figure 3 The bit line sensing amplifier 120-1 may be included Figure 1 In the bit line sensing amplifier array 120, and Figure 3 The local sensing amplifier 160-1 may be included Figure 1 In the local sensing amplifier block 160.

[0041] Reference Figure 2 Multiple bit lines (e.g., four bit line pairs) of memory cells 111 within memory cell array 110, connected to word lines WLn-1, WLn (where n is an integer of 2 or greater), can be connected to bit line sense amplifiers 120-1 to 120-4 within bit line sense amplifier array 120. Memory cell array 110 may include multiple memory banks, and each memory bank may include multiple memory cell blocks (MCBs).

[0042] Reference Figure 3 The local sensing amplifier 160-1 amplifies the voltage level transmitted through local I / O lines LIO and LIOB, and outputs the amplified level to global I / O lines GIO and GIOB. Global I / O lines GIO and GIOB can be connected via I / O sensing amplifiers (e.g., Figure 1 Item 170) and the data output buffer are connected to the data pins. The bit line pairs BL and BLB connected to the bit line sense amplifier 120-1 can be connected to the local I / O line pairs LIO and LIOB via column select transistors 141 and 142. Column select transistors 141 and 142 can electrically connect the bit line pairs BL and BLB to the local I / O line pairs LIO and LIOB in response to the column select signal CSL.

[0043] Figure 4 This is a perspective view showing the memory core circuitry according to an embodiment of the present disclosure.

[0044] exist Figure 4In the figure, the direction substantially perpendicular to the upper surface of the semiconductor substrate can be defined as the vertical direction Z, and two directions parallel to and intersecting each other on the upper surface of the semiconductor substrate can be defined as the row direction X and the column direction Y, respectively. For example, the row direction X and the column direction Y can intersect each other substantially perpendicularly. The row direction X can also be referred to as the first direction or the first horizontal direction, the column direction Y can also be referred to as the second direction or the second horizontal direction, and the vertical direction Z can be referred to as the third direction. The directions indicated by the arrows in the figure and their opposite directions can be described as the same direction.

[0045] Reference Figure 4 The memory device 100 may include a memory cell array 110 and peripheral circuitry CCC. The memory device 100 may have a peripheral upper cell (CoP) structure, wherein the peripheral circuitry CCC is disposed below the memory cell array 110 (e.g., in the -Z direction). Optionally, the memory device 100 may have a cell upper periphery (PoC) structure, wherein the peripheral circuitry CCC is disposed above the memory cell array 110 (e.g., in the +Z direction).

[0046] The memory cell array 110 may include multiple sub-cell arrays SCA arranged in a matrix of multiple array rows AR1 to AR4 and multiple array columns AC1 to AC8.

[0047] The peripheral circuit CCC may include, in addition to Figure 1 The peripheral circuitry CCC includes components other than the memory cell array 110. It may include multiple sub-peripheral circuits (SPCs), each SPC positioned below the multiple sub-cell arrays SCA in a matrix of array rows AR1 to AR4 and array columns AC1 to AC8, and each SPC controlling the operation of the multiple sub-cell arrays SCA. In addition to the multiple sub-peripheral circuits SPCs corresponding to the multiple sub-cell arrays SCA, the peripheral circuitry CCC may also include circuitry associated with the entire memory cell array 110 or with two or more sub-peripheral circuits SPCs.

[0048] Each subcell array (SCA) may include multiple memory cells, each connected to a word line extending in the row direction X and arranged in the column direction Y, and each connected to a bit line extending in the column direction Y and arranged in the row direction X. Each of the multiple memory cells may include a transistor and a cell capacitor.

[0049] For ease of explanation and description, Figure 4 The illustration shows thirty-two sub-cell arrays SCA and thirty-two corresponding sub-peripheral circuits SPC arranged in four array rows AR1 to AR4 and eight array columns AC1 to AC8, but embodiments of this disclosure are not limited to a specific number of array rows or array columns.

[0050] Figure 5 It is shown Figure 1 A block diagram of the detailed structure of the line decoder 112, and Figure 6 It is used to explain the sub-cell arrays SCA1, SCA2 and Figure 5 A diagram illustrating an example of the operation of sub-row decoders 112_1 and 112_2.

[0051] Reference Figure 1 and Figure 5 The row decoder 112 may include a plurality of sub-row decoders 112_1 to 112_P (where P is an integer of 2 or greater) (e.g., first sub-row decoder 112_1 to Pth sub-row decoder 112_P). Each of the plurality of sub-row decoders 112_1 to 112_P may be connected to a portion of the memory cells of the memory cell array 110.

[0052] Reference Figure 6 The memory cell array 110 may include sub-cell arrays SCA1 and SCA2. All memory cells of the memory cell array 110 may be divided into sub-cell arrays (such as sub-cell arrays SCA1 and SCA2). For ease of description, Figure 6 The diagram shows two sub-cell arrays, SCA1 and SCA2, but the number is not limited to this. For example, as shown... Figure 4 As shown, the memory cell array 110 may include multiple sub-cell arrays arranged in a matrix.

[0053] Sub-cell array SCA1 may include memory cells MC1 and MC2 (e.g., Figure 6 (W1 and W2 in the original text). Memory cells MC1 and MC2 can be connected to word lines WL1 and WL2 respectively, and can be connected to bit line BL1. Subcell array SCA2 may include memory cells MC3 and MC4 (e.g., Figure 6 (W3 and W4 in the text). Memory cells MC3 and MC4 can be connected to word lines WL3 and WL4 respectively, and can be connected to bit line BL2.

[0054] The memory cell array 110 may include a column selection switch 1112_1 that electrically connects bit line BL1 to I / O line IO. Column selection switch 1112_1 can electrically connect bit line BL1 to I / O line IO based on a column selection signal. The memory cell array 110 may also include a column selection switch 1112_2 that electrically connects bit line BL2 to I / O line IO. Column selection switch 1112_2 can electrically connect bit line BL2 to I / O line IO based on a column selection signal CSL. For example, column selection switches 1112_1 and 1112_2 may be connected to the same column selection line and can receive the same column selection signal through the same column selection line. The column selection signal can electrically connect bit lines BL1 and BL2 to the same I / O line.

[0055] In one embodiment, the number of sub-arrays in memory cell array 110, the number of memory cells in each sub-array, the number of word lines, and the number of bit lines are all illustrative only. Furthermore, the same number of bit line sense amplifiers as the number of bit lines in each sub-array SCA1 may be disposed adjacent to sub-array SCA1 (and the same applies to sub-array SCA2). Column selection switches 1112_1 and 1112_2 may be disposed between sub-array SCA1 and sub-array SCA2. Sub-array SCA1 may be disposed between other bit line sense amplifiers adjacent to sub-array SCA1. Memory cells MC1 to MC4 may be implemented identically to each other, sub-arrays SCA1 and SCA2 may be implemented identically to each other, and column selection switches 1112_1 and 1112_2 may be implemented identically to each other.

[0056] The row decoder 112 can decode the internal row address and can select at least one of the word lines WL1 to WL4 of the memory cells MC1 to MC4 connected to the memory cell array 110.

[0057] Row decoder 112 may include sub-row decoders 112_1 and 112_2. For example, sub-row decoder 112_1 may decode internal row addresses and may be selectively connected to one of the word lines WL1 and WL2 of the sub-cell array SCA1. For example, sub-row decoder 112_2 may decode internal row addresses and may be selectively connected to one of the word lines WL3 and WL4 of the sub-cell array SCA2. Sub-row decoders 112_1 and 112_2 may be implemented identically. Row decoder 112 may include as many sub-row decoders as there are sub-cell arrays in memory cell array 110.

[0058] Row decoder 112 decodes the internal row addresses used to select word lines WL2 and WL4, and column decoder 130 decodes the internal column addresses used to select column select lines. For example, row decoder 112 and column decoder 130 can sequentially select memory cells MC1 and MC3, and then select memory cells MC2 and MC4.

[0059] Figure 7 It is shown as Figure 4 A diagram illustrating examples of sub-peripheral circuits SPC1 and SPC2, which are part of the peripheral circuit CCC. Figure 8 This is a diagram showing in more detail the circuit structure set in the sub-peripheral circuits SPC1 and SPC2.

[0060] Reference Figure 4 and Figure 7Each sub-peripheral circuit SPC1, SPC2 can be connected to Figure 4 The circuitry of a corresponding sub-cell array SCA in the memory cell array 110. For example, a first sub-peripheral circuit SPC1 may be connected to a first sub-cell array, which is one of the sub-cell arrays SCA of the memory cell array 110 (e.g., Figure 6 SCA1 in memory cell array 110), and the second sub-peripheral circuit SPC2 can be connected to the second sub-cell array, which is another sub-cell array SCA in memory cell array 110 (e.g., Figure 6 SCA2 in the first sub-peripheral circuit SPC1 may be disposed above or below the first sub-cell array (e.g., in the +Z or -Z direction), and the second sub-peripheral circuit SPC2 may be disposed above or below the second sub-cell array (e.g., in the +Z or -Z direction).

[0061] Each of the sub-peripheral circuits SPC1 and SPC2 may include a bit line sense amplifier region (e.g., sub-peripheral circuit SPC1 may include bit line sense amplifier regions BLSA_O1 and BLSA_E1, and sub-peripheral circuit SPC2 may include bit line sense amplifier regions BLSA_O2 and BLSA_E2), a sub-word line driver region SWD, a connection region CONJ, and an empty region NULL.

[0062] Bit line sense amplifier regions BLSA_O1, BLSA_E1, BLSA_O2, and BLSA_E2 can be connected to sub-cell arrays connected to sub-peripheral circuits SPC1 and SPC2, respectively. For example, the bit line sense amplifier regions BLSA_O1 and BLSA_E1 of the first sub-peripheral circuit SPC1 can be connected to the first sub-cell array via bit line pairs BL and BLB, and the bit line sense amplifier regions BLSA_O2 and BLSA_E2 of the second sub-peripheral circuit SPC2 can be connected to the second sub-cell array via bit line pairs BL and BLB.

[0063] Each of the bit line sense amplifier regions BLSA_O1, BLSA_E1, BLSA_O2, and BLSA_E2 may include multiple bit line sense amplifiers. Each of the bit line sense amplifier regions BLSA_O1, BLSA_E1, BLSA_O2, and BLSA_E2 may be connected to the sub-cell array via bit line pairs BL and BLB disposed adjacent to the respective bit line sense amplifier region.

[0064] In one example, a sub-peripheral circuit may include two bit line sense amplifier regions. For instance, the bit line sense amplifier regions BLSA_O1 and BLSA_E1 of the first sub-peripheral circuit SPC1 may include a bit line sense amplifier region BLSA_O1 that includes bit line sense amplifiers connected to odd-numbered bit line pairs and a bit line sense amplifier region BLSA_E1 that includes bit line sense amplifiers connected to even-numbered bit line pairs. The bit line sense amplifier regions BLSA_O2 and BLSA_E2 of the second sub-peripheral circuit SPC2 may include a bit line sense amplifier region BLSA_O2 that includes bit line sense amplifiers connected to odd-numbered bit line pairs and a bit line sense amplifier region BLSA_E2 that includes bit line sense amplifiers connected to even-numbered bit line pairs.

[0065] In one example, bit line sense amplifier regions comprising bit line sense amplifiers connected to even-numbered bit line pairs can be arranged adjacent to each other between adjacent sub-peripheral circuits, or bit line sense amplifier regions comprising bit line sense amplifiers connected to odd-numbered bit line pairs can be arranged adjacent to each other. For example, the bit line sense amplifier region BLSA_E1 of the first sub-peripheral circuit SPC1 comprising bit line sense amplifiers connected to even-numbered bit line pairs and the bit line sense amplifier region BLSA_E2 of the second sub-peripheral circuit SPC2 comprising bit line sense amplifiers connected to even-numbered bit line pairs can be arranged adjacent to each other. Figure 7 Conversely, in another embodiment, the bit line sense amplifier region BLSA_O1 of the first sub-peripheral circuit SPC1, which includes bit line sense amplifiers connected to bit line pairs with odd numbers, and the bit line sense amplifier region BLSA_O2 of the second sub-peripheral circuit SPC2, which includes bit line sense amplifiers connected to bit line pairs with odd numbers, may be arranged adjacent to each other.

[0066] Each sub-word line driver region (SWD) may include sub-word line drivers that drive word lines (WL) respectively. Each sub-word line driver region (SWD) may be located between bit line sense amplifier regions in a sub-peripheral circuit. For example, the sub-word line driver region (SWD) of the first sub-peripheral circuit (SPC1) may be located between bit line sense amplifier regions BLSA_O1 and BLSA_E1, and the sub-word line driver region (SWD) of the second sub-peripheral circuit (SPC2) may be located between bit line sense amplifier regions BLSA_O2 and BLSA_E2.

[0067] The connection region CONJ can be located between bit line sense amplifier regions within a sub-peripheral circuit. For example, the connection region CONJ of the first sub-peripheral circuit SPC1 can be located between bit line sense amplifier regions BLSA_O1 and BLSA_E1, and the connection region CONJ of the second sub-peripheral circuit SPC2 can be located between bit line sense amplifier regions BLSA_O2 and BLSA_E2. Within a sub-peripheral circuit, the sub-word line driver region SWD can be located between the connection regions CONJ within the same sub-peripheral circuit.

[0068] Each connection region CONJ may include circuitry for the operation of the auxiliary sub-word line driver region SWD and / or the bit line sense amplifier regions BLSA_O1, BLSA_E2, BLSA_O2, or BLSA_E2. For example, each connection region CONJ may include transistors that supply (or additionally supply) power to the bit line sense amplifier regions BLSA_O1, BLSA_E2, BLSA_O2, or BLSA_E2, and transistors that transmit signals to the line decoder (e.g., ...). Figure 6 The inverters that boost the signal (items 112_1 and 112_2).

[0069] An empty region (NULL) can be a region in which no circuit corresponding to a specific sub-array is set. Circuits corresponding to two or more sub-arrays can be set in an empty region (NULL).

[0070] Reference Figure 8 The bit line sense amplifier region BLSA_E1 of the first sub-peripheral circuit SPC1 may include a first set of bit line sense amplifiers BLSA12, BLSA14, and BLSA16, respectively connected to even-numbered (or odd-numbered) bit lines, and the bit line sense amplifier region BLSA_E2 of the second sub-peripheral circuit SPC2 may include a second set of bit line sense amplifiers BLSA22, BLSA24, and BLSA26, respectively connected to even-numbered (or odd-numbered) bit lines. The first set of bit line sense amplifiers BLSA12, BLSA14, and BLSA16 and the second set of bit line sense amplifiers BLSA22, BLSA24, and BLSA26 may all be connected to either even-numbered or odd-numbered bit line pairs. For example, Figure 8 The bit line pairs BL12 and BLB12, BL14 and BLB14, BL22 and BLB22, and BL24 and BLB24 can all be bit line pairs with even numbers or all be bit line pairs with odd numbers.

[0071] Each of the plurality of bit line sense amplifiers can be connected to a sub-cell array via a corresponding bit line pair. For example, bit line sense amplifier BLSA12 can be connected to bit line pairs BL12 and BLB12, and bit line sense amplifier BLSA14 can be connected to bit line pairs BL14 and BLB14, thereby connecting to the first sub-cell array. Bit line sense amplifier BLSA22 can be connected to bit line pairs BL22 and BLB22, and bit line sense amplifier BLSA24 can be connected to bit line pairs BL24 and BLB24, thereby connecting to the second sub-cell array.

[0072] Within the empty region NULL, the following can be configured: first local I / O line pairs LIO1 and LIOB1; second local I / O line pairs LIO2 and LIOB2; common local I / O line pairs LIO_COM and LIOB_COM; multiple switching elements TG11 to TG14 and TG21 to TG24; a common local sense amplifier 810; and a switching circuit 820. However, the configuration is not limited to this, and some components or a portion of specific components may be located outside the empty region NULL.

[0073] The first local I / O line pair LIO1, LIOB1 can be electrically connected to the first set of bit line sense amplifiers BLSA12, BLSA14, BLSA16 in the bit line sense amplifier region BLSA_E1 of the first sub-peripheral circuit SPC1. For example, the first local I / O line pair LIO1, LIOB1 can be electrically connected to bit line pairs BL12, BLB12 and BL14, BLB14, which are respectively connected to bit line sense amplifiers BLSA12 and BLSA14 in the first set of bit line sense amplifiers BLSA12, BLSA14, BLSA16 in the bit line sense amplifier region BLSA_E1.

[0074] The first local I / O line pair LIO1, LIOB1 may include a first local I / O line LIO1 and a first complementary local I / O line LIOB1. The first local I / O line LIO1 may be connected to bit lines BL12, BL14, and the first complementary local I / O line LIOB1 may be connected to complementary bit lines BLB12, BLB14.

[0075] In one embodiment, the first set of bit line sense amplifiers BLSA12, BLSA14, and BLSA16 in the bit line sense amplifier region BLSA_E1 of the first sub-peripheral circuit SPC1 can be electrically connected to the first local I / O line pairs LIO1 and LIOB1 in response to column select transistors NM11, NM12, NM13, and NM14 (e.g., N-channel metal-oxide-semiconductor (NMOS) transistors) connected to the first set of bit line sense amplifiers BLSA12, BLSA14, and BLSA16 and turned on by column select signals CSL12 and CSL14. In one embodiment, the column select transistor corresponding to the bit line pair can be turned on when a read or write operation of the bit line pair is initiated. For example, when a read or write operation is initiated via the first line pair BL12, BLB12, the column select transistors NM11 and NM12 connected to the first line pair BL12, BLB12 can be turned on by the column select signal CSL12, and the other column select transistors NM13 and NM14 can be turned off, thereby allowing the bit line sense amplifier BLSA12 to be electrically connected to the first local I / O line pair LIO1, LIOB1.

[0076] The second local I / O line pair LIO2, LIOB2 can be electrically connected to the second set of bit line sense amplifiers BLSA22, BLSA24, BLSA26 in the bit line sense amplifier region BLSA_E2 of the second sub-peripheral circuit SPC2. For example, the second local I / O line pair LIO2, LIOB2 can be electrically connected to bit line pairs BL22, BLB22 and BL24, BLB24, which are respectively connected to bit line sense amplifiers BLSA22 and BLSA24 in the second set of bit line sense amplifiers BLSA22, BLSA24, BLSA26 in the bit line sense amplifier region BLSA_E2.

[0077] The second local I / O line pair LIO2, LIOB2 may include a second local I / O line LIO2 and a second complementary local I / O line LIOB2. The second local I / O line LIO2 may be connected to bit lines BL22, BL24, and the second complementary local I / O line LIOB2 may be connected to complementary bit lines BLB22, BLB24.

[0078] The second set of bit line sense amplifiers BLSA22, BLSA24, and BLSA26 in the bit line sense amplifier region BLSA_E2 of the second sub-peripheral circuit SPC2 can be electrically connected to the second local I / O line pairs LIO2 and LIOB2 in response to the column select transistors NM21, NM22, NM23, and NM24 (e.g., NMOS transistors) being turned on by the column select signals CSL22 and CSL24. For example, when a read or write operation is initiated by the bit line pair, the column select transistors corresponding to the bit line pair can be turned on. Specifically, when a read or write operation is initiated by the second bit line pair BL22 and BLB22, the column select transistors NM21 and NM22 connected to the second bit line pair BL22 and BLB22 can be turned on by the column select signal CSL22, and the other column select transistors NM23 and NM24 can be turned off, thereby allowing the bit line sense amplifier (such as BLSA22) to be electrically connected to the second local I / O line pair LIO2 and LIOB2.

[0079] The common local I / O line pairs LIO_COM and LIOB_COM can be connected to the first local I / O line pair LIO1 and LIOB1 and the second local I / O line pair LIO2 and LIOB2.

[0080] The common local I / O line pair LIO_COM and LIOB_COM may include a common local I / O line LIO_COM and a complementary common local I / O line LIOB_COM. The common local I / O line LIO_COM can be connected to a first local I / O line LIO1 and a second local I / O line LIO2, and the complementary common local I / O line LIOB_COM can be connected to a first complementary local I / O line LIOB1 and a second complementary local I / O line LIOB2.

[0081] Multiple switching elements TG11 to TG14, TG21 to TG24 can electrically connect the common local I / O line pair LIO_COM, LIOB_COM to one of the first local I / O line pairs LIO1, LIOB1 and the second local I / O line pairs LIO2, LIOB2, and can electrically isolate (e.g., disconnect) the common local I / O line pair LIO_COM, LIOB_COM from the other of the first local I / O line pairs LIO1, LIOB1 and the second local I / O line pairs LIO2, LIOB2. For example, the multiple switching elements TG11 to TG14, TG21 to TG24 may include multiple first switching elements TG11 to TG14 connected to the first local I / O line pairs LIO1, LIOB1 and multiple second switching elements TG21 to TG24 connected to the second local I / O line pairs LIO2, LIOB2. Multiple first switching elements TG11 to TG14 are turned on in response to the initiation of a read or write operation on a first sub-cell array connected to the first sub-peripheral circuit SPC1, and are turned off in response to the initiation of a read or write operation on a second sub-cell array connected to the second sub-peripheral circuit SPC2. Multiple second switching elements TG21 to TG24 are turned on in response to the initiation of a read or write operation on a second sub-cell array connected to the second sub-peripheral circuit SPC2, and are turned off in response to the initiation of a read or write operation on a first sub-cell array connected to the first sub-peripheral circuit SPC1.

[0082] Multiple switching elements TG11 to TG14 and TG21 to TG24 may include transmission gate circuits. (See below for reference.) Figure 11 Describe their details.

[0083] The common local sensing amplifier 810 amplifies the voltage level transmitted from the common local I / O lines to LIO_COM and LIOB_COM. The common local sensing amplifier 810 can be positioned between the bit line sensing amplifier region BLSA_E1 of the first sub-peripheral circuit SPC1 connected to the first sub-cell array and the bit line sensing amplifier region BLSA_E2 of the second sub-peripheral circuit SPC2 connected to the second sub-cell array. (Referring below...) Figure 12 Details of the common local sensing amplifier 810 are described.

[0084] The switching circuit 820 can electrically connect the common local sense amplifier 810 and the global I / O pairs GIO and GIOB in response to the activation of a read or write operation on the first sub-cell array connected to the first sub-peripheral circuit SPC1 or the second sub-peripheral circuit SPC2. (Refer to the following...) Figure 12 Describe the details of the 820 switching circuit.

[0085] The global I / O pairs GIO and GIOB can be connected to the common local sense amplifier 810 and the switching circuit 820.

[0086] Global I / O line pairs GIO and GIOB can include a global I / O line GIO and a complementary global I / O line GIOB. The global I / O line GIO can be connected to the common local I / O line LIO_COM, and the complementary global I / O line GIOB can be connected to the complementary common local I / O line LIOB_COM.

[0087] The I / O sense amplifier 170 can be electrically connected to the global I / O line pairs GIO and GIOB.

[0088] Based on the above reference Figure 8 The described circuit structure effectively reduces the parasitic resistance and / or capacitance associated with the global I / O line pairs GIO and GIOB, thereby reducing bottlenecks in data transmission using the global I / O line pairs GIO and GIOB, and improving data transmission speed by reducing the load on the global I / O line pairs GIO and GIOB. For example, in conventional circuit structures, local sense amplifiers are provided separately for each local I / O line pair and connected to the global I / O line pairs GIO and GIOB, while in the circuit structure according to this disclosure, a single common local sense amplifier 810 is provided. Therefore, compared to conventional circuit structures, the number of transistors directly connected to the global I / O line pairs GIO and GIOB is reduced in the circuit structure of this disclosure, thereby reducing parasitic resistance and / or parasitic capacitance. Therefore, the bottleneck of the global I / O line pairs GIO and GIOB is reduced and the data transmission speed is improved. Furthermore, by integrating multiple local sensing amplifiers into a single common local sensing amplifier 810, the transistor size of the common local sensing amplifier 810 and / or the switching circuit 820 can be expanded within the same device layout area, thereby further improving the data transmission speed.

[0089] Figure 9 It is shown as follows Figure 7 The diagram shows an example of additionally configured sub-peripheral circuitry, and Figure 10 To show in more detail Figure 9 A diagram showing a portion of the peripheral circuitry.

[0090] Reference Figure 9 The third peripheral circuit SPC3 can be connected to Figure 4 The memory cell array 110 may contain any of the sub-cell arrays SCA except those connected to the first sub-peripheral circuit SPC1 and the second sub-peripheral circuit SPC2, respectively. The third sub-peripheral circuit SPC3 may be located above or below the third sub-cell array (e.g., in the +Z or -Z direction).

[0091] The third sub-peripheral circuit SPC3 may include bit line sense amplifier regions BLSA_O3 and BLSA_E3, sub-word line driver region SWD, connection region CONJ, and empty region NULL.

[0092] The bit line sense amplifier regions BLSA_O3 and BLSA_E3 of the third sub-peripheral circuit SPC3 can be connected to the sub-cell array connected to the third sub-peripheral circuit SPC3. For example, the bit line sense amplifier regions BLSA_O3 and BLSA_E3 of the third sub-peripheral circuit SPC3 can be connected to the third sub-cell array via bit line pairs BL and BLB. Each of the bit line sense amplifier regions BLSA_O3 and BLSA_E3 can include multiple bit line sense amplifiers. Each of the bit line sense amplifier regions BLSA_O3 and BLSA_E3 can be connected to the sub-cell array via bit line pairs BL and BLB disposed adjacent to the corresponding bit line sense amplifier region.

[0093] The bit line sense amplifier regions BLSA_O3 and BLSA_E3 of the third sub-peripheral circuit SPC3 may include a bit line sense amplifier region BLSA_O3 that includes bit line sense amplifiers connected to odd-numbered bit line pairs and a bit line sense amplifier region BLSA_E3 that includes bit line sense amplifiers connected to even-numbered bit line pairs.

[0094] The bit line sensing amplifier regions BLSA_O2 in the second sub-peripheral circuit SPC2 and BLSA_O3 in the third sub-peripheral circuit SPC3 connected to odd-numbered bit lines can be arranged adjacent to each other. Optionally, when the bit line sensing amplifier regions BLSA_O1 in the first sub-peripheral circuit SPC1 and BLSA_O2 in the second sub-peripheral circuit SPC2 are arranged adjacent to each other, the bit line sensing amplifier regions BLSA_E2 in the second sub-peripheral circuit SPC2 and BLSA_E3 in the third sub-peripheral circuit SPC3 connected to even-numbered bit lines can be arranged adjacent to each other.

[0095] The sub-word line driver region SWD of the third sub-peripheral circuit SPC3 can be set between the bit line sense amplifier region BLSA_O3 and the sense amplifier region BLSA_E3.

[0096] The connection area CONJ of the third sub-peripheral circuit SPC3 can be located between the bit line sense amplifier area BLSA_O3 and the bit line sense amplifier area BLSA_E3. The sub-word line driver area SWD of the third sub-peripheral circuit SPC3 can be located between the connection areas CONJ of the third sub-peripheral circuit SPC3.

[0097] Reference Figure 10 The bit line sense amplifier region BLSA_O2 of the second sub-peripheral circuit SPC2 may include a third set of bit line sense amplifiers BLSA32, BLSA34, and BLSA36, respectively connected to odd-numbered bit lines, and the bit line sense amplifier region BLSA_O3 of the third sub-peripheral circuit SPC3 may include a fourth set of bit line sense amplifiers BLSA42, BLSA44, and BLSA46, respectively connected to odd-numbered bit lines. The third set of bit line sense amplifiers BLSA32, BLSA34, and BLSA36 and the fourth set of bit line sense amplifiers BLSA42, BLSA44, and BLSA46 may all be connected to odd-numbered bit line pairs. Conversely, when referring to the above... Figure 8 When the first group of bit line sense amplifiers BLSA12, BLSA14, and BLSA16, and the second group of bit line sense amplifiers BLSA22, BLSA24, and BLSA26 are all connected to odd-numbered bit line pairs, the third group of bit line sense amplifiers BLSA32, BLSA34, and BLSA36, and the fourth group of bit line sense amplifiers BLSA42, BLSA44, and BLSA46 can all be connected to even-numbered bit line pairs. For example, Figure 10 The bit line pairs BL32, BLB32, BL34, BLB34, BL42, BLB42, BL44, and BLB44 can all be bit line pairs with even numbers or all be bit line pairs with odd numbers.

[0098] Each of the plurality of bit line sense amplifiers can be connected to a bit line pair. Each of the plurality of bit line sense amplifiers can also be connected to a sub-cell array via a bit line pair. For example, bit line sense amplifier BLSA32 can be connected to bit line pairs BL32 and BLB32, and bit line sense amplifier BLSA34 can be connected to bit line pairs BL34 and BLB34, thereby connecting to a second sub-cell array. Similarly, bit line sense amplifier BLSA42 can be connected to bit line pairs BL42 and BLB42, and bit line sense amplifier BLSA44 can be connected to bit line pairs BL44 and BLB44, thereby connecting to a third sub-cell array.

[0099] Within the empty region NULL, the third local I / O line pair LIO3, LIOB3, the fourth local I / O line pair LIO4, LIOB4, the second common local I / O line pair LIO_COM2, LIOB_COM2, multiple switching elements TG31 to TG34, TG41 to TG44, the common local sense amplifier 1010, and the switching circuit 1020 can be configured. However, the configuration is not limited to this, and some components or a portion of specific components may be located outside the empty region NULL.

[0100] The third local I / O line pair LIO3, LIOB3 can be electrically connected to the third set of bit line sense amplifiers BLSA32, BLSA34, BLSA36 in the bit line sense amplifier region BLSA_O2 of the second sub-peripheral circuit SPC2. For example, the third local I / O line pair LIO3, LIOB3 can be electrically connected to bit line pairs BL32, BLB32 and BL34, BLB34, which are respectively connected to bit line sense amplifiers BLSA32 and BLSA34 in the third set of bit line sense amplifiers BLSA32, BLSA34, BLSA36 in the bit line sense amplifier region BLSA_O2.

[0101] The third local I / O line pair LIO3 and LIOB3 may include a third local I / O line LIO3 and a third complementary local I / O line LIOB3. The third local I / O line LIO3 may be connected to bit lines BL32 and BL34, and the third complementary local I / O line LIOB3 may be connected to complementary bit lines BLB32 and BLB34.

[0102] In one embodiment, a third set of bit line sense amplifiers BLSA32, BLSA34, and BLSA36 located in the bit line sense amplifier region BLSA_O2 of the second sub-peripheral circuit SPC2 may be electrically connected to a third local I / O line pair LIO3, LIOB3. This occurs in response to column select transistors NM31, NM32, NM33, and NM34 (e.g., NMOS transistors) connected to the third set of bit line sense amplifiers BLSA32, BLSA34, and BLSA36 and turned on by column select signals CSL32 and CSL34, respectively. When a read or write operation is initiated by a bit line pair, the column select transistors corresponding to the bit line pair are turned on. For example, if a read or write operation is initiated by the third bit line pair BL32, BLB32, the column select transistors NM31 and NM32 connected to the third bit line pair are turned on by the column select signal CSL32, and therefore, the other column select transistors NM33 and NM34 are turned off. This configuration allows the bit line sense amplifier BLSA32 to be electrically connected to the third local I / O line pair LIO3, LIOB3.

[0103] The fourth local I / O line pair LIO4, LIOB4 can be electrically connected to the fourth set of bit line sense amplifiers BLSA42, BLSA44, BLSA46 in the bit line sense amplifier region BLSA_O3 of the third sub-peripheral circuit SPC3. For example, the fourth local I / O line pair LIO4, LIOB4 can be electrically connected to bit line pairs BL42, BLB42 and BL44, BLB44, which are respectively connected to bit line sense amplifiers BLSA42 and BLSA44 in the fourth set of bit line sense amplifiers BLSA42, BLSA44, BLSA46 in the bit line sense amplifier region BLSA_O3.

[0104] The fourth local I / O line pair LIO4, LIOB4 may include a fourth local I / O line LIO4 and a fourth complementary local I / O line LIOB4. The fourth local I / O line LIO4 may be connected to bit lines BL42, BL44, and the fourth complementary local I / O line LIOB4 may be connected to complementary bit lines BLB42, BLB44.

[0105] In one embodiment, the fourth set of bit line sense amplifiers (BLSA42, BLSA44, BLSA46) in the bit line sense amplifier region BLSA_O3 of the third sub-peripheral circuit SPC3 can be electrically connected to the fourth local I / O line pair (LIO4, LIOB4) in response to column select transistors (NM41, NM42, NM43, NM44) (e.g., NMOS transistors) connected to the fourth set of bit line sense amplifiers and turned on by column select signals (CSL42, CSL44). For example, when a read or write operation is initiated by a bit line pair, the column select transistor corresponding to the bit line pair can be turned on. Specifically, when a read or write operation is initiated by the fourth bit line pair (BL42, BLB42), the column select transistors (NM41, NM42) connected to the fourth bit line pair can be turned on by the column select signal CSL42, and the other column select transistors (NM43, NM44) can be turned off. Therefore, the bit line sense amplifier (BLSA42) can be electrically connected to the fourth local I / O line pair (LIO4, LIOB4).

[0106] The second common local I / O line pair LIO_COM2, LIOB_COM2 can be connected to the third local I / O line pair LIO3, LIOB3 and the fourth local I / O line pair LIO4, LIOB4.

[0107] The second common local I / O line pair LIO_COM2 and LIOB_COM2 may include a second common local I / O line LIO_COM2 and a second complementary common local I / O line LIOB_COM2. The second common local I / O line LIO_COM2 may be connected to a third local I / O line LIO3 and a fourth local I / O line LIO4, and the second complementary common local I / O line LIOB_COM2 may be connected to a third complementary local I / O line LIOB3 and a fourth complementary local I / O line LIOB4.

[0108] Multiple switching elements TG31 to TG34 and TG41 to TG44 can electrically connect the second common local I / O line pair LIO_COM2 and LIOB_COM2 to one of the third local I / O line pairs LIO3 and LIOB3 and the fourth local I / O line pairs LIO4 and LIOB4, and can electrically disconnect the second common local I / O line pair LIO_COM2 and LIOB_COM2 from another of the third local I / O line pairs LIO3 and LIOB3 and the fourth local I / O line pairs LIO4 and LIOB4. For example, the multiple switching elements TG31 to TG34 and TG41 to TG44 may include multiple third switching elements TG31 to TG34 connected to the third local I / O line pairs LIO3 and LIOB3 and multiple fourth switching elements TG41 to TG44 connected to the fourth local I / O line pairs LIO4 and LIOB4. Multiple third switching elements TG31 to TG34 can be turned on in response to the initiation of a read or write operation on the sub-cell array connected to the second sub-peripheral circuit SPC2, and can be turned off in response to the initiation of a read or write operation on the sub-cell array connected to the third sub-peripheral circuit SPC3.

[0109] Multiple fourth switching elements TG41 to TG44 can be turned on in response to the initiation of a read or write operation on the third sub-cell array connected to the third sub-peripheral circuit SPC3, and can be turned off in response to the initiation of a read or write operation on the second sub-cell array connected to the second sub-peripheral circuit SPC2.

[0110] Multiple switching elements TG31 to TG34 and TG41 to TG44 may include transmission gate circuits. The implementation method is the same as described above. Figure 8 The described embodiments are the same.

[0111] The common local sensing amplifier 1010 amplifies the voltage level transmitted from the second common local I / O lines LIO_COM2 and LIOB_COM2. The common local sensing amplifier 1010 can be positioned between the bit line sensing amplifier region BLSA_O2 of the second sub-peripheral circuit SPC2 connected to the second sub-cell array and the bit line sensing amplifier region BLSA_O3 of the third sub-peripheral circuit SPC3 connected to the third sub-cell array. The structure of the common local sensing amplifier 1010 can be similar to... Figure 8 The structure corresponds to that of the common local sensing amplifier 810.

[0112] The switching circuit 1020 can electrically connect the common local sense amplifier 1010 and the global I / O pairs GIO and GIOB in response to the activation of a read or write operation on the sub-cell array connected to the second sub-peripheral circuit SPC2 or the sub-cell array connected to the third sub-peripheral circuit SPC3. The structure of the switching circuit 1020 can be compared with... Figure 8 The structure corresponds to the 820 switching circuit.

[0113] The global I / O line pairs GIO and GIOB can be connected to the common local sense amplifier 1010. The global I / O line GIO of the global I / O line pair GIO and GIOB can also be connected to the second common local I / O line LIO_COM2, and the complementary global I / O line GIOB of the global I / O line pair GIO and GIOB can also be connected to the second complementary common local I / O line LIOB_COM2.

[0114] Reference Figures 7 to 10 The circuit structures shown and described can be arranged in a repeating pattern for peripheral circuits. For example, refer to Figures 7 to 10 The circuit structure shown and described can be found in Figure 4 The peripheral circuitry of the CCC is repeatedly arranged in the X and Y directions.

[0115] Figure 11 It is used for explanation Figure 8 A diagram illustrating an example implementation of the multiple switching elements TG11 to TG14, TG21 to TG24. Figure 11 In the middle, only show Figure 8 Some of the switching elements TG11 to TG14 and TG21 to TG24, namely TG11, TG12, TG21, and TG22, but not in accordance with the reference... Figure 11 The embodiments associated with the switching elements shown and described can also be applied to Figure 8 Other switching elements TG13, TG14, TG23, and TG24 can also be applied to... Figure 10 Multiple switching elements TG31 to TG34 and TG41 to TG44.

[0116] Each of the switching elements TG11, TG12, TG21, and TG22 can be implemented as a transmission gate circuit that selectively connects the common local I / O line pair LIO_COM, LIOB_COM to the first local I / O line pair LIO1, LIOB1 or the second local I / O line pair LIO2, LIOB2, or electrically disconnects the common local I / O line pair LIO_COM, LIOB_COM from the first local I / O line pair LIO1, LIOB1 or the second local I / O line pair LIO2, LIOB2. For example, each of the switching elements TG11, TG12, TG21, and TG22 can be implemented as a circuit that connects a P-channel metal-oxide-semiconductor (PMOS) transistor and an NMOS transistor in parallel, and the block select signals Binfo1, Binfo2 and complementary block select signals Binfo1B, Binfo2B can be applied to the NMOS transistor and the PMOS transistor respectively as complementary gate signals.

[0117] In one example, consider the switching elements TG11 and TG12 connected to the first local I / O line pair LIO1, LIOB1. Each of the NMOS transistors NM51 and NM52 and the corresponding one of the PMOS transistors PM51 and PM52 can share two terminals as a common source-drain connection, and the block select signal Binfo1 and its complementary block select signal Binfo1B can be applied to the gates of the NMOS transistors NM51 and NM52 and the PMOS transistors PM51 and PM52, respectively. Here, when the block select signal Binfo1 is in a "high" (logic 1) state, the switching elements TG11 and TG12 are turned on, thereby electrically connecting the first local I / O line pair LIO1, LIOB1 to the common local I / O line pair LIO_COM, LIOB_COM. Conversely, when the block select signal Binfo1 is in a "low" (logic 0) state, the switching elements TG11 and TG12 can be turned off, thereby electrically disconnecting the first local I / O line pair LIO1 and LIOB1 from the common local I / O line pair LIO_COM and LIOB_COM.

[0118] In one example, consider the switching elements TG21 and TG22 connected to the second local I / O line pair LIO2, LIOB2. Each of the NMOS transistors NM53 and NM54 and a corresponding one of the PMOS transistors PM53 and PM54 can share two terminals as a common source-drain connection, and the block select signal Binfo2 and its complementary block select signal Binfo2B can be applied to the gates of the NMOS transistors NM53 and NM54 and the PMOS transistors PM53 and PM54, respectively. Here, when the block select signal Binfo2 is "high", the switching elements TG21 and TG22 are turned on, thereby electrically connecting the second local I / O line pair LIO2, LIOB2 to the common local I / O line pair LIO_COM, LIOB_COM. Conversely, when the block select signal Binfo2 is "low", the switching elements TG21 and TG22 are turned off, thereby electrically disconnecting the second local I / O line pair LIO2, LIOB2 from the common local I / O line pair LIO_COM, LIOB_COM.

[0119] The levels (e.g., high or low) of the block select signals Binfo1 and Binfo2 can be controlled by the memory device's control logic circuitry (e.g., Figure 1 Item 150) control. For example, in response to the initiation of a read or write operation for the first sub-cell array, the control logic circuit may apply a high-level block select signal Binfo1 to switching elements TG11 and TG12 to turn them on, thereby connecting the common local I / O line pairs LIO_COM and LIOB_COM to the first local I / O line pairs LIO1 and LIOB1, and may apply a low-level block select signal Binfo2 to switching elements TG21 and TG22 to turn them off, thereby preventing operation on another sub-cell array (e.g., a second sub-cell array). Similarly, in response to the initiation of a read or write operation for the second sub-array, the control logic circuit can apply a high-level block select signal Binfo2 to switching elements TG21 and TG22 to turn them on, thereby connecting the common local I / O line pairs LIO_COM and LIOB_COM to the second local I / O line pairs LIO2 and LIOB2, and can apply a low-level block select signal Binfo1 to switching elements TG11 and TG12 to turn them off, thereby preventing operation on the other sub-array (e.g., the first sub-array).

[0120] A unique block selection signal Binfo1, Binfo2 can be assigned to each sub-cell array; for example, block selection signal Binfo1 can specify the first sub-cell array (or the sub-row decoder connected to the first sub-cell array), and block selection signal Binfo2 can specify the second sub-cell array (or the sub-row decoder connected to the second sub-cell array).

[0121] According to the embodiments described above, because the electrical connections are turned on / off by transmission gate circuits, the common local I / O line pairs LIO_COM and LIOB_COM can be selectively connected only to the local I / O line pairs of the desired sub-cell array. Therefore, read or write operations in different sub-cell arrays can be performed independently without interference, and fast, stable memory operations can be achieved using simple gate control (e.g., block select signals Binfo1, Binfo2 and complementary block select signals Binfo1B, Binfo2B) that efficiently drive multiple switching elements.

[0122] Figure 12 It is shown Figure 8 A diagram illustrating an example of the detailed structure of the common local sensing amplifier 810 and the switching circuit 820. In one embodiment, refer to... Figure 12 The detailed structures of the common local sensing amplifier 810 and the switching circuit 820 shown and described can also be applied to... Figure 10 The common local sensing amplifier 1010 and the switching circuit 1020.

[0123] The common local sense amplifier 810 may include multiple NMOS transistors NM61 to NM63 and multiple PMOS transistors PM61 to PM63.

[0124] The first terminal of the first NMOS transistor NM61 can be connected to the common local I / O line LIO_COM, and the gate of the first NMOS transistor NM61 can be connected to the complementary common local I / O line LIOB_COM.

[0125] The first terminal of the second NMOS transistor NM62 can be connected to the complementary common local I / O line LIOB_COM, the second terminal of the second NMOS transistor NM62 can be connected to the second terminal of the first NMOS transistor NM61, and the gate of the second NMOS transistor NM62 can be connected to the common local I / O line LIO_COM.

[0126] The third NMOS transistor NM63 can be turned on in response to the application of the first activation signal PLSAEN to its gate; the first terminal of the third NMOS transistor NM63 can be connected to the ground voltage line, and the second terminal of the third NMOS transistor NM63 can be connected to the second terminal of the first NMOS transistor NM61 and the second terminal of the second NMOS transistor NM62.

[0127] The first terminal of the first PMOS transistor PM61 can be connected to the common local I / O line LIO_COM, and the gate of the first PMOS transistor PM61 can be connected to the complementary common local I / O line LIOB_COM.

[0128] The first terminal of the second PMOS transistor PM62 can be connected to the complementary common local I / O line LIOB_COM, the second terminal of the second PMOS transistor PM62 can be connected to the second terminal of the first PMOS transistor PM61, and the gate of the second PMOS transistor PM62 can be connected to the common local I / O line LIO_COM.

[0129] The third PMOS transistor PM63 can be turned on in response to the application of the second activation signal PCLSAEN to its gate; the first terminal of the third PMOS transistor PM63 can be connected to the internal power line, and the second terminal of the third PMOS transistor PM63 can be connected to the second terminal of the first PMOS transistor PM61 and the second terminal of the second PMOS transistor PM62.

[0130] Stable read / write operations on internal memory cells or other circuit blocks can be achieved by appropriately pulling down or pulling up the NMOS transistors NM61 to NM63 and PMOS transistors PM61 to PM63, which are configured as described above, on the common local I / O line LIO_COM and the complementary common local I / O line LIOB_COM, respectively.

[0131] For example, on the NMOS transistor side, when the first activation signal PLSAEN is "high", the third NMOS transistor NM63 can be turned on to pull down the internal node at the connection point of the first NMOS transistor NM61 and the second NMOS transistor NM62 to the ground voltage line.

[0132] On the side of multiple PMOS transistors (PM61, PM62, PM63), when the second activation signal PCLSAEN is "high", the third PMOS transistor (PM63) can connect the internal power supply voltage (VLSA) to the internal node on the PMOS side, thereby allowing the high level (e.g., VDD) to be stably maintained.

[0133] In summary, by appropriately controlling NMOS transistors NM61 to NM63 and PMOS transistors PM61 to PM63, the common local sense amplifier 810 can actively apply the voltage levels of the common local I / O lines LIO_COM and LIOB_COM to ground or the internal power supply voltage VLSA, or isolate the voltage levels of the common local I / O lines LIO_COM and LIOB_COM from ground or the internal power supply voltage VLSA. This enables the fast and stable I / O operation required in memory device or related circuit designs, and also facilitates signal level initialization when switching operating modes.

[0134] The switching circuit 820 may include a first transistor NM64 (e.g., an NMOS transistor) and a second transistor NM65 (e.g., an NMOS transistor).

[0135] The first terminal of the first transistor NM64 in the switching circuit 820 can be connected to the common local I / O line LIO_COM, and the second terminal of the first transistor NM64 can be connected to the global I / O line GIO. In response to the initiation of a read or write operation on the sub-cell array of LIO_COM and LIOB_COM electrically connected to the common local I / O line, a connection control signal PMUXON can be applied to the gate of the first transistor NM64, thereby turning on the first transistor NM64.

[0136] The first terminal of the second transistor NM65 in the switching circuit 820 can be connected to the complementary common local I / O line LIOB_COM, and the second terminal of the second transistor NM65 can be connected to the complementary global I / O line GIOB. In response to the initiation of a read or write operation on the sub-cell array of LIO_COM and LIOB_COM electrically connected to the common local I / O line, a connection control signal PMUXON can be applied to the gate of the second transistor NM65, thereby turning on the second transistor NM65.

[0137] In one embodiment, the control logic circuitry of the memory device (e.g., Figure 1 Item 150) can control the level (e.g., high or low) of the first activation signal PLSAEN, the second activation signal PCLSAEN and / or the connection control signal PMUXON.

[0138] Based on the above reference Figure 12The described circuit structure effectively reduces the parasitic resistance and / or capacitance associated with the global I / O line pairs GIO and GIOB; reduces the bottleneck in data transmission using the global I / O line pairs GIO and GIOB; and increases the data transmission speed by reducing the load on the global I / O line pairs GIO and GIOB. For example, compared to conventional local sense amplifier structures, in the circuit structure according to this disclosure, only two transistors NM64 and NM65 are configured in the switching circuit 820, thus reducing the number of transistors directly connected to the global I / O line pairs GIO and GIOB to two, thereby reducing parasitic resistance and / or capacitance. Therefore, the bottleneck of the global I / O line pairs GIO and GIOB is reduced and the data transmission speed is increased.

[0139] Figure 13 This is a diagram illustrating an example of an amplified voltage level transmitted from the common local I / O lines LIO_COM and LIOB_COM according to another embodiment of this disclosure. (Referring to the above...) Figure 8 and Figure 12 An alternative to the described structure of the common local sensing amplifier 810 and the switching circuit 820 is referenced. Figure 13 The circuit structure shown and described can amplify the voltage levels transmitted from the common local I / O line pairs LIO_COM and LIOB_COM, and can transmit the amplified levels to the global I / O line pairs GIO and GIOB. Additionally, see... Figure 13 The circuit structures shown and described can be optionally applied to Figure 10 The common local sensing amplifier 1010 and the switching circuit 1020.

[0140] For reference above Figure 8 and Figure 12 The described alternative to the common local sense amplifier 810 and switching circuit 820 includes a circuit structure comprising multiple PMOS transistors PM64 to PM66 and multiple NMOS transistors NM66 to NM72 that can amplify the voltage level transmitted from the common local I / O line pairs LIO_COM and LIOB_COM, and can transmit the amplified level to the global I / O line pairs GIO and GIOB.

[0141] The first terminal of the first PMOS transistor PM64 can be connected to the common local I / O line LIO_COM, the gate of the first PMOS transistor PM64 can be connected to the complementary common local I / O line LIOB_COM, and the second terminal of the first PMOS transistor PM64 can be connected to the internal node (hereinafter, "PMOS-side common internal node").

[0142] The first terminal of the second PMOS transistor PM65 can be connected to the complementary common local I / O line LIOB_COM, the second terminal of the second PMOS transistor PM65 can be connected to the same PMOS-side common internal node as the second terminal of the first PMOS transistor PM64, and the gate of the second PMOS transistor PM65 can be connected to the common local I / O line LIO_COM.

[0143] The third PMOS transistor PM66 can be turned on in response to the application of the first activation signal PCLSAEN to its gate; the first terminal of the third PMOS transistor PM66 can be connected to the internal power line, and the second terminal of the third PMOS transistor PM66 can be connected to the PMOS side common internal node.

[0144] The first NMOS transistor NM66 may have a first terminal connected to the ground voltage line, a gate connected to the internal power supply voltage, and a second terminal connected to the internal node (hereinafter, "NMOS-side common internal node").

[0145] The first terminal of the second NMOS transistor NM67 can be connected to a terminal (e.g., the second terminal) of the sixth NMOS transistor NM71, the second terminal of the second NMOS transistor NM67 can be connected to the same NMOS-side common internal node as the second terminal of the first NMOS transistor NM66, and the gate of the second NMOS transistor NM67 can be connected to the common local I / O line LIO_COM.

[0146] The first terminal of the third NMOS transistor NM68 can be connected to a terminal (e.g., the second terminal) of the seventh NMOS transistor NM72, the second terminal of the third NMOS transistor NM68 can be connected to the NMOS-side common internal node, and the gate of the third NMOS transistor NM68 can be connected to the complementary common local I / O line LIOB_COM.

[0147] The first terminal of the fourth NMOS transistor NM69 can be connected to the common local I / O line LIO_COM; the fourth NMOS transistor NM69 can be turned on in response to the application of the second activation signal PMUXON to its gate; and the second terminal of the fourth NMOS transistor NM69 can be connected to the global I / O line GIO and a terminal (e.g., the first terminal) of the sixth NMOS transistor NM71.

[0148] The first terminal of the fifth NMOS transistor NM70 can be connected to the complementary common local I / O line LIOB_COM; the fifth NMOS transistor NM70 can be turned on in response to the application of the second activation signal PMUXON to its gate; and the second terminal of the fifth NMOS transistor NM70 can be connected to the complementary global I / O line GIOB and a terminal (e.g., the first terminal) of the seventh NMOS transistor NM72.

[0149] The sixth NMOS transistor NM71 can be turned on in response to the application of the third activation signal PLSAEN to its gate; the first terminal of the sixth NMOS transistor NM71 can be connected to the second terminal of the fourth NMOS transistor NM69, and the second terminal of the sixth NMOS transistor NM71 can be connected to the first terminal of the second NMOS transistor NM67.

[0150] The seventh NMOS transistor NM72 can be turned on in response to the third activation signal PLSAEN being applied to its gate; the first terminal of the seventh NMOS transistor NM72 can be connected to the second terminal of the fifth NMOS transistor NM70 and the complementary global I / O line GIOB, and the second terminal of the seventh NMOS transistor NM72 can be connected to the first terminal of the third NMOS transistor NM68.

[0151] Figure 14 This is a circuit diagram used to explain the data flow when a read or write operation is performed on a memory cell. (The following is omitted as it has already been referenced.) Figure 8 The configuration description is provided.

[0152] The memory cell MC that is read or written to can be a volatile memory cell. For example, the memory cell MC can be implemented using a transistor NM80 (e.g., an NMOS transistor) and a cell capacitor Cs. The first terminal of the transistor NM80 in the memory cell MC can be connected to the bit line BL12, the gate can be connected to the word line WL, and the second terminal can be connected to the cell capacitor Cs. Figure 14 In this text, for ease of description, read or write operations on memory cells MC are referred to as... Figure 8 The bit line pairs BL12, BLB12, and bit line sense amplifier BLSA12 are shown and described, but reference is made to... Figure 14 The embodiments shown and described are not limited thereto, and can also be applied to read or write operations performed using any bit line pair within the memory device and bit line sense amplifiers connected to the bit line pair.

[0153] The bit-line sense amplifier BLSA12 may include a first NMOS transistor NM81, a second NMOS transistor NM82, a first PMOS transistor PM81, and a second PMOS transistor PM82. The bit-line sense amplifier BLSA12 can detect (or sense) and amplify signals from memory cells MC.

[0154] The first terminal of the first NMOS transistor NM81 can be connected to the bit line BL12, the second terminal of the first NMOS transistor NM81 can be connected to the ground voltage line, and the gate of the first NMOS transistor NM81 can be connected to the complementary bit line BLB12.

[0155] The first terminal of the second NMOS transistor NM82 can be connected to the complementary bit line BLB12, the second terminal of the second NMOS transistor NM82 can be connected to the ground voltage line and the second terminal of the first NMOS transistor NM81, and the gate of the second NMOS transistor NM82 can be connected to the bit line BL12.

[0156] The first terminal of the first PMOS transistor PM81 can be connected to the bit line BL12, the second terminal of the first PMOS transistor PM81 can be connected to the internal power supply voltage, and the gate of the first PMOS transistor PM81 can be connected to the complementary bit line BLB12.

[0157] The first terminal of the second PMOS transistor PM82 can be connected to the complementary bit line BLB12, the second terminal of the second PMOS transistor PM82 can be connected to the internal power supply voltage and the second terminal of the first PMOS transistor PM81, and the gate of the second PMOS transistor PM82 can be connected to the bit line BL12.

[0158] In the operation of these transistors, the voltage of the unit capacitor Cs can be transmitted to bit line BL12 through transistor NM80, and NMOS transistors NM81, NM82 and PMOS transistors PM81, PM82 can amplify or regenerate the small potential difference applied to bit line pairs BL12, BLB12, thereby supporting the reading or writing of stored data.

[0159] In one embodiment, the I / O sense amplifier 170 may include a plurality of NMOS transistors NM91 to NM97 and a plurality of PMOS transistors PM91 to PM92. The I / O sense amplifier 170 is not limited to... Figure 14 The structure shown is different and can be implemented differently in various embodiments.

[0160] The first terminal of the first NMOS transistor NM91 can be connected to the global I / O line GIO and a terminal (e.g., the second terminal) of the NMOS transistor NM64. The second terminal of the first NMOS transistor NM91 can be connected to the second terminal of the second NMOS transistor NM92 and the precharge voltage line VINTLP. The gate of the first NMOS transistor NM91 can be connected to the global precharge control signal line GIOPR.

[0161] The first terminal of the second NMOS transistor NM92 can be connected to the complementary global I / O line GIOB, the second terminal of the second NMOS transistor NM92 can be connected to the second terminal of the first NMOS transistor NM91 and the precharge voltage line VINTLP, and the gate of the second NMOS transistor NM92 can be connected to the global precharge control signal line GIOPR.

[0162] The first terminal of the third NMOS transistor NM93 can be connected to the global I / O line GIO, the second terminal of the third NMOS transistor NM93 can be connected to the complementary global I / O line GIOB, and the gate of the third NMOS transistor NM93 can be connected to the global precharge control signal line GIOPR.

[0163] The gates of the fourth NMOS transistor NM94 and the fifth NMOS transistor NM95 can each be connected to the global I / O pass line GIO_PASS, and in response to the global I / O pass line GIO_PASS, the fourth NMOS transistor NM94 and the fifth NMOS transistor NM95 are turned on, and data can be transmitted to the DQ line through the global I / O line pairs GIO and GIOB.

[0164] The sixth NMOS transistor NM96, the seventh NMOS transistor NM97, the first PMOS transistor PM91, and the second PMOS transistor PM92 can amplify the signals of GIO and GIOB on the global I / O lines through a cross-coupling structure, and can also transmit data to the DQ line (data path).

[0165] Use reference Figure 14 The circuit shown and described allows for the execution of read or write operations on memory cell MC.

[0166] Refer to together Figure 8 and Figure 14In response to the initiation of a read operation on the memory cell MC connected to the first line pairs BL12 and BLB12, the bit line sense amplifier BLSA12 connected to the first line pairs BL12 and BLB12 can sense and amplify the data stored in the memory cell MC, and can transmit the sensed and amplified data to the common local sense amplifier 810 through the first local I / O line pairs LIO1 and LIOB1 and the common local I / O line pairs LIO_COM and LIOB_COM. The common local sense amplifier 810 can amplify the voltage difference of the common local I / O line pairs LIO_COM and LIOB_COM, and can transmit the data corresponding to the amplified voltage difference to the I / O sense amplifier 170 through the global I / O line pairs GIO and GIOB. At this time, in response to the initiation of a read operation for the memory cell MC, multiple switching elements TG11 to TG14 and TG21 to TG24 can electrically connect the common local I / O line pair LIO_COM and LIOB_COM to the first local I / O line pair LIO1 and LIOB1, and can electrically isolate the common local I / O line pair LIO_COM and LIOB_COM from the second local I / O line pair LIO2 and LIOB2.

[0167] Refer to together Figure 8 and Figure 14 When a write operation is performed on a memory cell MC, global I / O drivers 183 (e.g., GIO drivers) and 185 (e.g., complementary global I / O (GIOB) drivers) can receive write data for the memory cell connected to the first line pairs BL12 and BLB12, and can transmit the received write data to a common local sense amplifier 810 via the global I / O lines GIO and GIOB. The common local sense amplifier 810 can transmit the received write data to a bit line sense amplifier BLSA12 via the common local I / O lines LIO_COM and LIOB_COM and the first local I / O lines LIO1 and LIOB1. The bit line sense amplifier BLSA12 can deliver the write data to the memory cell MC via the first line pairs BL12 and BLB12, such that the write data is written into the memory cell MC connected to the first line pairs BL12 and BLB12. In response to the initiation of a write operation for memory cell MC, multiple switching elements TG11 to TG14 and TG21 to TG24 can electrically connect the common local I / O line pair LIO_COM and LIOB_COM to the first local I / O line pair LIO1 and LIOB1, and can electrically isolate the common local I / O line pair LIO_COM and LIOB_COM from the second local I / O line pair LIO2 and LIOB2.

[0168] Figure 15This is an exemplary waveform diagram showing the level changes and timing relationships of the master control signal during a read operation in a circuit according to an embodiment of the present disclosure. Figure 15 The level of the main control signal shown in the figure can be determined by a memory device (e.g., Figure 1 The control logic circuit of item 100 (e.g., Figure 1 Item 150) is controlled. Although Figure 15 The execution of a read operation for some memory cells connected to bit lines is shown and described, but this also applies to the execution of a read operation for any memory cell within the memory device.

[0169] Reference Figure 8 , Figure 11 and Figure 15 In response to the receipt of an Activate (ACT) command, a specific row of the cell array can be activated, and the corresponding block select signal can be applied at a high level. For example, in Figure 15 In this configuration, the first block selection signal Binfo1 can be applied high to switching elements TG11 and TG12, and the second block selection signal Binfo2 can be applied low to switching elements TG21 and TG22. That is, the block selection signals Binfo1 and Binfo2 can be configured to indicate the sub-cell array and / or sub-row decoder to be read in the current read operation cycle; the data path for the selected sub-cell array (e.g., a path connecting the common local I / O pairs of the relevant sub-cell array to the global I / O pairs) can be electrically connected, and the data paths for other sub-cell arrays can be electrically isolated.

[0170] In response to the receipt of the ACT command, the relevant bit line sense amplifier can be activated, and the bit line sense amplifier can sense and amplify the data inside the memory cell through the bit line pairs.

[0171] Reference Figure 8 , Figure 14 and Figure 15 Then when the column selection signal CSL (e.g., Figure 8 When CSL12 is activated, the bit line pairs BL12 and BLB12 of the selected column and the local I / O line pairs LIO1 and LIOB1 can be connected, and the activation signals PLSAEN and PCLSAEN of the local sense amplifier 810 can be applied to operate the local sense amplifier 810, amplifying the voltage difference appearing on the local I / O line pairs LIO1 and LIOB1. Conversely, the signals of the unconnected local I / O line pairs LIO2 and LIOB2 can be held low.

[0172] When the connection control signal PMUXON of the switching circuit 820 is switched to a high level, the signal amplified by the local sensing amplifier 810 can be transmitted to the global I / O pairs GIO and GIOB through the common local I / O lines LIO_COM and LIOB_COM. Figure 15 As shown, during a read operation, after the global I / O pass line GIO_PASS is applied high, the I / O sense amplifier activation signal IOSA_EN and the global precharge control signal line GIOPR that activate the I / O sense amplifier 170 are sequentially applied high. This allows the I / O sense amplifier 170 to amplify the signals of the global I / O line pairs GIO and GIOB. Therefore, the control signals described above cooperate during the read operation to generate a stable read data voltage on the global I / O line pairs GIO and GIOB, and the read data can be output externally.

[0173] Figure 16 This is an exemplary waveform diagram showing the level changes and timing relationships of the master control signal during a write operation in a circuit according to an embodiment of the present disclosure. Figure 16 The level of the main control signal shown in the figure can be determined by a memory device (e.g., Figure 1 The control logic circuit of item 100 (e.g., Figure 1 Item 150) is controlled. Despite Figure 16 The execution of write operations for some memory cells connected to bit lines is shown and described, but this also applies to the execution of write operations for any memory cell within the memory device.

[0174] Reference Figure 8 , Figure 11 and Figure 16 In response to the receipt of the ACT command, a specific row of the cell array can be activated, and the corresponding block selection signal can be applied at a high level. For example, in Figure 16 In this configuration, the first block selection signal Binfo1 can be applied high to switching elements TG11 and TG12, and the second block selection signal Binfo2 can be applied low to switching elements TG21 and TG22. That is, the block selection signals Binfo1 and Binfo2 can be configured to indicate the sub-cell array and / or sub-row decoder to which a write operation will be performed in the current write operation cycle; the data path for the selected sub-cell array (e.g., a path connecting the common local I / O pairs of the relevant sub-cell array to the global I / O pairs) can be electrically connected, and the data paths for other sub-cell arrays can be electrically isolated.

[0175] Reference Figure 14 and Figure 16At the start of the cycle, the path of the selected sub-cell array is set via block select signals Binfo1 and Binfo2, and then global I / O is applied at a high level via line GIO_PASS to activate the global I / O drivers 183 and 185 of the memory bank. Therefore, the voltage levels of the global I / O lines GIO and GIOB can be split and changed according to the input data DQ.

[0176] The connection control signal PMUXON can be switched high to connect the global I / O pairs GIO and GIOB to the common local I / O pairs LIO_COM and LIOB_COM.

[0177] After the connection control signal PMUXON is switched to a low level, the activation signals PLSAEN and PCLSAEN of the local sense amplifier 810 can be applied at high and low levels respectively, thereby activating the transistors whose gates are applied by the activation signals PLSAEN and PCLSAEN.

[0178] When the column selection signal CSL (e.g., Figure 8 When CSL12 is applied high, write data prepared on local I / O pairs LIO1 and LIOB1 via the common local I / O pairs LIO_COM and LIOB_COM can be written to the memory cell via the selected column bit pairs BL12 and BLB12. After the write operation is complete, the column select signal CSL can return to low to disconnect the bit pairs from the local I / O pairs LIO1 and LIOB1. Through the series of signal operations described above, during the write operation, the input data is ultimately written to the memory cell, and no unused paths or circuits are blocked by appropriate signals (e.g., Binfo2), thereby preventing operational interference.

[0179] Figure 17 It is shown as Figure 4 The diagram shows examples of sub-peripheral circuits SPC4 to SPC8, which are part of the peripheral circuit CCC. Figure 18 This is a diagram showing in more detail the circuit structure set in the sub-peripheral circuits SPC4 to SPC8.

[0180] Reference Figure 4 and Figure 17 Each of the sub-peripheral circuits SPC4 to SPC8 can be connected to Figure 4 The circuitry of any one of the sub-cell arrays SCA of the memory cell array 110. Each of the sub-peripheral circuits SPC4 to SPC8 may be positioned above or below the corresponding sub-cell array connected to the sub-peripheral circuits SPC4 to SPC8 (e.g., in the +Z or -Z direction).

[0181] Each of the sub-peripheral circuits SPC4 to SPC8 may include a corresponding bit line sense amplifier region BLSA_O4 to BLSA_O7, a corresponding bit line sense amplifier region BLSA_E5 to BLSA_E8, a sub-word line driver region SWD, a connection region CONJ, and an empty region NULL.

[0182] Each of the bit-line sense amplifier regions BLSA_O4 to BLSA_O7 and BLSA_E5 to BLSA_E8 can be connected to a sub-cell array connected to the corresponding sub-peripheral circuits SPC4 to SPC8.

[0183] Each of the line sense amplifier regions BLSA_O4 to BLSA_O7 and BLSA_E5 to BLSA_E8 may include multiple bit line sense amplifiers. Each of the bit line sense amplifier regions BLSA_O4 to BLSA_O7 and BLSA_E5 to BLSA_E8 may be connected to the subcell array via bit line pairs BL and BLB disposed adjacent to the respective bit line sense amplifier region.

[0184] Each of the sub-peripheral circuits SPC4 through SPC8 may include two bit line sense amplifier regions. For example, each of the sub-peripheral circuits SPC4 through SPC8 may include a corresponding bit line sense amplifier region BLSA_O4 through BLSA_O7 and a corresponding bit line sense amplifier region BLSA_E5 through BLSA_E8. Bit line sense amplifier regions BLSA_O4 through BLSA_O7 include bit line sense amplifiers connected to odd-numbered bit line pairs, and bit line sense amplifier regions BLSA_E5 through BLSA_E8 include bit line sense amplifiers connected to even-numbered bit line pairs. Each of the bit line sense amplifier regions BLSA_O4 through BLSA_O7 or each of the bit line sense amplifier regions BLSA_E5 through BLSA_E8 may include multiple bit line sense amplifiers connected to even-numbered (or odd-numbered) bit lines. Each of the multiple bit line sense amplifiers can be connected to the sub-cell array via a corresponding bit line pair.

[0185] In one example, among adjacent sub-peripheral circuits SPC4 to SPC8, bit line sense amplifier regions including bit line sense amplifiers connected to even-numbered bit line pairs can be arranged adjacent to each other, or bit line sense amplifier regions including bit line sense amplifiers connected to odd-numbered bit line pairs can be arranged adjacent to each other. For example, the bit line sense amplifier region BLSA_O4 of the fourth sub-peripheral circuit SPC4, including bit line sense amplifiers connected to odd-numbered bit line pairs, and the bit line sense amplifier region BLSA_O5 of the fifth sub-peripheral circuit SPC5, including bit line sense amplifiers connected to odd-numbered bit line pairs, can be arranged adjacent to each other. Figure 17 Conversely, in another embodiment, the bit line sense amplifier region (not shown) in the fourth sub-peripheral circuit SPC4 connected to even-numbered bit line pairs and the bit line sense amplifier region BLSA_E5 in the fifth sub-peripheral circuit SPC5 connected to even-numbered bit line pairs may be arranged adjacent to each other.

[0186] For each of the sub-word line driver region (SWD), connection region (CONJ), and empty region (NULL) of the sub-peripheral circuits (SPC4 to SPC8), refer to the above. Figure 7 The described embodiments of the sub-word line driver region (SWD), connection region (CONJ), and empty region (NULL) for the sub-peripheral circuits (SPC1 to SPC2) are as follows: Figure 7 The same applies as shown in the diagram.

[0187] Reference Figure 18 Within the empty region NULL, local I / O line pairs LIO_O4 to LIO_O7, LIOB_O4 to LIOB_O7, LIO_E5 to LIO_E8, LIOB_E5 to LIOB_E8, common local I / O line pairs LIO_COM_E, LIOB_COM_E, LIO_COM_O, LIOB_COM_O, multiple switching elements TG31 to TG38, a common local sense amplifier, and switching circuitry can be configured. However, the configuration is not limited to this, and some components or portions of specific components may be located outside the empty region NULL.

[0188] Local I / O line pairs LIO_O4 and LIOB_O4 can be electrically connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_O4 of the fourth sub-peripheral circuit SPC4. For example, local I / O line pairs LIO_O4 and LIOB_O4 can be electrically connected to a bit line pair connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_O4.

[0189] Local I / O line pairs LIO_O5 and LIOB_O5 can be electrically connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_O5 of the fifth sub-peripheral circuit SPC5. For example, local I / O line pairs LIO_O5 and LIOB_O5 can be electrically connected to a bit line pair connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_O5.

[0190] Local I / O line pairs LIO_E5 and LIOB_E5 can be electrically connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_E5 of the fifth sub-peripheral circuit SPC5. For example, local I / O line pairs LIO_E5 and LIOB_E5 can be electrically connected to a bit line pair connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_E5.

[0191] Local I / O line pairs LIO_E6 and LIOB_E6 can be electrically connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_E6 of the sixth sub-peripheral circuit SPC6. For example, local I / O line pairs LIO_E6 and LIOB_E6 can be electrically connected to a bit line pair connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_E6.

[0192] Local I / O line pairs LIO_O6 and LIOB_O6 can be electrically connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_O6 of the sixth sub-peripheral circuit SPC6. For example, local I / O line pairs LIO_O6 and LIOB_O6 can be electrically connected to a bit line pair connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_O6.

[0193] Local I / O line pairs LIO_O7 and LIOB_O7 can be electrically connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_O7 of the seventh sub-peripheral circuit SPC7. For example, local I / O line pairs LIO_O7 and LIOB_O7 can be electrically connected to a bit line pair connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_O7.

[0194] Local I / O line pairs LIO_E7 and LIOB_E7 can be electrically connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_E7 of the seventh sub-peripheral circuit SPC7. For example, local I / O line pairs LIO_E7 and LIOB_E7 can be electrically connected to a bit line pair connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_E7.

[0195] Local I / O line pairs LIO_E8 and LIOB_E8 can be electrically connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_E8 of the eighth sub-peripheral circuit SPC8. For example, local I / O line pairs LIO_E8 and LIOB_E8 can be electrically connected to a bit line pair connected to the bit line sense amplifier in the bit line sense amplifier region BLSA_E8.

[0196] The aforementioned local I / O line pairs LIO_O4 to LIO_O7, LIOB_O4 to LIOB_O7, LIO_E5 to LIO_E8, and LIOB_E5 to LIOB_E8 can be referenced above. Figure 8 The bit line sense amplifiers are connected in the same manner in the described embodiments. For example, a column select transistor whose gate receives a column select signal can be connected between each of the local I / O line pairs LIO_O4 to LIO_O7, LIOB_O4 to LIOB_O7, LIO_E5 to LIO_E8, and LIOB_E5 to LIOB_E8 and the corresponding bit line sense amplifier. The local I / O line pair and the bit line sense amplifier can be electrically connected in response to the conduction of the column select transistor corresponding to the bit line sense amplifier.

[0197] Local I / O line pairs LIO_O4 to LIO_O7, LIO_O4 to LIO_O7 and LIO_E5 to LIO_E8, LIO_E5 to LIO_E8 may include local I / O lines LIO_O4 to LIO_O7, LIO_E5 to LIO_E8 and complementary local I / O lines LIO_O4 to LIO_O7, LIO_E5 to LIO_E8. Each of the local I / O lines LIO_O4 to LIO_O7, LIO_E5 to LIO_E8 may be connected to a bit line, and each of the complementary local I / O lines LIO_O4 to LIO_O7, LIO_E5 to LIO_E8 may be connected to a complementary bit line.

[0198] The first common local I / O line pairs LIO_COM_E and LIOB_COM_E can be connected to local I / O line pairs LIO_E5 to LIO_E8 and LIOB_E5 to LIOB_E8. The first common local I / O line pairs LIO_COM_E and LIOB_COM_E may include a first common local I / O line LIO_COM_E and a first complementary common local I / O line LIOB_COM_E. The first common local I / O line LIO_COM_E can be connected to local I / O lines LIO_E5 to LIO_E8, and the first complementary common local I / O line LIOB_COM_E can be connected to complementary local I / O lines LIOB_E5 to LIOB_E8. The bit line sense amplifier connected to the local I / O line pairs LIO_E5 to LIO_E8 and LIOB_E5 to LIOB_E8 can be connected to a bit line pair that is all even-numbered (or all odd-numbered).

[0199] Multiple switching elements TG31 to TG34 can electrically connect the first common local I / O line pair LIO_COM_E, LIOB_COM_E to any one of the local I / O line pairs LIO_E5 to LIO_E8, LIOB_E5 to LIOB_E8, and can electrically isolate the first common local I / O line pair LIO_COM_E, LIOB_COM_E from the remaining portions of the local I / O line pairs LIO_E5 to LIO_E8, LIOB_E5 to LIOB_E8.

[0200] For example, the multiple switching elements TG31 to TG34 may include multiple first switching elements TG31 connected to local I / O line pairs LIO_E7 and LIOB_E7, multiple second switching elements TG32 connected to local I / O line pairs LIO_E8 and LIOB_E8, multiple third switching elements TG33 connected to local I / O line pairs LIO_E6 and LIOB_E6, and multiple fourth switching elements TG34 connected to local I / O line pairs LIO_E5 and LIOB_E5.

[0201] Multiple first switching elements TG31 can be turned on in response to the initiation of a read or write operation on the sub-cell array connected to the seventh sub-peripheral circuit SPC7, and can be turned off in response to the initiation of a read or write operation on the sub-cell array connected to the fifth sub-peripheral circuit SPC5, the sixth sub-peripheral circuit SPC6, and the eighth sub-peripheral circuit SPC8.

[0202] Multiple second switching elements TG32 can be turned on in response to the initiation of a read or write operation on the sub-cell array connected to the eighth sub-peripheral circuit SPC8, and can be turned off in response to the initiation of a read or write operation on the sub-cell array connected to the fifth sub-peripheral circuit SPC5, the sixth sub-peripheral circuit SPC6, and the seventh sub-peripheral circuit SPC7.

[0203] Multiple third switching elements TG33 can be turned on in response to the initiation of a read or write operation on the sub-cell array connected to the sixth sub-peripheral circuit SPC6, and can be turned off in response to the initiation of a read or write operation on the sub-cell array connected to the fifth sub-peripheral circuit SPC5, the seventh sub-peripheral circuit SPC7, and the eighth sub-peripheral circuit SPC8.

[0204] Multiple fourth switching elements TG34 can be turned on in response to the initiation of a read or write operation on the sub-cell array connected to the fifth sub-peripheral circuit SPC5, and can be turned off in response to the initiation of a read or write operation on the sub-cell array connected to the sixth sub-peripheral circuit SPC6, the seventh sub-peripheral circuit SPC7, and the eighth sub-peripheral circuit SPC8.

[0205] The second common local I / O line pair LIO_COM_O and LIOB_COM_O can be connected to local I / O line pairs LIO_O4 to LIO_O7 and LIOB_O4 to LIOB_O7. The second common local I / O line pair LIO_COM_O and LIOB_COM_O may include a second common local I / O line LIO_COM_O and a second complementary common local I / O line LIOB_COM_O. The second common local I / O line LIO_COM_O can be connected to local I / O lines LIO_O4 to LIO_O7, and the second complementary common local I / O line LIOB_COM_O can be connected to complementary local I / O lines LIOB_O4 to LIOB_O7. The bit line sense amplifier connected to the local I / O line pairs LIO_O4 to LIO_O7 and LIOB_O4 to LIOB_O7 can be connected to a bit line pair that is entirely odd-numbered (or entirely even-numbered).

[0206] Multiple switching elements TG35 to TG38 can electrically connect the second common local I / O line pair LIO_COM_O, LIOB_COM_O to any one of the local I / O line pairs LIO_O4 to LIO_O7, LIOB_O4 to LIOB_O7, and can electrically isolate the second common local I / O line pair LIO_COM_O, LIOB_COM_O from the remaining portions of the local I / O line pairs LIO_O4 to LIO_O7, LIOB_O4 to LIOB_O7.

[0207] For example, the multiple switching elements TG35 to TG38 may include multiple fifth switching elements TG35 connected to local I / O line pairs LIO_O4 and LIOB_O4, multiple sixth switching elements TG36 connected to local I / O line pairs LIO_O5 and LIOB_O5, multiple seventh switching elements TG37 connected to local I / O line pairs LIO_O6 and LIOB_O6, and multiple eighth switching elements TG38 connected to local I / O line pairs LIO_O7 and LIOB_O7.

[0208] Multiple fifth switching elements TG35 can be turned on in response to the initiation of a read or write operation on the sub-cell array connected to the fourth sub-peripheral circuit SPC4, and can be turned off in response to the initiation of a read or write operation on the sub-cell array connected to the fifth sub-peripheral circuit SPC5, the sixth sub-peripheral circuit SPC6, and the seventh sub-peripheral circuit SPC7.

[0209] Multiple sixth switching elements TG36 can be turned on in response to the initiation of a read or write operation on the sub-cell array connected to the fifth sub-peripheral circuit SPC5, and can be turned off in response to the initiation of a read or write operation on the sub-cell array connected to the fourth sub-peripheral circuit SPC4, the sixth sub-peripheral circuit SPC6, and the seventh sub-peripheral circuit SPC7.

[0210] Multiple seventh switching elements TG37 can be turned on in response to the initiation of a read or write operation on the sub-cell array connected to the sixth sub-peripheral circuit SPC6, and can be turned off in response to the initiation of a read or write operation on the sub-cell array connected to the fourth sub-peripheral circuit SPC4, the fifth sub-peripheral circuit SPC5, and the seventh sub-peripheral circuit SPC7.

[0211] Multiple eighth switching elements TG38 can be turned on in response to the initiation of a read or write operation on the sub-cell array connected to the seventh sub-peripheral circuit SPC7, and can be turned off in response to the initiation of a read or write operation on the sub-cell array connected to the fourth sub-peripheral circuit SPC4, the fifth sub-peripheral circuit SPC5, and the sixth sub-peripheral circuit SPC6.

[0212] The multiple switching elements TG31 to TG38 may include transmission gate circuits. The multiple switching elements TG31 to TG38 may be related to the above-mentioned reference. Figure 11 The described embodiments are implemented in the same way.

[0213] Each of the first common local I / O line pairs LIO_COM_E, LIOB_COM_E and the second common local I / O line pairs LIO_COM_O, LIOB_COM_O can be connected to a common local sense amplifier and a switching circuit. The common local sense amplifier and switching circuit connected to the first common local I / O line pairs LIO_COM_E, LIOB_COM_E and the second common local I / O line pairs LIO_COM_O, LIOB_COM_O can be referenced above. Figure 8 , Figure 10 and Figure 12 The described common local sensing amplifier embodiment and switching circuit embodiment are implemented identically, or alternatively may be implemented with reference to the above. Figure 13 The described circuit structure is implemented in the same way.

[0214] For example, a common local sense amplifier connected to each of the first common local I / O line pairs LIO_COM_E, LIOB_COM_E and the second common local I / O line pairs LIO_COM_O, LIOB_COM_O can amplify the voltage level transmitted from each of the first common local I / O line pairs LIO_COM_E, LIOB_COM_E and the second common local I / O line pairs LIO_COM_O, LIOB_COM_O, and can transmit the amplified level to the I / O sense amplifier 170 via the global I / O line pairs GIO, GIOB. Switching circuits connected to each of the first and second common local I / O line pairs can electrically connect the common local sense amplifier and the global I / O line pairs GIO, GIOB in response to the initiation of a read or write operation for the sub-cell array.

[0215] Global I / O line pairs GIO and GIOB can include a global I / O line GIO and a complementary global I / O line GIOB. The global I / O line GIO can be connected to the common local I / O lines LIO_COM_E and LIO_COM_O, and the complementary global I / O line GIOB can be connected to the complementary common local I / O lines LIOB_COM_E and LIOB_COM_O.

[0216] The I / O sense amplifier 170 can be electrically connected to the global I / O line pairs GIO and GIOB.

[0217] Although reference Figure 17 and Figure 18 An embodiment in which four local I / O lines are connected to a common local I / O line is shown and described, but this disclosure is not limited thereto. For example, (2) n A total of 10 local I / O lines (where n is a natural number) can be connected to a common local I / O line.

[0218] By reference Figure 17 and Figure 18 The circuit structures shown and described allow for further reduction of parasitic resistance and / or capacitance associated with global I / O line pairs GIO and GIOB, further reducing bottlenecks in data transfer using these pairs, and further improving data transfer speed by reducing the load on the global I / O line pairs GIO and GIOB. Data transfer speed can also be further improved because the transistor size of the common local sense amplifier and / or switching circuitry can be further increased within the same device layout area.

[0219] Reference Figure 17 and Figure 18 The circuit structures shown and described can be arranged in a repeating pattern for peripheral circuits. For example, refer to Figure 17 and Figure 18 The circuit structure shown and described can be found in Figure 4 The peripheral circuitry of the CCC is repeatedly arranged in the X and Y directions.

[0220] This disclosure is not limited to the above embodiments and drawings, and those skilled in the art can make various substitutions, modifications and changes without departing from the technical spirit of this disclosure, and such substitutions, modifications and changes are also within the scope of this disclosure.

Claims

1. A memory device, comprising: The cell array includes a first sub-cell array and a second sub-cell array; The first line sensing amplifier is connected to the first sub-unit array; The second bit-line sensing amplifier is connected to the second sub-unit array; The first local input / output line pair is electrically connected to the first line pair connected to the first line sense amplifier; The second local input / output line pair is electrically connected to the second bit line pair connected to the second bit line sense amplifier; A common local input / output pair is connected to the first local input / output pair and the second local input / output pair; A common local sensing amplifier is configured to amplify the voltage level transmitted from the common local input / output line pair; Global input / output pairs are connected to a common local sense amplifier; and Input / output sense amplifier, electrically connected to the global input / output line pair.

2. The memory device of claim 1, wherein, A common local sensing amplifier is disposed between a first group of bit line sensing amplifiers and a second group of bit line sensing amplifiers. The first group of bit line sensing amplifiers includes a first bit line sensing amplifier and is connected to a first sub-cell array. The second group of bit line sensing amplifiers includes a second bit line sensing amplifier and is connected to a second sub-cell array.

3. The memory device of claim 1, wherein, The common local input / output line pair includes a common local input / output line and complementary common local input / output lines, and the common local sense amplifier includes: A first N-channel metal-oxide-semiconductor transistor has a first terminal connected to a common local input / output line and a gate connected to a complementary common local input / output line; The second N-channel metal-oxide-semiconductor transistor has a first terminal connected to a complementary common local input / output line, a second terminal connected to a second terminal of the first N-channel metal-oxide-semiconductor transistor, and a gate connected to the common local input / output line; The third N-channel metal-oxide-semiconductor transistor is configured to be turned on in response to a first activation signal applied to the gate of the third N-channel metal-oxide-semiconductor transistor, the third N-channel metal-oxide-semiconductor transistor having a first terminal connected to a ground voltage line and a second terminal connected to the second terminals of the first N-channel metal-oxide-semiconductor transistor and the second N-channel metal-oxide-semiconductor transistor. A first P-channel metal-oxide-semiconductor transistor has a first terminal connected to a common local input / output line and a gate connected to a complementary common local input / output line; A second P-channel metal-oxide-semiconductor transistor has a first terminal connected to a complementary common local input / output line, a second terminal connected to a second terminal of a first P-channel metal-oxide-semiconductor transistor, and a gate connected to the common local input / output line; and The third P-channel metal-oxide-semiconductor transistor is configured to be turned on in response to a second activation signal applied to the gate of the third P-channel metal-oxide-semiconductor transistor. The third P-channel metal-oxide-semiconductor transistor has a first terminal connected to an internal power line and a second terminal connected to the second terminals of the first P-channel metal-oxide-semiconductor transistor and the second P-channel metal-oxide-semiconductor transistor.

4. The memory device of claim 1, further comprising: The switching circuit is configured to electrically connect the common local sense amplifier and the global input / output line pair in response to the initiation of a read or write operation for the first sub-array or the second sub-array.

5. The memory device of claim 4, wherein, Common local input / output pairs include common local input / output lines and complementary common local input / output lines. Global input / output pairs include global input / output lines and complementary global input / output lines, and The switching circuit includes: A first transistor, configured to turn on in response to the initiation of the read operation or the write operation, has a first terminal connected to a common local input / output line and a second terminal connected to a global input / output line; and The second transistor is configured to turn on in response to the initiation of the read operation or the write operation, and the second transistor has a first terminal connected to a complementary common local input / output line and a second terminal connected to a complementary global input / output line.

6. The memory device of claim 1, further comprising: Multiple switching elements are configured to electrically connect a common local input / output pair to one of the first local input / output pairs and the second local input / output pairs, and to electrically isolate the common local input / output pair from the other of the first local input / output pairs and the second local input / output pairs.

7. The memory device of claim 6, wherein, The plurality of switching elements includes: a plurality of first switching elements connected to a first local input / output pair; and a plurality of second switching elements connected to a second local input / output pair. The plurality of first switching elements are configured to be turned on in response to the initiation of a read or write operation on the first sub-cell array, and to be turned off in response to the initiation of a read or write operation on the second sub-cell array. The plurality of second switching elements are configured to be turned on in response to the initiation of a read operation or write operation for the second sub-cell array, and to be turned off in response to the initiation of a read operation or write operation for the first sub-cell array.

8. The memory device of claim 1, wherein, The first line sense amplifier is configured to sense and amplify data stored in the memory cell in response to a read operation initiated for the memory cell connected to the first line pair, and to send the sensed and amplified data to the common local sense amplifier via the first local input / output line pair and the common local input / output line pair. The common local sensing amplifier is configured to amplify the voltage difference between the common local input / output line pairs and send data corresponding to the amplified voltage difference to the input / output sensing amplifier via the global input / output line pairs.

9. The memory device of claim 8, further comprising: Multiple switching elements are configured to electrically connect a common local input / output pair to a first local input / output pair and electrically isolate the common local input / output pair from a second local input / output pair in response to the initiation of a read operation for a memory cell connected to the first local input / output pair.

10. The memory device of claim 1, further comprising: The global input / output driver is configured to receive write data to a memory cell connected to the first bit line pair and to send the received write data to a common local sense amplifier via the global input / output line pair. The common local sensing amplifier is further configured to send the received write data to the first local sensing amplifier via the common local input / output line pair and the first local input / output line pair. The first line sense amplifier is configured to deliver write data to the memory cell via the first line pair, such that the write data is written to the memory cell connected to the first line pair.

11. The memory device of claim 10, further comprising: Multiple switching elements are configured to electrically connect a common local input / output pair to a first local input / output pair and electrically isolate the common local input / output pair from a second local input / output pair in response to the initiation of a write operation to a memory cell connected to the first local input / output pair.

12. The memory device according to any one of claims 1 to 11, wherein, The first bit pair and the second bit pair are bit pairs that are both even-numbered or both odd-numbered.

13. The memory device of claim 1, wherein, The cell array further includes: a third sub-cell array and a fourth sub-cell array, and the memory device further includes: The third bit-line sensing amplifier is connected to the third sub-unit array; The fourth bit-line sensing amplifier is connected to the fourth sub-unit array; The third local input / output line pair is electrically connected to the third bit line pair connected to the third bit line sense amplifier; The fourth local input / output pair is electrically connected to the fourth bit line pair connected to the fourth bit line sense amplifier; and Multiple switching elements, The common local input / output pair is also connected to the third local input / output pair and the fourth local input / output pair, and the plurality of switching elements are configured to: electrically connect the common local input / output pair to one of the first local input / output pairs to the fourth local input / output pairs, and electrically isolate the common local input / output pair from the remaining portions of the first local input / output pairs to the fourth local input / output pairs.

14. The memory device of claim 13, wherein, The plurality of switching elements include: Multiple first switching elements are connected to first local input / output pairs. Multiple second switching elements are connected to the second local input / output pairs. Multiple third switching elements are connected to third local input / output pairs, and Multiple fourth switching elements are connected to the fourth local input / output pair, and The plurality of first switching elements are configured to be turned on in response to the initiation of a read or write operation for a first sub-cell array, and to be turned off in response to the initiation of a read or write operation for a second, third, or fourth sub-cell array. The plurality of second switching elements are configured to be turned on in response to the initiation of a read or write operation for the second sub-cell array, and to be turned off in response to the initiation of a read or write operation for the first, third, or fourth sub-cell array. The plurality of third switching elements are configured to be turned on in response to the initiation of a read or write operation on the third sub-cell array, and to be turned off in response to the initiation of a read or write operation on the first, second, or fourth sub-cell array. The plurality of fourth switching elements are configured to be turned on in response to the initiation of a read or write operation for the fourth sub-cell array, and to be turned off in response to the initiation of a read or write operation for the first sub-cell array, the second sub-cell array, or the third sub-cell array.

15. The memory device of claim 13, wherein, The first, second, third, and fourth line pairs are either all even-numbered line pairs or all odd-numbered line pairs.

16. A memory device, comprising: The cell array includes a first sub-cell array and a second sub-cell array; The first line sensing amplifier is connected to the first sub-unit array; The second bit-line sensing amplifier is connected to the second sub-unit array; The first local input / output line pair is electrically connected to the first line pair connected to the first line sense amplifier; The second local input / output line pair is electrically connected to the second bit line pair connected to the second bit line sense amplifier; A common local input / output pair is connected to a first local input / output pair and a second local input / output pair. The common local input / output pair includes a common local input / output line and a complementary common local input / output line. Multiple transmission gates are configured to: electrically connect a common local input / output pair to one of the first local input / output pairs and the second local input / output pairs, and electrically isolate the common local input / output pair from the other of the first local input / output pairs and the second local input / output pairs; A common local sensing amplifier is configured to amplify the voltage level transmitted from the common local input / output line pair; Global input / output pairs are connected to a common local sense amplifier; and Input / output sense amplifier, electrically connected to the global input / output line pair.

17. A peripheral circuit, comprising: The first line sensing amplifier is connected to the first sub-cell array of the cell array; The second bit-line sensing amplifier is connected to the second sub-cell array of the cell array; The first local input / output line pair is electrically connected to the first line pair connected to the first line sense amplifier; The second local input / output line pair is electrically connected to the second bit line pair connected to the second bit line sense amplifier; The first common local input / output pair is connected to the first local input / output pair and the second local input / output pair; The first common local sensing amplifier is configured to amplify the voltage level transmitted from the first common local input / output line pair; The global input / output pair is connected to the first common local sense amplifier; and Input / output sense amplifier, electrically connected to the global input / output line pair. The peripheral circuit is located below or above the unit array.

18. The peripheral circuit as described in claim 17, further comprising: The third bit-line sensing amplifier is connected to the second sub-unit array; The fourth bit-line sensing amplifier is connected to the third sub-cell array of the cell array; The third local input / output line pair is electrically connected to the third bit line pair connected to the third bit line sense amplifier; The fourth local input / output pair is electrically connected to the fourth bit line pair connected to the fourth bit line sense amplifier; The second common local input / output pair is connected to the third and fourth local input / output pairs, and The second common local sensing amplifier is configured to amplify the voltage level transmitted from the second common local input / output line pair. The global input / output line pair is also connected to the second common local sense amplifier.

19. The peripheral circuit as described in claim 18, wherein, The first and second bit pairs are both even-numbered bit pairs, and the third and fourth bit pairs are both odd-numbered bit pairs.

20. The peripheral circuit as described in claim 18, further comprising: A plurality of first switching elements are configured to: electrically connect a first common local input / output pair to one of the first local input / output pairs and the second local input / output pairs, and electrically isolate the first common local input / output pair from the other of the first local input / output pairs and the second local input / output pairs. Multiple second switching elements are configured to: electrically connect a second common local input / output pair to one of the third and fourth local input / output pairs, and electrically isolate the second common local input / output pair from the other of the third and fourth local input / output pairs.

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