A static random access memory, a pre-charge method for reducing leakage, a processor, a chip and an electronic device

Abstract

The embodiment of the application provides a static random access memory, a pre-charge method for reducing leakage, a processor, a chip and electronic equipment, which can be applied to the technical field of memory. The static random access memory comprises a plurality of read bit lines, a plurality of pre-charge lines, a plurality of first switch devices, a plurality of second switch devices and a plurality of storage units arranged in an array. The plurality of storage units in the same column are electrically connected with the same read bit line, and the plurality of storage units in the same row correspond to the same pre-charge line. Each storage unit corresponds to a first switch device, the first electrode of each first switch device is connected with the pre-charge line of the corresponding storage unit, and the second electrode is connected with the read bit line of the corresponding storage unit. Each pre-charge line also corresponds to a second switch device, the first electrode of each second switch device is connected with a power supply, and the second electrode is connected with the corresponding pre-charge line. The embodiment of the application can reduce the leakage phenomenon, reduce the leakage power consumption and improve the performance.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a static random access memory, a precharge method for reducing leakage current, a processor, a chip, and an electronic device. Background Technology

[0002] With the rapid development of static random access memory (SRAM) and user demands, the performance and power consumption of SRAM have attracted much attention. Among them, multi-port SRAM, with its independent read and write ports, meaning that it has separate ports and paths for both read and write operations, offers greater flexibility and often receives more attention.

[0003] To ensure the accuracy of each read operation, before performing a read operation on a multi-port static random access memory (SRAM), all read lines connected to all memory cells in the SRAM are often pre-charged, i.e., all read lines are pulled high. However, in SRAM, one read word line often corresponds to multiple read bit lines. During a read operation, when a read word line is activated, a leakage current loop is generated between each pre-charged read bit line and the read port of the corresponding memory cell. Therefore, in addition to the memory cells that need to read data, other memory cells that do not need to read data corresponding to the activated read word line will also have leakage current loops, resulting in too many leakage current loops in the memory, excessive power consumption, and affecting memory performance.

[0004] Therefore, how to provide a memory with low leakage current is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This application provides a static random access memory (SRAM), a pre-charging method for reducing leakage current, a processor, a chip, and an electronic device, which can reduce leakage current, lower leakage power consumption, and improve the performance of the SRAM.

[0006] In a first aspect, embodiments of this application provide a static random access memory (SRAM), including multiple read lines, multiple precharge lines, multiple first switching devices, multiple second switching devices, and multiple memory cells arranged in an array. Multiple memory cells in the same column are electrically connected to the same read line, and multiple memory cells in different columns of the same row are electrically connected to different read lines. Multiple memory cells in the same row correspond to the same precharge line, and multiple memory cells in different rows of the same column correspond to different precharge lines. Each memory cell corresponds to one of the first switching devices, with the first terminal of each first switching device connected to the precharge line of the corresponding memory cell, and the second terminal of the first switching device connected to the read line of the corresponding memory cell. Each precharge line also corresponds to one of the second switching devices, with the first terminal of each second switching device connected to a power supply, and the second terminal of the second switching device connected to the corresponding precharge line.

[0007] Currently, when a memory cell in a static random access memory (SRAM) performs a read operation, the existing pre-charge mechanism often has many redundant leakage loops, resulting in significant leakage power consumption and affecting the performance of the SRAM. To address this, this application provides a SRAM comprising multiple read lines, multiple pre-charge lines, multiple first switching devices, multiple second switching devices, and multiple memory cells arranged in an array. In this embodiment, independently configured pre-charge transistors are eliminated; only a global pre-charge mechanism is implemented, meaning that a row of memory cells shares a single pre-charge path (e.g., power supply - second switching device - pre-charge line). Each read line connected to the aforementioned memory cell is connected to its corresponding pre-charge line via the corresponding first switching device. Furthermore, a second switching device is also configured between the pre-charge line and the power supply. This connection method allows pre-charging of the read line connected to the first switching device when both the second switching device and the first switching device are simultaneously turned on; conversely, pre-charging is not possible when either the second switching device or the first switching device is turned off. Therefore, multiple read bit lines can be selectively precharged by controlling the on / off state of the first and second switching devices. For example, after receiving a read operation for any memory cell, the first switching device for that memory cell and the second switching device for the precharge line corresponding to the row containing that memory cell can be turned on. This allows precharging only the read bit line corresponding to that memory cell, without precharging the read bit lines corresponding to other memory cells in the same row. This ensures that when other memory cells are inactive, their corresponding read bit lines are also inactive, avoiding redundant leakage loops in memory cells that do not need to perform read operations after activating the read word line. This significantly reduces redundant leakage loops in the static random access memory, reduces leakage phenomena, lowers the overall leakage power consumption of the static random access memory, and improves performance.

[0008] In some possible implementations, a plurality of third switching devices are also included, wherein each of the aforementioned precharge lines is also electrically connected to the gate of a third switching device; the first terminal of each of the aforementioned third switching devices is grounded, and the second terminal is the output terminal of the third switching device.

[0009] In this embodiment of the application, after the read bit line connected to the memory cell to be read is precharged, the read operation can be performed. Therefore, the gate of the corresponding third switching device receives the level control on the precharge line, which causes the second pole of the third switching device to be in different level states according to the corresponding level control, thereby indicating that the data to be read is 0 or 1, so as to complete the read operation.

[0010] In some possible implementations, the aforementioned storage unit is a multi-port storage unit, wherein the multi-port storage unit includes at least a read port, and the read port of each of the aforementioned storage units is electrically connected to a corresponding read bit line.

[0011] In the embodiments of this application, the multi-port storage unit can read data from the storage unit individually through the read port, thereby enabling the static random access memory to have higher parallelism and flexibility.

[0012] In some possible implementations, the first switching device is an N-type metal-oxide-semiconductor field transistor (MOS) or a P-type MOS transistor.

[0013] In this embodiment, the first switching device is a transistor capable of rapid on / off switching, which can quickly pre-charge the read bit line, thereby improving the efficiency of the read operation and reducing the execution time of the read operation. Moreover, different types of transistors can be more flexibly applied to different circuit structures.

[0014] In some possible implementations, the second switching device is a P-type metal-oxide-semiconductor field transistor (MOS) or an N-type MOS transistor.

[0015] In this embodiment, the second switching device can be a P-type MOSFET or an N-type MOSFET; thus, in the global pre-charge mechanism, pre-charging is performed by charging the P-type MOSFET or N-type MOSFET to a high level, so as to flexibly adapt to various circuit connection scenarios.

[0016] In some possible implementations, the aforementioned static random access memory further includes a control circuit; the control circuit is configured to: when no read operation is received, control all first switching devices corresponding to the plurality of memory cells to remain off; the control circuit is further configured to: when a read operation is received for the first memory cell, control the second switching device corresponding to the first precharge line to turn on, and control the first switching device corresponding to the first memory cell to turn on, so as to precharge the first read bit line; the first memory cell is any one of the plurality of memory cells, the first precharge line is the precharge line corresponding to the first memory cell, and the first read bit line is the read bit line corresponding to the first memory cell.

[0017] In this embodiment of the application, the static random access memory may further include a control circuit, which can be used to control the switching device to turn on or off, thereby selectively precharging the read bit line corresponding to the memory cell to be read, without precharging the read bit line corresponding to other memory cells, reducing redundant leakage circuits in the memory cell, reducing the overall leakage power consumption of the static random access memory, and improving performance.

[0018] In some possible implementations, the control circuit is further configured to: after completing the read operation on the first storage cell, control the first switching device corresponding to the first storage cell to turn off.

[0019] In this embodiment of the application, after completing the read operation on the first storage unit, the control circuit can turn off the pre-charging of the read bit line to prevent the power supply from continuously charging the read bit line, thereby reducing power consumption.

[0020] Secondly, embodiments of this application also provide a pre-charge method for reducing leakage current, applied to a static random access memory (SRAM). The SRAM includes multiple read lines, multiple pre-charge lines, multiple first switching devices, multiple second switching devices, and multiple memory cells arranged in an array. Multiple memory cells in the same column are electrically connected to the same read line, and multiple memory cells in different columns of the same row are electrically connected to different read lines. Multiple memory cells in the same row correspond to the same pre-charge line, and multiple memory cells in different rows of the same column correspond to different pre-charge lines. Each memory cell corresponds to one of the first switching devices. The first terminal of each first switching device is connected to the pre-charge line of the corresponding memory cell, and the second terminal of the first switching device is connected to the read line of the corresponding memory cell. Each pre-charge line... Each line also corresponds to a second switching device, the first terminal of each second switching device is connected to a power supply, and the second terminal of the second switching device is connected to a corresponding precharge line; the method includes: when no read operation is received, controlling the first switching devices corresponding to the plurality of memory cells to remain off; receiving a read operation for the first memory cell; after receiving a read operation for the first memory cell, controlling the first switching device corresponding to the first memory cell to turn on from the plurality of memory cells, and controlling the second switching device corresponding to the first precharge line to turn on, so as to precharge the first read bit line; wherein the first memory cell is any one of the plurality of memory cells, the first precharge line is the precharge line corresponding to the first memory cell, and the first read bit line is the read bit line corresponding to the first memory cell.

[0021] In one possible implementation, the static random access memory further includes a plurality of third switching devices, wherein each of the aforementioned precharge lines is also electrically connected to the gate of a third switching device; the first terminal of each of the aforementioned third switching devices is grounded, and the second terminal is the output terminal of the third switching device.

[0022] In one possible implementation, the aforementioned storage unit is a multi-port storage unit, wherein the multi-port storage unit includes at least a read port, and the read port of each of the aforementioned storage units is electrically connected to a corresponding read bit line.

[0023] In one possible implementation, the first switching device is an N-type metal-oxide-semiconductor field transistor (MOS) or a P-type MOS transistor.

[0024] In one possible implementation, the second switching device is a P-type metal-oxide-semiconductor field transistor (MOS) or an N-type MOS transistor.

[0025] In one possible implementation, the method further includes: after completing the read operation on the first storage cell, controlling the first switching device corresponding to the first storage cell to turn off.

[0026] Thirdly, embodiments of this application provide a processor, including logic circuitry and a static random access memory as described in any of the first aspects, wherein the logic circuitry is electrically connected to the static random access memory.

[0027] Fourthly, embodiments of this application provide a chip including a stacked and packaged processor chip and a memory chip, wherein the processor chip and the memory chip are electrically connected, and the processor chip is the processor chip provided in the third aspect.

[0028] Fifthly, embodiments of this application provide an electronic device, which includes a circuit board and the processor provided according to the third aspect, wherein the circuit board is electrically connected to the processor.

[0029] In a sixth aspect, embodiments of this application provide an electronic device, which includes a circuit board and the chip provided according to the fourth aspect, wherein the circuit board and the chip are electrically connected.

[0030] It should be understood that the pre-charging method for reducing leakage provided in the second aspect of this application, the processor provided in the third aspect, the chip provided in the fourth aspect, the electronic device provided in the fifth aspect, and the electronic device provided in the sixth aspect are consistent with the technical solutions of the first aspect of this application. Their specific contents and beneficial effects can be referred to the static random access memory provided in the first aspect above, and will not be repeated here. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0032] Figure 1 This is a schematic diagram of the structure of an 8T storage unit provided in an embodiment of this application.

[0033] Figure 2 This is a schematic diagram of a storage array structure based on an 8T storage unit provided in an embodiment of this application.

[0034] Figure 3A This is a schematic diagram of the structure of a static random access memory provided in an embodiment of this application.

[0035] Figure 3B This is a schematic diagram of another static random access memory provided in an embodiment of this application.

[0036] Figure 4 This application provides a method based on... Figure 3A The timing diagram of the storage structure is shown.

[0037] Figure 5 This is a schematic flowchart of a pre-charging method for reducing leakage current provided in an embodiment of this application.

[0038] Figure 6 This is a schematic diagram of the structure of a processor provided in an embodiment of this application.

[0039] Figure 7 This is a schematic diagram of the structure of a chip provided in an embodiment of this application.

[0040] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0041] Figure 9 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application. Detailed Implementation

[0042] The embodiments of this application will now be described with reference to the accompanying drawings.

[0043] The terms "first," "second," and "third," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0044] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0045] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0046] First, to facilitate understanding of the embodiments of this application, the following detailed analysis addresses the technical problems to be solved and the applicable application scenarios of the embodiments of this application.

[0047] With the rapid development of memory and user demands, the performance and power consumption of multi-port SRAM, especially in Static Random-Access Memory (SRAM), have attracted much attention.

[0048] Currently, most memory cells in multi-port memories have an 8-transistor structure. Please refer to the appendix. Figure 1 , Figure 1 This is a schematic diagram of the structure of an 8T storage unit provided in an embodiment of this application. For example... Figure 1 As shown, the memory cell includes eight transistors, such as T1, T2, T3, T4, T5, T6, T7, and T8. During a read operation on the memory cell, the read word line RWL is activated, for example, by setting it to a high level. The read transistors T7 and T8 couple the storage transistors (i.e., T1, T2, T3, and T4) to the read bit line RBL, allowing the data stored in the storage transistors to be read via RBL.

[0049] In order to ensure the accuracy of each read operation, before performing a read operation on a multi-port memory, the read bit lines connected to all memory cells in the multi-port memory are often pre-charged, that is, pulled up to a high level.

[0050] Please refer to the attached document. Figure 2 , Figure 2 This is a schematic diagram of a storage array structure based on 8T storage cells provided in an embodiment of this application. Figure 2 As shown, multiple memory cells in the same row share a single read word line RWL, and each memory cell in the same row corresponds to a separate read bit line RBL. Before reading data from a memory cell or a portion of the memory cells in the row, a precharge transistor (not shown) is used to precharge all the read bit lines corresponding to the memory cells in the row. That is, each read bit line is precharged together, so that the read bit line corresponding to each memory cell in the row remains at a high level.

[0051] For example, such as Figure 2 As shown, before data is read from memory cell 00, the read lines corresponding to memory cells 00, 01, 02, and 03 all need to be pre-charged. At this time, since the memory cells in this row share a single read word line RWL, when all read lines are at a high level, all four memory cells will generate leakage loops (i.e., from the read line through T7 and T8 to ground), causing leakage and affecting memory performance. Furthermore, since the read operation is only performed on memory cell 00, keeping the read lines of the other memory cells at a high level is meaningless. Therefore, the read lines of the other three memory cells will not only have redundant leakage loops but also redundant pre-charge power consumption, resulting in excessive memory power consumption.

[0052] To address this issue, this application provides a static random access memory (SRAM) comprising multiple read lines, multiple precharge lines, multiple first switching devices, multiple second switching devices, and multiple memory cells arranged in an array. In this embodiment, independently configured precharge transistors are eliminated; only a global precharge mechanism is implemented, meaning that a row of memory cells shares a single precharge path (e.g., power supply - second switching device - precharge line). Each memory cell's read line is connected to its corresponding precharge line via the first switching device. Each precharge line is also connected to a corresponding second switching device. This connection allows the read line to be precharged when both the second and first switching devices are simultaneously active. Conversely, precharging is impossible when either the second or first switching device is deactivated. Therefore, selective precharging of multiple read lines can be achieved by controlling the on / off states of the first and second switching devices. For example, upon receiving a read operation for any memory cell, the first switching device of that memory cell and the second switching device of the precharge line corresponding to the row containing that memory cell can be turned on. This allows precharging to be performed only on the read bit line corresponding to that memory cell, without precharging the read bit lines corresponding to other memory cells in the same row. This ensures that when other memory cells are inactive, their corresponding read bit lines are also inactive, preventing redundant leakage circuits in other memory cells that do not require read operations after activating the read word line. This significantly reduces redundant leakage circuits in the static random access memory (SRAM), reduces leakage current, lowers the overall leakage power consumption of the SRAM, and improves performance. The specific structure of the SRAM can be further illustrated in the following embodiments.

[0053] Secondly, based on the technical problems mentioned above, and in order to facilitate understanding of the embodiments of this application, several static random access memories on which the embodiments of this application are based will be described below.

[0054] This application provides a static random access memory (SRAM) comprising multiple read lines, multiple precharge lines, multiple first switching devices, multiple second switching devices, and multiple memory cells arranged in an array. Multiple memory cells in the same column are electrically connected to the same read line, and multiple memory cells in different columns of the same row are electrically connected to different read lines. Multiple memory cells in the same row correspond to the same precharge line, and multiple memory cells in different rows of the same column correspond to different precharge lines. Each memory cell corresponds to a first switching device, with its first terminal connected to the precharge line of the corresponding memory cell and its second terminal connected to the read line of the corresponding memory cell. Each precharge line also corresponds to a second switching device, with its first terminal connected to a power supply and its second terminal connected to the corresponding precharge line.

[0055] Please refer to the attached document. Figure 3A , Figure 3A This is a schematic diagram of the structure of a static random access memory provided in an embodiment of this application, as shown below. Figure 3A As shown, the static random access memory (SRAM) may include multiple memory cells arranged in an array, such as: memory cells 00, 01, 02, and 03 in the first row; and memory cells 10, 11, 12, and 13 in the second row. It can be understood that... Figure 3A The illustration only shows eight storage units, but the static random access memory is not limited to these eight storage units. This application does not make any specific limitation on this embodiment.

[0056] like Figure 3A As shown, in this array of multiple storage cells (also referred to as a storage array), multiple storage cells in the same column are electrically connected to the same read bit line RBL, and multiple storage cells in different columns of the same row are electrically connected to different read bit lines RBL. Furthermore, multiple storage cells in the same row correspond to the same precharge line GBL, and multiple storage cells in different rows of the same column correspond to different precharge lines. For example, storage cells 00, 01, 02, and 03 in the first row can all correspond to the same precharge line GBL0 and be connected to the same read word line RWL0; storage cells 10, 11, 12, and 13 in the second row can all correspond to the same precharge line GBL1 and be connected to the same read word line RWL1. The storage cells 00 and 10 in the first column are connected to the same read line RBL0; the storage cells 01 and 11 in the second column are connected to the same read line RBL1; the storage cells 02 and 12 in the third column are connected to the same read line RBL2; and the storage cells 03 and 13 in the fourth column are connected to the same read line RBL3.

[0057] It should be noted that this storage unit can be called a bit storage unit, bit cell, etc. Each storage unit is used to store or write 1 bit of data. For example, each storage unit can be used to store or write "0" or "1".

[0058] In some embodiments, the storage unit is a multi-port storage unit or a dual-port storage unit, wherein the multi-port storage unit includes at least a read port, and the read port of each storage unit is electrically connected to a corresponding read bit line. Therefore, embodiments of this application can read data from the storage unit through the read port, thereby achieving higher parallelism and flexibility.

[0059] It should be noted that the structure of each storage unit can be as described above. Figure 1 The 8T storage cell structure shown, or other possible multi-port storage cell structures, are not specifically limited in this embodiment. Each storage cell has independent ports for reading and writing data. For example, when the storage cell is as described above... Figure 1 When the 8T storage cell structure shown is presented, the read port is as described above. Figure 1 The end of T7 shown is connected to the read line.

[0060] Each memory cell is equipped with a corresponding first switching device, which is connected between the read bit line and the precharge line of the corresponding memory cell. That is, the first terminal of each first switching device is connected to the precharge line of the corresponding memory cell, and the second terminal of the first switching device is connected to the read bit line of the corresponding memory cell. Figure 3A As shown, memory cell 00 corresponds to a switching device Y00. The first terminal of the switching device Y00 is connected to the precharge line GBL0, and the second terminal is connected to the read line RBL0. Similarly, each memory cell has an independently configured first switching device for connecting the precharge line and the read line. When the first switching device is turned on, the corresponding precharge line and read line are connected through this first switching device, allowing the precharge line to precharge the connected read line. This precharging process involves pulling the corresponding read line to a high level.

[0061] In addition, a second switching device is provided between each precharge line and the power supply in the static random access memory; the first pole of each second switching device is connected to the power supply, and the second pole of the second switching device is connected to the corresponding precharge line.

[0062] As mentioned above Figure 3AAs shown, each of the precharge lines is further provided with a second switching device between it and the power supply VDD. That is, the first terminal of the second switching device can be used to connect to the power supply VDD, and the second terminal is connected to the corresponding precharge line. This allows the power supply to be controlled to charge the connected multiple read bit lines through the second switching device and the precharge line. For example, a second switching device G0 is connected between the precharge line GBL0 corresponding to the first row of memory cells and the power supply VDD. When a read operation is received for memory cell 00, in order to precharge the read bit line RBL0 of memory cell 00, the second switching device G0 and the first switching device Y00 can be controlled to be turned on. This allows the power supply VDD to precharge the read bit line RBL0 through the second switching device G0, the precharge line GBL0, and the first switching device Y00, causing the read bit line RBL0 to be pulled up to a high level.

[0063] In existing technologies, each read bit line of a memory cell is independently equipped with a pre-charge transistor for pre-charging; that is, each read bit line has its own pre-charge transistor. However, in this embodiment, the independently equipped pre-charge transistors are eliminated, and only one row of memory cells shares a single pre-charge path. In this case, without independently equipped pre-charge transistors, and with the current charging path requiring at least the second and first switching devices, the charging amplitude during each pre-charging of the read bit line is reduced, optimizing the discharge swing of the read operation and improving performance. Specifically, the voltage corresponding to the high-level state of the read bit line cannot be directly equal to the power supply voltage; the charging potential can change from VDD to VDD-Vth. Therefore, with a reduced charging amplitude, faster discharge is possible, resulting in faster read-to-zero pull-down and shorter read time. Furthermore, with a reduced charging amplitude during pre-charging, the leakage voltage corresponding to the leakage circuit is further reduced, thereby reducing leakage power consumption.

[0064] Additionally, it should be noted that the power supplies corresponding to the precharge lines in different rows can be the same or different, and this application does not specifically limit this.

[0065] In some embodiments, the first switching device can be an N-type metal-oxide-semiconductor field-effect transistor (MOSFET) or a P-type MOSFET. The first switching device can be selected as a switching transistor capable of rapid on / off switching to quickly pre-charge the read bit line, thereby improving the efficiency of the read operation and reducing the execution time of the read operation. This embodiment of the application does not specifically limit this aspect.

[0066] It should be noted that, depending on the type of the first switching device, the first terminal of the first switching device can be the source and the second terminal can be the drain; or, the first terminal of the first switching device can be the drain and the second terminal can be the source. This application does not specifically limit this. For example, when the first switching device is an N-type MOSFET, the first terminal can be the source and the second terminal can be the drain.

[0067] It should also be noted that in some embodiments, the first switching device described above can also be a selector transistor (MUX) for each memory cell, that is, it can select the read data of the corresponding memory cell and output it to the read bit line (RBL) according to the address information in the read operation. Accordingly, in the embodiments of this application, the read data can be output through the read bit line and the corresponding precharge line (GBL), and the relevant description can be referred to below. Figure 4 Example. In this embodiment, the selector transistor is reused as the first switching device. Upon receiving a read operation, the selector transistor can be turned on in advance according to the address information or the corresponding selection signal. This, in conjunction with the second switching device, pre-charges the read bit line corresponding to the selected memory cell. After pre-charging, the first switching device continues to conduct to complete the read operation, and the second switching device can be directly turned off. This reuse of the selector transistor reduces the number of transistors (compared to designing a separate switching device for each port), eliminating the need for additional switching devices, significantly reducing chip area, and simplifying control logic. Furthermore, unselected memory cells can still be completely isolated from pre-charging the read bit lines corresponding to other memory cells, further avoiding leakage interference.

[0068] It is understood that the control of each switching device involved in the embodiments of this application and the following related embodiments is only for the control during the read operation, and does not limit its conduction or shutdown during the write operation. Therefore, the embodiments of this application do not impose specific limitations on this.

[0069] In some embodiments, the second switching device is a P-type metal-oxide-semiconductor field transistor (MOS) or an N-type MOS transistor.

[0070] The second switching device, also known as a pre-charge transistor, can be controlled to turn on or off according to a pre-charge control signal sent by the control circuit. For example, when the second switching device is a P-type MOS transistor, its first terminal can be the source connected to the power supply VDD, and its second terminal can be the drain connected to the pre-charge line. The corresponding gate can receive the pre-charge control signal. For instance, after the gate receives the pre-charge control signal to turn on, in conjunction with the turn-on of the first switching device, the power supply can pre-charge the selected read line. In other embodiments, the second switching device can also be a diode or other types of switching devices, which are not specifically limited in this application.

[0071] In other embodiments, the static random access memory further includes a plurality of third switching devices, wherein each of the precharge lines GBL is also electrically connected to the gate of a third switching device; the first terminal of the third switching device is grounded, and the second terminal is the output terminal of the third switching device.

[0072] Among them, as mentioned above Figure 3A As shown, each precharge line GBL is also electrically connected to the gate of a third switching device. The first terminal of each third switching device is grounded, and the second terminal is the output terminal of the third switching device. For example, precharge line GBL0 is connected to the gate of the third switching device K0, and the level state of precharge line GBL0 is used to control the conduction or cutoff of the third switching device K0. The first terminal of the third switching device K0 is grounded, and the second terminal serves as the output terminal of the third switching device. The specific data read, whether 0 or 1, can be determined by detecting the level state of the second terminal.

[0073] In addition, during a read operation, the first memory cell can be used to: after pre-charging the first read bit line, output a first level signal to the first read bit line in response to the read operation; the third switching device can be used to: based on the control of the first level signal, output a second level signal through a second electrode, the second level signal being used to indicate that the read data is 0 or 1. The first level signal can be transmitted to the gate of the third switching device through the first read bit line and the first pre-charge line to control the third switching device.

[0074] It is understandable that the third switching device can be a P-type MOSFET or an N-type MOSFET, and the corresponding first and second terminals will differ depending on the type of switching device. For example, when the third switching device is an N-type MOSFET, the first terminal can be the source and the second terminal can be the drain.

[0075] It is also understandable that the gate of the third switching device receives level control from the precharge line, which causes the second electrode of the third switching device to be in different level states according to the corresponding level control, thereby indicating that the read data is 0 or 1 to complete the read operation. The first level signal output by the memory cell can be transmitted to the gate of the third switching device through the first read bit line and the first precharge line; the first level signal can be used to indicate whether the first memory cell stores 0 or 1; moreover, the level state of the precharge line GBL is also controlled by the level signal output by the power supply through the second switching device. Therefore, the level state of the gate of the third switching device is affected by the combined influence of the first level signal output by the memory cell and the level signal output by the power supply through the second switching device.

[0076] In some embodiments, the static random access memory further includes a control circuit; the control circuit is configured to: when no read operation is received, control all first switching devices corresponding to the plurality of memory cells to remain off; the control circuit is further configured to: when a read operation is received for the first memory cell, control the second switching device corresponding to the first precharge line to turn on, and control the first switching device corresponding to the first memory cell to turn on, so as to precharge the first read bit line; the first memory cell is any one of the plurality of memory cells, the first precharge line is the precharge line corresponding to the first memory cell, and the first read bit line is the read bit line corresponding to the first memory cell.

[0077] Please refer to the attached document. Figure 3B , Figure 3B This is a schematic diagram of another static random access memory (SRAM) provided in an embodiment of this application. For example... Figure 3B As shown, the static random access memory also includes a control circuit, which can be referred to as a logic control circuit, storage control circuit, control unit, etc., and can be used to control the writing or reading of data in each storage cell. In the embodiments of this application, it can also be used to control the on or off of switching devices, which is not specifically limited in this embodiment.

[0078] For example, in this embodiment of the application, the control circuit can be used to keep the first switching devices corresponding to the plurality of memory cells off when no read operation is received; the control circuit is also used to: when a read operation is received for the first memory cell, control the first switching device corresponding to the first memory cell to be turned on, so that the first precharge line precharges the first read bit line through the first switching device; wherein, the first memory cell is any one of the plurality of memory cells, the first precharge line is the precharge line corresponding to the first memory cell, and the first read bit line is the read bit line corresponding to the first memory cell.

[0079] For example, when no read operation is received, the first switching device corresponding to each memory cell remains off. In this state, no conductive loop is formed, preventing leakage. If a read operation is received on the first memory cell (as described above)... Figure 3AWhen a read operation is performed on storage cell 00 (taking the first storage cell as an example), the control circuit can control the first switching device Y00 corresponding to storage cell 00 to be turned on, and control the first switching devices corresponding to the remaining storage cells in the row where storage cell 00 is located (such as storage cells 01, 02, and 03) and other storage cells that have not received a read operation to remain off. At this time, the first precharge line GBL0 corresponding to storage cell 00 can precharge the first read bit line RBL0, and the first precharge line GBL0 cannot precharge the read bit lines RBL1, RBL2, and RBL3 corresponding to storage cells 01, 02, and 03 in the same row. The read bit lines RBL1, RBL2, and RBL3 can only remain in a non-charging state and cannot be read. Therefore, in this embodiment of the application, before performing a read operation on any memory cell, selective precharging can be performed only on the read bit line corresponding to that memory cell, without precharging the read bit lines corresponding to other memory cells. This greatly reduces the leakage circuit of the static random access memory. For example, even if the read word line in memory cells 01, 02, and 03 is in an active (high level) state, since the read bit line is not synchronously pulled to a high level, the leakage current in memory cells 01, 02, and 03 will be greatly reduced, and thus the overall leakage power consumption of the static random access memory will also be greatly reduced.

[0080] It should be noted that this application only uses a read operation on a single storage cell as an example for illustrative purposes. The embodiments of this application are not limited to reading data from only one storage cell at a time; they can also read data from multiple storage cells simultaneously. In this case, the first switching devices corresponding to the multiple storage cells can be turned on, while the first switching devices corresponding to the remaining storage cells remain off. For example, data from eight storage cells can be read at once. In this case, only the first switching devices corresponding to these eight storage cells are turned on, and the read bit lines corresponding to the eight storage cells in that row are pre-charged. Pre-charging the read bit lines of other storage cells in that row is not required. This application does not specifically limit the scope of this embodiment.

[0081] Taking an N-type MOSFET as the first switching device and a P-type MOSFET as the second switching device, the read operation of memory cell 00 is illustrated below. Please refer to the appendix. Figure 4 , Figure 4 This application provides a method based on... Figure 3A The timing diagram of the storage structure is shown.

[0082] like Figure 4As shown, after receiving the clock signal Clk for reading the first memory cell, the precharge control signal corresponding to the gate of the second switching device G0 is pulled down to 0 to control the second switching device G0 to turn on. Then, the precharge control signal corresponding to the gate of the first switching device Y00 is pulled up to 1 to control the first switching device Y00 to turn on. At this time, the power supply can precharge the read bit line RBL0 through the precharge line GBL0.

[0083] After pre-charging is complete, RBL0 remains high. When performing a read operation on memory cell 00, the level changes according to the storage state of memory cell 00. Specifically, if the memory cell stores 0, the corresponding read bit line RBL will be pulled down to low; if the memory cell stores 1, the corresponding read bit line RBL will remain high.

[0084] like Figure 4 As shown, after pre-charging is complete, when memory cell 00 stores 0, in response to a read operation, memory cell 00 outputs a first-level signal. Since the first-level signal is low, the read bit line RBL0 is pulled down from high to low. Correspondingly, GBL0 begins to discharge until it reaches a low level. At this time, the second electrode of the third switching device also changes according to the gate's level. When the gate's level is low (e.g., 0), the third switching device is turned off, and the second electrode also becomes low. Therefore, memory cell 00 stores 0, and the read operation is complete.

[0085] Furthermore, since this embodiment eliminates the independently configured precharge transistor and only retains the global precharge path, the high level of the precharge line GBL0 after precharge is complete does not reach the level corresponding to VDD. For example, it can reach a maximum of VDD-Vth. Therefore, if a 0 is read at this time, it can be discharged faster and the 0 read can be completed more quickly compared to when the independently configured precharge transistor is not eliminated. It should be noted that the level change of the precharge line GBL0 is as described above when the independently configured precharge transistor is not eliminated. Figure 4 As shown by the dashed line, the precharged line GBL0 will have a longer charging time and a greater charging amplitude (i.e., reaching VDD) at this time. Correspondingly, a longer discharge time is required when reading 0.

[0086] It is understandable that when memory cell 00 stores a 1, after pre-charging is complete, in response to a read operation, memory cell 00 will output a first-level signal. Since this first-level signal is high, the read bit line RBL0 will remain high, and correspondingly, GBL0 will also remain high. At this time, the second electrode of the third switching device will also change according to the gate's level. When the gate's level is high, the third switching device is turned on, and its second electrode will remain high. Therefore, it can be seen that memory cell 00 stores a 1, and a read operation is completed. It is understood that this situation is not illustrated.

[0087] It should be noted that the above Figure 4 This only illustrates one possible implementation. The corresponding timing signals will change depending on the type of switching device or the circuit connection. This application does not impose specific limitations on this implementation. For example, when the second switching device is an N-type MOSFET, it conducts when the pre-charge control signal is high.

[0088] It is understandable that the existing technology sets up precharge transistors for all read bit lines to precharge them in advance in order to avoid being affected by the address signal when performing a read operation. In this embodiment, in order to ensure that reading 1 is not affected, the first switching device can be controlled to turn on in advance. For example, the first switching device can be controlled to turn on immediately after the second switching device turns on, or it can be turned on simultaneously with the second switching device, etc. It can be adjusted according to the specific circuit connection relationship and control timing. Therefore, this embodiment does not make specific limitations on the timing and duration of sending the precharge control signal.

[0089] It should also be noted that the specific voltage value of the high level mentioned for each line or switching device in this embodiment is not specifically limited. The voltage value of the high level varies depending on the operating voltage of the switching device. This embodiment does not specifically limit this. For example, if the operating voltage of the switching device in a static random access memory is 1V, the voltage value corresponding to its high level state can also be around 1V, etc. If the operating voltage of the switching device in a static random access memory is 0.5V, the voltage value corresponding to its high level state can also be around 0.5V, etc.

[0090] In some embodiments, the control circuit is further configured to: after completing a read operation on the first storage cell, control the first switching device corresponding to the first storage cell to turn off.

[0091] Understandably, after completing the read operation on the first memory cell, the control circuit can disable the pre-charging of the read bit line. For example, it can control the first switching device corresponding to the first memory cell to turn off at this time. This avoids leakage paths that could affect the storage performance of the device when no stored data is being read. Correspondingly, after completing the read operation on the first memory cell, the control circuit can also control the second switching device to turn off to prevent the power supply from continuously charging the pre-charging line.

[0092] Currently, when a memory cell in a static random access memory (SRAM) performs a read operation, the existing pre-charge mechanism often has many redundant leakage loops, resulting in significant leakage power consumption and affecting the performance of the SRAM. To address this, this application provides a SRAM comprising multiple read lines, multiple pre-charge lines, multiple first switching devices, multiple second switching devices, and multiple memory cells arranged in an array. In this embodiment, independently configured pre-charge transistors are eliminated; only a global pre-charge mechanism is implemented, meaning that a row of memory cells shares a single pre-charge path (e.g., power supply - second switching device - pre-charge line). Each read line connected to the aforementioned memory cell is connected to its corresponding pre-charge line via the corresponding first switching device. Furthermore, a second switching device is also configured between the pre-charge line and the power supply. This connection method allows pre-charging of the read line connected to the first switching device when both the second switching device and the first switching device are simultaneously turned on; conversely, pre-charging is not possible when either the second switching device or the first switching device is turned off. Therefore, multiple read bit lines can be selectively precharged by controlling the on / off state of the first and second switching devices. For example, after receiving a read operation for any memory cell, the first switching device for that memory cell and the second switching device for the precharge line corresponding to the row containing that memory cell can be turned on. This allows precharging only the read bit line corresponding to that memory cell, without precharging the read bit lines corresponding to other memory cells in the same row. This ensures that when other memory cells are inactive, their corresponding read bit lines are also inactive, avoiding redundant leakage loops in memory cells that do not need to perform read operations after activating the read word line. This significantly reduces redundant leakage loops in the static random access memory, reduces leakage phenomena, lowers the overall leakage power consumption of the static random access memory, and improves performance.

[0093] Secondly, this application provides a pre-charging method to reduce leakage current, which can be applied to the static random access memory (SRAM) mentioned in the above embodiments. The SRAM includes multiple read lines, multiple pre-charge lines, multiple first switching devices, multiple second switching devices, and multiple memory cells arranged in an array. Multiple memory cells in the same column are electrically connected to the same read line, and multiple memory cells in different columns of the same row are electrically connected to different read lines. Multiple memory cells in the same row correspond to the same pre-charge line, and multiple memory cells in different rows of the same column correspond to different pre-charge lines. Each memory cell corresponds to one first switching device, and the first terminal of each first switching device is connected to the pre-charge line of the corresponding memory cell, and the second terminal of the first switching device is connected to the read line of the corresponding memory cell. Each pre-charge line also corresponds to one second switching device, and the first terminal of each second switching device is connected to a power supply, and the second terminal of the second switching device is connected to the corresponding pre-charge line.

[0094] Please refer to the attached document. Figure 5 , Figure 5 This is a schematic flowchart of a pre-charging method for reducing leakage current provided in an embodiment of this application. Wherein, as... Figure 5 As shown:

[0095] Step S101: When no read operation is received, control the first switching devices corresponding to the multiple memory cells to remain off;

[0096] Specifically, before a read operation is received, there is no need to precharge the read bit lines connected to the memory cell. Therefore, the first switching device corresponding to each memory cell can be kept off. When the first switching device is off, it is impossible to precharge its connected read bit lines, and therefore, no leakage current loop is generated in the corresponding memory cell.

[0097] Step S102: Receive a read operation for the first memory cell.

[0098] Specifically, each storage unit can be used to store one bit of data, and therefore can receive read operations on some or all of the multiple storage units. For example, a read operation on the first storage unit can be received. This first storage unit can be any one of the multiple storage units mentioned above.

[0099] Step S103: After receiving a read operation for the first storage cell, control the first switching device corresponding to the first storage cell to turn on from among multiple storage cells, and control the second switching device corresponding to the first precharge line to turn on, so as to precharge the first read bit line.

[0100] Specifically, after receiving a read operation for the first storage cell, the system selects and controls the first switching device corresponding to the first storage cell to be turned on from among the plurality of storage cells, and controls the second switching device corresponding to the first precharge line to be turned on. Furthermore, it can also control the first switching devices corresponding to the remaining storage cells in the row where the first storage cell is located to remain off. Here, the first precharge line is the precharge line corresponding to the first storage cell, and the first read bit line is the read bit line corresponding to the first storage cell.

[0101] In some embodiments, the static random access memory further includes a plurality of third switching devices, wherein each of the aforementioned precharge lines is also electrically connected to the gate of a third switching device; the first terminal of each of the aforementioned third switching devices is grounded, and the second terminal is the output terminal of the third switching device.

[0102] In some embodiments, the storage unit is a multi-port storage unit, wherein the multi-port storage unit includes at least a read port, and the read port of each storage unit is electrically connected to a corresponding read bit line.

[0103] In some embodiments, the first switching device is an N-type metal-oxide-semiconductor field transistor (MOS) or a P-type MOS transistor.

[0104] In some embodiments, the second switching device is a P-type metal-oxide-semiconductor field transistor (MOS) or an N-type MOS transistor.

[0105] In some embodiments, the method further includes: after completing the read operation on the first storage cell, controlling the first switching device corresponding to the first storage cell to turn off.

[0106] Please refer to the attached document. Figure 6 , Figure 6 This is a schematic diagram of a processor provided in an embodiment of this application. Wherein, as... Figure 6 As shown, this application provides a processor that may include logic circuitry and a static random access memory (SRAM) as described in any of the above embodiments, wherein the logic circuitry is electrically connected to the SRAM.

[0107] Please refer to the attached document. Figure 7 , Figure 7 This is a schematic diagram of the structure of a chip provided in an embodiment of this application, as shown below. Figure 7 As shown, the chip may include a stacked packaged processor chip and a memory chip, the processor chip and the memory chip being electrically connected, and the processor chip being the processor chip provided in the third aspect.

[0108] Please refer to the attached document. Figure 8 , Figure 8This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 8 As shown, the electronic device may include a circuit board and a processor, wherein the circuit board is electrically connected to the processor. The processor may be one of the aforementioned... Figure 6 The processor shown.

[0109] Please refer to the attached document. Figure 9 , Figure 9 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application, such as... Figure 9 As shown, the electronic device includes a circuit board and the chip. The chip can be packaged on a packaging substrate (not shown). In this case, the chip can be mounted on the circuit board and electrically connected to the circuit board via the packaging substrate. The circuit board is electrically connected to the chip. The chip can be as described above... Figure 7 The chip shown.

[0110] In addition, the above Figure 8 and Figure 9 The electronic device mentioned can be a terminal device, such as: a mobile phone, a tablet, a television, a smart wearable product (e.g., a smartwatch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) device, a server, a workstation, etc. This application embodiment describes... Figure 8 The electronic devices shown and Figure 9 The specific form of the electronic device shown is not subject to any special restrictions.

[0111] It should be understood that the pre-charging method, processor, chip, and electronic device for reducing leakage provided in this application can be consistent with the static random access memory technology solution provided in this application, and their specific content and beneficial effects can be referred to the above. Figures 1-4 The static random access memory mentioned in the illustrated embodiment will not be described in detail here.

[0112] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0113] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0114] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A static random access memory, characterized in that, It includes multiple read lines, multiple precharge lines, multiple first switching devices, multiple second switching devices, and multiple memory cells arranged in an array; Among them, multiple storage cells in the same column are electrically connected to the same read bit line, multiple storage cells in different columns in the same row are electrically connected to different read bit lines, and multiple storage cells in the same row correspond to the same precharge line, while multiple storage cells in different rows in the same column correspond to different precharge lines. Each of the memory cells corresponds to one of the first switching devices, the first pole of each first switching device is connected to the precharge line of the corresponding memory cell, and the second pole of the first switching device is connected to the read bit line of the corresponding memory cell. Each of the precharge lines also corresponds to a second switching device, with the first pole of each second switching device connected to the power supply and the second pole of the second switching device connected to the corresponding precharge line.

2. The static random access memory according to claim 1, characterized in that, The static random access memory also includes multiple third switching devices; Each of the precharge lines is also electrically connected to the gate of a third switching device; the first terminal of each third switching device is grounded, and the second terminal is the output terminal of the third switching device.

3. The static random access memory according to claim 1 or 2, characterized in that, The storage unit is a multi-port storage unit, wherein the multi-port storage unit includes at least a read port, and the read port of each storage unit is electrically connected to the corresponding read bit line.

4. The static random access memory according to any one of claims 1-3, characterized in that, The first switching device is an N-type metal-oxide-semiconductor field transistor (MOS) or a P-type MOS transistor.

5. The static random access memory according to any one of claims 1-4, characterized in that, The second switching device is a P-type metal-oxide-semiconductor field transistor (MOS) or an N-type MOS transistor.

6. The static random access memory according to any one of claims 1-5, characterized in that, The static random access memory also includes a control circuit. The control circuit is used to: keep the first switching devices corresponding to the plurality of memory cells off when no read operation is received; The control circuit is further configured to: when receiving a read operation for the first storage cell, control the second switching device corresponding to the first precharge line to turn on, and control the first switching device corresponding to the first storage cell to turn on, so as to precharge the first read bit line; The first storage unit is any one of the plurality of storage units, the first precharge line is the precharge line corresponding to the first storage unit, and the first read bit line is the read bit line corresponding to the first storage unit.

7. The static random access memory according to claim 6, characterized in that, The control circuit is further configured to: after completing the read operation on the first storage cell, control the second switching device corresponding to the first precharge line to turn off, and control the first switching device corresponding to the first storage cell to turn off.

8. A pre-charging method for reducing leakage current, characterized in that, It is applied to static random access memory, which includes multiple read lines, multiple precharge lines, multiple first switching devices, multiple second switching devices, and multiple memory cells arranged in an array; Among them, multiple storage cells in the same column are electrically connected to the same read bit line, multiple storage cells in different columns in the same row are electrically connected to different read bit lines, and multiple storage cells in the same row correspond to the same precharge line, while multiple storage cells in different rows in the same column correspond to different precharge lines. Each of the memory cells corresponds to one of the first switching devices, the first pole of each first switching device is connected to the precharge line of the corresponding memory cell, and the second pole of the first switching device is connected to the read bit line of the corresponding memory cell. Each of the precharge lines also corresponds to a second switching device, the first pole of each second switching device is connected to the power supply, and the second pole of the second switching device is connected to the corresponding precharge line; The method includes: When no read operation is received, the first switching devices corresponding to the plurality of storage cells are kept off. Receive a read operation for the first memory cell; Upon receiving a read operation for the first storage cell, the system controls the first switching device corresponding to the first storage cell to turn on from among the plurality of storage cells, and controls the second switching device corresponding to the first precharge line to turn on, so as to precharge the first read bit line. Wherein, the first storage unit is any one of the plurality of storage units, the first precharge line is the precharge line corresponding to the first storage unit, and the first read bit line is the read bit line corresponding to the first storage unit.

9. A processor, characterized in that, It includes logic circuitry and a static random access memory as described in claims 1 to 7, wherein the logic circuitry is electrically connected to the static random access memory.

10. A chip, characterized in that, It includes a stacked packaged processor chip and a memory chip, the processor chip and the memory chip being electrically connected, and the processor chip being the processor chip as described in claim 9.

11. An electronic device, characterized in that, The electronic device includes: a circuit board and a processor as described in claim 9; the circuit board is electrically connected to the processor.

12. An electronic device, characterized in that, The electronic device includes: a circuit board and a chip as described in claim 10; the circuit board is electrically connected to the chip.

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