Memory device with adaptive write control and related methods
Patent Information
- Application Number
- CN202610420000.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2026-03-16
- Filing Date
- 2026-04-01
- Publication Date
- 2026-10-16
Smart Images
Figure CN122930145A_ABST
Abstract
Description
[0001] Cross-reference to related applications
[0002] This application claims priority and benefit to U.S. Provisional Patent Application Serial No. 63 / 782,171, filed April 2, 2025, entitled “Memory Device with Adaptive Write Control and Related Methods Thereof,” the entire contents of which are incorporated herein by reference. Technical Field
[0003] Exemplary embodiments of this disclosure generally relate to memory devices, and in particular, to write control for memory devices. Background Technology
[0004] Static random access memory (SRAM) consists of an array of bit cells, each bit cell having a 0 or 1 state representing the stored information. The state of each bit cell can be written to (i.e., changed) to store information, and can be read to retrieve the stored information. A common type of SRAM is called 6T SRAM because each bit cell includes six transistors.
[0005] An exemplary SRAM device includes: a plurality of horizontal word lines, each word line connected to a row of a corresponding bit cell; a plurality of vertical bit lines, each bit line connected to a column of a corresponding bit cell; and a plurality of vertical bit inversion lines, each bit inversion line connected to a column of a corresponding bit cell. Each bit line and its corresponding bit inversion line have opposite states. Desired bit cells can be written to or read from by controlling signals on the word lines, bit lines, and bit inversion lines.
[0006] Such an exemplary SRAM device also includes multiple write driver lines, each of which is selectively connected to at least one bit line or bit inversion line of a corresponding column of a bit cell. In addition to the signals controlling the word lines, bit lines, and bit inversion lines, the desired bit cell is written to by pulling the write driver line low to 0. As technology scales, high-density 6T SRAM suffers from stability issues and often uses read assist and write assist circuitry to ensure stable operation. The most common write assist technique is known as negative bit line. Negative bit line technology uses multiple boost capacitors to add a negative charge to the write driver line, thereby making the write driver line voltage below 0 when the write driver line is pulled low.
[0007] The requirements for negative bit lines are higher when the supply voltage is low and the operating temperature is low. Conversely, the requirements for negative bit lines are lower when the supply voltage is high. However, as the supply voltage increases, the negative bit line bump (i.e., the difference between the supply voltage and the voltage on the write driver line) increases, and this increase in the difference between the supply voltage and the voltage on the write driver line can cause overstress to some components of the SRAM and may lead to reliability and oxide breakdown issues.
[0008] The applicant has identified numerous technical challenges and difficulties associated with write operations on SRAM devices. Through effort, ingenuity, and innovation, the applicant has solved the problems related to write operations on SRAM devices by developing solutions embodied in this disclosure, which are described in detail below. Summary of the Invention
[0009] The various embodiments described herein relate to memory devices with adaptive write control and related methods for write control in memory devices.
[0010] According to various embodiments of the present disclosure, a memory device is provided. In some embodiments, the memory device includes: a plurality of bit cells arranged in a matrix of rows and columns; a plurality of bit lines, each bit line connected to a bit cell in a column of a corresponding bit cell; a plurality of bit inversion lines, each bit inversion line connected to a bit cell in a column of a corresponding bit cell; a plurality of word lines, each word line connected to a bit cell in a row of a corresponding bit cell; a plurality of write driver lines, each write driver line selectively connected to at least one bit line or bit inversion line in a column of a corresponding bit cell; a plurality of write driver line switches for selectively connecting a corresponding write driver line to ground; a plurality of boost capacitors, each boost line capacitor connected to a corresponding write driver line to selectively inject negative charge thereto; and a plurality of adaptive control transistors. Each adaptive control transistor is connected to a corresponding write driver line to automatically remove some of the negative charge thereon when a voltage applied to the gate of the adaptive control transistor is equal to or exceeds a threshold voltage of the adaptive control transistor.
[0011] In some embodiments, the memory device includes a static random access memory device.
[0012] In some embodiments, each of the plurality of adaptive control transistors includes an N-channel metal-oxide-semiconductor (NMOS) transistor.
[0013] In some embodiments, the voltage applied to the gate of each of the adaptive control transistors is the process-voltage-temperature (PVT) regulated operating voltage of the memory device.
[0014] In some embodiments, the voltage applied to the gate of each of the adaptive control transistors is the process-voltage-temperature (PVT) adjustment value of the operating voltage of the memory device minus the voltage delta by which the plurality of word lines are selected to underdrive.
[0015] In some embodiments, the voltage applied to each of the plurality of word lines is provided by a read auxiliary word line underdrive circuit; and wherein the operating voltage of the memory device minus the amount of voltage variation selected to underdrive the plurality of word lines is provided by a copy of the read auxiliary word line underdrive circuit.
[0016] In some embodiments, each of the plurality of write driver line switches includes a metal-oxide-semiconductor (MOS) transistor.
[0017] In some embodiments, the voltage applied to the gate of each of the adaptive control transistors is selectively delivered from the voltage subtraction unit via an adaptive control line.
[0018] In some embodiments, the memory device further includes a bleed switch connected to the adaptive control line to selectively pull the adaptive control line to zero volts at the start of each write operation.
[0019] In some embodiments, the threshold voltage of each of the plurality of adaptive control transistors is selected to limit the difference between the voltage applied to each of the plurality of word lines and the voltage on the write driver line, in order to limit overstress of one or more components of the memory device.
[0020] According to various embodiments of this disclosure, a method for adaptive write control of a memory device is provided. In some embodiments, the method includes: injecting negative charge into each of a plurality of write driver lines via a plurality of boost capacitors, each boost capacitor being connected to a corresponding one of the plurality of write driver lines, each write driver line being selectively connected to one of a plurality of bit lines or one of a plurality of bit inversion lines of a column of at least one of a plurality of bit cells arranged in a matrix of rows and columns; and automatically applying a voltage to the gate of each of a plurality of adaptive control transistors, each adaptive control transistor being connected to a corresponding one of the plurality of write driver lines, to draw away some of the negative charge on each of the plurality of write driver lines when the voltage applied to the gate of each adaptive control transistor is equal to or exceeds a threshold voltage of the corresponding adaptive control transistor. Each of the plurality of bit lines and each of the plurality of bit inversion lines is connected to a bit cell in a column of a corresponding bit cell.
[0021] The above overview is provided merely to outline some exemplary embodiments to provide a basic understanding of some aspects of this disclosure. Therefore, it will be understood that the above embodiments are merely examples and should not be construed in any way as limiting the scope or spirit of this disclosure. It will also be understood that, in addition to those outlined herein, the scope of this disclosure covers many other potential embodiments, some of which will be further described below. Attached Figure Description
[0022] The description of exemplary embodiments can be read in conjunction with the accompanying drawings. It will be understood that, for purposes of simplicity and clarity, the elements shown in the drawings are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of some elements may be exaggerated relative to other elements unless otherwise stated. Embodiments incorporating the teachings of this disclosure are shown and described in conjunction with the accompanying drawings, in which:
[0023] Figure 1 An example architecture of an exemplary memory device according to some embodiments of the present disclosure is shown; and
[0024] Figure 2 An example architecture of an exemplary memory device according to some alternative embodiments of the present disclosure is shown. Detailed Implementation
[0025] Some embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, which illustrate some, but not all, of the embodiments of the present disclosure. In fact, these disclosures may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will satisfy applicable legal requirements. The same numerals indicate the same elements throughout the drawings.
[0026] As used herein, terms such as “front,” “rear,” and “top” are used in the examples provided below to describe the relative positions of certain components or portions of components. Furthermore, as will be apparent to those skilled in the art from this disclosure, terms such as “substantially” and “approximately” indicate that the elements or related descriptions referred to are accurate within applicable engineering tolerances.
[0027] As used herein, the term “comprising” means including but not limited to, and should be interpreted in the manner in which it is typically used in the patent context. The use of broader terms (e.g., including, comprising, and having) should be understood to provide support for narrower terms, such as consisting of, substantially consisting of, and primarily consisting of.
[0028] The phrases “in one embodiment”, “according to one embodiment”, etc., generally refer to a specific feature, structure, or characteristic that immediately follows the phrase and may be included in at least one embodiment of this disclosure, and may be included in more than one embodiment of this disclosure (importantly, these phrases do not necessarily refer to the same embodiment).
[0029] The terms “exemplary” or “example” are used to mean “served as an example, instance, or illustration.” Any implementation described as “exemplary” in this document is not necessarily to be construed as preferred or advantageous over other implementations.
[0030] If the specification states that a component or feature "may," "can," "may," "should," "will," "preferably," "possibly," "usually," "optionally," "for example," "often," or "may" (or other such language) be included or have the feature, it does not mean that the specific component or feature is not required to be included or have the feature. Such a component or feature may be optionally included in some embodiments, or it may be excluded.
[0031] Various embodiments of this disclosure overcome the aforementioned technical challenges and difficulties, and based on, for example (but not limited to), a memory device (e.g., SRAM) with adaptive write control (which may also be referred to as adaptive write assist) provides various technical improvements and advantages, which limit the amount of negative bit line bulge by absorbing some negative charge on the write driver lines when the supply voltage or operating voltage increases, thereby reducing the likelihood of reliability and oxide breakdown problems.
[0032] Now for reference Figure 1 This illustrates an example architecture of an example storage device according to some embodiments of the present disclosure. Figure 1 The storage device (e.g., SRAM) 100 includes a memory array 102 comprising a plurality of bit cells 104 arranged in a plurality of rows (labeled as cells 11…1k to n1…nk) and a plurality of columns (labeled as cells 11…n1 to 1k…nk). A plurality of vertical bit lines 106 (BL1, BLm…BLk) are each connected to a corresponding column of the bit cell 104, and a plurality of vertical bit-bar lines 108 (BLB1, BLBm…BLBk) are each connected to a corresponding column of the bit cell 104. (Bit-bar lines can also be referred to as bit-bar inversion lines.) Each bit line 106 and its corresponding bit-bar line 108 have opposite states. A plurality of horizontal word lines 110 (WL1…WLn) are each connected to a corresponding row of the bit cell 104. Desired bit cells can be written to or read from by controlling signals on the word lines, bit lines, and bit-bar lines.
[0033] Figure 1 The storage device 100 includes a plurality of write driver lines 112. Each write driver line 112 is selectively connected via a multiplexer 114 to a bit line 106 or bit inversion line 108 of at least one corresponding column of the bit cell 104. Figure 1 The storage device 100 includes a plurality of write driver line switches 116 for selectively connecting corresponding write driver lines 112 to ground. In the illustrated embodiment, the write driver line switches 116 include N-channel metal-oxide-semiconductor (NMOS) transistors. Figure 1The storage device 100 includes a plurality of boost capacitors 118, each connected to a corresponding write driver line 112 to selectively inject negative charge thereon to perform a negative bitline write-assisted technique. As mentioned above, the requirements for negative bitlines are lower when the supply voltage is high, and the increase in negative bitline bulge as the supply voltage increases may cause overstress to some components of the SRAM and may lead to reliability and oxide breakdown issues.
[0034] To address the issue of increased negative bit bulge as the supply voltage increases, various embodiments of this disclosure provide adaptive write control that limits the amount of negative bit bulge by siphoning off some negative charge on the write driver lines as the supply voltage increases. For example... Figure 1 As seen in the diagram, the storage device 100 includes a plurality of adaptive control transistors 122. Each adaptive control transistor 122 is connected to a corresponding write driver line 112. In the illustrated embodiment, each of the plurality of adaptive control transistors 122 includes an NMOS transistor, with its source connected to the corresponding write driver line 112, its drain connected to ground, and its gate connected to a voltage subtraction unit 124 via an adaptive control line 120.
[0035] An NMOS transistor operates by creating a conductive channel between its source and drain terminals when a positive voltage is applied to its gate. This channel allows electrons to flow and essentially acts as a switch that can be turned on or off by a gate voltage. The higher the gate voltage, the greater the current that can flow through the channel. The minimum positive voltage required on the gate (called the threshold voltage) is used to create the conductive channel and turn the NMOS transistor on.
[0036] In various embodiments, a threshold voltage for each adaptive control transistor 122 is selected to limit the difference between the voltage applied to each of the plurality of word lines 110 and the voltage on the write driver line 112, in order to limit overstress of the components of the memory device 100.
[0037] exist Figure 1In this embodiment, voltage subtraction unit 124 provides an adjusted version of the supply / operating voltage Vdd of the memory device 100 to the gate of adaptive control NMOS transistor 122. Voltage subtraction unit 124 includes a first diode-connected NMOS transistor 134 connected in series with an NMOS transistor 136 connected to a second diode. By allowing the supply voltage Vdd to pass through the first diode-connected NMOS transistor 134 and the second diode-connected NMOS transistor 136, the voltage supplied to the adaptive control NMOS transistor is adjusted for process, voltage, and temperature (PVT). Therefore, the voltage supplied to the adaptive control NMOS transistor can be referred to as a PVT-considered voltage or a PVT-adjusted voltage. The two diode-connected NMOS transistors in the voltage subtraction unit are selected to have the same process angle as the NMOS transistors in unit 104 (i.e., fast-slow (FS) or slow-fast (SF)). In this respect, the voltage supplied to the adaptive control NMOS transistor is adjusted for the process (i.e., based on the transistor's process angle). As Vdd changes, the voltage supplied to the adaptive control NMOS transistor also changes. In this respect, the voltage supplied to the adaptive control NMOS transistor is adjusted for voltage. The NMOS transistor in the voltage subtraction unit, connected by two diodes, is affected by temperature in the same way as the NMOS transistor in unit 104. In this respect, the voltage supplied to the adaptive control NMOS transistor is adjusted for temperature. By providing this PVT-adjusted voltage to the adaptive control NMOS transistor, voltage subtraction unit 124 achieves more finely tuned adaptive control of the negative bit convexity.
[0038] In various embodiments, such as Figure 1 As shown, the source of PMOS transistor 138 is connected to the source of NMOS transistor 134 (connected by a first diode) and the gate of NMOS transistor 136 (connected by a second diode). PMOS transistor 138 quickly stabilizes the adaptive control line voltage, thereby preventing the voltage on the adaptive control line from continuing to increase.
[0039] The adaptive control transistor 122 is selected based on its threshold voltage. Specifically, in Figure 1 In this embodiment, the threshold voltage of the adaptive control transistor 122 is selected to be equal to the PVT adjustment voltage at which it is desired to begin drawing some negative charge from the write driver line. That is, the threshold voltage of each adaptive control transistor 122 is selected such that when the PVT adjustment voltage rises to a level where the negative bit convexity is sufficiently high to overstress the components of the memory device 100, the adaptive control transistor 122 begins to draw some negative charge from the write driver line 112.
[0040] As the PVT-adjusted voltage increases and reaches a certain level (above which it has been predetermined that negative bit surges may begin to cause component damage) (i.e., the PVT-adjusted voltage reaches the threshold voltage of the adaptive control transistor 122), the adaptive control transistor 122 becomes active and begins to draw some negative charge from the corresponding write driver line 112 to ground. As the PVT-adjusted voltage continues to increase, the adaptive control transistor 122 allows more current to flow, and more negative charge is drawn from the write driver line 112. In this respect, the adaptive write control of embodiments of this disclosure automatically limits negative bit surges as the PVT-adjusted voltage increases.
[0041] like Figure 1 As seen, the voltage subtraction unit 124 of the storage device 100 includes an enable line 130 to provide a PVT-adjusted voltage to the adaptive control transistor 122 during each write operation. Figure 1 As seen, the voltage subtraction unit 124 of the storage device 100 includes a bleed switch 132 connected to the adaptive control line 120 to selectively pull the adaptive control line 120 to zero volts at the start of each write operation.
[0042] Figure 2 An example architecture of an example storage device according to some alternative embodiments of the present disclosure is shown. Figure 2 An alternative embodiment is shown, wherein an adjusted voltage value is provided to the voltage subtraction unit and the gate of the adaptively controlled NMOS transistor, as further described below.
[0043] Figure 2 The storage device (e.g., SRAM) 200 includes a memory array 202 comprising a plurality of bit cells 204 (labeled cell 1…cell n) arranged in multiple rows and columns. A plurality of vertical bit lines 206 (BL1, BLm…BLk) are each connected to a corresponding column of the bit cell 204, and a plurality of vertical bit inversion lines 208 (BLB1, BLBm…BLBk) are each connected to a corresponding column of the bit cell 204. Each bit line 206 and its corresponding bit inversion line 208 have opposite states. A plurality of horizontal word lines 210 (WL1…WLn) are each connected to a corresponding row of the bit cell 204. Desired bit cells can be written to or read from by controlling signals on the word lines, bit lines, and bit inversion lines.
[0044] Figure 2 The storage device 200 includes a plurality of write driver lines 212. Each write driver line 212 may be selectively connected to a bit line 206 or a bit inversion line 208 of at least one corresponding column of the bit cell 204 via a multiplexer 214. Figure 2The storage device 200 includes a plurality of write driver line switches 216 for selectively connecting corresponding write driver lines 212 to ground. In the illustrated embodiment, the write driver line switches 216 include NMOS transistors. Figure 2 The storage device 200 includes a plurality of boost capacitors 218, each boost capacitor being connected to a corresponding write driver line 212 to selectively inject negative charge thereon to perform a negative bit line write assist technique.
[0045] It is commonly known that SRAM devices include read auxiliary word line underdrive circuitry. Such read auxiliary word line underdrive circuitry 226 is... Figure 2 The circuit is shown connected to each word line 210. This read-assist word line underdrive circuit reduces the voltage supplied to the word line from Vdd to (Vdd - ΔV). Reducing the voltage on the word line by ΔV helps keep the bit cell stable during read operations (the value stored in the bit cell should not change during read operations), but may hinder write operations because it reduces the difference between the voltage on the word line and the voltage on the write driver line. The larger ΔV is (i.e., the lower the voltage on the word line), the more negatively the write operation may be affected. Therefore, the larger ΔV is, the less negative voltage we want to draw from the write driver line. The value of ΔV is determined by the read-assist word line underdrive circuit based on the manufacturing characteristics (and therefore, speed) of the individual transistors in each bit cell.
[0046] Figure 2 The embodiment addresses the problem of the relatively large ΔV's impact on write operations by providing an input to the voltage subtraction unit through a copy of the read auxiliary word line underdrive circuit. In this respect, the voltage value provided to the voltage subtraction unit is the same as the voltage on the word line (Vdd - ΔV). Such a copied read auxiliary word line underdrive circuit 228... Figure 2 The diagram shows a voltage subtraction unit 224 connected to the adaptive control transistor 222, which selectively supplies the voltage from the copied read auxiliary word line underdrive circuit 228 to the adaptive control transistor 222 via the adaptive control line 220.
[0047] As ΔV increases (and therefore Vdd-ΔV decreases), less charge is drawn from the write driver line, and as ΔV decreases (and therefore Vdd-ΔV increases), more charge is drawn from the write driver line. In this respect, the decrease in the difference between the voltage on the word line and the voltage on the write driver line due to the increase in ΔV is not exacerbated by unnecessary drawing of negative charge from the write driver line.
[0048] and Figure 1 As with the previous implementation, an increase or decrease in Vdd will also affect Figure 2In the embodiments, the amount of charge drawn from the write driver line. Essentially, in various embodiments, the voltage applied to the gate of each of the adaptive control transistors is a PVT-adjusted version of the voltage applied to each of the plurality of word lines.
[0049] like Figure 2 As seen, the voltage subtraction unit 224 of the memory device 200 includes an enable line 230 to provide an adjusted version of the word line voltage (Vdd-ΔV) to the adaptive control transistor 222 during each write operation. The voltage subtraction unit 224 includes a first diode-connected NMOS transistor 234 connected in series with an NMOS transistor 236 connected to a second diode. By allowing the word line voltage (Vdd-ΔV) to be passed through the first diode-connected NMOS transistor 234 and the second diode-connected NMOS transistor 236, the voltage provided to the adaptive control NMOS transistor is adjusted for process, voltage, and temperature (PVT). Therefore, the voltage provided to the adaptive control NMOS transistor can be referred to as a PVT-considered voltage or a PVT-adjusted voltage. The two diode-connected NMOS transistors in the voltage subtraction unit are selected to have the same process angle (i.e., fast-slow (FS) or slow-fast (SF)) as the NMOS transistors in unit 204. In this respect, the voltage provided to the adaptive control NMOS transistor is adjusted for the process (i.e., based on the transistor's process angle). As Vdd-ΔV changes, the voltage supplied to the adaptive control NMOS transistor also changes. In this respect, the voltage supplied to the adaptive control NMOS transistor is adjusted for voltage. The NMOS transistor in the voltage subtraction unit, connected by two diodes, is affected by temperature in the same way as the NMOS transistor in unit 204. In this respect, the voltage supplied to the adaptive control NMOS transistor is adjusted for temperature. By supplying this PVT-adjusted voltage to the adaptive control NMOS transistor, the voltage subtraction unit 224 enables more finely tuned adaptive control of the negative bit convexity. Figure 2 As seen, the voltage subtraction unit 224 of the storage device 200 includes a bleeder switch 232 connected to the adaptive control line 220 to selectively pull the adaptive control line 220 to zero volts at the start of each write operation.
[0050] In various embodiments of this disclosure, such as Figure 2 As shown, the source of PMOS transistor 238 is connected to the source of NMOS transistor 234 (connected by a first diode) and the gate of NMOS transistor 236 (connected by a second diode). PMOS transistor 238 quickly stabilizes the adaptive control line voltage, thereby preventing the voltage on the adaptive control line from continuing to increase.
[0051] In various embodiments of this disclosure, limiting negative bit bulges at higher voltages helps ensure reliable operation of the storage device over a wide voltage range.
[0052] in conclusion
[0053] Many modifications and other embodiments of the invention described herein will readily occur to those skilled in the art, aided by the teachings provided in this specification and the accompanying drawings. Although the drawings show only some components of the apparatus and systems described herein, it should be understood that various other components can be used in conjunction with said systems. Therefore, it should be understood that this disclosure is not limited to the specific embodiments disclosed, and that such modifications and other embodiments are intended to be included within the scope of the appended claims. Furthermore, the steps in the described methods do not necessarily occur in the order depicted in the drawings, and in some cases, one or more of the depicted steps may occur substantially simultaneously, or additional steps may be involved. Although specific terminology is used herein, it is used only in a general and descriptive sense and not for limiting purposes.
[0054] Although various embodiments based on the principles disclosed herein have been shown and described above, those skilled in the art can modify them without departing from the spirit and teachings of this disclosure. The embodiments described herein are merely representative and are not intended to be limiting. Many variations, combinations, and modifications are possible and are within the scope of this disclosure. Alternative embodiments resulting from combining, integrating, and / or omitting features of the embodiments are also within the scope of this disclosure. Therefore, the scope of protection is not limited by the foregoing description.
[0055] Furthermore, the section headings used herein are for the purpose of maintaining consistency with the recommendations under 37 CFR 1.77, or to otherwise provide organizational clues. These headings do not limit or characterize the disclosure set forth in any claims that may arise from this disclosure.
[0056] While some embodiments of this disclosure have been set forth in the detailed description herein, the appended claims cover other embodiments of this disclosure that differ from the described embodiments, according to various modifications and improvements. For example, the appended claims may cover any form of memory device, such as any form of SRAM memory device.
[0057] In the appended claims, unless the specific terms “means for…” or “steps for…” are used in a given claim, the claim is not intended to be interpreted in accordance with paragraph 6 of 35 USC 112.
Claims
1. A memory device, comprising: Multiple bit units are arranged into a matrix of rows and columns; Multiple bit lines, each bit line connected to a bit cell in the column of the corresponding bit cell; Multiple bit inverting lines, each bit inverting line is connected to a bit cell in the column of the corresponding bit cell; Multiple word lines, each word line connecting to a bit cell in the corresponding row of bit cells; Multiple write driver lines, each of which can be selectively connected to the bit line or bit inversion line of at least one corresponding bit cell column; Multiple write driver line switches are used to selectively connect the corresponding write driver lines to ground; Multiple boost capacitors, each boost line capacitor connected to a corresponding write driver line, are used to selectively inject negative charge into it; as well as Multiple adaptive control transistors, each connected to a corresponding write driver line, are used to automatically remove some of the negative charge on the gate of the adaptive control transistor when the voltage applied to the gate of the adaptive control transistor is equal to or exceeds the threshold voltage of the adaptive control transistor.
2. The memory device according to claim 1, wherein, The memory device includes a static random access memory device.
3. The memory device according to claim 1, wherein, Each of the plurality of adaptive control transistors includes an N-channel metal-oxide-semiconductor (NMOS) transistor.
4. The memory device according to claim 1, wherein, The voltage applied to the gate of each of the adaptive control transistors is the process-voltage-temperature (PVT) adjusted operating voltage of the memory device.
5. The memory device according to claim 1, wherein, The voltage applied to the gate of each of the adaptive control transistors is the process-voltage-temperature (PVT) adjusted value of the operating voltage of the memory device minus the voltage variation selected to underdrive the plurality of word lines.
6. The memory device according to claim 5, wherein, The voltage applied to each of the plurality of word lines is provided by the read auxiliary word line underdrive circuit; as well as The operating voltage of the memory device minus the voltage variation selected to underdrive the plurality of word lines is provided by a copy of the read auxiliary word line underdrive circuit.
7. The memory device according to claim 1, wherein, Each of the plurality of write driver line switches includes a metal-oxide-semiconductor (MOS) transistor.
8. The memory device according to claim 1, wherein, The voltage applied to the gate of each of the adaptive control transistors is selectively delivered from the voltage subtraction unit via an adaptive control line; as well as The voltage subtraction unit includes an N-channel metal-oxide-semiconductor (NMOS) transistor connected in series with a first diode and an NMOS transistor connected in series with a second diode.
9. The memory device of claim 8, further comprising a P-channel metal-oxide-semiconductor (PMOS) transistor to stabilize the adaptive control line voltage, wherein, The source of the PMOS transistor is connected to the source of the NMOS transistor connected by the first diode and the gate of the NMOS transistor connected by the second diode.
10. The memory device of claim 8, further comprising a bleed switch connected to the adaptive control line to selectively pull the adaptive control line to zero volts at the start of each write operation.
11. The memory device according to claim 1, wherein, The threshold voltage of each of the adaptive control transistors is selected to limit the difference between the voltage applied to each of the plurality of word lines and the voltage on the write driver line, thereby limiting overstress of one or more components of the memory device.
12. A method for adaptive write control of a memory device, the method comprising: Negative charge is injected into each of a plurality of write driver lines via a plurality of boost capacitors, each boost line capacitor being connected to a corresponding one of the plurality of write driver lines, each write driver line being selectively connected to one of a plurality of bit lines or one of a plurality of bit lines of at least one of a corresponding bit cell arranged in a matrix of rows and columns. as well as A voltage is automatically applied to the gate of each of a plurality of adaptive control transistors, each of which is connected to a corresponding one of the plurality of write driver lines, so as to remove some of the negative charge on each of the plurality of write driver lines when the voltage applied to the gate of each adaptive control transistor is equal to or exceeds the threshold voltage of the corresponding adaptive control transistor. Each of the plurality of bit lines and each of the plurality of bit inversion lines is connected to a bit cell in the column of the corresponding bit cell.
13. The method according to claim 12, wherein, The memory device includes a static random access memory device.
14. The method according to claim 12, wherein, Each of the plurality of adaptive control transistors includes an N-channel metal-oxide-semiconductor (NMOS) transistor.
15. The method according to claim 12, wherein, The voltage applied to the gate of each of the adaptive control transistors is the process-voltage-temperature (PVT) adjusted operating voltage of the memory device.
16. The method according to claim 12, wherein, The voltage applied to the gate of each of the adaptive control transistors is the process-voltage-temperature (PVT) adjusted operating voltage of the memory device minus the voltage variation selected to underdrive multiple word lines, each word line being connected to a bit cell in a row of corresponding bit cells.
17. The method according to claim 16, wherein, The voltage applied to each of the plurality of word lines is provided by the read auxiliary word line underdrive circuit; as well as The operating voltage of the memory device minus the voltage variation selected to underdrive the plurality of word lines is provided by a copy of the read auxiliary word line underdrive circuit.
18. The method according to claim 12, wherein, The voltage applied to the gate of each of the adaptive control transistors is selectively delivered from the voltage subtraction unit via an adaptive control line; The voltage subtraction unit includes an N-channel metal-oxide-semiconductor (NMOS) transistor connected in series with a first diode and an NMOS transistor connected in series with a second diode; and The method further includes stabilizing the adaptive control line voltage by connecting the source of the P-channel metal-oxide-semiconductor (PMOS) transistor to the source of the first diode-connected NMOS transistor and the gate of the second diode-connected NMOS transistor.
19. The method of claim 18, further comprising selectively pulling each of the adaptive control lines to zero volts at the start of each write operation.
20. The method according to claim 12, wherein, The threshold voltage of each of the adaptive control transistors is selected to limit the difference between the voltage applied to each of the plurality of word lines and the voltage on the write driver line, thereby limiting overstress of one or more components of the memory device. Each word line connects to a bit cell in the corresponding row of bit cells.