Memory device and operating method thereof, memory system

Abstract

The present disclosure provides a memory device and an operating method thereof, a memory system, the memory device comprising a memory array and a peripheral circuit coupled with the memory array; the peripheral circuit is configured to: perform a first detection operation on a plurality of memory cells coupled with a target word line in the memory array to obtain a first detection result; the first detection operation comprises a plurality of read stages, and different read voltages are applied to the target word line in different read stages; the first detection result comprises detection states of the plurality of read stages included in the first detection operation; perform a second detection operation on the plurality of memory cells coupled with the target word line based on the first detection result; the number of read stages included in the second detection operation is obtained based on the detection states of the plurality of read stages included in the first detection operation.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device and its operation method, and a memory system. Background Technology

[0002] Memory devices are storage equipment used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become the mainstream product in the memory market due to its high storage density, controllable production costs, and suitable erase / encode speeds. However, as people's requirements for storage devices continue to increase, memory devices and their systems still have considerable room for improvement. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a memory device and a method for operating the same, as well as a memory system.

[0004] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0005] In a first aspect, this disclosure provides a memory device, including a memory array and peripheral circuitry coupled to the memory array; the peripheral circuitry is configured to:

[0006] A first detection operation is performed on multiple memory cells in the memory array that are coupled to a target word line to obtain a first detection result; the first detection operation includes multiple read stages, and different read voltages are applied to the target word line at different read stages; the first detection result includes the detection status of the multiple read stages included in the first detection operation;

[0007] A second detection operation is performed on a plurality of memory cells coupled to the target word line based on the first detection result; the number of read stages included in the second detection operation is obtained based on the detection status of the plurality of read stages included in the first detection operation.

[0008] In an alternative implementation, the peripheral circuitry is further configured as follows:

[0009] In the first reading phase, N sensing operations are performed, and the N sensing operations are performed at N different time points in the first reading phase; the first reading phase is one of the multiple reading phases included in the first detection operation; and N is an integer greater than 1.

[0010] The detection state of the first reading stage is obtained based on the sensing results of the N sensing operations in the first reading stage.

[0011] In one alternative implementation, the peripheral circuit is specifically configured as follows:

[0012] The number of storage cells in the first storage state is obtained based on the sensing results of the sensing operation in the first reading phase; the sensing operation is any one of the N sensing operations; the threshold voltage of the storage cell in the first storage state is less than the compensation reading voltage corresponding to the time point when the sensing operation is performed; the compensation reading voltage is greater than or equal to the reading voltage of the first reading phase.

[0013] In one optional implementation, N is an integer greater than 3; the peripheral circuit is specifically configured as follows:

[0014] Based on the sensing results of the N sensing operations in the first reading phase, N-1 differences are obtained; any one of the N-1 differences is the difference in the number of storage cells in the first storage state obtained based on the sensing results of two adjacent sensing operations in the N sensing operations; the first detection result also includes the changing trend of the N-1 differences.

[0015] The detection status of the first reading stage is obtained based on the changing trend of the N-1 differences.

[0016] In an alternative implementation, the peripheral circuitry is further configured as follows:

[0017] Mark the detection state of the first reading stage; if the trend of the N-1 differences is increasing or decreasing, mark the detection state of the first reading stage as the first state; if the trend of the N-1 differences is decreasing first and then increasing, mark the detection state of the first reading stage as the second state.

[0018] In one optional implementation, the number of reading stages included in the second detection operation is the difference between the number of reading stages included in the first detection operation and the number of reading stages in the first detection operation whose detection state is the second state.

[0019] In one optional implementation, the detection state of the first reading stage is the first state; the peripheral circuit is further configured to:

[0020] The reading voltage of the second reading stage corresponding to the first reading stage is obtained based on the reading voltage of the first reading stage and the changing trend of the N-1 differences; the second reading stage is a reading stage in the second detection operation.

[0021] In one optional implementation, the detection state of the first reading phase is the second state; the peripheral circuit is further configured to:

[0022] Based on the changing trends of the N-1 differences in the first reading phase and the compensation reading voltage corresponding to the time points of the N sensing operations, a reading reference voltage corresponding to the first reading phase is obtained; the first detection result also includes the reading reference voltage.

[0023] In one alternative implementation, a plurality of memory cells coupled to the target word line are configured to store M pages of data; where M is a positive integer; the peripheral circuitry is configured as follows:

[0024] Multiple detection operations are performed on multiple memory cells coupled to the target word line to obtain multiple read reference voltages; the first detection operation and the second detection operation are two adjacent detection operations in the multiple detection operations;

[0025] A read operation is performed on a plurality of memory cells coupled to the target word line using the plurality of read reference voltages to obtain one page of data from the M pages of data.

[0026] Secondly, this disclosure provides a memory system, comprising:

[0027] At least one memory device according to any of the above embodiments;

[0028] A controller is coupled to at least one of the memory devices and configured to control the memory devices.

[0029] In one alternative implementation, the controller is configured to send a first detection command;

[0030] The peripheral circuit is configured to: execute the first detection operation in response to the first detection command; and send the first detection result to the controller;

[0031] The controller is also configured to generate a second detection command based on the first detection result;

[0032] The peripheral circuit is also configured to execute the second detection operation in response to the second detection command.

[0033] Thirdly, this disclosure provides a method for operating a memory device, including:

[0034] A first detection operation is performed on multiple memory cells in the memory array that are coupled to a target word line to obtain a first detection result; the first detection operation includes multiple read stages, and different read voltages are applied to the target word line at different read stages; the first detection result includes the detection status of the multiple read stages included in the first detection operation;

[0035] A second detection operation is performed on a plurality of memory cells coupled to the target word line based on the first detection result; the number of read stages included in the second detection operation is obtained based on the detection status of the plurality of read stages included in the first detection operation.

[0036] In one optional implementation, the operation method further includes:

[0037] In the first reading phase, N sensing operations are performed, and the N sensing operations are performed at N different time points in the first reading phase; the first reading phase is one of the multiple reading phases included in the first detection operation; and N is an integer greater than 1.

[0038] The detection state of the first reading stage is obtained based on the sensing results of the N sensing operations in the first reading stage.

[0039] In one optional implementation, the operation method further includes:

[0040] The number of storage cells in the first storage state is obtained based on the sensing results of the sensing operation in the first reading phase; the sensing operation is any one of the N sensing operations; the threshold voltage of the storage cell in the first storage state is less than the compensation reading voltage corresponding to the time point when the sensing operation is performed; the compensation reading voltage is greater than or equal to the reading voltage of the first reading phase.

[0041] In one optional implementation, obtaining the detection state of the first reading stage based on the sensing results of the N sensing operations in the first reading stage includes:

[0042] Based on the sensing results of the N sensing operations in the first reading phase, N-1 differences are obtained; any one of the N-1 differences is the difference in the number of storage cells in the first storage state obtained based on the sensing results of two adjacent sensing operations in the N sensing operations; the first detection result also includes the changing trend of the N-1 differences; where N is an integer greater than 3.

[0043] The detection status of the first reading stage is obtained based on the changing trend of the N-1 differences.

[0044] In one optional implementation, the operation method further includes:

[0045] Mark the detection state of the first reading stage; if the trend of the N-1 differences is increasing or decreasing, mark the detection state of the first reading stage as the first state; if the trend of the N-1 differences is decreasing first and then increasing, mark the detection state of the first reading stage as the second state.

[0046] In one optional implementation, the number of reading stages included in the second detection operation is the difference between the number of reading stages included in the first detection operation and the number of reading stages in the first detection operation whose detection state is the second state.

[0047] In one optional implementation, the detection state of the first reading stage is the first state; the operation method further includes:

[0048] The reading voltage of the second reading stage corresponding to the first reading stage is obtained based on the reading voltage of the first reading stage and the changing trend of the N-1 differences; the second reading stage is a reading stage in the second detection operation.

[0049] In one optional implementation, the detection state of the first reading phase is the second state; the operation method further includes:

[0050] Based on the changing trends of the N-1 differences in the first reading phase and the compensation reading voltage corresponding to the time points of the N sensing operations, a reading reference voltage corresponding to the first reading phase is obtained; the first detection result also includes the reading reference voltage.

[0051] In one optional implementation, the operation method includes:

[0052] Multiple detection operations are performed on multiple memory cells coupled to the target word line to obtain multiple read reference voltages; the first detection operation and the second detection operation are two adjacent detection operations in the multiple detection operations;

[0053] A read operation is performed on a plurality of memory cells coupled to the target word line using the plurality of read reference voltages to obtain one page of data from the M pages of data stored in the plurality of memory cells; where M is a positive integer. Attached Figure Description

[0054] Figure 1 A schematic diagram of an electronic device including a memory system provided for an embodiment of this disclosure;

[0055] Figure 2 A schematic diagram of a memory card provided in an embodiment of this disclosure;

[0056] Figure 3 A schematic diagram of a solid-state drive provided in an embodiment of this disclosure;

[0057] Figure 4 Schematic diagram of a memory device provided for embodiments of this disclosure Figure 1 ;

[0058] Figure 5 Schematic diagram of a memory device provided for embodiments of this disclosure Figure 2 ;

[0059] Figure 6 A schematic diagram of the threshold voltage distribution of a memory cell coupled to a target word line, provided in an embodiment of this disclosure;

[0060] Figure 7 A schematic diagram of two adjacent threshold voltage portions provided in an embodiment of this disclosure;

[0061] Figure 8 Voltage curves for performing the first detection operation and the second detection operation provided in embodiments of this disclosure;

[0062] Figure 9 A schematic diagram of the first reading stage provided for an embodiment of this disclosure;

[0063] Figure 10 A schematic diagram of a memory system provided in an embodiment of this disclosure;

[0064] Figure 11 This is a flowchart illustrating the operation method of a memory device provided in an embodiment of this disclosure. Detailed Implementation

[0065] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0066] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0067] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0068] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0069] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0070] The memory systems in the embodiments of this disclosure include, but are not limited to, memory systems including three-dimensional NAND type memory. For ease of understanding, the memory systems provided in this disclosure will be described using a memory system including three-dimensional NAND type memory as an example.

[0071] Figure 1 This is a schematic diagram of an exemplary system with a memory system provided for embodiments of this disclosure. In embodiments of this disclosure, system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1As shown, system 100 may include a host device 101 and a memory system 102. The memory system 102 may include one or more memory devices 103 and a controller 104. The host device 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host device 101 may be configured to send data to or receive data from the memory system 102.

[0072] In some embodiments, controller 104 is coupled to memory device 103 and host device 101 and is configured to control memory device 103. Controller 104 can manage data stored in memory device 103 and communicate with host device 101. In some embodiments, controller 104 is designed to operate in low duty cycle environments, such as in secure digital cards, compact flash cards (CFC), Universal Serial Bus (USB) flash drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, controller 104 is designed to operate in high duty cycle environments, such as in solid-state drives or embedded multi-media cards (eMMC).

[0073] In some embodiments, the controller 104 and one or more memory devices 103 can be integrated into various types of storage devices, that is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0074] In such Figure 2 In one example shown, the controller 104 and a single memory device 103 can be integrated into a memory card 201. The memory card 201 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 201 may also include a connection between the memory card 201 and a host device (e.g., Figure 1 The host device 101) is coupled to the memory card connector 202. In such a... Figure 3 In another example shown, the controller 104 and multiple memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include a connection between the SSD 203 and a host device (e.g., Figure 1 The SSD connector 204 is coupled to the host device 101. In some embodiments, the storage capacity and / or operating speed of the SSD 203 is greater than the storage capacity and / or operating speed of the memory card 201.

[0075] Figure 4 A circuit diagram of an exemplary memory device 300 including peripheral circuitry, provided for embodiments of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 103 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND type memory array, where memory cells 305 are NAND memory cells, provided in the form of an array of memory cell strings 304, each memory cell string 304 extending vertically above a substrate (not shown). In some embodiments, each memory cell string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 305. Each memory cell 305 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0076] In some implementations, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0077] like Figure 4As shown, each memory cell string 304 may include a bottom select transistor (BST) 307 at its source end and a top select transistor (TST) 306 at its drain end. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory cell string 304 during read and program operations. In some embodiments, the sources of memory cell strings 304 within the same memory block 303 may be coupled via a common source line (CSL) 310. In other words, all memory cell strings 304 within the same memory block 303 share a common source (ACS). According to some embodiments, the top select transistor 306 of each memory cell string 304 is coupled to a corresponding bit line (BL) 311, from which data can be read or written via an output bus (not shown). In some implementations, each memory cell string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the top select gate (TSG) of the corresponding top select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the bottom select gate (BSG) of the corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0078] like Figure 4 As shown, the memory cell string 304 can be organized into multiple memory blocks 303, each of which may have a common source line 310. In some embodiments, each memory block 303 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. To erase memory cells 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 of adjacent memory cell strings 304 can be coupled via word lines 312, which select which row of memory cells 305 is affected by a read or program operation.

[0079] In some embodiments, peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 305 via bit line 311, word line 312, common-source line 310, bottom select line 309, and top select line 308, and for sensing voltage and / or current signals from each target memory cell 305 to operate the memory array 301. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0080] Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, control logic 405, a register set 406, a flash memory interface 407, and a data bus 408. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0081] Page buffer / sensor amplifier 401 can be configured to read data from and program (write) data to memory array 301 according to control signals from control logic 405. In one example, page buffer / sensor amplifier 401 can store a page of programming data (write data) to be programmed into memory array 301. In another example, page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 401 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 402 can be configured to be controlled by control logic 405 and select one or more memory cell strings by applying a bit line voltage generated from voltage generator 404.

[0082] The row decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks of memory array 301 and select / deselect word lines of memory blocks. The row decoder / word line driver 403 can also be configured to drive word lines using word line voltages generated from voltage generator 404. In some embodiments, the row decoder / word line driver 403 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the row decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0083] Control logic 405 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register set 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from host devices (not shown) and relay them to control logic 405, as well as to buffer status information received from control logic 405 and relay it to the controller. Flash interface 407 can also be coupled to column decoder / bitline driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0084] In some embodiments, data stored in multi-level storage units can be read using a single-page read method. Taking a four-level cell (QLC) storage unit as an example... Figure 6This diagram illustrates the threshold voltage distribution of a memory cell coupled to the target word line. Each memory cell stores four bits of data. The threshold voltage of each memory cell falls within the range of one of several threshold voltage distributions corresponding to the erase state P0 and the fifteen programming states P1 to P15. Each threshold voltage distribution corresponds to a Gray code. Based on the Gray code encoding method, the data stored in multiple memory cells can be logically divided into four pages: the top page (UP), the middle page (MP), the bottom page (LP), and the extra page (XP). Taking reading the data of the bottom page (LP) using a single-page read method as an example, read voltages V1, V2, V3, and V4 can be applied to the target word line. Here, the Gray code encoding method is only an example. When different encoding methods are used to write the Gray code, the number and magnitude of the read voltages required to read the data of each page will also be different. This disclosure does not limit the specific encoding method of the Gray code.

[0085] In the read method provided in the above embodiments, the read voltage applied to the target word line is usually the default read voltage. However, over time or due to environmental factors (such as temperature), the threshold voltage of the memory cell may change, which may lead to a shift and / or widening of the threshold voltage distribution. Figure 7 This is a schematic diagram showing the distribution of two adjacent threshold voltages, referencing... Figure 7 Two adjacent threshold voltage distributions may overlap, and if the default read voltage Vrd0 is used to perform the read operation after the threshold voltage distribution shifts and / or widens, a large number of error bits (Fail Bit Count, FBC) may be generated. In this case, a valley search operation can be used to redetermine the read voltage to improve the reliability of the read operation.

[0086] In some embodiments, continue to refer to Figure 7 Valley search operations can include multiple single-level read operations. For example, single-level read operations can be performed using read voltages Vrd0, Vrd1, Vrd2, Vrd3, and Vrd4 respectively. Here, read voltages Vrd1, Vrd2, Vrd3, and Vrd4 are all compensation read voltages obtained based on the default read voltage Vrd0. Based on the read results of multiple single-level read operations, the changing trend of the number of memory cells with threshold voltages lower than the read voltage can be obtained. Based on this changing trend, the read reference voltage can be obtained. For example, the read reference voltage here can be Vrd1, and its magnitude can be equal to the default read voltage Vrd0 minus the compensation value.

[0087] However, in conjunction with reference Figure 6 and Figure 7When the memory cell is a QLC or other multi-level cell, the number of valleys between adjacent threshold voltage distributions is large. This necessitates multiple valley search operations to obtain multiple read reference voltages corresponding to these valleys. Furthermore, each valley search operation includes multiple single-level read operations, which results in a prolonged search time to obtain all read reference voltages. Consequently, the read operation efficiency is low, impacting the overall performance of the memory device. To address this, the present disclosure provides the following implementation method.

[0088] This disclosure provides a memory device, in conjunction with reference to [reference]. Figure 4 and Figure 5 The memory device 300 includes a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. The peripheral circuitry 302 can be configured to: perform a first detection operation on a plurality of memory cells in the memory array 301 coupled to a target word line to obtain a first detection result; the first detection operation includes multiple read stages, and different read voltages are applied to the target word line at different read stages; the first detection result includes the detection states of the multiple read stages included in the first detection operation; and perform a second detection operation on the plurality of memory cells coupled to the target word line based on the first detection result; the number of read stages included in the second detection operation is obtained based on the detection states of the multiple read stages included in the first detection operation. Here, the target word line can be any word line 312 in the memory array 301.

[0089] Figure 8 The voltage curves for performing the first and second detection operations provided in the embodiments of this disclosure are referenced. Figure 8 The first detection operation includes multiple reading stages. Here, taking the first detection operation as having four reading stages (reading stage A1, reading stage B1, reading stage C1 and reading stage D1) as an example, the peripheral circuit 302 can be configured to apply different reading voltages to the target word line in different reading stages.

[0090] In some specific examples, in conjunction with reference Figure 6 and Figure 8 The first detection operation can be performed on multiple valleys of a logical page. For example, the first detection operation can be performed on the four valleys of the next page LP. Then, the read voltages of the four read stages included in the first detection operation can be four read voltages V1, V2, V3, and V4 used to read the next page LP. Here, we take the example of applying four read voltages to the target word line in descending order of read voltage as an example. However, this disclosure is not limited to this. In other embodiments, read voltages can also be applied to the target word line in ascending order of read voltage. This disclosure does not impose specific limitations on this.

[0091] In this embodiment of the disclosure, the valley search operation can be performed on a logical page basis, which can improve the efficiency of the valley search operation compared to the valley search operation performed on a valley floor basis.

[0092] In some embodiments, the peripheral circuit 302 is further configured to: perform N sensing operations in the first reading phase, wherein the N sensing operations are performed at N different time points in the first reading phase; the first reading phase is one of the multiple reading phases included in the first detection operation; N is an integer greater than 1; and obtain the detection state of the first reading phase based on the sensing results of the N sensing operations in the first reading phase.

[0093] In some embodiments, the peripheral circuit 302 is specifically configured to: obtain the number of memory cells in a first storage state among a plurality of memory cells based on the sensing result of the sensing operation in the first reading phase. Here, the sensing operation is any one of the N sensing operations performed in the first reading phase; the threshold voltage of the memory cell in the first storage state is less than the compensation reading voltage corresponding to the time point at which the sensing operation is performed; the compensation reading voltage is greater than or equal to the reading voltage of the first reading phase.

[0094] Figure 9 A schematic diagram of the first reading stage provided in an embodiment of this disclosure, with reference to... Figure 9 The peripheral circuit 302 can be configured to: apply a reading voltage V0 to the target word line during the first reading phase; after the voltage on the target word line stabilizes at the reading voltage V0, perform N sensing operations, and perform the N sensing operations at N different time points during the first reading phase. Here, taking N=4 as an example, the reading phase includes four sensing operations performed at t1, t2, t3, and t4 respectively; the reading voltage V0 can be equal to any one of the reading voltages V1, V2, V3, and V4.

[0095] It is understandable that when a read voltage V0 is applied to the target word line, for memory cells whose threshold voltage is lower than the read voltage V0 among multiple memory cells coupled to the target word line, the larger the difference between the read voltage V0 and the threshold voltage of the memory cell, the faster the memory cell turns on; conversely, the smaller the difference between the read voltage V0 and the threshold voltage of the memory cell, the slower the memory cell turns on. Therefore, when a sensing operation is performed at different time points, the number of memory cells in the first storage state obtained based on the sensing results will be different. Here, the threshold voltage of the memory cells in the first storage state is lower than the compensation read voltage corresponding to the time point when the sensing operation is performed. Specifically, refer to... Figure 9The magnitude of the compensation read voltage at time point t1 corresponding to the first sensing operation can be equal to V0 + ΔV1, and the number of storage cells in the first storage state obtained based on the sensing result can be D1; the magnitude of the compensation read voltage at time point t2 corresponding to the second sensing operation can be equal to V0 + ΔV2, and the number of storage cells in the first storage state obtained based on the sensing result can be D2; the magnitude of the compensation read voltage at time point t3 corresponding to the third sensing operation can be equal to V0 + ΔV3, and the number of storage cells in the first storage state obtained based on the sensing result can be D3; the magnitude of the compensation read voltage at time point t4 corresponding to the fourth sensing operation can be equal to V0 + ΔV4, and the number of storage cells in the first storage state obtained based on the sensing result can be D3, and ΔV4 > ΔV3 > ΔV2 > ΔV1, D4 > D3 > D2 > D1.

[0096] In this embodiment of the disclosure, a reading phase may include multiple sensing operations performed at different time points. Thus, multiple shifts in the reading voltage can be simulated while keeping the reading voltage on the target word line constant. Compared to the method of performing multiple reading operations with different reading voltages, this can greatly improve the efficiency of valley search for a valley.

[0097] In some embodiments, the peripheral circuit 302 is specifically configured to: obtain N-1 differences based on the sensing results of N sensing operations in the first reading phase; any one of the N-1 differences is the difference in the number of memory cells in the first storage state obtained based on the sensing results of two adjacent sensing operations in the N sensing operations; the first detection result also includes the changing trend of the N-1 differences; and obtain the detection state of the first reading phase based on the changing trend of the N-1 differences. For example, referring to... Figure 9 The peripheral circuit 302 can be configured to obtain three differences based on the sensing results of four sensing operations in the first reading stage. The three differences can be △D1, △D2, and △D3, where △D1 = D2 - D1, △D2 = D3 - D2, and △D3 = D4 - D3. The peripheral circuit 302 can be configured to obtain the detection state of the first reading stage based on the changing trends of △D1, △D2, and △D3.

[0098] In this embodiment, the trend of the N-1 differences can be increasing, decreasing, or decreasing then increasing. Specifically, when the trend of the N-1 differences is increasing, it means that the N compensated read voltages corresponding to the N time points of the N sensing operations are all greater than the read reference voltage, and the detection state should be failure, indicating that the read reference voltage has not yet been determined. When the trend of the N-1 differences is decreasing, it means that the N compensated read voltages corresponding to the N time points of the N sensing operations are all less than the read reference voltage, and the detection state should also be failure. When the trend of the N-1 differences is decreasing then increasing, it means that the N compensated read voltages corresponding to the N time points of the N sensing operations include compensated read voltages greater than the read reference voltage and compensated read voltages less than the read reference voltage, and the detection state should be success, indicating that the read reference voltage can be determined.

[0099] In some embodiments, the peripheral circuit 302 is further configured to: mark the detection state of the first reading stage; if the trend of the N-1 differences is increasing or decreasing, mark the detection state of the first reading stage as the first state; if the trend of the N-1 differences is decreasing first and then increasing, mark the detection state of the first reading stage as the second state.

[0100] In some embodiments, the detection state of the first reading stage can be a second state, then the peripheral circuit 302 is further configured to: obtain a reading reference voltage corresponding to the first reading stage based on the changing trend of N-1 differences in the first reading stage and the compensation reading voltage at the time points of performing N sensing operations. For example, referring to Figure 9 If △D2 is the minimum among △D1, △D2 and △D3, then V0+△V2 or V0+△V3 can be used as the reading reference voltage corresponding to the first reading stage. Alternatively, the reading reference voltage can be determined based on the changing trends of △D1, △D2 and △D3 using a fitting algorithm. In this case, the reading reference voltage may not be equal to any one of the compensation reading voltages.

[0101] In this embodiment of the disclosure, the detection status of multiple reading stages in the first detection operation can be obtained by the method for obtaining the detection status of the first reading stage provided by the above embodiment, and the peripheral circuit 302 can mark the detection status of multiple reading stages in the first detection operation.

[0102] In a specific example, refer to Figure 8 The detection states of reading phase A1, reading phase C1 and reading phase D1 can all be in the first state (FAIL), and the detection state of reading phase B1 can be in the second state (PASS).

[0103] In some embodiments, the number of read stages included in the second detection operation is the difference between the number of read stages included in the first detection operation and the number of read stages in the first detection operation whose detection state is the second state. For example, refer to Figure 8 The first detection operation includes four reading stages, and one of the four reading stages has a detection state of the second state. Therefore, the second detection operation includes three reading stages.

[0104] In this embodiment of the disclosure, since the offset of different threshold voltage distributions may be different, the progress of valley search for different valleys in the threshold voltage distribution may be different. For example, for the valley corresponding to reading stage B1 in the first detection operation, its reading reference voltage can be determined in the first detection operation. However, for the valleys corresponding to reading stages A1, C1, and D1, their reading reference voltage cannot be determined by the first detection operation. Therefore, at least one more detection operation needs to be performed, namely the second detection operation. In the process of performing the second detection operation, the reading stage corresponding to reading stage B1 can be omitted, and only the reading stage A2 corresponding to reading stage A1, the reading stage C2 corresponding to reading stage C1, and the reading stage D2 corresponding to reading stage D1 are included. As a result, the time for performing the next detection operation can be shortened, thereby further improving the efficiency of the valley search operation.

[0105] In some specific examples, refer to Figure 5 The control logic 405 in the peripheral circuit 302 can be configured to store the detection status of multiple reading stages in the detection operation in register 406 after performing a detection operation. When performing the next detection operation, the detection status of multiple reading stages can be obtained from register 406 to determine which reading stages can be omitted. After the next detection operation is completed, the detection status of the reading stages can be updated.

[0106] In some embodiments, the detection state of the first reading stage can be a first state. Then, the peripheral circuit 302 is further configured to: obtain the reading voltage of the second reading stage corresponding to the first reading stage based on the reading voltage of the first reading stage and the changing trend of N-1 differences; the second reading stage is a reading stage in the second detection operation. Specifically, if the changing trend of the N-1 differences is increasing, the reading voltage of the second reading stage can be equal to the reading voltage of the first reading stage plus a negative compensation value; if the changing trend of the N-1 differences is decreasing, the reading voltage of the second reading stage can be equal to the reading voltage of the first reading stage plus a positive compensation value.

[0107] In this embodiment of the disclosure, for a reading stage where the detection state was in the first state in the previous detection operation, the reading voltage of the corresponding reading stage in the next detection operation can be obtained based on the changing trend of the reading voltage of that reading stage and N-1 differences. For example, referring to... Figure 8 The reading voltage of reading stage A2, corresponding to reading stage A1, can be the reading voltage V1 of reading stage A1 plus a compensation value △Va. The reading voltage of reading stage C2, corresponding to reading stage C1, can be the reading voltage V3 of reading stage C1 plus a compensation value △Vb. The reading voltage of reading stage D2, corresponding to reading stage D1, can be the reading voltage V4 of reading stage D1 plus a compensation value △Vc. Here, the compensation values ​​△Va, △Vb, and △Vc can be positive or negative.

[0108] In some embodiments, a plurality of memory cells coupled to a target word line are configured to store M pages of data, where M is a positive integer; peripheral circuitry 302 is configured to: perform multiple detection operations on the plurality of memory cells coupled to the target word line to obtain a plurality of read reference voltages; the first detection operation and the second detection operation are two adjacent detection operations in the multiple detection operations; and perform a read operation on the plurality of memory cells coupled to the target word line using the plurality of read reference voltages to obtain one page of data from the M pages of data. For example, in conjunction with reference to... Figure 6 and Figure 8 Taking M=4 as an example, performing multiple detection operations on multiple memory cells coupled to the target word line can yield four read reference voltages. The first and second detection operations are two adjacent detection operations in the multiple detection operations. By performing read operations on multiple memory cells coupled to the target word line using the four read reference voltages, one page of data (the next page LP) out of four pages can be obtained.

[0109] In this embodiment, the peripheral circuit can be configured to perform valley search operations in a highly efficient manner. Firstly, valley search operations for multi-level memory cells are performed on a logical page basis. A valley search operation for a single logical page can include multiple detection operations, and each detection operation can include multiple read stages. One read stage can correspond to a valley bottom, which is more efficient than a valley search method where each detection operation targets only one valley bottom. Secondly, after performing a detection operation, the detection states of each read stage in the detection operation can be marked. For a read stage where the read reference voltage can be determined (i.e., a read stage with a detection state of the second state), the corresponding read stage can be omitted in the next detection operation, thereby shortening the time of the next detection operation and improving the overall efficiency of the valley search operation. Thirdly, a read stage can include N sensing operations performed at different time points, which can simulate multiple offsets of the read voltage while keeping the read voltage of the target word line constant. This is more efficient than a valley search method that performs multiple read operations with different read voltages.

[0110] Based on a concept similar to the memory devices described above, this disclosure also provides a memory system, comprising: at least one memory device as described in any of the above embodiments; and a controller coupled to the at least one memory device and configured to control the memory device.

[0111] Figure 10 A schematic diagram of a memory system provided in an embodiment of this disclosure, with reference to... Figure 10 The memory system 500 includes a memory device 300 and a controller 501 coupled to the memory device 300. Here, the memory device 300 can be the memory device in any of the above embodiments, including a memory array 301 and peripheral circuitry 302 coupled to the memory array.

[0112] In some embodiments, the controller 501 may include a processor 5011 and a first interface 5012, a second interface 5013, and a cache 5014 coupled to the processor 5011 via a bus 5010. The controller 501 may be coupled to the memory device 300 via the second interface 5013. During data writing, the controller 501 may receive a write command, write data, and the logical address of the write data via the first interface 5012, and may temporarily store the write data in the cache 5014. It may also establish a logical address to physical address (L2P) mapping relationship for the write data. The controller 501 may send a programming command to the memory device 300 via the second interface 5013. The memory device 300 may receive the programming command and, in response to the programming command, receive the write data and the physical address of the write data, and store the write data in the memory array 301 at the location corresponding to the physical address of the write data.

[0113] In some embodiments, the controller 501 is configured to: send a first detection command; the peripheral circuit 302 is configured to: perform a first detection operation in response to the first detection command; and send a first detection result to the controller 501; the controller 501 is further configured to: generate a second detection command based on the first detection result; and the peripheral circuit 302 is further configured to: perform a second detection operation in response to the second detection command.

[0114] In this embodiment of the disclosure, the storage device in the memory system can execute a first detection operation in response to a first detection command generated by the controller. After executing the first detection operation, the peripheral circuit in the memory device can record or update the detection status of each reading stage in the first detection operation. The controller can generate a second detection command based on the first detection result of the first detection operation. Before executing the second detection operation in response to the second detection command, the peripheral circuit can obtain the detection status of multiple reading stages in the first detection operation and determine the number of reading stages in the second detection operation based on the detection status of multiple reading stages. For example, if the detection status of the first reading stage in the first detection operation is the second state, the second detection operation may not include the second reading stage corresponding to the first reading stage. Thus, the time of the second detection operation can be shortened, the efficiency of the valley search operation can be improved, and the efficiency of the memory system in performing the reading operation can be improved.

[0115] Based on a concept similar to the memory device described above, this disclosure also provides a method for operating a memory device. Figure 11 This is a flowchart illustrating an operation method of a memory device provided in an embodiment of this disclosure. The operation method of the memory device includes the following steps:

[0116] Step S10: Perform a first detection operation on multiple memory cells in the memory array that are coupled to the target word line to obtain a first detection result; the first detection operation includes multiple read stages, and different read voltages are applied to the target word line in different read stages; the first detection result includes the detection status of the multiple read stages included in the first detection operation;

[0117] Step S20: Perform a second detection operation on a plurality of memory cells coupled to the target word line based on the first detection result; the number of read stages included in the second detection operation is obtained based on the detection status of the plurality of read stages included in the first detection operation.

[0118] In some embodiments, the method of operating the memory device further includes: performing N sensing operations in a first reading phase, wherein the N sensing operations are performed at N different time points in the first reading phase; the first reading phase is one of a plurality of reading phases included in the first detection operation; N is an integer greater than 1; and obtaining the detection state of the first reading phase based on the sensing results of the N sensing operations in the first reading phase.

[0119] In some embodiments, the method of operating the memory device further includes: obtaining the number of memory cells in a first storage state among a plurality of memory cells based on the sensing result of a sensing operation in a first reading phase; the sensing operation is any one of N sensing operations; the threshold voltage of the memory cell in the first storage state is less than the compensation reading voltage corresponding to the time point at which the sensing operation is performed; and the compensation reading voltage is greater than or equal to the reading voltage of the first reading phase.

[0120] In some embodiments, obtaining the detection state of the first reading stage based on the sensing results of N sensing operations in the first reading stage includes: obtaining N-1 differences based on the sensing results of N sensing operations in the first reading stage; any one of the N-1 differences is the difference in the number of storage cells in the first storage state obtained based on the sensing results of two adjacent sensing operations in the N sensing operations; the first detection result also includes the changing trend of the N-1 differences; N is an integer greater than 3; and obtaining the detection state of the first reading stage based on the changing trend of the N-1 differences.

[0121] In some embodiments, the operation method of the memory device further includes: marking the detection state of the first reading stage; if the trend of the N-1 differences is increasing or decreasing, marking the detection state of the first reading stage as a first state; if the trend of the N-1 differences is decreasing first and then increasing, marking the detection state of the first reading stage as a second state.

[0122] In some embodiments, the number of reading stages included in the second detection operation is the difference between the number of reading stages included in the first detection operation and the number of reading stages in the plurality of reading stages included in the first detection operation where the detection state is the second state.

[0123] In some embodiments, the detection state of the first reading stage is a first state; the operation method of the memory device further includes: obtaining the reading voltage of the second reading stage corresponding to the first reading stage based on the reading voltage of the first reading stage and the changing trend of N-1 differences; the second reading stage is a reading stage in the second detection operation.

[0124] In some embodiments, the detection state of the first reading stage is a second state; the operation method of the memory device further includes: obtaining a reading reference voltage corresponding to the first reading stage based on the changing trend of N-1 differences in the first reading stage and the compensation reading voltage corresponding to the time point of performing N sensing operations; the first detection result further includes the reading reference voltage.

[0125] In some embodiments, the method of operating the memory device includes: performing multiple detection operations on a plurality of memory cells coupled to a target word line to obtain a plurality of read reference voltages; the first detection operation and the second detection operation are two adjacent detection operations in the plurality of detection operations; performing a read operation on the plurality of memory cells coupled to the target word line through the plurality of read reference voltages to obtain one page of data from M pages of data stored in the plurality of memory cells; M is a positive integer.

[0126] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0127] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0128] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory device, characterized in that, Includes a memory array and peripheral circuitry coupled to the memory array; the peripheral circuitry is configured to: A first detection operation is performed on multiple memory cells in the memory array that are coupled to a target word line to obtain a first detection result; the first detection operation includes multiple read stages, and different read voltages are applied to the target word line at different read stages; the first detection result includes the detection status of the multiple read stages included in the first detection operation; A second detection operation is performed on a plurality of memory cells coupled to the target word line based on the first detection result; the number of read stages included in the second detection operation is obtained based on the detection status of the plurality of read stages included in the first detection operation.

2. The memory device according to claim 1, characterized in that, The peripheral circuit is also configured to: N sensing operations are performed during the first reading phase, and the N sensing operations are performed at N different time points during the first reading phase. The first reading stage is one of the multiple reading stages included in the first detection operation; N is an integer greater than 1. The detection state of the first reading stage is obtained based on the sensing results of the N sensing operations in the first reading stage.

3. The memory device according to claim 2, characterized in that, The peripheral circuit is specifically configured as follows: The number of storage units in the first storage state among the plurality of storage units is obtained based on the sensing results of the sensing operation in the first reading phase; the sensing operation is any one of the N sensing operations; The threshold voltage of the storage cell in the first storage state is less than the compensation read voltage corresponding to the time point when the sensing operation is performed; the compensation read voltage is greater than or equal to the read voltage of the first read stage.

4. The memory device according to claim 3, characterized in that, N is an integer greater than 3; the peripheral circuit is specifically configured as follows: Based on the sensing results of the N sensing operations in the first reading phase, N-1 differences are obtained; any one of the N-1 differences is the difference in the number of storage cells in the first storage state obtained based on the sensing results of two adjacent sensing operations in the N sensing operations; the first detection result also includes the changing trend of the N-1 differences. The detection status of the first reading stage is obtained based on the changing trend of the N-1 differences.

5. The memory device according to claim 4, characterized in that, The peripheral circuit is also configured to: Mark the detection state of the first reading stage; if the trend of the N-1 differences is increasing or decreasing, mark the detection state of the first reading stage as the first state; if the trend of the N-1 differences is decreasing first and then increasing, mark the detection state of the first reading stage as the second state.

6. The memory device according to claim 5, characterized in that, The number of reading stages included in the second detection operation is the difference between the number of reading stages included in the first detection operation and the number of reading stages in the first detection operation whose detection state is the second state.

7. The memory device according to claim 5, characterized in that, The detection state during the first reading phase is the first state; the peripheral circuit is further configured as follows: The reading voltage of the second reading stage corresponding to the first reading stage is obtained based on the reading voltage of the first reading stage and the changing trend of the N-1 differences; the second reading stage is a reading stage in the second detection operation.

8. The memory device according to claim 5, characterized in that, The detection state of the first reading phase is the second state; the peripheral circuit is further configured as follows: Based on the changing trends of the N-1 differences in the first reading stage and the compensation reading voltage corresponding to the time points of the N sensing operations, a reading reference voltage corresponding to the first reading stage is obtained; The first detection result also includes the read reference voltage.

9. The memory device according to claim 1, characterized in that, Multiple memory cells coupled to the target word line are configured to store M pages of data; where M is a positive integer; the peripheral circuitry is configured as follows: Multiple detection operations are performed on multiple memory cells coupled to the target word line to obtain multiple read reference voltages; the first detection operation and the second detection operation are two adjacent detection operations in the multiple detection operations; A read operation is performed on a plurality of memory cells coupled to the target word line using the plurality of read reference voltages to obtain one page of data from the M pages of data.

10. A memory system, characterized in that, include: At least one memory device as described in any one of claims 1 to 9; A controller is coupled to at least one of the memory devices and configured to control the memory devices.

11. The memory system according to claim 10, characterized in that, The controller is configured to send a first detection command; The peripheral circuit is configured to: execute the first detection operation in response to the first detection command; and send the first detection result to the controller; The controller is also configured to generate a second detection command based on the first detection result; The peripheral circuit is also configured to execute the second detection operation in response to the second detection command.

12. A method of operating a memory device, characterized in that, include: A first detection operation is performed on multiple memory cells in the memory array that are coupled to the target word line to obtain a first detection result; The first detection operation includes multiple reading stages, and different reading voltages are applied to the target word line at different reading stages; the first detection result includes the detection status of the multiple reading stages included in the first detection operation; A second detection operation is performed on a plurality of memory cells coupled to the target word line based on the first detection result; the number of read stages included in the second detection operation is obtained based on the detection status of the plurality of read stages included in the first detection operation.

13. The method of operating the memory device according to claim 12, characterized in that, The operation method further includes: In the first reading phase, N sensing operations are performed, and the N sensing operations are performed at N different time points in the first reading phase; the first reading phase is one of the multiple reading phases included in the first detection operation; and N is an integer greater than 1. The detection state of the first reading stage is obtained based on the sensing results of the N sensing operations in the first reading stage.

14. The method of operating the memory device according to claim 13, characterized in that, The operation method further includes: The number of storage cells in the first storage state is obtained based on the sensing results of the sensing operation in the first reading phase; the sensing operation is any one of the N sensing operations; the threshold voltage of the storage cell in the first storage state is less than the compensation reading voltage corresponding to the time point when the sensing operation is performed; the compensation reading voltage is greater than or equal to the reading voltage of the first reading phase.

15. The method of operating the memory device according to claim 14, characterized in that, The detection state of the first reading stage is obtained based on the sensing results of the N sensing operations in the first reading stage, including: Based on the sensing results of the N sensing operations in the first reading phase, N-1 differences are obtained; any one of the N-1 differences is the difference in the number of storage cells in the first storage state obtained based on the sensing results of two adjacent sensing operations in the N sensing operations; the first detection result also includes the changing trend of the N-1 differences; where N is an integer greater than 3. The detection status of the first reading stage is obtained based on the changing trend of the N-1 differences.

16. The method of operating the memory device according to claim 15, characterized in that, The operation method further includes: Mark the detection state of the first reading stage; if the trend of the N-1 differences is increasing or decreasing, mark the detection state of the first reading stage as the first state; if the trend of the N-1 differences is decreasing first and then increasing, mark the detection state of the first reading stage as the second state.

17. The method of operating the memory device according to claim 16, characterized in that, The number of reading stages included in the second detection operation is the difference between the number of reading stages included in the first detection operation and the number of reading stages in the first detection operation whose detection state is the second state.

18. The method of operating the memory device according to claim 16, characterized in that, The detection state in the first reading phase is the first state; the operation method further includes: The reading voltage of the second reading stage corresponding to the first reading stage is obtained based on the reading voltage of the first reading stage and the changing trend of the N-1 differences; the second reading stage is a reading stage in the second detection operation.

19. The method of operating a memory device according to claim 16, characterized in that, The detection state in the first reading phase is the second state; the operation method further includes: Based on the changing trends of the N-1 differences in the first reading phase and the compensation reading voltage corresponding to the time points of the N sensing operations, a reading reference voltage corresponding to the first reading phase is obtained; the first detection result also includes the reading reference voltage.

20. The method of operating the memory device according to claim 12, characterized in that, The operation method includes: Multiple detection operations are performed on multiple memory cells coupled to the target word line to obtain multiple read reference voltages; the first detection operation and the second detection operation are two adjacent detection operations in the multiple detection operations; A read operation is performed on a plurality of memory cells coupled to the target word line using the plurality of read reference voltages to obtain one page of data from the M pages of data stored in the plurality of memory cells; where M is a positive integer.

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