Memory device

Abstract

A memory device is provided. A first selection circuit selectively connects a first global word line decoder to portions of a first global word line based on a selected even memory block. A second selection circuit delivers a first global word line select signal to the selected even memory block based on the selected even memory block. A third selection circuit selectively connects a second global word line decoder to portions of a second global word line based on a selected odd memory block. A fourth selection circuit delivers a second global word line select signal to the selected odd memory block based on the selected odd memory block.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a memory device. Background Technology

[0002] With the rapid development of semiconductor technology, memory capacity is increasing daily, and the word line length in memory cell arrays is also becoming longer. However, longer word lines lead to higher capacitive loads, requiring a corresponding increase in drive current. This results in a larger area for the charge pump circuit and increased current consumption, which is detrimental to energy conservation and carbon reduction. Summary of the Invention

[0003] The present invention provides a memory device that can effectively reduce the high capacitive load caused by long word lines, and avoid increasing the area and current consumption of the charge pump circuit.

[0004] The memory device of the present invention includes a memory cell array, an even-row decoder circuit, and an odd-row decoder circuit. The memory cell array includes a plurality of even-numbered memory blocks and a plurality of odd-numbered memory blocks. The even-row decoder circuit is coupled to the memory cell array and includes a first global word line decoder, a first selection circuit, and a second selection circuit. The first global word line decoder provides a plurality of first global word line selection signals. The first selection circuit is coupled to the first global word line decoder and the plurality of first global word lines, and selectively connects the first global word line decoder to a portion of the first global word lines based on the selected even-numbered memory block. The second selection circuit is coupled to the plurality of first global word lines and the plurality of even-numbered memory blocks, and transmits the plurality of first global word line selection signals to the selected even-numbered memory block. The odd-row decoder circuit is coupled to the memory cell array and includes a second global word line decoder, a second selection circuit, and a third selection circuit. The second global word line decoder provides a plurality of second global word line selection signals. The third selection circuit is coupled to the second global word line decoder and multiple second global word lines, and selects to connect the second global word line decoder to a portion of the second global word lines based on the selected odd-numbered memory blocks. The fourth selection circuit is coupled to the multiple second global word lines and the multiple odd-numbered memory blocks, and transmits the selection signals of the multiple second global word lines to the selected odd-numbered memory blocks.

[0005] In one embodiment of the present invention, the aforementioned memory device is a NAND memory device. Based on the above, in this embodiment, the first selection circuit selects and connects the first global word line decoder to a portion of the first global word lines based on the selected even-numbered memory blocks; the second selection circuit transmits the first global word line selection signal to the selected even-numbered memory blocks based on the selected even-numbered memory blocks; the third selection circuit selects and connects the second global word line decoder to a portion of the second global word lines based on the selected odd-numbered memory blocks; and the fourth selection circuit transmits the second global word line selection signal to the selected odd-numbered memory blocks based on the selected odd-numbered memory blocks. By selecting and connecting the global word line decoder to a portion of the global word lines based on the selected memory blocks, the length of the global word lines can be shortened, and the number of word line decoders connected to the global word line decoder can be reduced, effectively avoiding increasing the area and current consumption of the charge pump circuit. Attached Figure Description

[0006] Figure 1 and Figure 2 This is a schematic diagram of a memory device according to an embodiment of the present invention;

[0007] Figure 3 This is a schematic diagram of a transmission circuit according to an embodiment of the present invention;

[0008] Figure 4 and Figure 5 This is a schematic diagram of a memory device according to another embodiment of the present invention. Detailed Implementation

[0009] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0010] Please refer to the following: Figure 1 , Figure 1 This is a schematic diagram of a memory device according to an embodiment of the present invention. The memory device 100 may be, for example, a NAND memory device, including a memory cell array 102, an even-row decoder circuit 104, and an odd-row decoder circuit 106. The memory cell array 102 is coupled to the even-row decoder circuit 104 and the odd-row decoder circuit 106. The memory cell array 102 may include multiple memory blocks MB, which may include, for example, NAND strings. The even-row decoder circuit 104 decodes row addresses and selects the corresponding even-numbered memory blocks among the multiple memory blocks MB for reading or writing data. Similarly, the odd-row decoder circuit 106 decodes row addresses and selects the corresponding odd-numbered memory blocks among the multiple memory blocks MB for reading or writing data.

[0011] Furthermore, in Figure 1 In this embodiment, the storage cell array 102 may, for example, include 2048 memory blocks (MB), and the even-row decoder circuit 104 may be as follows: Figure 1 As shown, the array includes a first global word line decoder GWLDR1, a first selection circuit 108, and a second selection circuit 110. The first selection circuit 108 is coupled to the first global word line decoder GWLDR1 and is coupled to the second selection circuit 110 via the first global word lines EGWL1 and EGWL2. The second selection circuit 110 is also coupled to even-numbered memory blocks in the memory cell array 102. For example, the first global word line EGWL1 can be used to couple 512 even-numbered memory blocks out of 1024 even-numbered memory blocks, while the first global word line EGWL2 is used to couple the remaining 512 even-numbered memory blocks out of the 1024 even-numbered memory blocks. The first global word line decoder GWLDR1 can be coupled to a portion of the even-numbered memory blocks in the memory cell array 102 via the first selection circuit 108, the first global word line EGWL1, and the second selection circuit 110, and can also be coupled to another portion of the even-numbered memory blocks in the memory cell array 102 via the first selection circuit 108, the first global word line EGWL2, and the second selection circuit 110.

[0012] Similarly, the odd-row decoder circuit 106 may include a second global word line decoder GWLDR2, a third selection circuit 112, and a fourth selection circuit 114. The second selection circuit 110 is coupled to the second global word line decoder GWLDR2 and is coupled to the fourth selection circuit 114 via second global word lines OGWL1 and OGWL2. The fourth selection circuit 114 is also coupled to odd-numbered memory blocks in the memory cell array 102. For example, the second global word line OGWL1 may be used to couple 512 of the 1024 odd-numbered memory blocks, while the second global word line OGWL2 is used to couple the remaining 512 odd-numbered memory blocks. The second global word line decoder GWLDR2 can be coupled to a portion of the odd-numbered memory blocks in the memory cell array 102 via the third selection circuit 112, the second global word line OGWL1, and the fourth selection circuit 114, and can also be coupled to another portion of the odd-numbered memory blocks in the memory cell array 102 via the third selection circuit 112, the second global word line OGWL2, and the fourth selection circuit 114.

[0013] The first selection circuit 108 can select and connect the first global word line decoder GWLDR1 to the first global word line of the selected even-numbered memory block according to the selected even-numbered memory block, so as to transmit the first global word line selection signal EGWL[31:0] to the selected even-numbered memory block. For example, in Figure 1In the embodiment, if the selected even-numbered memory block corresponds to the first global word line EGWL1, the first selection circuit 108 can select and connect the first global word line decoder GWLDR1 to the first global word line EGWL1 according to the selected even-numbered memory block, and the second selection circuit 110 will transmit the first global word line selection signal EGWL[31:0] from the first global word line EGWL1 to the selected even-numbered memory block according to the selected even-numbered memory block.

[0014] Similarly, the third selection circuit 112 can selectively connect the second global word line decoder GWLDR2 to the second global word line corresponding to the selected odd memory block, based on the selected odd memory block, to transmit the second global word line selection signal OGWL[31:0] to the selected odd memory block. For example, if the selected odd memory block corresponds to the second global word line OGWL1, the third selection circuit 112 can selectively connect the second global word line decoder GWLDR2 to the second global word line OGWL1 based on the selected odd memory block, and the fourth selection circuit 114 transmits the second global word line selection signal OGWL[31:0] from the second global word line OGWL1 to the selected odd memory block based on the selected odd memory block.

[0015] By selectively connecting the first global word line decoder GWLDR1 to a portion of the first global word lines (for example, as shown in the previous embodiment, connecting the first global word line decoder GWLDR1 to the first global word line EGWL1 corresponding to the selected even-numbered memory block, but not to the first global word line EGWL2), the length of the first global word line can be effectively shortened, and the number of circuit components connected to the first global word line decoder GWLDR1 when driving the selected even-numbered memory blocks (e.g., the number of unselected word line decoders) can be reduced. Furthermore, the number of memory blocks connected to the first global word line decoder GWLDR1 can be reduced, thereby significantly reducing the capacitive load of the global word line and effectively avoiding increasing the area and current consumption of the charge pump circuit used to drive the even-numbered row decoder circuit 104. Similarly, selectively connecting the second global word line decoder GWLDR2 to a portion of the second global word lines can also effectively avoid increasing the area and current consumption of the charge pump circuit used to drive the odd-numbered row decoder circuit 106.

[0016] Furthermore, the first selection circuit 108, the second selection circuit 110, the third selection circuit 112, and the fourth selection circuit 114 can, for example, be implemented as multiple transmission circuits. For example, such as... Figure 2As shown, the first selection circuit 108 may include two first transmission circuits BK0[0] and BK0[2], the second selection circuit 110 may include 1024 second transmission circuits BK1[0]~BK1

[2046] , the third selection circuit 112 may include two fourth transmission circuits BK0[1] and BK0[3], and the fourth selection circuit 114 may include 1024 fifth transmission circuits BK1[1]~BK1

[2047] . The first transmission circuit BK0[0] is coupled to the first global word line decoder GWLDR1 and the corresponding first global word line EGWL1, the first transmission circuit BK0[2] is coupled to the first global word line decoder GWLDR1 and the corresponding first global word line EGWL2, the second transmission circuits BK1[0]~BK1

[1022] are respectively coupled to the corresponding first transmission circuit BK0[0] and the corresponding even memory block, and the second transmission circuits BK1

[1024] ~BK1

[2046] are respectively coupled to the corresponding first transmission circuit BK0[2] and the corresponding even memory block.

[0017] Similarly, the fourth transmission circuit BK0[1] is coupled to the second global word line decoder GWLDR2 and the corresponding second global word line OGWL1, the fourth transmission circuit BK0[3] is coupled to the second global word line decoder GWLDR2 and the corresponding second global word line OGWL2, the fifth transmission circuits BK1[1]~BK1

[1023] are respectively coupled to the corresponding fourth transmission circuit BK0[1] and the corresponding odd memory block, and the fifth transmission circuits BK1

[1025] ~BK1

[2047] are respectively coupled to the corresponding fourth transmission circuit BK0[3] and the corresponding even memory block.

[0018] The first transmission circuits BK0[0] and BK0[2] can transmit the first global word line selection signal EGWL[31:0] to a portion of the first global word lines (e.g., first global word lines EGWL1 or EGWL2) based on the selected even-numbered memory blocks. The second transmission circuits BK1[0] to BK1

[2046] can transmit the first global word line selection signal EGWL[31:0] to the selected even-numbered memory blocks based on the selected even-numbered memory blocks. The third transmission circuits BK0[1] and BK0[3] can transmit the second global word line selection signal OGWL[31:0] to a portion of the second global word lines (e.g., second global word lines OGWL1 or OGWL2) based on the selected odd-numbered memory blocks. The fourth transmission circuits BK1[1] to BK1

[2047] can transmit the second global word line selection signal OGWL[31:0] to the selected odd-numbered memory blocks based on the selected odd-numbered memory blocks.

[0019] In detail, the first transmission circuits BK0[0], BK0[2], the second transmission circuits BK1[0]~BK1

[2046] , the fourth transmission circuits BK0[1], BK0[3], and the fifth transmission circuits BK1[1]~BK1

[2047] may each include a block decoder and a word line decoder, wherein the word line decoder may include multiple transistors. For example, such as Figure 3 As shown, taking the second transmission circuit BK1[0] as an example, it includes a block decoder EBD1[0] and a word line decoder WLD1[0]. The word line decoder WLD1[0] includes 32 transistors, each transistor being coupled between the corresponding first global word line and the corresponding local word line, and the control terminal of each transistor being coupled to the block decoder EBD1[0]. When the second transmission circuit BK1[0] is coupled to the selected even-numbered memory blocks, each transistor can be controlled by the block decoder EBD1[0] to provide the first global word line selection signals EGWL[0]~EGWL

[31] as local word line selection signals WL[0]~WL

[31] to the selected even-numbered memory blocks. When the second transmission circuit BK1[0] is coupled to the unselected even-numbered memory blocks, each transistor is controlled by the block decoder EBD1[0] and is in the off state.

[0020] Similarly, taking the first transmission circuit BK0[0] as an example, each transistor in the first transmission circuit BK0[0] is coupled between the first global word line decoder GWLDR1 and the corresponding first global word line EGWL1, and the conduction state of each transistor is controlled by the corresponding block decoder. When the first transmission circuit BK0[0] is coupled to the selected even-numbered memory blocks, each transistor can be controlled by the corresponding block decoder to transmit the first global word line selection signal EGWL[31:0] to the first global word line EGWL1, while when the first transmission circuit BK0[0] is coupled to the unselected even-numbered memory blocks, each transistor is controlled by the corresponding block decoder to be in the off state. The implementation methods of the first transmission circuit BK0[2], the fourth transmission circuit BK0[1], and BK0[3] are similar to those of the first transmission circuit BK0[0]. The implementation methods of the second transmission circuit BK1[2]~BK1

[2046] and the fifth transmission circuit BK1[1]~BK1

[2047] are similar to those of the second transmission circuit BK1[0], and will not be described again here.

[0021] It is worth noting that in other embodiments, the first selection circuit 108, the second selection circuit 110, the third selection circuit 112, and the fourth selection circuit 114 may include more transmission circuits, and are not limited to the above embodiments. For example... Figure 4 and Figure 5As shown (for readability of the figures, implementation details of even-row decoder circuit 104 and odd-row decoder circuit 106 are shown separately in the figures below), Figure 4 and Figure 5 The first selection circuit 108 may include four first transmission circuits BK0[0]~BK0[6], and the second selection circuit 110 may include 32 second transmission circuits BK1[0]~BK1

[62] and 1024 third transmission circuits BK2[0]~BK2

[2046] , wherein each first transmission circuit is coupled to the corresponding eight second transmission circuits, and each second transmission circuit is coupled to the corresponding 32 third transmission circuits. For example, the first transmission circuit BK0[0] is coupled to the second transmission circuits BK1[0]~BK1

[14] , the first transmission circuit BK0[2] is coupled to the second transmission circuits BK1

[16] ~BK1

[30] , ..., the first transmission circuit BK0[6] is coupled to the second transmission circuits BK1

[48] ~BK1

[62] . The second transmission circuit BK1[0] is coupled to the third transmission circuit BK2[0]~BK2

[62] , the second transmission circuit BK1[2] is coupled to the third transmission circuit BK2

[64] ~BK2

[126] , ..., and so on.

[0022] The first transmission circuit BK0[0]~BK0[6], the second transmission circuit BK1[0]~BK1

[62] , and the third transmission circuit BK2[0]~BK2

[2046] in this embodiment can also Figure 3 The implementation method is as described in the embodiment. In this embodiment, the transistors in the first transmission circuit BK0[0]~BK0[6] are coupled between the first global word line decoder GWLDR1 and the corresponding first global word lines EGWL1~EGWL4, the transistors in the second transmission circuit BK1[0]~BK1

[62] are coupled between the corresponding first global word lines EGWL1~EGWL4 and the corresponding third global word lines PGWL1~PGWL32, and the transistors in the third transmission circuit BK2[0]~BK2

[2046] are coupled between the corresponding third global word lines PGWL1~PGWL32 and the corresponding even-numbered memory blocks.

[0023] Similar to Figure 2In this embodiment, the first transmission circuits BK0[0] to BK0[6] can transmit the first global word line selection signal EGWL[31:0] to a portion of the first global word lines (e.g., one of the first global word lines EGWL1 to EGWL4) according to the selected even-numbered memory blocks. The second transmission circuits BK1[0] to BK1

[31] can transmit the first global word line selection signal EGWL[31:0] to a portion of the third global word lines (e.g., one of the third global word lines PGWL1 to PGWL32) according to the selected even-numbered memory blocks. The third transmission circuits BK2[0] to BK2

[1023] can transmit the first global word line selection signal EGWL[31:0] to the selected even-numbered memory blocks according to the selected even-numbered memory blocks.

[0024] For example, if the selected even-numbered memory block is coupled to the third transmission circuit BK2[0], since the third transmission circuit BK2[0] is coupled to the second transmission circuit BK1[0] through the third global word line PGWL1, and the second transmission circuit BK1[0] is coupled to the first global word line decoder GWLDR1 through the first global word line EGWL1, that is, the selected even-numbered memory block corresponds to the first global word line EGWL1 and the third global word line PGWL1. The first transmission circuit BK0[0] can transmit the first global word line selection signal EGWL[31:0] to the first global word line EGWL1 according to the selected even-numbered memory block. The second transmission circuit BK1[0] can transmit the first global word line selection signal EGWL[31:0] to the third global word line PGWL1 according to the selected even-numbered memory block. The third transmission circuit BK2[0] then transmits the first global word line selection signal EGWL[31:0] to the selected even-numbered memory block. While the third transmission circuit BK2[0] transmits the first global word line selection signal EGWL[31:0] to the selected even-numbered memory block, the third transmission circuit BK2[2]~BK2

[2046] , the second transmission circuit BK1[2]~BK1

[62] , and the first transmission circuit BK0[2]~BK0[6] are unable to transmit the first global word line selection signal EGWL[31:0], that is, the transistors in the third transmission circuit BK2[2]~BK2

[2046] , the second transmission circuit BK1[2]~BK1

[62] , and the first transmission circuit BK0[2]~BK0[6] are in the off state.

[0025] Compared to Figure 2 In this embodiment, the number of circuit components connected to the first global word line decoder GWLDR1 when driving the selected even-numbered memory blocks (the number of unselected word line decoders) is further reduced, thereby further reducing the capacitive load of the global word lines and reducing the area and current consumption of the charge pump circuit used to drive the even-numbered row decoder circuit 104.

[0026] Similarly, the third selection circuit 112 and the fourth selection circuit 114 can be implemented as follows: Figure 5 As shown, the third selection circuit 112 and the fourth selection circuit 114 can be connected via the second global word lines OGWL1~OGWL4. The third selection circuit 112 may include four fourth transmission circuits BK0[1]~BK0[7], and the fourth selection circuit 114 may include 32 fifth transmission circuits BK1[1]~BK1

[63] and 1024 sixth transmission circuits BK2[1]~BK2

[2047] . The fifth transmission circuits BK1[1]~BK1

[63] and the sixth transmission circuits BK2[1]~BK2

[2047] can be connected via the fourth global word lines PGWL33~PGWL64. Since the odd-row decoder circuit 106 and the even-row decoder circuit 104 have symmetrical circuit structures, those skilled in the art should be able to deduce the detailed implementation of the odd-row decoder circuit 106 from the above embodiments, which will not be repeated here.

[0027] It is worth noting that, in other embodiments, the number of transmission circuits in the first selection circuit 108, the second selection circuit 110, the third selection circuit 112, and the fourth selection circuit 114 is not limited to the above embodiments. By increasing the number of transmission circuits in the first selection circuit 108, the second selection circuit 110, the third selection circuit 112, and the fourth selection circuit 114 in the manner described in the above embodiments, the number of circuit components connected to the first global word line decoder GWLDR1 when driving the selected even-numbered memory blocks can be reduced, which can effectively and significantly reduce the capacitive load of the global word lines and reduce the area and current consumption of the charge pump circuit used to drive the even-numbered row decoder circuit 104.

[0028] Additionally, it should be noted that, for the sake of simplifying the illustrations, in Figure 1 , Figure 2 , Figure 4 and Figure 5 In the example, only one of each of the following global word lines is shown as a representative example: EGWL1~EGWL4, OGWL1~OGWL4, PGWL1~PGWL32, and PGWL33~PGWL64. However, in reality... Figure 1 , Figure 2 , Figure 4 and Figure 5In the example, the number of first global word lines EGWL1~EGWL4, second global word lines OGWL1~OGWL4, third global word lines PGWL1~PGWL32, and fourth global word lines PGWL33~PGWL64 is 32 each. In other embodiments, the number of first global word lines EGWL1~EGWL4, second global word lines OGWL1~OGWL4, third global word lines PGWL1~PGWL32, and fourth global word lines PGWL33~PGWL64 is the same as the number of local word lines in a memory block.

[0029] In summary, the first selection circuit of this embodiment selects and connects the first global word line decoder to a portion of the first global word lines based on the selected even-numbered memory blocks; the second selection circuit transmits the first global word line selection signal to the selected even-numbered memory blocks based on the selected even-numbered memory blocks; the third selection circuit selects and connects the second global word line decoder to a portion of the second global word lines based on the selected odd-numbered memory blocks; and the fourth selection circuit transmits the second global word line selection signal to the selected odd-numbered memory blocks based on the selected odd-numbered memory blocks. This shortens the length of the global word lines and reduces the number of word line decoders connected to the global word line decoder, effectively avoiding increasing the area and current consumption of the charge pump circuit.

[0030] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory device, characterized in that, include: The storage cell array comprises multiple even-numbered memory blocks and multiple odd-numbered memory blocks; Even-row decoder circuit, coupled to the memory cell array, the even-row decoder circuit includes: The first global word line decoder provides multiple first global word line selection signals; A first selection circuit, coupled to the first global word line decoder and multiple first global word lines, selectively connects the first global word line decoder to a portion of the first global word lines based on the selected even-numbered memory blocks; and A second selection circuit, coupled to the plurality of first global word lines and the plurality of even-numbered memory blocks, transmits the plurality of first global word line selection signals to the selected even-numbered memory block according to the selected even-numbered memory block; and Odd-row decoder circuit, coupled to the memory cell array, the odd-row decoder circuit includes: The second global word line decoder provides multiple second global word line selection signals; A third selection circuit, coupled to the second global word line decoder and multiple second global word lines, selectively connects the second global word line decoder to a portion of the second global word lines based on the selected odd-numbered memory blocks; and The fourth selection circuit is coupled to the plurality of second global word lines and the plurality of odd memory blocks, and transmits the plurality of second global word line selection signals to the selected odd memory block according to the selected odd memory block.

2. The memory device according to claim 1, characterized in that, The first selection circuit includes: Multiple first transmission circuits are respectively coupled to the first global word line decoder and the corresponding first global word line, and transmit the multiple first global word line selection signals to the first global word line of the selected even-numbered memory block.

3. The memory device according to claim 2, characterized in that, The second selection circuit includes: Multiple second transmission circuits are respectively coupled between the corresponding first transmission circuit and the corresponding even-numbered memory block, and transmit the multiple first global word line selection signals according to the selected even-numbered memory block, so as to transmit the multiple first global word line selection signals to the selected even-numbered memory block.

4. The memory device according to claim 3, characterized in that, The second selection circuit also includes: Multiple third transmission circuits are respectively coupled between the corresponding second transmission circuit and the corresponding even-numbered memory block, and transmit the multiple first global word line selection signals according to the selected even-numbered memory block, so as to transmit the multiple first global word line selection signals to the selected even-numbered memory block.

5. The memory device according to any one of claims 2 to 4, characterized in that, Each of the first transmission circuits, each of the second transmission circuits, and each of the third transmission circuits includes: Block decoder; and A word line decoder, controlled by the block decoder, transmits the plurality of first global word line select signals to the selected even-numbered memory blocks.

6. The memory device according to claim 5, characterized in that, Each first word line decoder includes: A plurality of first transistors, the control terminals of which are coupled to the block decoder, wherein the conduction state of the plurality of first transistors is controlled by the block decoder to transmit the plurality of first global word line selection signals.

7. The memory device according to claim 1, characterized in that, The third selection circuit includes: Multiple fourth transmission circuits are respectively coupled to the second global word line decoder and the corresponding second global word line, and transmit the multiple second global word line selection signals to the second global word line of the selected odd memory block.

8. The memory device according to claim 7, characterized in that, The fourth selection circuit includes: Multiple fifth transmission circuits are respectively coupled between the corresponding fourth transmission circuit and the corresponding odd memory block, and transmit the multiple second global word line selection signals according to the selected odd memory block, so as to transmit the multiple second global word line selection signals to the selected odd memory block.

9. The memory device according to claim 8, characterized in that, The second selection circuit includes: Multiple sixth transmission circuits are respectively coupled between the corresponding fifth transmission circuit and the corresponding odd memory block, and transmit the multiple second global word line selection signals according to the selected odd memory block, so as to transmit the multiple second global word line selection signals to the selected odd memory block.

10. The memory device according to any one of claims 7 to 9, characterized in that, Each of the fourth transmission circuits, the fifth transmission circuits, and the sixth transmission circuits includes: Block decoder; and A word line decoder, controlled by the block decoder, transmits the plurality of second global word line select signals to the selected odd memory block.

11. The memory device according to claim 10, characterized in that, Each second word line decoder includes: A plurality of second transistors, the control terminals of which are coupled to the block decoder, wherein the conduction state of the plurality of second transistors is controlled by the block decoder to transmit the plurality of second global word line selection signals.

12. The memory device according to claim 1, characterized in that, The memory device is a NAND memory device.

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