Storage device and method of operating a storage device

Abstract

A storage device and a method of operating a storage device are provided. The method of operating a storage device includes, in response to a first erase command for a first memory block among a plurality of memory blocks, applying a first erase voltage to the first memory block, determining a number of cut-off cells each having a threshold voltage greater than or equal to a reference voltage among memory cells included in the first memory block, in response to the number of cut-off cells exceeding a reference number, obtaining a second erase voltage by adding a unit erase voltage to the first erase voltage, and in response to a second erase command for the first memory block, applying the second erase voltage to the first memory block.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2025-0045563, filed on April 8, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a storage device and a method of operating the storage device. Background Technology

[0003] Semiconductor memory devices can be broadly classified into volatile memory devices and non-volatile memory devices. Volatile memory devices offer high read and write speeds, but they have the disadvantage of losing stored data when their power supply is interrupted. Non-volatile memory devices, on the other hand, retain their stored data even when their power supply is interrupted. Therefore, non-volatile memory devices are used to store data that needs to be preserved regardless of whether power is available.

[0004] Flash memory devices are a representative example of non-volatile memory devices. They are widely used as storage media for voice and image data in information devices such as computers, mobile phones, smartphones, personal digital assistants (PDAs), digital cameras, camcorders, recorders, MP3 players, handheld personal computers (PCs), game consoles, fax machines, scanners, or printers.

[0005] The characteristics of flash memory devices can change depending on various factors, such as the usage environment, frequency of use, or duration of use. For example, as the number of times a flash memory device is used increases, its characteristics may change, thus requiring an operating voltage that matches the changed characteristics.

[0006] Therefore, methods for controlling the operating voltage of flash memory devices based on changes in the characteristics of the flash memory devices have been studied. Summary of the Invention

[0007] This disclosure provides a memory device configured to adaptively control the magnitude of the operating voltage based on the threshold voltage distribution of memory cells, and a method for operating the memory device.

[0008] According to one aspect of this disclosure, a method of operating a memory device includes: applying a first erase voltage to a first memory block in response to a first erase command for a first memory block among a plurality of memory blocks; determining a number of cutoff cells, each having a threshold voltage greater than or equal to a reference voltage, among memory cells included in the first memory block; obtaining a second erase voltage by adding a unit erase voltage to the first erase voltage in response to the number of cutoff cells exceeding the reference number; and applying the second erase voltage to the first memory block in response to a second erase command for the first memory block.

[0009] According to one aspect of this disclosure, a storage device includes: a memory device comprising a plurality of memory blocks; and a memory controller configured to control erase operations, programming operations, and read operations on the memory device. The memory controller may be configured to: apply a first erase voltage to memory cells included in the first memory block in response to a first erase command for a first memory block; determine a number of cutoff cells, each having a threshold voltage greater than or equal to a reference voltage, among the memory cells; obtain a second erase voltage by adding a unit erase voltage to the first erase voltage in response to the number of cutoff cells exceeding the reference number; and apply the second erase voltage to the memory cells in response to a second erase command for the first memory block.

[0010] According to one aspect of this disclosure, a method of operating a storage device includes: applying a first erase voltage to memory cells included in the first memory block in response to a first erase command for a first memory block among a plurality of memory blocks; applying a first programming voltage to memory cells included in the first page via a first word line connected to the first page in response to a first programming command for a first page in the first memory block; determining a number of cut-off cells, each having a threshold voltage greater than or equal to a reference voltage, among the memory cells included in the first memory block; obtaining a second programming voltage by subtracting a unit programming voltage from the first programming voltage in response to the number of cut-off cells exceeding the reference number; and applying the second programming voltage via the first word line in response to a second programming command for memory cells included in the first page. Attached Figure Description

[0011] Figure 1 It is a block diagram of a memory system according to one or more embodiments.

[0012] Figure 2 This is a block diagram of a storage device according to one or more embodiments.

[0013] Figure 3 This is a block diagram of a memory device according to one or more embodiments.

[0014] Figure 4 This is a circuit diagram illustrating a first memory block among a plurality of memory blocks according to one or more embodiments.

[0015] Figure 5 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a first erase voltage to a first memory block.

[0016] Figure 6 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, determines the number of memory cells, each having a threshold voltage greater than or equal to a first reference voltage.

[0017] Figure 7 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a second erase voltage to a first memory block.

[0018] Figure 8 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a first programming voltage via a first word line.

[0019] Figure 9 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, determines the number of memory cells, each having a threshold voltage greater than or equal to a second reference voltage.

[0020] Figure 10 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a second programming voltage via a first word line.

[0021] Figure 11 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a first read voltage via a first word line.

[0022] Figure 12 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, generates a first read voltage from a pre-read voltage.

[0023] Figure 13 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a first batch erase voltage to a first superblock.

[0024] Figure 14 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a second batch erase voltage to a first superblock.

[0025] Figure 15This is a flowchart illustrating a method for controlling the magnitude of an erase voltage based on a threshold voltage of a memory cell, performed by a storage device according to one or more embodiments.

[0026] Figure 16 This is a flowchart illustrating a method performed by a storage device according to one or more embodiments to control the magnitude of the erase voltage based on a threshold voltage of a memory cell after a programming operation is performed.

[0027] Figure 17 This is a flowchart illustrating a method performed by a storage device according to one or more embodiments to control the magnitude of a programming voltage based on a threshold voltage of a memory cell after a programming operation has been performed.

[0028] Figure 18 This is a flowchart illustrating a method for controlling the magnitude of a read voltage based on a threshold voltage of a memory cell, performed by a storage device according to one or more embodiments.

[0029] Figure 19 This is a flowchart illustrating a method for controlling the magnitude of a bulk erase voltage applied to a superblock based on a threshold voltage of a memory cell, performed by a storage device according to one or more embodiments.

[0030] Figure 20 This is a block diagram illustrating an example in which a storage device according to one or more embodiments is implemented as a solid-state drive (SSD).

[0031] Figure 21 This is a diagram illustrating a flash memory according to one or more embodiments. Detailed Implementation

[0032] The following description, with reference to the accompanying drawings, is provided to aid in a comprehensive understanding of various embodiments of this disclosure.

[0033] Without limiting the exemplary embodiments, the terms “first,” “second,” etc., used herein may modify various elements regardless of the order and / or priority of the elements, and are used only to distinguish one element from another.

[0034] Figure 1 It is a block diagram of a memory system according to one or more embodiments. Figure 2 This is a block diagram of a storage device according to one or more embodiments. Figure 3 This is a block diagram of a memory device according to one or more embodiments. Figure 4 This is a circuit diagram illustrating a first memory block among a plurality of memory blocks according to one or more embodiments.

[0035] Reference Figure 1The memory system 10 may include a storage device 100 and a host 200. The storage device 100 may be connected to the host 200 via a host interface 101.

[0036] Storage device 100 may be based on non-volatile memory. For example, storage device 100 may be a flash memory device. Flash memory devices may include solid-state drives (SSDs), universal flash storage (UFS), or memory cards.

[0037] Reference Figure 1 and Figure 2 The storage device 100 may include a memory device 110 and a memory controller 120.

[0038] According to one or more embodiments, storage device 100 may include memory controller 120 for controlling storage device 110.

[0039] The memory controller 120 can control at least one other component of the storage device 100 (e.g., peripheral circuitry 112) by executing software (or programs) and can perform various data processing or operations. The memory controller 120 may include a central processing unit or a microprocessor and can control the overall operation of the storage device 100. Therefore, operations performed by the storage device 100 can be understood as being performed under the control of the memory controller 120.

[0040] Storage device 100 may include memory device 110 configured to store data.

[0041] For example, memory device 110 may be referred to as NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc. Memory device 110 may be implemented using a three-dimensional array structure. Memory device 110 according to one or more embodiments may be referred to as a flash memory device in which the charge storage layer includes a conductive floating gate and a charge-trapping flash memory (CTF) in which the charge storage layer includes an insulating layer. For clarity, an example of a vertical NAND flash memory device (VNAND) is provided where memory device 110 is an example.

[0042] The memory device 110 may include a memory cell array 111 and peripheral circuitry 112.

[0043] According to one or more embodiments, the memory cell array 111 may include a plurality of memory blocks BLK1 to BLKn. Each memory block may have a vertical three-dimensional structure. Each memory block may include a plurality of memory cells.

[0044] In one example, multiple bits of data can be stored in each memory cell. Each memory cell may be referred to as a multilevel cell (MLC).

[0045] In another example, unit data can be stored in each memory cell. Each memory cell can be referred to as a single-level cell (SLC).

[0046] In terms of design layout, the memory cell array 111 can be positioned next to or above the peripheral circuit 112. The structure in which the memory cell array 111 is positioned above the peripheral circuit 112 can be referred to as a cell-on-periphery (COP) structure.

[0047] According to one or more embodiments, the memory cell array 111 and the peripheral circuitry 112 can each be manufactured as separate chips. The upper chip including the memory cell array 111 and the lower chip including the peripheral circuitry 112 can be connected to each other by a bonding method. Such a structure can be referred to as a chip-to-chip (C2C) structure.

[0048] According to one or more embodiments, the peripheral circuit 112 may receive external power from the memory controller 120 and generate internal power at various levels.

[0049] For example, refer to Figure 2 The peripheral circuit 112 can receive commands CMD, address ADDR, and data DATA from the memory controller 120. The peripheral circuit 112 can store the data DATA in the memory cell array 111 specified by address ADDR based on the control signal CTRL. The peripheral circuit 112 can read the data DATA stored in the memory cell array 111 specified by address ADDR and provide the read data DATA to the memory controller 120.

[0050] Reference Figure 2 and Figure 3 The peripheral circuit 112 may include a control logic circuit 113, an address decoder 114, a page buffer circuit 115, an input / output (I / O) circuit 116, a voltage generator 117, and a cell counter 118.

[0051] According to one or more embodiments, the memory cell array 111 may include a plurality of memory blocks BLK1 to BLKn (where n is an integer greater than or equal to 2). Each memory block may include a plurality of pages. Each page may include a plurality of memory cells. Each memory block may be a unit of erase operation, and each page may be a unit of read operation or programmable operation.

[0052] According to one or more embodiments, the memory cell array 111 may be formed in a direction perpendicular to the substrate. Gate electrode layers and insulating layers may be alternately disposed on the substrate. Each memory block (e.g., the first memory block BLK1) may be connected to a serial select line SSL, multiple word lines WL1 to WLm (where m is an integer greater than or equal to 2), and a ground select line GSL.

[0053] For example, refer to Figure 4 The first memory block BLK1 may include multiple memory strings STR1 to STR4 connected between bit lines BL1 and BL2 and the common source line CSL.

[0054] Each of the multiple memory strings STR1 to STR4 may include a string selection transistor SST, multiple memory cells MC1 to MC5, and a ground selection transistor GST. Figure 4 In the diagram, each of the multiple memory strings STR1 to STR4 is shown as comprising five memory cells MC1 to MC5, but the embodiment is not limited thereto.

[0055] The serial select transistor SST can be connected to the corresponding one of the serial select lines SSLa and SSLb. Multiple memory cells MC1 to MC5 can be connected to their respective word lines WL1 to WL5. A portion of the word lines WL1 to WL5 can correspond to dummy word lines.

[0056] The ground select transistor GST can be connected to the corresponding ground select line GSLa and GSLb. The string select transistor SST can be connected to the corresponding bit line BL1 and BL2, and the ground select transistor GST can be connected to the common source line CSL.

[0057] Word lines at the same height (e.g., the first word line WL1) can be connected together, and ground select lines GSLa and GSLb, as well as string select lines SSLa and SSLb, can be separated separately. Figure 4 In the diagram, the first memory block BLK1 is shown connected to five word lines WL1 to WL5 and two bit lines BL1 and BL2, but the embodiment is not limited to this.

[0058] Each of the multiple memory blocks BLK1 to BLKn, excluding the first memory block BLK1, may have substantially the same configuration as the first memory block BLK1.

[0059] return Figure 3According to one or more embodiments, the control logic circuit 113 can use commands CMD, addresses ADDR, and control signals CTRL provided from the memory controller 120 to control read operations, programming operations, erase operations, or verification operations of the memory device 110. The address ADDR may include a block selection address for selecting a memory block, a row address X-ADDR for selecting a single page, and a column address Y-ADDR for selecting a single memory cell.

[0060] Address decoder 114 can be connected to memory cell array 111 via select lines (e.g., serial select line SSL and ground select line GSL) and word lines WL1 to WLm. Address decoder 114 can select word lines during programming or reading operations. Address decoder 114 can receive word line voltage VWL from voltage generator 117 and provide programming or reading voltage to the selected word line. For example, address decoder 114 can provide programming or reading voltage to the word line specified by row address X-ADDR received from control logic circuitry 113.

[0061] Page buffer circuit 115 can be connected to memory cell array 111 via multiple bit lines BL. Page buffer circuit 115 can temporarily store data to be stored in memory cell array 111 or data read from memory cell array 111.

[0062] Page buffer circuit 115 according to one or more embodiments may include multiple page buffers respectively connected to multiple bit lines BL. Each page buffer may include multiple latches for storing or retrieving multiple bits of data. For example, page buffer circuit 115 may control page buffers connected to bit lines specified by column address Y-ADDR received from control logic circuit 113.

[0063] Input / output circuitry 116 is internally connected to page buffer circuitry 115 via data lines and externally connected to memory controller 120 via input / output lines IO1 to IOj (where "j" is any integer greater than or equal to 2). Input / output circuitry 116 can receive programming data from memory controller 120 during programming operations. Input / output circuitry 116 can provide data read from memory cell array 111 to memory controller 120 during read operations.

[0064] Voltage generator 117 can generate the word line voltage VWL required for reading or writing data based on the voltage control signal CTRL_VOL received from control logic circuit 113. The word line voltage VWL can be provided to the selected word line sWL (not shown) or the unselected word line uWL (not shown) via address decoder 114.

[0065] The cell counter 118 can count memory cells that each have a threshold voltage falling within a specific voltage range, based on data stored in the page buffer circuit 115.

[0066] For example, cell counter 118 can count the number of memory cells, each with a threshold voltage within a specific range, by processing data stored in page buffer circuit 115.

[0067] In one example, the cell counter 118 may be implemented as a circuit separate from the control logic circuit 113. In another example, the cell counter 118 may be implemented within the control logic circuit 113, or it may be implemented as a single circuit with the control logic circuit 113.

[0068] Cell counter 118 can output a count result nC, including the number of memory cells, each with a threshold voltage within a specific range, to memory controller 120.

[0069] According to one or more embodiments, the memory controller 120 can control the magnitude of the operating voltage applied to the operation of the memory device 110 based on the counting result nC of the cell counter 118.

[0070] For example, the memory controller 120 may control the magnitude of the operating voltage in response to the fact that the number of memory cells among the plurality of memory cells included in the memory cell array 111 having a threshold voltage greater than or equal to a reference voltage exceeds a reference number.

[0071] The reference voltage and the reference quantity can each be predetermined and stored in the memory device 110. For example, the memory controller 120 can control at least a portion of the reference voltage and the reference quantity based on the temperature at which the memory device 100 operates.

[0072] According to one or more embodiments, the memory controller 120 may increase the magnitude of the erase voltage applied during an erase operation on the first memory block BLK1 in response to the number of memory cells included in the first memory block BLK1 having a threshold voltage greater than or equal to a reference voltage exceeding a reference number.

[0073] For example, the memory controller 120 may individually control the operating voltage (e.g., erase voltage) for each memory block operation (e.g., erase operation) based on the threshold voltage distribution of each of the plurality of memory blocks BLK1 to BLKn.

[0074] Compared to situations where the operating voltage is controlled based on the number of operations (e.g., erase operations) on each of a plurality of memory blocks BLK1 to BLKn, the memory controller 120 can more adaptively control the operating voltage for each memory block.

[0075] According to one or more embodiments, the memory controller 120 may reduce the magnitude of the programming voltage applied through the first word line WL1 in response to the number of memory cells connected to the first word line WL1 having a threshold voltage greater than or equal to a reference voltage exceeding a reference number.

[0076] According to one or more embodiments, the memory controller 120 may increase the magnitude of the read voltage applied through the first word line WL1 in response to the number of memory cells connected to the first word line WL1 having a threshold voltage greater than or equal to a reference voltage exceeding a reference number.

[0077] Referring to the configuration described above, the memory controller 120 according to one or more embodiments can control the magnitude of the operating voltage for the operation of the memory device 110 based on the distribution of threshold voltages of the memory cells.

[0078] Compared to situations where the magnitude of the operating voltage is controlled based on the number of operations (e.g., erase operations), when the memory controller 120 controls the magnitude of the operating voltage based on a threshold voltage distribution, the memory controller 120 can more adaptively control the magnitude of the operating voltage.

[0079] The voltage required for the erase operation can increase as the time interval between consecutive programming operations decreases. Therefore, the memory controller 120 can control the magnitude of the erase voltage based on a threshold voltage distribution to perform the erase operation with a voltage corresponding to the required voltage magnitude as the time interval between consecutive programming operations decreases.

[0080] The voltage required for programming operations can decrease as the time interval between consecutive programming operations decreases. Therefore, the memory controller 120 controls the magnitude of the programming voltage based on a threshold voltage distribution to perform programming operations with a voltage corresponding to the required voltage magnitude as the time interval between consecutive programming operations decreases.

[0081] For example, the memory controller 120 may control the operation of the memory device 110 based on a threshold voltage distribution, using a voltage corresponding to the operating voltage required due to changes in the characteristics of the memory device 110.

[0082] The configuration described above enables the memory system 10 (or storage device 100) according to one or more embodiments to improve the performance of operations on the memory device 110 (e.g., erase operations, programming operations, or read operations).

[0083] Figure 5 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a first erase voltage to a first memory block. Figure 6This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, determines the number of memory cells, each having a threshold voltage (Vth) greater than or equal to a first reference voltage. Figure 7 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a second erase voltage to a first memory block.

[0084] Reference Figure 5 and Figure 7 The storage device 100A according to one or more embodiments may include a memory device 110 and a memory controller 120. Figure 5 and Figure 7 The storage device 100A shown can be understood as Figure 2 An example of storage device 100 is shown. Therefore, components that are the same or substantially the same as those described above are indicated by the same reference numerals, and redundant descriptions of components that are the same or substantially the same as those described above will be omitted.

[0085] Reference Figures 5 to 7 According to one or more embodiments, the memory controller 120 may control the erase voltage for the erase operation of the first memory block BLK1 based on the distribution of threshold voltages of memory cells included in the first memory block BLK1.

[0086] Reference Figure 5 According to one or more embodiments, the memory controller 120 can perform an erase operation on a first memory block BLK1. The memory controller 120 can erase a plurality of memory cells included in the first memory block BLK1.

[0087] For example, the memory controller 120 may apply a first erase voltage Ve1 to the first memory block BLK1 in response to the first erase command EC1. The memory controller 120 may also apply the first erase voltage Ve1 to a plurality of memory cells included in the first memory block BLK1 in response to the first erase command EC1.

[0088] Reference Figure 5 and Figure 6 The memory controller 120 may, in response to the first erase command EC1, change the distribution of threshold voltages of memory cells included in the first memory block BLK1 to erase state E.

[0089] Reference Figure 6According to one or more embodiments, the memory controller 120 can determine the number of off-cell (OFC) cells in a memory cell in erase state E whose threshold voltage is greater than or equal to a first reference voltage V1. The memory controller 120 can count the number of off-cell (OFC) cells in a memory cell in erase state E whose threshold voltage is greater than or equal to the first reference voltage V1. For example, the first reference voltage V1 may be a predetermined value stored in the memory device 110.

[0090] For example, the memory controller 120 may apply a first reference voltage V1 to each of the memory cells included in the first memory block BLK1. The memory controller 120 may count the number of cutoff cells OFC, each having a threshold voltage equal to or greater than the first reference voltage V1, based on the current output from each of the memory cells included in the first memory block BLK1.

[0091] The memory controller 120 can determine whether the number of cutoff cells (OFCs) among the memory cells included in the first memory block BLK1, each having a threshold voltage greater than or equal to a first reference voltage V1, exceeds a reference number. For example, the reference number may be a predetermined value stored in the memory device 110.

[0092] For example, the memory controller 120 can determine whether the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the first reference voltage V1, in the memory cells of the first memory block BLK1 in the erase state E exceeds a reference number.

[0093] According to one or more embodiments, the memory controller 120 may control a first reference voltage V1 and / or a reference quantity based on the temperature at which the storage device 100A operates.

[0094] In one embodiment, the memory controller 120 may increase the magnitude of the first reference voltage V1 and decrease the number of references in response to the temperature at which the storage device 100A operates being below a preset threshold temperature (or a predetermined threshold temperature).

[0095] In another example, the memory controller 120 may decrease the magnitude of the first reference voltage V1 and increase the number of references in response to the temperature at which the storage device 100A operates exceeding a predetermined threshold temperature.

[0096] Reference Figure 6 and Figure 7 The memory controller 120 may obtain a second erase voltage Ve2 in response to the number of cutoff cells OFC exceeding the reference number.

[0097] For example, the memory controller 120 may, in response to the number of cutoff cells (OFCs) exceeding a reference number, obtain a second erase voltage Ve2 by adding a unit erase voltage to a first erase voltage Ve1. The value of the unit erase voltage may be predetermined and stored in the memory device 110.

[0098] For example, the memory controller 120 may update the first voltage code corresponding to the first erase voltage Ve1 to the second voltage code corresponding to the second erase voltage Ve2 in response to the number of cutoff cells OFC exceeding the reference number.

[0099] For example, after an erase operation, when the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the first reference voltage V1, included in the first memory block BLK1 exceeds the reference number, the memory controller 120 may increase the erase voltage used for the erase operation.

[0100] The memory controller 120 may store the value of the second erase voltage Ve2 or a second voltage code corresponding to the second erase voltage Ve2. For example, the memory controller 120 may store the value of the second erase voltage Ve2 or the second voltage code corresponding to the second erase voltage Ve2 in the memory device 110. For example, the memory controller 120 may store the value of the second erase voltage Ve2 or the second voltage code corresponding to the second erase voltage Ve2 in at least a portion of a plurality of memory blocks BLK1 to BLKn.

[0101] Reference Figure 7 The memory controller 120 can apply a second erase voltage Ve2 to the first memory block BLK1.

[0102] For example, the memory controller 120 may apply a second erase voltage Ve2 to the first memory block BLK1 in response to the second erase command EC2. Alternatively, the memory controller 120 may perform an erase operation on the first memory block BLK1 using the second erase voltage Ve2 in response to the second erase command EC2. Or, the memory controller 120 may apply the stored second erase voltage Ve2 to the first memory block BLK1 in response to receiving the second erase command EC2.

[0103] For example, after updating the erase voltage based on the threshold voltage distribution of the memory cell, the memory controller 120 may, in response to an erase command (e.g., a second erase command EC2), perform an erase operation using the updated erase voltage (e.g., a second erase voltage Ve2).

[0104] Referring to the configuration described above, the memory controller 120 according to one or more embodiments may determine, after performing an erase operation on the first memory block BLK1, whether the number of cutoff cells OFC, each having a threshold voltage greater than or equal to a reference voltage (e.g., a first reference voltage V1), exceeds a reference number.

[0105] The memory controller 120 may increase the erase voltage for the erase operation on the first memory block BLK1 in response to the number of cutoff cells OFC exceeding a reference number.

[0106] The voltage required for the erase operation can be increased as the time interval between consecutive programming operations decreases.

[0107] Therefore, for example, the memory controller 120 may control the magnitude of the erase voltage based on a threshold voltage distribution, so that as the time interval between consecutive programming operations decreases, the erase voltage is increased to a magnitude corresponding to the desired voltage.

[0108] For example, the memory controller 120 may control the erase voltage to a magnitude corresponding to the required voltage magnitude that varies according to the characteristics of the memory device 110, based on the threshold voltage distribution, in order to perform an erase operation on the memory device 110.

[0109] The configuration described above enables the storage device 100A according to one or more embodiments to improve the performance of operations (e.g., erase operations) on the memory device 110.

[0110] Figure 8 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a first programming voltage via a first word line. Figure 9 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, determines the number of memory cells, each having a threshold voltage greater than or equal to a second reference voltage. Figure 10 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a second programming voltage via a first word line. Figure 11 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a first read voltage via a first word line. Figure 12 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, generates a first read voltage from a pre-read voltage.

[0111] Reference Figure 8 , Figure 10 and Figure 11 The storage device 100B according to one or more embodiments may include a memory device 110 and a memory controller 120. Figure 8 , Figure 10 and Figure 11 The storage device 100B shown can be understood as Figure 2 An example of storage device 100 is shown. Therefore, components that are the same or substantially the same as those described above are indicated by the same reference numerals, and redundant descriptions of components that are the same or substantially the same as those described above will be omitted.

[0112] Reference Figures 8 to 10 According to one or more embodiments, the memory controller 120 can control the programming voltage for programming operations on the memory cells included in the first page PG1 based on the threshold voltage distribution of the memory cells included in the first page PG1.

[0113] Reference Figure 8 The memory controller 120 can perform programming operations on memory cells included in the first page PG1. The memory controller 120 can program data into the memory cells included in the first page PG1. The first page PG1 may include memory cells connected to the first word line WL1 among the memory cells included in the first memory block BLK1.

[0114] For example, the memory controller 120 may apply a first programming voltage Vp1 via a first word line WL1 in response to a first programming command PC1. The first word line WL1 can be understood as being connected to a first page PG1. Therefore, the memory controller 120 may apply the first programming voltage Vp1 to the memory cells included in the first page PG1 via the first word line WL1 in response to the first programming command PC1.

[0115] Reference Figure 8 and Figure 9 The memory controller 120 may, in response to a first programming command PC1, change the threshold voltage distribution of at least a portion of the memory cells included in the first page PG1 to a programming state P.

[0116] For example, Figure 8 The programming operations on the first page PG1 shown can be understood as... Figure 5 The operation performed after the erase operation on the first memory block BLK1 is shown in the figure.

[0117] For example, Figure 8 The programming operations on the first page PG1 shown can be understood as... Figure 5 The first programming operation performed after the erase operation on the first memory block BLK1 is shown in the figure.

[0118] According to one or more embodiments, the memory controller 120 can determine the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the second reference voltage V2, included in the memory cells in the first page PG1.

[0119] For example, the memory controller 120 can count the number of cutoff cells OFC in the memory cells in the programming state P, each having a threshold voltage greater than or equal to the second reference voltage V2.

[0120] The memory controller 120 can determine whether the number of cutoff cells (OFCs) among the memory cells included in the first page PG1, each having a threshold voltage greater than or equal to the second reference voltage V2, exceeds a reference number. For example, the reference number may be a predetermined value stored in the memory device 110.

[0121] For example, the memory controller 120 can determine whether the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the second reference voltage V2, in the memory cells in the programming state P within the first page PG1 exceeds a reference number.

[0122] Reference Figure 9 and Figure 10 The memory controller 120 can obtain a second programming voltage Vp2 in response to the number of cutoff cells OFC exceeding the reference number.

[0123] For example, the memory controller 120 may obtain a second programming voltage Vp2 by subtracting a unit programming voltage from a first programming voltage Vp1 in response to the number of cutoff cells (OFCs) exceeding a reference number. The value of the unit programming voltage may be predetermined and stored in the memory device 110.

[0124] For example, the memory controller 120 may update the first voltage code corresponding to the first programming voltage Vp1 to the second voltage code corresponding to the second programming voltage Vp2 in response to the number of cutoff cells OFC exceeding the reference number.

[0125] For example, after a programming operation, when the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the second reference voltage V2, included in the memory cells of the first page PG1 exceeds the reference number, the memory controller 120 may reduce the programming voltage.

[0126] The memory controller 120 can store the value of the second programming voltage Vp2 or a second voltage code corresponding to the second programming voltage Vp2. For example, the memory controller 120 can store the value of the second programming voltage Vp2 or the second voltage code corresponding to the second programming voltage Vp2 in the memory device 110. For example, the memory controller 120 can store the value of the second programming voltage Vp2 or the second voltage code corresponding to the second programming voltage Vp2 in at least a portion of a plurality of memory blocks BLK1 to BLKn.

[0127] Reference Figure 10The memory controller 120 can apply a second programming voltage Vp2 through the first word line WL1.

[0128] For example, the memory controller 120 may, in response to the second programming command PC2, apply a second programming voltage Vp2 to the first page PG1 via the first word line WL1. For example, the second programming voltage Vp2 may have a value corresponding to a second voltage code stored in the memory device 110.

[0129] For example, the memory controller 120 may, in response to a second programming command PC2, perform a programming operation on the memory cells included in the first page PG1 using a second programming voltage Vp2. For example, the memory controller 120 may, in response to receiving the second programming command PC2, apply a pre-stored second programming voltage Vp2 through the first word line WL1.

[0130] For example, after updating the programming voltage based on the threshold voltage distribution of the memory cell, the memory controller 120 may perform a programming operation using the updated programming voltage (e.g., the second programming voltage Vp2) in response to a programming command (e.g., the second programming command PC2).

[0131] Referring to the configuration described above, the memory controller 120 can determine, after performing a programming operation on the first page PG1, whether the number of cutoff cells OFC, each having a threshold voltage greater than or equal to a reference voltage (e.g., a second reference voltage V2), exceeds a reference number.

[0132] The memory controller 120 may reduce the programming voltage for programming operations on memory cells included in the first page PG1 in response to the number of cutoff cells OFC exceeding a reference number.

[0133] For example, the memory controller 120 may control the programming voltage to a level corresponding to the required voltage level that varies according to the characteristics of the memory device 110, based on the threshold voltage distribution, in order to perform programming operations on the memory device 110.

[0134] Reference Figure 8 , Figure 9 , Figure 11 and Figure 12 According to one or more embodiments, the memory controller 120 may control the read voltage for read operations on memory cells included in the first page PG1 based on the threshold voltage distribution of the memory cells included in the first page PG1.

[0135] Reference Figure 11 and Figure 12The memory controller 120 can perform read operations on memory cells included in the first page PG1. The memory controller 120 can read data stored in the memory cells included in the first page PG1.

[0136] For example, the memory controller 120 may apply a first read voltage Vr1 via the first word line WL1 in response to a read command RC for a memory cell included in the first page PG1.

[0137] The first word line WL1 can be understood as being connected to the first page PG1. Therefore, the memory controller 120 can apply a first read voltage Vr1 to the memory cell included in the first page PG1 via the first word line WL1 in response to the read command RC.

[0138] Figure 11 The read operation on the first page PG1 shown can be understood as... Figure 9 The operation performed after updating the voltage code based on the number of cutoff cells (OFCs) is shown in the diagram. For example, Figure 11 The read operation on the first page PG1 shown can be understood as... Figure 9 The operation performed after the operation of storing the second voltage code (e.g., the second voltage code corresponding to the second programming voltage Vp2) based on the number of cutoff cells OFC shown in the figure.

[0139] Therefore, the first read voltage Vr1 according to one or more embodiments may have a value corresponding to a pre-stored second voltage code (e.g., a second voltage code corresponding to the second programming voltage Vp2). The second voltage code can be understood as a code stored in response to the number of cutoff cells (OFCs) exceeding a reference number. In one embodiment, Figure 11 The read operation on the first page PG1 shown can be understood as... Figure 6 The operation performed after the operation of storing the second voltage code (e.g., the second voltage code corresponding to the second erase voltage Ve2) based on the number of cutoff cells OFC shown in the figure, and the first read voltage Vr1 according to the embodiment may have a value corresponding to the pre-stored second voltage code (e.g., the second voltage code corresponding to the second erase voltage Ve2).

[0140] Reference Figure 12 The first read voltage Vr1 can have a value obtained by adding the unit read voltage Vur to the pre-read voltage Vr0. The pre-read voltage Vr0 can be understood as... Figure 8 The voltage applied through the first word line WL1 during the read operation performed prior to the programming operation shown in the diagram. The unit read voltage Vur can be predetermined and stored in the memory device 110.

[0141] For example, the memory controller 120 may increase the read voltage for read operations on the first page PG1 in response to the number of cutoff cells OFC among the memory cells included in the first page PG1 exceeding a reference number.

[0142] Referring to the configuration described above, the memory controller 120 can determine, after performing a programming operation on the first page PG1, whether the number of cutoff cells OFCs whose threshold voltage is greater than or equal to a reference voltage (e.g., a second reference voltage V2) exceeds a reference number.

[0143] The memory controller 120 may update the voltage code corresponding to the operating voltage for the operation of the memory cells included in the first page PG1 in response to the number of cutoff cells OFC exceeding the reference number.

[0144] The memory controller 120 can perform operations on the memory cells included in the first page PG1 using an operating voltage corresponding to the updated voltage code in response to an operation command for the memory cells included in the first page PG1.

[0145] For example, the memory controller 120 may, in response to the second programming command PC2, perform a programming operation on the memory cells included in the first page PG1 using a second programming voltage Vp2 corresponding to the second voltage code.

[0146] The voltage required for programming operations can be reduced as the time interval between consecutive programming operations decreases.

[0147] Therefore, the memory controller 120 can control the magnitude of the programming voltage based on the threshold voltage distribution, so as the time interval between consecutive programming operations decreases, the programming voltage is reduced to a magnitude corresponding to the desired voltage.

[0148] In another example, the memory controller 120 may use a first read voltage Vr1 corresponding to the second voltage code to perform a read operation on a memory cell included in the first page PG1.

[0149] For example, the memory controller 120 may control the read voltage to a level corresponding to the required voltage magnitude that varies according to the characteristics of the memory device 110, based on the threshold voltage distribution, in order to perform a read operation on the memory device 110.

[0150] The configuration described above enables the storage device 100B, according to one or more embodiments, to improve the performance of operations (e.g., programming and reading operations) on the memory device 110.

[0151] Figure 13This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a first batch erase voltage to a first superblock. Figure 14 This is a diagram illustrating a configuration in which a memory controller, according to one or more embodiments, applies a second batch erase voltage to a first superblock.

[0152] Reference Figure 13 and Figure 14 The storage device 100C according to one or more embodiments may include a memory device 110 and a memory controller 120. Figure 13 and Figure 14 The storage device 100C shown can be understood as Figure 2 An example of storage device 100 is shown. Therefore, components that are the same or substantially the same as those described above are indicated by the same reference numerals, and redundant descriptions of components that are the same or substantially the same as those described above will be omitted.

[0153] Reference Figure 13 and 14 According to one or more embodiments, the memory controller 120 may control the bulk erase voltage for bulk erase operations on the first superblock SPB1 based on the threshold voltage distribution of memory cells included in the first superblock SPB1.

[0154] According to one or more embodiments, the memory cell array 111 may include a plurality of superblocks SPB1 to SPBa (where “a” is any integer greater than or equal to 2). Each of the plurality of superblocks SPB1 to SPBa may include a plurality of memory blocks. For example, the first superblock SPB1 may include a plurality of memory blocks BLK1 to BLKb (where “b” is any integer greater than or equal to 2). Each of the superblocks SPB1 to SPBa other than the first superblock SPB1 may include “b” memory blocks.

[0155] Each of the multiple superblocks SPB1 to SPBa can be a unit of a batch erase operation controlled by the memory controller 120. For example, the memory controller 120 can control a batch erase operation on each of the multiple superblocks SPB1 to SPBa.

[0156] Reference Figure 13 According to one or more embodiments, the memory controller 120 can perform a bulk erase operation on the first superblock SPB1. The memory controller 120 can erase a plurality of memory cells included in the first superblock SPB1.

[0157] For example, memory controller 120 may apply a first batch erase voltage Vte1 to a first superblock SPB1 in response to a first batch erase command TEC1. Memory controller 120 may also apply the first batch erase voltage Vte1 to each of a plurality of memory blocks BLK1 to BLKb included in the first superblock SPB1 in response to the first batch erase command TEC1.

[0158] For example, the memory controller 120 may, in response to a first batch erase command TEC1, change the threshold voltage distribution of memory cells included in the first superblock SPB1 to an erase state.

[0159] According to one or more embodiments, the memory controller 120 can determine the number of cutoff cells in each of a plurality of memory blocks BLK1 to BLKb, each having a threshold voltage greater than or equal to a first reference voltage.

[0160] The memory controller 120 can determine whether the number of memory blocks among a plurality of memory blocks BLK1 to BLKb in which the number of cutoff cells exceeds a reference number is greater than or equal to a first number. Each of the reference number and the first number may be a predetermined value stored in the memory device 110.

[0161] In one example, the value of the first quantity can be "1". For example, the memory controller 120 can determine whether the number of memory blocks among a plurality of memory blocks BLK1 to BLKb in which the number of cutoff cells exceeds a reference quantity is equal to or greater than 1.

[0162] In another example, the value of the first quantity can be half of "b". For example, memory controller 120 can determine whether the number of memory blocks among a plurality of memory blocks BLK1 to BLKb in which the number of cutoff cells exceeds a reference quantity is greater than or equal to half of "b".

[0163] For example, the memory controller 120 may determine whether the number of memory blocks among a plurality of memory blocks BLK1 to BLKb, each having a threshold voltage greater than or equal to a first reference voltage, is greater than or equal to a first number.

[0164] Reference Figure 13 and Figure 14 The memory controller 120 may obtain a second batch erase voltage Vte2 ​​in response to the number of memory blocks in which the number of cutoff cells exceeds a reference number being greater than or equal to a first number.

[0165] For example, the memory controller 120 may obtain a second batch erase voltage Vte2 ​​by adding a unit erase voltage to a first batch erase voltage Vte1 in response to a number of memory blocks in which the number of cutoff cells exceeds a reference number. The value of the unit erase voltage may be predetermined and stored in the memory device 110.

[0166] For example, the memory controller 120 may update the first voltage code corresponding to the first batch erase voltage Vte1 to the second voltage code corresponding to the second batch erase voltage Vte2 ​​in response to the number of memory blocks in which the number of cutoff cells exceeds the reference number being greater than or equal to a first number.

[0167] For example, after a batch erase operation, when the number of memory blocks in the first superblock SPB1 in which the number of cutoff cells exceeds a reference number is greater than or equal to a first number, the memory controller 120 may increase the batch erase voltage.

[0168] The memory controller 120 may store the value of the second batch erase voltage Vte2 ​​or a second voltage code corresponding to the second batch erase voltage Vte2. For example, the memory controller 120 may store the value of the second batch erase voltage Vte2 ​​or the second voltage code corresponding to the second batch erase voltage Vte2 ​​in the memory device 110. For example, the memory controller 120 may store the value of the second batch erase voltage Vte2 ​​or the second voltage code corresponding to the second batch erase voltage Vte2 ​​in at least a portion of a plurality of memory blocks BLK1 to BLKb.

[0169] Reference Figure 14 The memory controller 120 can apply a second batch erase voltage Vte2 ​​to the first superblock SPB1.

[0170] For example, the memory controller 120 may, in response to a second bulk erase command TEC2, apply a second bulk erase voltage Vte2 ​​to each of the plurality of memory blocks BLK1 to BLKb included in the first superblock SPB1. For example, the memory controller 120 may, in response to the second bulk erase command TEC2, perform a bulk erase operation on the first superblock SPB1 using the second bulk erase voltage Vte2. For example, the memory controller 120 may, in response to receiving the second bulk erase command TEC2, apply a pre-stored second bulk erase voltage Vte2 ​​to the first superblock SPB1.

[0171] For example, after updating the batch erase voltage based on the threshold voltage distribution of memory cells, the memory controller 120 may, in response to a batch erase command (e.g., a second batch erase command TEC2), perform a batch erase operation using the updated batch erase voltage (e.g., a second batch erase voltage Vte2).

[0172] Referring to the configuration described above, the memory controller 120 can determine, after performing a bulk erase operation on the first superblock SPB1, whether the number of memory blocks in which the number of cutoff cells exceeds a reference number is greater than or equal to a first number.

[0173] The memory controller 120 may increase the bulk erase voltage for the bulk erase operation on the first superblock SPB1 in response to the number of memory blocks in which the number of cutoff cells exceeds a reference number being greater than or equal to a first number.

[0174] The voltage required for batch erase operations can be increased as the time interval between consecutive programming operations decreases.

[0175] Therefore, for example, the memory controller 120 may control the magnitude of the batch erase voltage based on a threshold voltage distribution, so as the time interval between consecutive programming operations decreases, the batch erase voltage increases to a magnitude corresponding to the desired voltage.

[0176] For example, the memory controller 120 may control the bulk erase voltage to a size corresponding to the required voltage size that varies according to the characteristics of the memory device 110, based on the threshold voltage distribution, in order to perform a bulk erase operation on the memory device 110.

[0177] Referring to the configuration described above, the memory controller 120 according to one or more embodiments can control the bulk erase voltage for the first superblock SPB1 based on the threshold voltage distribution of multiple memory blocks BLK1 to BLKb.

[0178] Therefore, compared to the case where the erase voltage for each of the multiple memory blocks BLK1 to BLKb is controlled individually, the memory controller 120 can control the batch erase voltage in a relatively short time.

[0179] The configuration described above enables the storage device 100C according to one or more embodiments to improve the performance of operations (e.g., bulk erase operations) on the memory device 110.

[0180] Figure 15 This is a flowchart illustrating a method for controlling the magnitude of an erase voltage based on a threshold voltage of a memory cell, performed by a storage device according to one or more embodiments. (Refer to...) Figure 5 , Figure 6 and Figure 7 right Figure 15 Describe it.

[0181] Reference Figure 15According to one or more embodiments, the memory controller 120 (or storage device 100) may control the erase voltage for the erase operation of the first memory block BLK1 based on the threshold voltage distribution of the memory cells included in the first memory block BLK1.

[0182] In operation S10, the memory controller 120 according to one or more embodiments may apply a first erase voltage Ve1 to the first memory block BLK1 in response to a first erase command EC1.

[0183] For example, the memory controller 120 may, in response to a first erase command EC1, apply a first erase voltage Ve1 to a plurality of memory cells included in a first memory block BLK1.

[0184] For example, according to one or more embodiments, the memory controller 120 may perform an erase operation on the first memory block BLK1 in response to a first erase command EC1.

[0185] The memory controller 120 may, in response to the first erase command EC1, change or drive the threshold voltage distribution of the memory cells included in the first memory block BLK1 to an erase state E.

[0186] In operation S20, the memory controller 120 according to one or more embodiments may determine the number of cutoff cells (OFCs).

[0187] For example, the memory controller 120 can determine that each memory cell in the erase state E has a reference voltage greater than or equal to a reference voltage (e.g., Figure 6 The number of cutoff cells OFC of the threshold voltage of the first reference voltage (V1).

[0188] For example, the memory controller 120 may count the number of cutoff cells OFC, each having a threshold voltage greater than or equal to a reference voltage, in the memory cells in the erase state E.

[0189] In operation S30, the memory controller 120, according to one or more embodiments, may determine whether the number of cutoff cells (OFCs) exceeds a reference number RN. For example, the reference number RN may be a predetermined value stored in the memory device 110.

[0190] For example, the memory controller 120 can determine whether the number of cutoff cells OFC, each having a threshold voltage greater than or equal to a reference voltage, in the memory cells of the first memory block BLK1 in the erase state E exceeds the reference number RN.

[0191] According to one or more embodiments, the memory controller 120 may control the reference voltage and / or reference quantity RN based on the temperature at which the storage device 100 operates.

[0192] In one example, the memory controller 120 may increase the magnitude of the reference voltage and decrease the reference quantity RN in response to the temperature at which the storage device 100 operates being lower than or equal to a predetermined threshold temperature.

[0193] In another example, the memory controller 120 may decrease the magnitude of the reference voltage and increase the number of references RN in response to the temperature at which the storage device 100 operates exceeding a predetermined threshold temperature.

[0194] In operation S40, the memory controller 120 according to one or more embodiments may respond to the number of cutoff cells OFC exceeding a reference number RN. Figure 15 The second erase voltage Ve2 is obtained when the number of cutoff cells OFC is less than or equal to the reference number RN. In one example, the memory controller 120 according to one or more embodiments may respond to the fact that the number of cutoff cells OFC is less than or equal to the reference number RN. Figure 15 If the value in the text is "No", the operation will terminate.

[0195] For example, the memory controller 120 may, in response to the number of cutoff cells (OFCs) exceeding a reference number RN, obtain a second erase voltage Ve2 by adding a unit erase voltage to a first erase voltage Ve1. The value of the unit erase voltage may be predetermined and stored in the memory device 110.

[0196] For example, the memory controller 120 may update the first voltage code corresponding to the first erase voltage Ve1 to the second voltage code corresponding to the second erase voltage Ve2 in response to the number of cutoff cells OFC exceeding the reference number RN.

[0197] For example, after an erase operation, when the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the reference voltage, among the memory cells included in the first memory block BLK1 exceeds the reference number RN, the memory controller 120 may increase the erase voltage used for the erase operation.

[0198] The memory controller 120 may store the value of the second erase voltage Ve2 or a second voltage code corresponding to the second erase voltage Ve2. For example, the memory controller 120 may store the value of the second erase voltage Ve2 or the second voltage code corresponding to the second erase voltage Ve2 in the memory device 110. For example, the memory controller 120 may store the value of the second erase voltage Ve2 or the second voltage code corresponding to the second erase voltage Ve2 in at least a portion of a plurality of memory blocks BLK1 to BLKn.

[0199] In operation S50, the memory controller 120 according to one or more embodiments may apply a second erase voltage Ve2 to the first memory block BLK1.

[0200] For example, the memory controller 120 may apply a second erase voltage Ve2 to the first memory block BLK1 in response to the second erase command EC2. Alternatively, the memory controller 120 may perform an erase operation on the first memory block BLK1 using the second erase voltage Ve2 in response to the second erase command EC2. Or, the memory controller 120 may apply the stored second erase voltage Ve2 to the first memory block BLK1 in response to receiving the second erase command EC2.

[0201] For example, after updating the erase voltage based on the threshold voltage distribution of the memory cell, the memory controller 120 may, in response to receiving an erase command (e.g., a second erase command EC2), perform an erase operation using the updated erase voltage (e.g., a second erase voltage Ve2).

[0202] Referring to the configuration described above, the memory controller 120 can determine whether the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the reference voltage, exceeds the reference number RN after performing an erase operation on the first memory block BLK1.

[0203] The memory controller 120 may increase the erase voltage for the erase operation on the first memory block BLK1 in response to the number of cutoff cells OFC exceeding the reference number RN.

[0204] The voltage required for the erase operation can be increased as the time interval between consecutive programming operations decreases.

[0205] Therefore, for example, the memory controller 120 may control the magnitude of the erase voltage based on a threshold voltage distribution, so that as the time interval between consecutive programming operations decreases, the erase voltage is increased to a magnitude corresponding to the desired voltage.

[0206] For example, the memory controller 120 may control the erase voltage to a magnitude corresponding to the required voltage magnitude that varies according to the characteristics of the memory device 110, based on the threshold voltage distribution, in order to perform an erase operation on the memory device 110.

[0207] The configuration described above enables the storage device 100 according to one or more embodiments to improve the performance of operations (e.g., erase operations) on the memory device 110.

[0208] According to one or more embodiments, the memory controller 120 may determine the number of cutoff cells OFC in response to performing an erase operation on the first memory block BLK1 a predetermined number of times using a second erase voltage Ve2.

[0209] For example, after performing an erase operation on the first memory block BLK1 a predetermined number of times using the second erase voltage Ve2, the memory controller 120 may, in response to an erase command, determine the number of cutoff cells OFCs whose threshold voltage is greater than or equal to a reference voltage (that is, the number of cutoff cells OFCs, each of the memory cells included in the first memory block BLK1, that have a threshold voltage greater than or equal to the reference voltage). For example, once the erase voltage of the erase operation has been updated to the second erase voltage Ve2, after performing an erase operation a predetermined number of times using the second erase voltage Ve2, the memory controller 120 may execute the steps corresponding to operation S20 to determine whether to perform an update of the erase voltage based on the number of cutoff cells.

[0210] The third erase voltage can be obtained by adding the unit erase voltage to the second erase voltage Ve2 in response to the number of cutoff cells OFC exceeding the reference number RN.

[0211] For example, the memory controller 120 can determine whether the number of cutoff cells (OFCs) exceeds a reference number RN based on a specified operating cycle. When the number of cutoff cells (OFCs) exceeds the reference number RN, the memory controller 120 can increase the erase voltage.

[0212] Referring to the configuration described above, the memory controller 120 according to one or more embodiments can determine whether the number of cutoff cells (OFCs) exceeds a reference number RN each time a predetermined number of erase operations are performed. When the number of cutoff cells (OFCs) exceeds the reference number RN, the memory controller 120 can increase the erase voltage.

[0213] Therefore, compared to the case where the operating voltage is controlled based on whether the number of cutoff cells (OFCs) exceeds the reference number RN each time an erase operation is performed, the memory controller 120 can control the operating voltage a relatively small number of times.

[0214] The configuration described above enables the storage device 100 according to one or more embodiments to reduce the time and power consumed by the control operating voltage.

[0215] Figure 16 This is a flowchart illustrating a method performed by a storage device according to one or more embodiments to control the magnitude of the erase voltage based on a threshold voltage of a memory cell after a programming operation. (Refer to...) Figure 5 , Figure 7 , Figure 8 and Figure 9 right Figure 16 Describe it.

[0216] Reference Figure 16According to one or more embodiments, the memory controller 120 (or storage device 100) may control the erase voltage for the erase operation of the first memory block BLK1 based on the threshold voltage distribution of the memory cells included in the first memory block BLK1.

[0217] In operation S10, the memory controller 120 according to one or more embodiments may apply a first erase voltage Ve1 to the first memory block BLK1 in response to a first erase command EC1.

[0218] For example, the memory controller 120 may, in response to a first erase command EC1, apply a first erase voltage Ve1 to a plurality of memory cells included in a first memory block BLK1.

[0219] For example, according to one or more embodiments, the memory controller 120 may perform an erase operation on the first memory block BLK1 in response to a first erase command EC1.

[0220] In operation S15, the memory controller 120 according to one or more embodiments may apply a first programming voltage Vp1 via the first word line WL1.

[0221] For example, the memory controller 120 may apply a first programming voltage Vp1 via a first word line WL1 in response to a first programming command PC1 for a memory cell included in the first page PG1. The first word line WL1 can be understood as being connected to the first page PG1. Therefore, the memory controller 120 may apply the first programming voltage Vp1 to the memory cell included in the first page PG1 via the first word line WL1 in response to the first programming command PC1.

[0222] For example, memory controller 120 may, in response to a first programming command PC1 for memory cells included in the first page PG1, transition a threshold voltage of at least a portion of the memory cells included in the first page PG1 to a programming state P. In one example, at least a portion of the memory cells in the first page PG1 that are in an erase state E may be programmed by a first programming voltage Vp1.

[0223] In operation S21, the memory controller 120 according to one or more embodiments may determine the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the second reference voltage V2.

[0224] For example, the memory controller 120 may determine the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the second reference voltage V2, in memory cells in programming state P (e.g., at least a portion of memory cells in erasing state E in the first page PG1 that are programmed by a first programming voltage Vp1). For example, the memory controller 120 may count the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the second reference voltage V2, in memory cells in programming state P (e.g., memory cells in the first page PG1).

[0225] In operation S31, the memory controller 120, according to one or more embodiments, may determine whether the number of cutoff cells (OFCs) exceeds a reference number RN. For example, the reference number RN may be a predetermined value stored in the memory device 110.

[0226] For example, the memory controller 120 can determine whether the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the second reference voltage V2, in the memory cells of the first memory block BLK1 in the programmed state P exceeds the reference number RN.

[0227] In operation S41, the memory controller 120 according to one or more embodiments may respond to the number of cutoff cells OFC exceeding a reference number RN. Figure 16 The second erase voltage Ve2 is obtained when the number of cutoff cells OFC is less than or equal to the reference number RN. In one example, the memory controller 120 according to one or more embodiments may respond to the fact that the number of cutoff cells OFC is less than or equal to the reference number RN. Figure 16 If the value in the text is "No", the operation will terminate.

[0228] For example, the memory controller 120 may obtain a second erase voltage Ve2 by adding a unit erase voltage to a first erase voltage Ve1 in response to the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the second reference voltage V2, exceeding a reference number RN. The value of the unit erase voltage may be predetermined and stored in the memory device 110.

[0229] For example, the memory controller 120 may update the first voltage code corresponding to the first erase voltage Ve1 to the second voltage code corresponding to the second erase voltage Ve2 in response to the number of cutoff cells OFC exceeding the reference number RN.

[0230] For example, after an erase operation, when the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the second reference voltage V2, among the memory cells included in the first memory block BLK1 exceeds the reference number RN, the memory controller 120 may increase the erase voltage used for the erase operation.

[0231] The memory controller 120 may store the value of the second erase voltage Ve2 or a second voltage code corresponding to the second erase voltage Ve2. For example, the memory controller 120 may store the value of the second erase voltage Ve2 or the second voltage code corresponding to the second erase voltage Ve2 in the memory device 110.

[0232] In operation S51, the memory controller 120 according to one or more embodiments may apply a second erase voltage Ve2 to the first memory block BLK1.

[0233] For example, the memory controller 120 may apply a second erase voltage Ve2 to the first memory block BLK1 in response to the second erase command EC2. Alternatively, the memory controller 120 may perform an erase operation on the first memory block BLK1 using the second erase voltage Ve2 in response to the second erase command EC2. Or, the memory controller 120 may apply the stored second erase voltage Ve2 to the first memory block BLK1 in response to receiving the second erase command EC2.

[0234] For example, after updating the erase voltage based on the threshold voltage distribution of the memory cell, the memory controller 120 may, in response to an erase command (e.g., a second erase command EC2), perform an erase operation using the updated erase voltage (e.g., a second erase voltage Ve2).

[0235] Referring to the configuration described above, after applying the programming voltage through the first word line WL1, the memory controller 120 can determine whether the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the second reference voltage V2, in the memory cells in the programming state P exceeds the reference number RN.

[0236] The memory controller 120 may increase the erase voltage for the erase operation on the first memory block BLK1 in response to the number of cutoff cells OFC in the memory cells in the programming state P exceeding the reference number RN.

[0237] The memory controller 120 can perform an erase operation using an increased erase voltage in response to an erase command for the first memory block BLK1.

[0238] The voltage required for the erase operation can be increased as the time interval between consecutive programming operations decreases.

[0239] Therefore, the memory controller 120 can control the magnitude of the erase voltage based on the threshold voltage distribution, so as the time interval between consecutive programming operations decreases, the erase voltage is increased to a magnitude corresponding to the required voltage.

[0240] For example, the memory controller 120 may control the erase voltage to a magnitude corresponding to the required voltage magnitude that varies according to the characteristics of the memory device 110, based on the threshold voltage distribution, in order to perform an erase operation on the memory device 110.

[0241] The configuration described above enables the storage device 100 according to one or more embodiments to improve the performance of operations (e.g., erase operations) on the memory device 110.

[0242] Figure 17 This is a flowchart illustrating a method performed by a storage device according to one or more embodiments to control the magnitude of a programming voltage based on a threshold voltage of a memory cell after a programming operation has been performed. Figure 18 This is a flowchart illustrating a method for controlling the magnitude of a read voltage based on a threshold voltage of a memory cell, performed by a storage device according to one or more embodiments. (Refer to...) Figures 5 to 12 describe Figure 17 and Figure 18 .

[0243] Reference Figure 17 According to one or more embodiments, the memory controller 120 (or memory device 100) may control the programming voltage for programming operations on the first page PG1 based on the threshold voltage distribution of the memory cells included in the first page PG1.

[0244] In operation S10, the memory controller 120 according to one or more embodiments may apply a first erase voltage Ve1 to the first memory block BLK1 in response to a first erase command EC1.

[0245] For example, the memory controller 120 may, in response to a first erase command EC1, apply a first erase voltage Ve1 to a plurality of memory cells included in a first memory block BLK1.

[0246] For example, according to one or more embodiments, the memory controller 120 may perform an erase operation on the first memory block BLK1 in response to a first erase command EC1.

[0247] In operation S15, the memory controller 120 according to one or more embodiments may apply a first programming voltage Vp1 via the first word line WL1.

[0248] For example, the memory controller 120 may apply a first programming voltage Vp1 via a first word line WL1 in response to a first programming command PC1 for a memory cell included in the first page PG1. The first word line WL1 can be understood as being connected to the first page PG1. Therefore, the memory controller 120 may apply the first programming voltage Vp1 to the memory cell included in the first page PG1 via the first word line WL1 in response to the first programming command PC1.

[0249] For example, the memory controller 120 may, in response to a first programming command PC1 for memory cells included in the first page PG1, change the threshold voltage distribution of at least a portion of the memory cells included in the first page PG1 to a programming state P.

[0250] In operation S22, the memory controller 120 according to one or more embodiments may determine the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the second reference voltage V2.

[0251] For example, the memory controller 120 may determine the number of cutoff cells (OFCs) among the memory cells included in the first page PG1, each having a threshold voltage greater than or equal to the second reference voltage V2. For example, the memory controller 120 may count the number of cutoff cells (OFCs) among the memory cells in the first page PG1 that are in a programmed state P, each having a threshold voltage greater than or equal to the second reference voltage V2.

[0252] In operation S32, the memory controller 120, according to one or more embodiments, may determine whether the number of cutoff cells (OFCs) among the memory cells in the programmed state P within the first page PG1 exceeds a reference number RN. For example, the reference number RN may be a predetermined value stored in the memory device 110.

[0253] For example, the memory controller 120 can determine whether the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the second reference voltage V2, in the memory cells of the first memory block BLK1 in the programmed state P exceeds the reference number RN.

[0254] In operation S42, the memory controller 120 according to one or more embodiments may respond to the number of cutoff cells OFC exceeding a reference number RN. Figure 17 The second programming voltage Vp2 is obtained by indicating "yes" in the code. In one example, the memory controller 120 according to one or more embodiments may respond to a number of cutoff cells OFC being less than or equal to a reference number RN. Figure 17 If the value in the text is "No", the operation will terminate.

[0255] For example, the memory controller 120 may obtain a second programming voltage Vp2 by subtracting a unit programming voltage from a first programming voltage Vp1 in response to the number of cutoff cells (OFCs) in the memory cells in programming state P exceeding a reference number RN. The value of the unit programming voltage may be predetermined and stored in the memory device 110.

[0256] For example, the memory controller 120 may update the first voltage code corresponding to the first programming voltage Vp1 to the second voltage code corresponding to the second programming voltage Vp2 in response to the number of cutoff cells OFC in the memory cells in the programming state P exceeding the reference number RN.

[0257] For example, after a programming operation, when the number of cutoff cells OFC, each having a threshold voltage greater than or equal to the second reference voltage V2, included in the memory cells of the first page PG1 exceeds the reference number RN, the memory controller 120 may reduce the programming voltage.

[0258] The memory controller 120 can store the value of the second programming voltage Vp2 or the second voltage code corresponding to the second programming voltage Vp2. For example, the memory controller 120 can store the value of the second programming voltage Vp2 or the second voltage code corresponding to the second programming voltage Vp2 in the memory device 110.

[0259] In operation S52, the memory controller 120 according to one or more embodiments can apply a second programming voltage Vp2 to the first page PG1 via the first word line WL1.

[0260] For example, in response to a second programming command PC2, the memory controller 120 may apply a second programming voltage Vp2 to the first page PG1 via the first word line WL1. For example, in response to the second programming command PC2, the memory controller 120 may perform a programming operation on the memory cells included in the first page PG1 using the second programming voltage Vp2. For example, in response to receiving the second programming command PC2, the memory controller 120 may apply the stored second programming voltage Vp2 via the first word line WL1.

[0261] For example, after updating the programming voltage based on the threshold voltage distribution of the memory cell, the memory controller 120 may perform a programming operation using the updated programming voltage (e.g., the second programming voltage Vp2) in response to a programming command (e.g., the second programming command PC2).

[0262] Referring to the configuration described above, the memory controller 120 can, after applying a programming voltage through the first word line WL1, determine whether the number of cutoff cells (OFCs) in the memory cells in the programming state P, each having a threshold voltage greater than or equal to the second reference voltage V2, exceeds a reference number RN. The memory controller 120 can reduce the programming voltage in response to the number of cutoff cells (OFCs) exceeding the reference number RN.

[0263] The memory controller 120 can perform a programming operation using a reduced programming voltage in response to a programming command for a memory cell included in the first page PG1.

[0264] The voltage required for programming operations can be reduced as the time interval between consecutive programming operations decreases.

[0265] Therefore, for example, the memory controller 120 may control the magnitude of the programming voltage based on a threshold voltage distribution, so as the time interval between consecutive programming operations decreases, the programming voltage is reduced to a magnitude corresponding to the desired voltage.

[0266] For example, the memory controller 120 may control the programming voltage to a level corresponding to the required voltage level that varies according to the characteristics of the memory device 110, based on the threshold voltage distribution, in order to perform programming operations on the memory device 110.

[0267] The configuration described above enables the storage device 100 according to one or more embodiments to improve the performance of programming operations on the memory device 110.

[0268] Reference Figure 17 and Figure 18 According to one or more embodiments, the memory controller 120 may control the read voltage for read operations on the first page PG1 based on the threshold voltage distribution of the memory cells included in the first page PG1.

[0269] In operation S60, the memory controller 120 according to one or more embodiments may apply a first read voltage Vr1 via the first word line WL1 in response to a read command.

[0270] According to one or more embodiments, the first read voltage Vr1 may have a value corresponding to a pre-stored second voltage code. The second voltage code can be understood as a code stored in response to the number of cutoff cells (OFCs) exceeding the reference number RN.

[0271] For example, as referenced Figure 12The first read voltage Vr1, as described, may have a value obtained by adding the unit read voltage Vur to the pre-read voltage Vr0. The pre-read voltage Vr0 can be understood as the voltage applied through the first word line WL1 during a read operation performed prior to the programming operation in operation S15. The unit read voltage Vur may be predetermined and stored in the memory device 110.

[0272] For example, the memory controller 120 may increase the read voltage for read operations on the first page PG1 in response to the number of cutoff cells OFC among the memory cells included in the first page PG1 exceeding a reference number.

[0273] The configuration described above enables the storage device 100 according to one or more embodiments to improve the performance of read operations for the memory device 110.

[0274] Figure 19 This is a flowchart illustrating a method for controlling the magnitude of a bulk erase voltage applied to a superblock based on a threshold voltage of a memory cell, performed by a storage device according to one or more embodiments. (Refer to...) Figure 13 and Figure 14 right Figure 19 Describe it.

[0275] Reference Figure 19 According to one or more embodiments, the memory controller 120 may control the bulk erase voltage for bulk erase operations on the first superblock SPB1 based on the threshold voltage distribution of memory cells included in the first superblock SPB1.

[0276] According to one or more embodiments, the memory cell array 111 may include references Figure 13 The description includes multiple superblocks SPB1 to SPBa. The first superblock SPB1 may include multiple memory blocks BLK1 to BLKb. Each of the multiple superblocks SPB1 to SPBa, excluding the first superblock SPB1, may include "b" memory blocks.

[0277] Each of the multiple superblocks SPB1 to SPBa can be a unit of erase operation controlled by the memory controller 120. For example, the memory controller 120 can control a batch erase operation on each of the multiple superblocks SPB1 to SPBa.

[0278] In operation S100, the memory controller 120 according to one or more embodiments may apply a first batch erase voltage (or first total erase voltage) Vte1 to the first superblock SPB1 in response to a first batch erase command (or first total erase command) TEC1.

[0279] For example, the memory controller 120 may, in response to a first bulk erase command TEC1, apply a first bulk erase voltage Vte1 to each of the plurality of memory blocks BLK1 to BLKb included in the first superblock SPB1.

[0280] For example, the memory controller 120 may perform a bulk erase operation on the first superblock SPB1 in response to a first bulk erase command TEC1.

[0281] The memory controller 120 may, in response to a first batch erase command TEC1, change the threshold voltage distribution of memory cells included in the first superblock SPB1 to an erase state.

[0282] In operation S200, the memory controller 120 according to one or more embodiments may determine the number of cutoff cells OFC in each of a plurality of memory blocks BLK1 to BLKb, each having a threshold voltage greater than or equal to the first reference voltage V1.

[0283] In operation S300, the memory controller 120, according to one or more embodiments, may determine whether the number of memory blocks among a plurality of memory blocks BLK1 to BLKb in which the number of cutoff cells OFC exceeds a reference number RN is greater than or equal to a first number N1. Each of the reference number RN and the first number N1 may be a predetermined value stored in the memory device 110.

[0284] In one example, the value of the first quantity N1 can be "1". For example, the memory controller 120 can determine whether the number of memory blocks among a plurality of memory blocks BLK1 to BLKb in which the number of cutoff cells OFC exceeds a reference quantity RN is greater than or equal to 1.

[0285] In another example, the value of the first quantity N1 can be half of "b", which represents the number of memory blocks. For example, memory controller 120 can determine whether the number of memory blocks among a plurality of memory blocks BLK1 to BLKb in which the number of cutoff cells OFC exceeds a reference quantity RN is greater than or equal to half of "b".

[0286] For example, the memory controller 120 may determine whether the number of memory blocks among a plurality of memory blocks BLK1 to BLKb in which the number of cutoff cells OFCs, each having a threshold voltage greater than or equal to a first reference voltage, exceeds a reference number RN, is greater than or equal to a first number N1.

[0287] In operation S400, the memory controller 120 according to one or more embodiments may respond to the fact that the number of memory blocks in which the number of cutoff cells OFC exceeds a reference number RN is greater than or equal to a first number N1. Figure 19The second batch erase voltage (or second total erase voltage) Vte2 ​​is obtained by indicating "yes" in the code. In one example, the memory controller 120 according to one or more embodiments may respond to the fact that the number of memory blocks in which the number of cutoff cells OFC exceeds a reference number RN is less than a first number N1. Figure 19 If the value in the text is "No", the operation will terminate.

[0288] For example, the memory controller 120 may, in response to the number of memory blocks in which the number of cutoff cells (OFCs) exceeds a reference number RN and is greater than or equal to a first number N1, obtain a second batch erase voltage Vte2 ​​by adding a unit erase voltage to a first batch erase voltage Vte1. The value of the unit erase voltage may be predetermined and stored in the memory device 110.

[0289] For example, the memory controller 120 may update the first voltage code corresponding to the first batch erase voltage Vte1 to the second voltage code corresponding to the second batch erase voltage Vte2 ​​in response to the fact that the number of memory blocks in which the number of cutoff cells OFC exceeds the reference number RN is greater than or equal to the first number N1.

[0290] For example, after a batch erase operation, when the number of memory blocks in the first superblock SPB1 in which the number of cutoff cells OFC exceeds the reference number RN is greater than or equal to the first number N1, the memory controller 120 may increase the batch erase voltage.

[0291] The memory controller 120 may store the value of the second batch erase voltage Vte2 ​​or a second voltage code corresponding to the second batch erase voltage Vte2. For example, the memory controller 120 may store the value of the second batch erase voltage Vte2 ​​or the second voltage code corresponding to the second batch erase voltage Vte2 ​​in the memory device 110. For example, the memory controller 120 may store the value of the second batch erase voltage Vte2 ​​or the second voltage code corresponding to the second batch erase voltage Vte2 ​​in at least a portion of a plurality of memory blocks BLK1 to BLKn.

[0292] In operation S500, the memory controller 120 according to one or more embodiments may apply a second batch erase voltage Vte2 ​​to the first superblock SPB1.

[0293] For example, the memory controller 120 may, in response to a second bulk erase command (or a second total erase command) TEC2, apply a second bulk erase voltage Vte2 ​​to each of the plurality of memory blocks BLK1 to BLKb included in the first superblock SPB1. For example, the memory controller 120 may, in response to the second bulk erase command TEC2, perform a bulk erase operation on the first superblock SPB1 using the second bulk erase voltage Vte2. For example, the memory controller 120 may, in response to receiving the second bulk erase command TEC2, apply the stored second bulk erase voltage Vte2 ​​to the first superblock SPB1.

[0294] For example, after updating the batch erase voltage based on the threshold voltage distribution of memory cells, the memory controller 120 may, in response to a batch erase command (e.g., a second batch erase command TEC2), perform a batch erase operation using the updated batch erase voltage (e.g., a second batch erase voltage Vte2).

[0295] Referring to the configuration described above, the memory controller 120 can determine, after performing a bulk erase operation on the first superblock SPB1, whether the number of memory blocks in which the number of cutoff cells OFC exceeds the reference number RN is greater than or equal to the first number N1.

[0296] The memory controller 120 may increase the bulk erase voltage for the bulk erase operation on the first superblock SPB1 in response to the number of memory blocks in which the number of cutoff cells OFC exceeds a reference number RN and is greater than or equal to a first number N1.

[0297] The voltage required for batch erase operations can be increased as the time interval between consecutive programming operations decreases.

[0298] Therefore, for example, the memory controller 120 may control the magnitude of the batch erase voltage based on a threshold voltage distribution, so as the time interval between consecutive programming operations decreases, the batch erase voltage increases to a magnitude corresponding to the desired voltage.

[0299] For example, the memory controller 120 may control the bulk erase voltage to a size corresponding to the required voltage size that varies according to the characteristics of the memory device 110, based on the threshold voltage distribution, in order to perform a bulk erase operation on the memory device 110.

[0300] Referring to the configuration described above, the memory controller 120 according to one or more embodiments can control the bulk erase voltage for the first superblock SPB1 based on the threshold voltage distribution of multiple memory blocks BLK1 to BLKb.

[0301] Therefore, compared to the case where the erase voltage for each of the multiple memory blocks BLK1 to BLKb is controlled individually, the memory controller 120 can control the batch erase voltage in a relatively short time.

[0302] The configuration described above enables the storage device 100C according to one or more embodiments to improve the performance of bulk erase operations for the memory device 110.

[0303] Figure 20 This is a block diagram illustrating an example of a storage device implemented as a solid-state drive (SSD).

[0304] Reference Figure 20 The SSD 4000 may include multiple flash memory modules 4101 to 4104 and an SSD controller 4200. Figure 20 The SSD controller 4200 shown can be understood as being related to... Figure 2 The memory controller 120 shown is basically the same in configuration.

[0305] The first flash memory 4101 and the second flash memory 4102 can be connected to the SSD controller 4200 via the first channel CH1. The third flash memory 4103 and the fourth flash memory 4104 can be connected to the SSD controller 4200 via the second channel CH2. The number of channels connected to the SSD controller 4200 can be greater than 2. The number of flash memory modules connected to a single channel can be greater than 2.

[0306] The SSD controller 4200 may include a host interface 4201, a flash memory interface 4202, a buffer interface 4203, a control unit 4210, and working memory 4220. The SSD controller 4200 can be connected to the host 200 via the host interface 4201. The SSD controller 4200 can write data to or read data from the corresponding flash memory upon request from the host 200.

[0307] The SSD controller 4200 can be connected to multiple flash memory modules 4101 to 4104 via flash memory interface 4202, and can be connected to buffer memory 1300 via buffer interface 4203. Flash memory interface 4202 can provide data temporarily stored in buffer memory 1300 to the flash memory modules via channels CH1 and CH2. Flash memory interface 4202 can also transfer data read from flash memory modules 4101 to 4104 to buffer memory 1300.

[0308] The control unit 4210 can analyze and process signals input from the host 200. The control unit 4210 can control the host 200 through the host interface 4201 or control the flash memory 4101 to 4104 through the flash memory interface 4202. The control unit 4210 can control the operation of the flash memory 4101 to 4104 based on the firmware used to operate the SSD 4000.

[0309] The SSD controller 4200 manages the data to be stored in flash memory 4101 to 4104. The SSD controller 4200 can back up data stored in working memory 4220 or buffer memory 1300 to flash memory 4101 to 4104 during a sudden power outage.

[0310] According to one or more embodiments, after performing an erase operation on a specific memory block in the first flash memory 4101, the SSD controller 4200 may determine whether the number of cutoff cells OFC, each having a threshold voltage greater than or equal to a reference voltage (e.g., a first reference voltage V1), exceeds a reference number.

[0311] The SSD controller 4200 can increase the erase voltage used for erasing operations on the corresponding memory block in response to the number of cutoff cells (OFCs) exceeding the reference number.

[0312] The voltage required for the erase operation can be increased as the time interval between consecutive programming operations decreases.

[0313] Therefore, for example, the SSD controller 4200 can control the magnitude of the erase voltage based on the threshold voltage distribution, so that as the time interval between consecutive programming operations decreases, the erase voltage is increased to a magnitude corresponding to the desired voltage.

[0314] For example, the SSD controller 4200 may control the erase voltage to a size corresponding to the required voltage size that varies according to the characteristics of the first flash memory 4101 based on the threshold voltage distribution, so as to perform an erase operation on the first flash memory 4101.

[0315] The configuration described above enables the SSD 4000, according to one or more embodiments, to improve the performance of operations (e.g., erase operations) on the first flash memory 4101.

[0316] Figure 21 This is a diagram illustrating a flash memory according to one or more embodiments.

[0317] Reference Figure 21 The flash memory 5000 may have a chip-to-chip (C2C) structure. A C2C structure may represent a structure in which at least one upper chip, including a cell region (CELL), and at least one lower chip, including a peripheral circuit region (PERI), are manufactured separately and then connected to each other by a bonding method. Figure 21 The flash memory 5000 shown can be understood as being related to... Figure 2 The memory device 110 shown has a substantially the same configuration.

[0318] In one example, the bonding method may refer to a method of electrically or physically connecting a bonding metal pattern formed on the uppermost metal layer of an upper chip to a bonding metal pattern formed on the uppermost metal layer of a lower chip. For example, when the bonding metal pattern is formed of copper (Cu), the bonding method may be a copper-copper (Cu-Cu) bonding method. In another example, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0319] The flash memory 5000 may include at least one on-chip containing cell regions. For example, such as Figure 21 As shown, the flash memory 5000 can be implemented as including two upper chips. However, this is merely an example, and the number of upper chips is not limited to this. When the flash memory 5000 is implemented as including two upper chips, the flash memory 5000 can be manufactured by first separately manufacturing a first upper chip including a first cell region CELL1, a second upper chip including a second cell region CELL2, and a lower chip including a peripheral circuit region PERI, and then connecting the first upper chip, the second upper chip, and the lower chip to each other by a bonding method. The first upper chip can be flipped and connected to the lower chip by a bonding method, and the second upper chip can also be flipped and connected to the first upper chip by a bonding method. In the following description, the upper and lower portions of the first upper chip and the upper and lower portions of the second upper chip are defined based on the first and second upper chips before they are flipped. For example, in Figure 21 In this context, the upper part of the lower chip represents the upper part defined based on the positive Z-axis direction, and the upper parts of the first upper chip and the second upper chip represent the upper parts defined based on the negative Z-axis direction. However, this is merely an example, and only one of the first and second upper chips can be flipped and connected by a bonding method.

[0320] Each of the peripheral circuit region PERI and the first cell region CELL1 and the second cell region CELL2 of the flash memory 5000 may include an external pad bonding region PA, a word line bonding region WLBA and a bit line bonding region BLBA.

[0321] The Peripheral Circuit Area (PERI) may include a first substrate 210 and a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210. An interlayer dielectric 215 comprising one or more dielectrics may be disposed on the plurality of circuit elements 220a, 220b, and 220c, and a plurality of metal wires connecting the plurality of circuit elements 220a, 220b, and 220c may be disposed in the interlayer dielectric 215. For example, the plurality of metal wires may include first metal wires 230a, 230b, and 230c respectively connected to the plurality of circuit elements 220a, 220b, and 220c, and second metal wires 240a, 240b, and 240c formed on the first metal wires 230a, 230b, and 230c. The plurality of metal wires may be formed of at least one of various conductive materials. For example, the first metal terminals 230a, 230b and 230c may be formed of tungsten with relatively high resistivity, and the second metal terminals 240a, 240b and 240c may be formed of copper with relatively low resistivity.

[0322] In this disclosure, only the first metal wires 230a, 230b, and 230c and the second metal wires 240a, 240b, and 240c are shown and described, but the embodiments are not limited thereto. At least one additional metal wire may also be formed on the second metal wires 240a, 240b, and 240c, and the second metal wires 240a, 240b, and 240c may be formed of aluminum. At least a portion of the additional metal wires formed on the second metal wires 240a, 240b, and 240c may be formed of copper or the like, which has a lower resistivity than the aluminum of the second metal wires 240a, 240b, and 240c.

[0323] Interlayer dielectric 215 may be disposed on first substrate 210 and may include insulating material (such as silicon oxide, silicon nitride, etc.).

[0324] The first cell region CELL1 and the second cell region CELL2 may each include at least one memory block. The first cell region CELL1 may include a second substrate 310 and a common source line 320. Word lines 330 (e.g., multiple word lines 331 to 338) may be stacked on the second substrate 310 in a direction perpendicular to the upper surface of the second substrate 310 (Z-axis direction). Serial select lines and ground select lines may be disposed above and below the word lines 330, and the word lines 330 may be disposed between the serial select lines and the ground select lines. Similarly, the second cell region CELL2 may include a third substrate 410 and a common source line 420, and word lines 430 (e.g., multiple word lines 431 to 438) may be stacked in a direction perpendicular to the upper surface of the third substrate 410 (Z-axis direction). Each of the second substrate 310 and the third substrate 410 may be formed of various materials and may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single-crystal epitaxial layer grown on a single-crystal silicon substrate. Multiple channel structures CH can be formed in each of the first unit region CELL1 and the second unit region CELL2.

[0325] In one or more embodiments, as shown in region A1 as an alternative embodiment of region A, a channel structure CH is disposed in a bit line bonding region BLBA and extends in a direction perpendicular to the upper surface of the second substrate 310, and can penetrate word lines 330, serial select lines, and ground select lines. The channel structure CH may include a data storage layer, a channel layer, an embedded insulating layer, etc. The channel layer may be electrically connected to a first metal connection 350c and a second metal connection 360c in the bit line bonding region BLBA. For example, the second metal connection 360c may be a bit line and can be connected to the channel structure CH via the first metal connection 350c. The bit line 360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310. For example, the first direction, the second direction, and the third direction may be perpendicular to each other.

[0326] In one or more embodiments, as shown in region A2, an alternative embodiment of region A, the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process for the lower channel LCH and a process for the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the upper surface of the second substrate 310 and may penetrate the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, a buried insulating layer, etc., and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, an embedded insulating layer, etc., and the channel layer of the upper channel UCH may be electrically connected to the first metal terminal 350c and the second metal terminal 360c. As the length of the channel increases, it may become difficult to form a channel with a consistent width due to manufacturing processes. The flash memory 5000 according to one or more embodiments may include channels with improved width consistency formed by a lower channel (LCH) and an upper channel (UCH) through sequential processes.

[0327] When the channel structure CH is formed to include a lower channel LCH and an upper channel UCH as shown in region A2, the word lines located near the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. For example, word lines 332 and 333 formed near the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. Data may not be stored in memory cells connected to the dummy word lines. Optionally, the number of pages corresponding to memory cells connected to dummy word lines may be smaller than the number of pages corresponding to memory cells connected to normal word lines. The voltage level applied to the dummy word lines may be different from the voltage level applied to the normal word lines, thereby reducing the impact of the non-uniform channel width between the lower channel LCH and the upper channel UCH on the operation of the flash memory.

[0328] In region A2, the number of lower word lines 331 and 332 penetrated by the lower channel LCH is shown to be smaller than the number of upper word lines 333 to 338 penetrated by the upper channel UCH. However, this is merely an example, and the embodiment is not limited thereto. In another example, the number of lower word lines penetrated by the lower channel LCH may be the same as or greater than the number of upper word lines penetrated by the upper channel UCH. The structure and connection relationships described above for the channel structure CH disposed in the first cell region CELL1 can be similarly applied to the channel structure CH disposed in the second cell region CELL2.

[0329] In the bit line bonding region BLBA, a first through-electrode THV1 can be disposed in the first cell region CELL1, and a second through-electrode THV2 can be disposed in the second cell region CELL2. For example... Figure 21 As shown, the first through-electrode THV1 can penetrate the common source line 320 and the word line 330. However, this is only an example, and the first through-electrode THV1 can also penetrate the second substrate 310. The first through-electrode THV1 may include a conductive material. Optionally, the first through-electrode THV1 may include a conductive material surrounded by an insulating material. The second through-electrode THV2 may also be configured with the same shape and structure as the first through-electrode THV1.

[0330] In one or more embodiments, the first through electrode THV1 and the second through electrode THV2 can be electrically connected via a first through metal pattern 372d and a second through metal pattern 472d. The first through metal pattern 372d can be formed at the lower end of a first upper chip including a first cell region CELL1, and the second through metal pattern 472d can be formed at the upper end of a second upper chip including a second cell region CELL2. The first through electrode THV1 can be electrically connected to a first metal terminal 350c and a second metal terminal 360c. The second through electrode THV2 can be electrically connected to the first metal terminal 450c and the second metal terminal 460c. A lower via 371d can be formed between the first through electrode THV1 and the first through metal pattern 372d, and an upper via 471d can be formed between the second through electrode THV2 and the second through metal pattern 472d. The first through metal pattern 372d and the second through metal pattern 472d can be connected using a bonding method.

[0331] In the bit line bonding area (BLBA), an upper metal pattern 252 may be formed on the uppermost metal layer of the peripheral circuit region (PERI), and an upper metal pattern 392 having the same shape as the upper metal pattern 252 may be formed on the uppermost metal layer of the first cell region (CELL1). The upper metal pattern 392 of the first cell region (CELL1) and the upper metal pattern 252 of the peripheral circuit region (PERI) may be electrically connected to each other using a bonding method. In the bit line bonding area (BLBA), a bit line 360c may be electrically connected to a page buffer included in the peripheral circuit region (PERI). For example, a portion of the circuit element 220c in the peripheral circuit region (PERI) may provide a page buffer, and the bit line 360c may be electrically connected to the circuit element 220c providing the page buffer via the upper bonding metal 370c of the first cell region (CELL1) and the upper bonding metal 270c of the peripheral circuit region (PERI).

[0332] Continue to refer to Figure 21In the word line bonding area WLBA, the word line 330 of the first cell region CELL1 may extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 310 and may be connected to cell contact plugs 340 (e.g., a plurality of cell contact plugs 341 to 347). A first metal wire 350b and a second metal wire 360b may be sequentially connected above the cell contact plugs 340 connected to the word line 330. The cell contact plugs 340 may be connected to the peripheral circuit region PERI in the word line bonding area WLBA via the upper bonding metal 370b of the first cell region CELL1 and the upper bonding metal 270b of the peripheral circuit region PERI.

[0333] Cell contact plug 340 may be electrically connected to an address decoder included in the peripheral circuitry region PERI. For example, a portion of the circuitry element 220b in the peripheral circuitry region PERI may provide an address decoder, and cell contact plug 340 may be electrically connected to the circuitry element 220b providing the address decoder via the upper bonding metal 370b of the first cell region CELL1 and the upper bonding metal 270b of the peripheral circuitry region PERI. In one or more embodiments, the operating voltage of the circuitry element 220b providing the address decoder may differ from the operating voltage of the circuitry element 220c providing the page buffer. For example, the operating voltage of the circuitry element 220c providing the page buffer may be greater than the operating voltage of the circuitry element 220b providing the address decoder.

[0334] Similarly, in the word line bonding area WLBA, the word line 430 of the second cell region CELL2 may extend along a second direction (X-axis direction) parallel to the upper surface of the third substrate 410 and may be connected to cell contact plugs 440 (e.g., a plurality of cell contact plugs 441 to 447). The cell contact plugs 440 may be connected to the peripheral circuit region PERI via the upper metal pattern of the second cell region CELL2, the lower metal pattern and upper metal pattern of the first cell region CELL1, and the cell contact plug 348.

[0335] In the word line bonding area WLBA, upper bonding metal 370b is formed in the first cell area CELL1, and upper bonding metal 270b may be formed in the peripheral circuit area PERI. The upper bonding metal 370b of the first cell area CELL1 and the upper bonding metal 270b of the peripheral circuit area PERI are electrically connected to each other by a bonding method. The upper bonding metals 370b and 270b may be formed of aluminum, copper, or tungsten.

[0336] In the external pad bonding area PA, a lower metal pattern 371e may be formed at the bottom (or lower part) of the first cell region CELL1, and an upper metal pattern 472a may be formed at the top (or upper part) of the second cell region CELL2. The lower metal pattern 371e of the first cell region CELL1 and the upper metal pattern 472a of the second cell region CELL2 may be connected in the external pad bonding area PA using a bonding method. Similarly, the upper metal pattern 372a may be formed in the first cell region CELL1 (e.g., at the top of the first cell region CELL1), and the upper metal pattern 272a may be formed in the peripheral circuit region PERI (e.g., at the top of the peripheral circuit region PERI). The upper metal pattern 372a of the first cell region CELL1 and the upper metal pattern 272a of the peripheral circuit region PERI may be connected using a bonding method.

[0337] Common source electrode contact plugs 380 and 480 may be disposed in the external pad bonding region PA. Common source electrode contact plugs 380 and 480 may be formed of a conductive material (such as a metal, metal compound, or doped polysilicon). Common source electrode contact plug 380 of the first cell region CELL1 may be electrically connected to common source electrode 320, and common source electrode contact plug 480 of the second cell region CELL2 may be electrically connected to common source electrode 420. First metal wire 350a and second metal wire 360a may be sequentially stacked on common source electrode contact plug 380 of the first cell region CELL1, and first metal wire 450a and second metal wire 460a may be sequentially stacked on common source electrode contact plug 480 of the second cell region CELL2.

[0338] Input / output pads 205, 405, and 406 can be disposed within the external pad mating area PA. (See reference...) Figure 21 The lower insulating layer 201 may cover the lower surface of the first substrate 210, and the first input / output pad 205 may be formed on the lower insulating layer 201. The first input / output pad 205 may be connected to at least one of a plurality of circuit elements 220a disposed in the peripheral circuit region PERI via the first input / output contact plug 203, and may be separated from the first substrate 210 via the lower insulating layer 201. A side insulating layer may be disposed between the first input / output contact plug 203 and the first substrate 210 to electrically isolate the first input / output contact plug 203 from the first substrate 210.

[0339] An upper insulating layer 401 covering the upper surface of the third substrate 410 may be formed on the third substrate 410. A second input / output pad 405 and / or a third input / output pad 406 may be disposed on the upper insulating layer 401. The second input / output pad 405 is connected to at least one of a plurality of circuit elements 220a disposed in the peripheral circuit region PERI via second input / output contact plugs 403 and 303, and the third input / output pad 406 is connected to at least one of a plurality of circuit elements 220a disposed in the peripheral circuit region PERI via third input / output contact plugs 404 and 304.

[0340] In one or more embodiments, the third substrate 410 may not be disposed in the region where the input / output contact plug is disposed. For example, as shown in region B, the third input / output contact plug 404 is separated from the third substrate 410 in a direction parallel to the upper surface of the third substrate 410 and can penetrate the interlayer dielectric 415 of the second cell region CELL2 to connect to the third input / output pad 406. The third input / output contact plug 404 may be formed by various processes.

[0341] For example, as shown in region B1, an alternative embodiment of region B, the third input / output contact plug 404 may extend in the third direction (Z-axis direction) and may be formed having a diameter that increases in the direction toward the upper insulating layer 401. For example, the diameter of the channel structure CH described in region A1 decreases in the direction toward the upper insulating layer 401, while the diameter of the third input / output contact plug 404 may increase in the direction toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed after the second cell region CELL2 and the first cell region CELL1 are joined together.

[0342] For example, as shown in region B2, an alternative embodiment of region B, the third input / output contact plug 404 may extend in the third direction (Z-axis direction) and may be formed having a diameter that decreases in the direction toward the upper insulating layer 401. For example, similar to the channel structure CH, the third input / output contact plug 404 may be formed having a diameter that decreases in the direction toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed before engagement with the cell contact plug 440 in the second cell region CELL2 and the first cell region CELL1.

[0343] In one or more embodiments, the input / output contact plug may be configured to be stacked with the third substrate 410. For example, as shown in region C, the second input / output contact plug 403 is formed to penetrate the interlayer dielectric 415 of the second cell region CELL2 in the third direction (Z-axis direction) and can be electrically connected to the second input / output pad 405 through the third substrate 410. The connection structure of the second input / output contact plug 403 and the second input / output pad 405 can be implemented in various ways.

[0344] For example, as shown in region C1, an alternative embodiment of region C, the opening 408 may be formed to penetrate the third substrate 410, and the second input / output contact plug 403 may be directly connected to the second input / output pad 405 through the opening 408 formed in the third substrate 410. As shown in region C1, the second input / output contact plug 403 may be formed to have a diameter that increases in the direction toward the second input / output pad 405. However, this is merely an example, and the second input / output contact plug 403 may also be formed to have a diameter that decreases in the direction toward the second input / output pad 405.

[0345] For example, as shown in region C2, an alternative embodiment of region C, an opening 408 may be formed to penetrate the third substrate 410, and a contact 407 may be formed within the opening 408. One end of the contact 407 may be connected to the second input / output pad 405, and the other end of the contact 407 may be connected to the second input / output contact plug 403. Thus, the second input / output contact plug 403 can be electrically connected to the second input / output pad 405 through the contact 407 in the opening 408. As shown in region C2, the diameter of the contact 407 may increase in the direction toward the second input / output pad 405, and the diameter of the second input / output contact plug 403 may decrease in the direction toward the second input / output pad 405. For example, the second input / output contact plug 403 may be formed before the engagement of the cell contact plug 440 with the second cell region CELL2 and the first cell region CELL1, and the contact 407 may be formed after the engagement of the second cell region CELL2 and the first cell region CELL1.

[0346] For example, as shown in region C3, an alternative embodiment of region C, a stop member 409 may also be formed on the upper surface of the opening 408 of the third substrate 410, compared to region C2. The stop member 409 may be a metal connection formed on the same layer as the common source line 420. However, this is merely an example, and the stop member 409 may also be a metal connection formed on the same layer as at least one of the word lines 430. The second input / output contact plug 403 may be electrically connected to the second input / output pad 405 via the contact 407 and the stop member 409.

[0347] Similar to the second input / output contact plug 403 and the third input / output contact plug 404 of the second cell region CELL2, each of the second input / output contact plug 303 and the third input / output contact plug 304 of the first cell region CELL1 may be formed with a diameter that decreases in the direction toward the lower metal pattern 371e, or a diameter that increases in the direction toward the lower metal pattern 371e.

[0348] According to one or more embodiments, slit 411 may be formed in the third substrate 410. For example, slit 411 may be formed at any location in the outer pad engagement region PA. In one example, as shown in region D, when viewed in a plan view, slit 411 may be positioned between the second input / output pad 405 and the cell contact plug 440. However, this is merely an example, and slit 411 may be formed such that, when viewed in a plan view, the second input / output pad 405 is positioned between slit 411 and the cell contact plug 440.

[0349] For example, as shown in region D1, an alternative embodiment of region D, slit 411 may be formed to penetrate the third substrate 410. Slit 411 may be used, for example, to prevent micro-fractures of the third substrate 410 when the opening 408 is formed. However, this is merely an example, and slit 411 may be formed to a depth of approximately 60% to 70% of the thickness of the third substrate 410.

[0350] For example, as shown in region D2, an alternative embodiment of region D, conductive material 412 may be formed within slit 411. Conductive material 412 may be used, for example, to discharge leakage current generated during operation of circuit elements within the external pad bonding region PA to the external entity. Conductive material 412 may be connected to an external ground wire.

[0351] For example, as shown in region D3, an alternative embodiment of region D, an insulating material 413 may be formed within the slit 411. The insulating material 413 may be formed, for example, to electrically isolate the second input / output pad 405 and the second input / output contact plug 403 disposed in the outer pad bonding region PA from the word line bonding region WLBA. Forming the insulating material 413 within the slit 411 prevents the voltage supplied through the second input / output pad 405 from affecting the metal layer disposed on the third substrate 410 within the word line bonding region WLBA.

[0352] According to one or more embodiments, the first input / output pad 205, the second input / output pad 405, and the third input / output pad 406 may be selectively formed. For example, the flash memory 5000 may be implemented to include only the first input / output pad 205 disposed on the first substrate 210, or only the second input / output pad 405 disposed on the third substrate 410, or only the third input / output pad 406 disposed on the upper insulating layer 401.

[0353] According to one or more embodiments, at least one of the second substrate 310 of the first cell region CELL1 and the third substrate 410 of the second cell region CELL2 can be used as a sacrificial substrate and can be completely or partially removed before or after the bonding process. Additional layers can be stacked after substrate removal. For example, the second substrate 310 of the first cell region CELL1 can be removed before or after the bonding of the peripheral circuit region PERI and the first cell region CELL1, and an insulating layer covering the upper surface of the common source electrode 320 or a conductive layer for connection can be formed. Similarly, the third substrate 410 of the second cell region CELL2 can be removed before or after the bonding of the first cell region CELL1 and the second cell region CELL2, and an upper insulating layer 401 covering the upper surface of the common source electrode 420 or a conductive layer for connection can be formed.

[0354] As described above, the memory controller 120 according to one or more embodiments may determine, after performing an erase operation on the first memory block BLK1, whether the number of cutoff cells OFC, each having a threshold voltage greater than or equal to a reference voltage (e.g., a first reference voltage V1), exceeds a reference number.

[0355] The memory controller 120 may increase the erase voltage for the erase operation on the first memory block BLK1 in response to the number of cutoff cells OFC exceeding a reference number.

[0356] The voltage required for the erase operation can be increased as the time interval between consecutive programming operations decreases.

[0357] Therefore, for example, the memory controller 120 may control the magnitude of the erase voltage based on a threshold voltage distribution, so as the time interval between consecutive programming operations decreases, the erase voltage increases to a magnitude corresponding to the desired voltage.

[0358] For example, the memory controller 120 may control the erase voltage to a level corresponding to the voltage required to perform an erase operation on the memory device 110 based on a threshold voltage distribution.

[0359] The voltage required for programming operations can be reduced as the time interval between consecutive programming operations decreases.

[0360] Therefore, for example, the memory controller 120 may control the magnitude of the programming voltage based on a threshold voltage distribution, so as the time interval between consecutive programming operations decreases, the programming voltage is reduced to a magnitude corresponding to the desired voltage.

[0361] Furthermore, the memory controller 120 can control the read voltage to a level corresponding to the required voltage magnitude that varies according to the characteristics of the memory device 110, based on the threshold voltage distribution, in order to perform a read operation on the memory device 110.

[0362] The configuration described above enables the storage device 100 according to one or more embodiments to improve the performance of operations (e.g., erase operations, programming operations, or read operations) on the memory device 110.

[0363] As described above, according to the embodiments, the performance of the operation of the memory device can be improved.

[0364] While various embodiments have been shown and described above, those skilled in the art will understand that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A method of operating a storage device, the method comprising: In response to a first erase command for a first memory block among a plurality of memory blocks, a first erase voltage is applied to the first memory block; Determine the number of cutoff cells, each having a threshold voltage greater than or equal to the reference voltage, among the memory cells included in the first memory block. In response to the number of cutoff cells exceeding the reference number, a second erase voltage is obtained by adding the unit erase voltage to the first erase voltage; as well as In response to a second erase command for the first memory block, a second erase voltage is applied to the first memory block.

2. The method according to claim 1, wherein, The steps for determining the number of cutoff cells among the memory cells included in the first memory block include: Determine the number of cutoff cells, each having a threshold voltage greater than or equal to the first reference voltage, among the memory cells erased by the first erase voltage.

3. The method according to claim 1, wherein, The step of determining the number of cutoff cells among the memory cells included in the first memory block further includes: In response to a first programming command for a first page in a first memory block, a first programming voltage is applied via a first word line connected to the first page to at least a portion of the memory cells in the first page that are in an erased state; and Determine the number of cutoff cells, each having a threshold voltage greater than or equal to the second reference voltage, among the at least a portion of the memory cells in the erased state included in the first page. The at least portion of the memory cells in the erased state included in the first page are programmed by a first programming voltage.

4. The method according to claim 3, wherein, The steps to obtain the second erase voltage include: A second erase voltage is obtained in response to the number of cutoff cells, each having a threshold voltage greater than or equal to the second reference voltage, exceeding the reference number.

5. The method according to claim 3, further comprising: After the second erase voltage is applied to the first memory block, in response to a second programming command for a memory cell included in the first page that is in an erased state, a second programming voltage obtained by subtracting a unit programming voltage from the first programming voltage is applied to the first word line.

6. The method according to claim 3, further comprising: In response to obtaining a second erase voltage, a voltage code corresponding to the second erase voltage is stored in at least a portion of the plurality of memory blocks.

7. The method according to claim 6, further comprising: After storing the voltage code, in response to a read command for a memory cell in an erased state included in the first page, a first read voltage corresponding to the voltage code is applied to the first word line.

8. The method according to claim 1, further comprising: In response to a first bulk erase command for the plurality of memory blocks, a first bulk erase voltage is applied to memory cells included in each of the plurality of memory blocks; When the number of memory blocks in which the number of cutoff cells exceeds the reference number is greater than or equal to the first number, the second batch erase voltage is obtained by adding the unit erase voltage to the first batch erase voltage. as well as In response to a second batch erase command for the plurality of memory blocks, a second batch erase voltage is applied to memory cells included in each of the plurality of memory blocks.

9. The method according to claim 1, further comprising: The reference voltage is adjusted in response to the temperature at which the storage device operates being lower than or equal to a predetermined threshold temperature.

10. The method according to claim 1, further comprising: In response to performing an erase operation on the first memory block a predetermined number of times using a second erase voltage, the number of cutoff cells, each having a threshold voltage greater than or equal to a reference voltage, among the memory cells included in the first memory block is determined. as well as In response to the number of cut-off cells in the memory cells erased by the second erase voltage exceeding a reference number, a third erase voltage is obtained by adding a unit erase voltage to the second erase voltage.

11. A storage device, comprising: A memory device comprising multiple memory blocks; as well as The memory controller is configured to control erase, program, and read operations on the memory device. The memory controller is configured as follows: In response to a first erase command for a first memory block among the plurality of memory blocks, a first erase voltage is applied to the memory cells included in the first memory block; Determine the number of cutoff cells, each having a threshold voltage greater than or equal to the reference voltage, among the memory cells included in the first memory block. In response to the number of cutoff cells exceeding the reference number, a second erase voltage is obtained by adding the unit erase voltage to the first erase voltage; and In response to a second erase command for the first memory block, a second erase voltage is applied to the memory cells included in the first memory block.

12. The storage device according to claim 11, wherein, The memory controller is also configured to determine the number of cutoff cells, each having a threshold voltage greater than or equal to a first reference voltage, among the memory cells erased by the first erase voltage.

13. The storage device according to claim 11, wherein, The memory controller is also configured to: In response to a first programming command for a memory cell in an erased state included in a first page of a first memory block, a first programming voltage is applied to at least a portion of the memory cell in an erased state included in the first page via a first word line connected to the first page; and The number of cutoff cells, each having a threshold voltage greater than or equal to a second reference voltage, is determined among the at least portion of the memory cells in the erased state included in the first page, wherein the at least portion of the memory cells in the erased state included in the first page is programmed by a first programming voltage.

14. The storage device according to claim 13, wherein, The memory controller is also configured to: In response to the number of cutoff cells exceeding the reference number, a second programming voltage is obtained by subtracting the unit programming voltage from the first programming voltage; and In response to a second programming command for a memory cell included in the first page that is in an erased state, a second programming voltage is applied through the first word line.

15. The storage device according to any one of claims 11 to 14, wherein, The memory controller is also configured to store a voltage code corresponding to the second erase voltage in the memory device in response to obtaining the second erase voltage.

16. A method of operating a storage device, the method comprising: In response to a first erase command for a first memory block among a plurality of memory blocks, a first erase voltage is applied to the memory cells included in the first memory block; In response to a first programming command for a first page in a first memory block, a first programming voltage is applied to a memory cell included in the first page via a first word line connected to the first page. Determine the number of cutoff cells, each having a threshold voltage greater than or equal to the reference voltage, among the memory cells included in the first memory block. In response to the number of cutoff cells exceeding the reference number, a second programming voltage is obtained by subtracting the unit programming voltage from the first programming voltage; as well as In response to a second programming command for a memory cell included in the first page, a second programming voltage is applied via the first word line.

17. The method according to claim 16, wherein, The steps for determining the number of cutoff cells also include: Determine the number of cutoff cells in the memory cells that are in the erase state, each having a threshold voltage greater than or equal to a first reference voltage.

18. The method according to claim 16, wherein, The steps to determine the number of cutoff cells include: Determine the number of cutoff cells, each having a threshold voltage greater than or equal to a second reference voltage, among the memory cells programmed by the first programming voltage.

19. The method according to claim 18, further comprising: In response to the number of cutoff cells exceeding the reference number, a second erase voltage is obtained by adding the unit erase voltage to the first erase voltage; as well as In response to a second erase command for the first memory block, a second erase voltage is applied to the memory cells included in the first memory block.

20. The method according to claim 19, further comprising: In response to performing an erase operation on the first memory block a predetermined number of times using a second erase voltage, the number of cutoff cells, each having a threshold voltage greater than or equal to a reference voltage, among the memory cells included in the first memory block is determined. as well as In response to the number of cut-off cells in the memory cells erased by the second erase voltage exceeding a reference number, a third erase voltage is obtained by adding a unit erase voltage to the second erase voltage.

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