Method and apparatus for controlling a storage device

Abstract

A method and apparatus for controlling a storage device, including: reading a plurality of voltages from a target memory cell included in a non-volatile memory; obtaining a plurality of initial log likelihood ratio (LLR) values by providing the plurality of voltages to an initial threshold model; generating at least one adjusted model parameter based on the plurality of initial LLR values; adjusting the initial threshold model based on the at least one adjusted model parameter to obtain an adjusted threshold model; obtaining a plurality of uncalibrated LLR values by providing the plurality of voltages to the adjusted threshold model; calculating a calibration parameter based on the plurality of uncalibrated LLR values; modifying the adjusted threshold model based on the calibration parameter to obtain a calibrated adjusted threshold model; obtaining a final predicted LLR value by providing at least one of the plurality of voltages to the calibrated adjusted threshold model; and obtaining data based on the final predicted LLR value.

Description

Technical Field

[0001] This disclosure relates to a process for performing equalization and denoising in a storage device, and more specifically, to a self-adjusting machine learning-assisted voltage equalization process. Background Technology

[0002] Storage devices such as NAND flash memory allow storing a number of bits of data in each memory cell. A memory cell storing multiple bits of data is called a multilevel memory cell. A multilevel memory cell can divide the voltage range of the memory cell into several voltage states and can extract the data value written to the memory cell based on the voltage level of the memory cell.

[0003] Due to the physical characteristics of the device, the voltage of each cell may leak to its neighboring cells, resulting in a loss of voltage value in the cell. This phenomenon is known as inter-cell interference (ICI) and can be affected by the device's operating point, which can be determined by attributes such as programming / erase cycles or the amount of time elapsed since the device was manufactured.

[0004] Equalization, also known as denoising, can be used to compensate for noise encountered in the voltage read from memory cells. However, some equalization methods use models trained through an offline training process, which can be inconvenient, time-consuming, and resource-intensive. Summary of the Invention

[0005] Systems, apparatus, and methods for performing self-adjusting balancing in storage devices are provided.

[0006] Additional aspects will be set forth in part in the description which follows, and will become apparent in part from the description itself, or may be learned by practice of the embodiments presented.

[0007] According to one aspect of this disclosure, a method for reading data stored in a storage device includes: reading a plurality of voltages from target memory cells included in a non-volatile memory of the storage device; obtaining a plurality of initial log-likelihood ratio (LLR) values ​​by providing the plurality of voltages to the initial threshold model; generating at least one adjusted model parameter based on the plurality of initial LLR values; adjusting the initial threshold model based on the at least one adjusted model parameter to obtain an adjusted threshold model; obtaining a plurality of uncalibrated LLR values ​​by providing the plurality of voltages to the adjusted threshold model; calculating calibration parameters based on the plurality of uncalibrated LLR values; modifying the adjusted threshold model based on the calibration parameters to obtain a calibrated and adjusted threshold model; obtaining a final predicted LLR value by providing at least one of the plurality of voltages to the calibrated and adjusted threshold model; and obtaining data based on the final predicted LLR value.

[0008] According to one aspect of this disclosure, a storage device includes: a non-volatile memory including a plurality of sectors, the plurality of sectors including a first sector and a second sector; and a storage controller configured to: read a plurality of voltages from target memory cells included in the non-volatile memory; obtain a plurality of initial log-likelihood ratio (LLR) values ​​by providing the plurality of voltages to the initial threshold model; generate at least one adjusted model parameter based on the plurality of initial LLR values; adjust the initial threshold model based on the at least one adjusted model parameter to obtain an adjusted threshold model; obtain a plurality of uncalibrated LLR values ​​by providing the plurality of voltages to the adjusted threshold model; calculate calibration parameters based on the plurality of uncalibrated LLR values; modify the adjusted threshold model based on the calibration parameters to obtain a calibrated and adjusted threshold model; obtain a final predicted LLR value by providing at least one of the plurality of voltages to the calibrated and adjusted threshold model; and obtain data based on the final predicted LLR value.

[0009] According to one aspect of this disclosure, a storage controller for controlling a storage device includes: at least one processor configured to: read a plurality of voltages from target memory cells included in a non-volatile memory of the storage device; obtain a plurality of initial log-likelihood ratio (LLR) values ​​by providing the plurality of voltages to the initial threshold model; generate at least one adjusted model parameter based on the plurality of initial LLR values; adjust the initial threshold model based on the at least one adjusted model parameter to obtain an adjusted threshold model; obtain a plurality of uncalibrated LLR values ​​by providing the plurality of voltages to the adjusted threshold model; calculate calibration parameters based on the plurality of uncalibrated LLR values; modify the adjusted threshold model based on the calibration parameters to obtain a calibrated and adjusted threshold model; obtain a final predicted LLR value by providing at least one of the plurality of voltages to the calibrated and adjusted threshold model; and obtain data based on the final predicted LLR value. Attached Figure Description

[0010] The above and other aspects, features, and advantages of certain embodiments of this disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram of a computer system according to an embodiment;

[0012] Figure 2 This is a block diagram of a host storage system according to an embodiment;

[0013] Figure 3 This is a block diagram of a memory system according to an embodiment;

[0014] Figure 4 This is a block diagram of a memory device according to an embodiment;

[0015] Figure 5 This is a block diagram of a UFS system according to an embodiment;

[0016] Figures 6A to 6C This is a diagram of the shape factor of the UFS card according to an embodiment;

[0017] Figure 7 This is a block diagram of a memory system according to an embodiment;

[0018] Figure 8 This is a diagram of a 3D V-NAND structure applicable to a UFS device according to an embodiment;

[0019] Figure 9A This is a block diagram of a storage system according to an embodiment;

[0020] Figure 9B This is a block diagram of the equalization module according to an embodiment;

[0021] Figure 10 This is a diagram illustrating an example of a voltage threshold according to an embodiment;

[0022] Figure 11 This is a block diagram of the equalization module according to an embodiment;

[0023] Figures 12A to 12B This is a diagram illustrating an example of voltage distribution according to an embodiment;

[0024] Figures 13A to 13B This is a flowchart of a process for controlling a storage system according to an embodiment; and

[0025] Figure 14 This is a block diagram of a data center according to an embodiment. Detailed Implementation

[0026] Some aspects of this disclosure provide a self-adjusting equilibration scheme that can be used to self-adjust or self-train models for equilibration. This can reduce or eliminate the cumbersome or inconvenient offline training process for such models in embodiments.

[0027] Figure 1 This is a diagram of system 10000 that can be applied to the embodiments. Figure 1 The system 10000 can be, for example, a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet PC, a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 1 The system 10000 is not necessarily limited to mobile systems, and can be a PC, laptop, server, media player, or automotive device (e.g., navigation device).

[0028] refer to Figure 1System 10000 may include a main processor 1100, memory (e.g., 1200a and 1200b), and storage devices (e.g., 1300a and 1300b). Furthermore, system 10000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0029] The main processor 1100 can control all operations of the system 10000, and more specifically, can control the operations of other components included in the system 10000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor.

[0030] The main processor 1100 may include at least one CPU core 1110 and a controller 1120 configured to control memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some embodiments, the main processor 1100 may also include an accelerator 1130, which is dedicated circuitry for high-speed data operations, such as artificial intelligence (AI) data operations. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU) and may be implemented as a chip physically separate from other components of the main processor 1100.

[0031] Memory 1200a and 1200b can be used as the main storage device of system 10000. Although each of memory 1200a and 1200b may include volatile memory, such as static random access memory (SRAM) and / or dynamic RAM (DRAM), each of memory 1200a and 1200b may include non-volatile memory, such as flash memory, phase-change RAM (PRAM), and / or resistive RAM (RRAM). Memory 1200a and 1200b can be implemented in the same package as the main processor 1100.

[0032] Storage devices 1300a and 1300b can be used as non-volatile storage devices, configured to store data regardless of power supply, and have a larger storage capacity than memories 1200a and 1200b. Storage devices 1300a and 1300b may each include storage controllers (STRG CTRL) 1310a and 1310b and non-volatile memory (NVM) 1320a and 1320b, wherein the non-volatile memory (NVM) 1320a and 1320b are configured to store data under the control of storage controllers 1310a and 1310b. Although NVM 1320a and 1320b may include flash memory with a two-dimensional (2D) or three-dimensional (3D) V-NAND structure, embodiments are not limited thereto, and NVM 1320a and 1320b may include other types of NVM, such as PRAM and / or RRAM.

[0033] Storage devices 1300a and 1300b can be physically separate from the main processor 1100 and included in the system 10000, or implemented in the same package as the main processor 1100. Furthermore, storage devices 1300a and 1300b can be of SSD or memory card type and can be detachably combined with other components of the system 10000 via an interface (such as connection interface 1480 described below). Storage devices 1300a and 1300b can be devices applying standard protocols, such as Universal Flash Memory (UFS), eMMC, or Non-Volatile Memory Fast (NVMe), but are not limited to these.

[0034] Image capture device 1410 can capture still images or moving images. Image capture device 1410 may include a camera, video camera, and / or webcam.

[0035] User input device 1420 can receive various types of user input data from system 10000, and includes a touchpad, keypad, keyboard, mouse and / or microphone.

[0036] Sensor 1430 can detect various types of physical quantities obtained from outside the system 10000 and convert the detected physical quantities into electrical signals. Sensor 1430 may include temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors.

[0037] Communication device 1440 can send and receive signals between other devices outside system 10000 according to various communication protocols. Communication device 1440 may include an antenna, transceiver, and / or modem.

[0038] The display 1450 and speaker 1460 can be used as output devices, which are configured to output visual and auditory information to the user of system 10000, respectively.

[0039] The power supply device 1470 can appropriately convert the power provided by the battery embedded in the system 10000 and / or an external power source, and provide the converted power to each component of the system 10000.

[0040] The connection interface 1480 provides connectivity between the system 10000 and external devices that connect to the system 10000 and can send and receive data from the system 10000. The connection interface 1480 can be implemented using various interface schemes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, eMMC interface, UFS interface, Embedded UFS (eUFS) interface, and Compact Flash (CF) card interface.

[0041] Figure 2 This is a block diagram of a host storage system 10 according to an example embodiment.

[0042] Host storage system 10 may include host 100 and storage device 200. Furthermore, storage device 200 may include storage controller (STRG CTRL) 210 and NVM 220. According to an example embodiment, host 100 may include host controller 110 and host memory 120. Host memory 120 may be used as a buffer memory configured to temporarily store data to be sent to or received from storage device 200.

[0043] Storage device 200 may include storage media configured to store data in response to a request from host 100. As an example, storage device 200 may include at least one of an SSD, embedded memory, and removable external storage. When storage device 200 is an SSD, it may be an NVMe-compliant device. When storage device 200 is embedded memory or external storage, it may be a UFS-compliant or eMMC-compliant device. Each of host 100 and storage device 200 may generate and send data packets according to the adopted standard protocol.

[0044] When the NVM 220 of storage device 200 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, storage device 200 may include a variety of other types of NVM. For example, storage device 200 may include magnetic RAM (MRAM), spin-transfer torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FRAM), PRAM, RRAM, and a variety of other types of memory.

[0045] According to embodiments, the host controller 110 and host memory 120 can be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller 110 and host memory 120 can be integrated into the same semiconductor chip. As an example, the host controller 110 can be any one of a plurality of modules included in an application processor (AP). The AP can be implemented as a system-on-a-chip (SoC). Furthermore, the host memory 120 can be embedded memory included in the AP, or it can be an NVM or memory module located outside the AP.

[0046] The host controller 110 can manage operations that store data (e.g., write data) in the buffer of the host memory 120 in the NVM 220, or operations that store data (e.g., read data) in the buffer of the NVM 220.

[0047] Storage controller 210 may include host interface 211, memory interface 212, and CPU 213. Furthermore, storage controller 210 may also include a flash translation layer (FTL) 214, a packet manager (PCK MNG) 215, a buffer memory (BUFMEM) 216, an error correction code engine (ECC ENG) 217, and an advanced encryption standard engine (AES ENG) 218. Storage controller 210 may also include working memory in which the FTL 214 is loaded. CPU 213 can execute FTL 214 to control data write and read operations on NVM 220.

[0048] Host interface 211 can send and receive data packets to host 100. Data packets sent from host 100 to host interface 211 may include commands or data to be written to NVM 220. Data packets sent from host interface 211 to host 100 may include responses to commands or data read from NVM 220. Memory interface 212 can send data to NVM 220 to NVM 220 or receive data read from NVM 220. Memory interface 212 can be configured to comply with standard protocols such as Toggle or Open NAND Flash Interface (ONFI).

[0049] FTL 214 can perform various functions, such as address mapping, wear leveling, and garbage collection. Address mapping can be the process of translating logical addresses received from host 100 into physical addresses for storing data in NVM 220. Wear leveling can be a technique that prevents excessive corruption of specific blocks by allowing blocks in NVM 220 to be used uniformly. As an example, wear leveling can be implemented using firmware techniques that balance the erase counts of physical blocks. Garbage collection can be a technique that ensures available capacity in NVM 220 by erasing existing blocks after copying valid data from existing blocks to new blocks.

[0050] The packet manager 215 can generate packets according to the interface protocol agreed upon by the host 100, or parse various types of information from packets received from the host 100. Furthermore, the buffer memory 216 can temporarily store data to be written to or read from the NVM 220. Although the buffer memory 216 may be a component included in the storage controller 210, it can also be external to the storage controller 210.

[0051] ECC engine 217 can perform error detection and correction operations on read data read from NVM 220. More specifically, ECC engine 217 can generate parity bits for write data to be written to NVM 220, and the generated parity bits can be stored in NVM 220 along with the write data. During data reading from NVM 220, ECC engine 217 can correct errors in the read data by using the parity bits read from NVM 220 and the read data, and output the error-corrected read data.

[0052] The AES engine 218 can perform at least one of encryption and decryption operations on the data input to the storage controller 210 using a symmetric key algorithm.

[0053] Figure 3 This is a block diagram of a memory system 15 according to an embodiment. (See reference...) Figure 3 The memory system 15 may include a memory device 15 and a memory controller 16. The memory system 15 may support multiple channels CH1 to CHm, and the memory device 15 may be connected to the memory controller 16 through multiple channels CH1 to CHm. For example, the memory system 15 may be implemented as a storage device, such as an SSD.

[0054] Memory device 17 may include a plurality of NVM devices NVM11 to NVMmn. Each of the NVM devices NVM11 to NVMmn can be connected to one of a plurality of channels CH1 to CHm via a corresponding path. For example, NVM devices NVM11 to NVM1n can be connected to the first channel CH1 via paths W11 to W1n, and NVM devices NVM21 to NVM2n can be connected to the second channel CH2 via paths W21 to W2n. In an example embodiment, each of the NVM devices NVM11 to NVMmn can be implemented as any memory cell that can be operated according to individual commands from memory controller 16. For example, each of the NVM devices NVM11 to NVMmn can be implemented as a chip or a die, but embodiments of this disclosure are not limited thereto.

[0055] The memory controller 16 can send signals to and receive signals from the memory device 17 through multiple channels CH1 to CHm. For example, the memory controller 16 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 17 through channels CH1 to CHm, or receive data DATAa to DATAm from the memory device 17.

[0056] The memory controller 16 can select one of the NVM devices NVM11 to NVMmn connected to each of channels CH1 to CHm by using the corresponding channels among them, and send signals to and receive signals from the selected NVM device. For example, the memory controller 16 can select NVM11 from NVM11 to NVM1n connected to the first channel CH1. The memory controller 16 can send command CMDa, address ADDRa, and data DATAa to the selected NVM device NVM11 through the first channel CH1, or receive data DATAa from the selected NVM device NVM11.

[0057] The memory controller 16 can send signals to and receive signals from the memory device 17 in parallel through different channels. For example, the memory controller 16 can send the command CMDb to the memory device 17 through the second channel CH2, while simultaneously sending the command CMDa to the memory device 17 through the first channel CH1. For example, the memory controller 16 can receive data DATAb from the memory device 17 through the second channel CH2, while simultaneously receiving data DATAa from the memory device 17 through the first channel CH1.

[0058] The memory controller 16 can control all operations of the memory device 17. The memory controller 16 can send signals to channels CH1 to CHm and control each of the NVM devices NVM11 to NVMmn connected to channels CH1 to CHm. For example, the memory controller 16 can send the command CMDa and the address ADDRa to the first channel CH1 and control the selection of one of the NVM devices NVM11 to NVM1n.

[0059] Each of the NVM devices NVM11 to NVMmn can be operated under the control of the memory controller 16. For example, NVM11 can program data DATAa based on the command CMDa, address ADDRa, and data DATAa provided to the first channel CH1. For example, NVM21 can read data DATAb based on the command CMDb and address ADDb provided to the second channel CH2, and send the read data DATAb to the memory controller 16.

[0060] although Figure 3 An example is shown where memory device 17 communicates with memory controller 16 via m channels and includes n NVM devices corresponding to each channel, but the number of channels and the number of NVM devices connected to a channel can be varied.

[0061] Figure 4 This is a block diagram of a memory device 300 according to an example embodiment. (See reference...) Figure 4 The memory device 300 may include control logic circuitry 320, a memory cell array 330, a page buffer 340, a voltage generator 350, and a row decoder 360. The memory device 300 may also include... Figure 7 The memory interface circuit 310 is shown. In addition, the memory device 300 may also include column logic circuitry, a pre-decoder, a temperature sensor, a command decoder, and / or an address decoder.

[0062] The control logic circuit 320 can control all kinds of operations of the memory device 300. The control logic circuit 320 can output various control signals in response to commands CMD and / or addresses ADDR from the memory interface circuit 310. For example, the control logic circuit 320 can output voltage control signals CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0063] The memory cell array 330 may include multiple memory blocks BLK1 to BLKz (where z is a positive integer), and each memory block may include multiple memory cells. The memory cell array 330 can be connected to the page buffer 340 via the bit line BL, and to the line decoder 360 via the word line WL, the serial select line SSL, and the ground select line GSL.

[0064] In an example embodiment, the memory cell array 330 may include a 3D memory cell array comprising a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. The disclosures of U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235 and U.S. Patent Publication No. 2011 / 0233648 are incorporated herein by reference. In an example embodiment, the memory cell array 330 may include a 2D memory cell array comprising a plurality of NAND strings arranged along row and column directions.

[0065] Page buffer 340 may include multiple page buffers PB1 to PBn (where n is an integer greater than or equal to 3), each connected to a memory cell via multiple bit lines BL. Page buffer 340 can select at least one of the bit lines BL in response to column address Y-ADDR. Page buffer 340 can operate as a write driver or a sense amplifier depending on the operating mode. For example, during a programming operation, page buffer 340 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, page buffer 340 may sense the current or voltage of the selected bit line BL and sense the data stored in the memory cell.

[0066] Voltage generator 350 can generate various voltages for programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 350 can generate programming voltage, reading voltage, programming verification voltage, and erasing voltage as word line voltage VWL.

[0067] The row decoder 360 can select one of multiple word lines WL and one of multiple string select lines SSL in response to the row address X-ADDR. For example, the row decoder 360 can apply a programming voltage and a programming verification voltage to the selected word line WL during a programming operation and a read voltage to the selected word line WL during a read operation.

[0068] Figure 5This is a diagram of a UFS system 2000 according to an embodiment. The UFS system 2000 may be a system conforming to the UFS standard published by the Joint Electronic Equipment Committee (JEDEC) and includes a UFS host 2100, a UFS device 2200, and a UFS interface 2300. The above... Figure 1 The description of System 10000 is in relation to Figure 5 The following descriptions, to the extent that they do not conflict, may also be applied. Figure 5 The UFS system 2000.

[0069] refer to Figure 5 UFS host 2100 can connect to UFS device 2200 via UFS interface 2300. When Figure 1 When the main processor 1100 is an access point (AP), the UFS host 2100 can be implemented as part of the AP. The UFS host controller 2110 and host memory 2140 can be respectively connected to... Figure 1 The main processor 1100 corresponds to the controller 1120 and the memories 1200a and 1200b. The UFS device 2200 can be... Figure 1 The storage devices 1300a and 1300b correspond to each other, and the UFS device controller 2210 and NVM 2220 can be respectively connected to... Figure 1 The storage controllers 1310a and 1310b correspond to NVM 1320a and 1320b.

[0070] UFS host 2100 may include UFS host controller 2110, application 2120, UFS driver 2130, host memory 2140, and UFS interconnect (UIC) layer 2150. UFS device 2200 may include UFS device controller 2210, NVM 2220, storage interface 2230, device memory 2240, UIC layer 2250, and regulator 2260. NVM 2220 may include multiple memory cells 2221. While each of the memory cells 2221 may include V-NAND flash memory with a 2D or 3D structure, each of the memory cells 2221 may include another type of NVM, such as PRAM and / or RRAM. UFS device controller 2210 can be connected to NVM 2220 via storage interface 2230. Storage interface 2230 may be configured to conform to standard protocols such as Toggle or ONFI.

[0071] Application 2120 can refer to a program that wants to communicate with UFS device 2200 to use the functions of UFS device 2200. Application 2120 can send input / output requests (IOR) to UFS drive 2130 to perform input / output (I / O) operations on UFS device 2200. IOR can refer to data read requests, data storage (or write) requests, and / or data erase (or discard) requests, but is not limited to these.

[0072] UFS drive 2130 can manage UFS host controller 2110 through the UFS Host Controller Interface (UFS-HCI). UFS drive 2130 can convert the IOR generated by application 2120 into UFS commands defined by the UFS standard and send the UFS commands to UFS host controller 2110. One IOR can be converted into multiple UFS commands. Although UFS commands can be largely defined by the SCSI standard, UFS commands can be commands specific to the UFS standard.

[0073] UFS host controller 2110 can send UFS commands, translated by UFS drive 2130, to UIC layer 2250 of UFS device 2200 via UIC layer 2150 and UFS interface 2300. During UFS command transmission, UFS host register 2111 of UFS host controller 2110 can be used as a command queue (CQ).

[0074] The UIC layer 2150 on the UFS host 2100 side may include the Mobile Industrial Processor Interface (MIPI) M-PHY 2151 and MIPI UniPro 2152, and the UIC layer 2250 on the UFS device 2200 side may also include MIPI M-PHY 2251 and MIPI UniPro 2252.

[0075] UFS interface 2300 may include a line configured to transmit a reference clock signal REF_CLK, a line configured to transmit a hardware reset signal RESET_n of UFS device 2200, a line pair configured to transmit a pair of differential input signals DIN_t and DIN_c, and a line pair configured to transmit a pair of differential output signals DOUT_t and DOUT_c.

[0076] The frequency of the reference clock signal REF_CLK provided from the UFS host 2100 to the UFS device 2200 can be one of, but is not limited to, 19.2MHz, 26MHz, 38.4MHz, and 52MHz. The UFS host 2100 can change the frequency of the reference clock signal REF_CLK during operation, i.e., during data transmission / reception operations between the UFS host 2100 and the UFS device 2200. The UFS device 2200 can generate clock signals with various frequencies from the reference clock signal REF_CLK provided by the UFS host 2100 using a phase-locked loop (PLL). Furthermore, the UFS host 2100 can set the data rate between the UFS host 2100 and the UFS device 2200 by using the frequency of the reference clock signal REF_CLK. That is, the data rate can be determined based on the frequency of the reference clock signal REF_CLK.

[0077] The UFS interface 2300 can support multiple channels, each of which can be implemented as a pair of differential lines. For example, the UFS interface 2300 may include at least one receive channel and at least one transmit channel. Figure 5 In this configuration, a pair of lines configured to transmit a pair of differential input signals DIN_T and DIN_C can form a receiving channel, and a pair of lines configured to transmit a pair of differential output signals DOUT_T and DOUT_C ​​can form a transmitting channel. Although in Figure 5 The diagram shows one transmit channel and one receive channel, but the number of transmit channels and the number of receive channels can be changed.

[0078] The receive and transmit channels can transmit data based on a serial communication scheme. Due to the separate structure of the receive and transmit channels, full-duplex communication between the UFS host 2100 and the UFS device 2200 can be achieved. That is, while receiving data from the UFS host 2100 via the receive channel, the UFS device 2200 can send data to the UFS host 2100 via the transmit channel. Furthermore, control data (e.g., commands) from the UFS host 2100 to the UFS device 2200, as well as user data to be stored in or read from the NVM 2220 of the UFS device 2200, can be transmitted through the same channel. Accordingly, in addition to the pair of receive channels and the pair of transmit channels, it may not be necessary to provide a separate channel for data transmission between the UFS host 2100 and the UFS device 2200.

[0079] The UFS device controller 2210 of the UFS device 2200 can control all operations of the UFS device 2200. The UFS device controller 2210 can manage the NVM 2220 using logical units (LUs) 2211, which are logical data storage units. The number of LUs 2211 can be eight, but is not limited to this. The UFS device controller 2210 can include an FTL and translates logical data addresses (e.g., logical block addresses (LBAs)) received from the UFS host 2100 into physical data addresses (e.g., physical block addresses (PBAs)) using the address mapping information of the FTL. Logical blocks configured to store user data in the UFS system 2000 can have sizes within a predetermined range. For example, the minimum size of a logical block can be set to 4KB.

[0080] When a command from UFS host 2100 is applied to UFS device 2200 through UIC layer 2250, UFS device controller 2210 can respond to the command to perform an operation and send a completion response to UFS host 2100 when the operation is completed.

[0081] As an example, when UFS host 2100 intends to store user data in UFS device 2200, UFS host 2100 can send a data storage command to UFS device 2200. When it receives a response from UFS device 2200 indicating that UFS host 2100 is ready to receive user data (ready to transfer) (a 'ready to transfer' response), UFS host 2100 can send the user data to UFS device 2200. UFS device controller 2210 can temporarily store the received user data in device memory 2240 and store the user data temporarily stored in device memory 2240 in a selected location of NVM 2220 based on FTL address mapping information.

[0082] As another example, when UFS host 2100 intends to read user data stored in UFS device 2200, UFS host 2100 can send a data read command to UFS device 2200. Upon receiving the command, UFS device controller 2210 can read the user data from NVM 2220 based on the data read command and temporarily store the read user data in device memory 2240. During the read operation, UFS device controller 2210 can detect and correct errors in the read user data using an embedded ECC engine. More specifically, the ECC engine can generate parity bits for the write data to be written to NVM 2220, and the generated parity bits can be stored in NVM 2220 along with the write data. During data reading from NVM 2220, the ECC engine can correct errors in the read data using the parity bits read from NVM 2220 and the read data, and output the error-corrected read data.

[0083] Furthermore, the UFS device controller 2210 can send user data temporarily stored in the device memory 2240 to the UFS host 2100. Additionally, the UFS device controller 2210 may include an AES engine. The AES engine can perform at least one of encryption and decryption operations on the data sent to the UFS device controller 2210 using a symmetric key algorithm.

[0084] UFS host 2100 can sequentially store commands to be sent to UFS device 2200 in UFS host register 2111, which can be used as a common queue, and sequentially send the commands to UFS device 2200. In this case, even while a previously sent command is still being processed by UFS device 2200, that is, even before receiving notification that a previously sent command has been processed by UFS device 2200, UFS host 2100 can send the next command waiting in the CQ to UFS device 2200. Therefore, UFS device 2200 can also receive the next command from UFS host 2100 while processing a previously sent command. The maximum number of commands (or queue depth) that can be stored in the CQ can be, for example, 32. Furthermore, the CQ can be implemented as a circular queue, where the start and end of the command lines stored in the queue are indicated by head pointers and tail pointers.

[0085] Each of the plurality of memory cells 2221 may include a memory cell array and control circuitry configured to control the operation of the memory cell array. The memory cell array may include a 2D memory cell array or a 3D memory cell array. The memory cell array may include a plurality of memory cells. While each of the memory cells is configured to store 1 bit of information in a single-level cell (SLC), each of the memory cells may be a cell configured to store 2 or more bits of information, such as a multi-level cell (MLC), a three-level cell (TLC), and a four-level cell (QLC). A 3D memory cell array may include vertical NAND strings, wherein at least one memory cell is vertically oriented and situated on top of another memory cell.

[0086] Voltages VCC, VCCQ, and VCCQ2 can be applied as power supply voltages to the UFS device 2200. Voltage VCC can be the main power supply voltage of the UFS device 2200, ranging from 2.4V to 3.6V. Voltage VCCQ can be a low-voltage power supply voltage primarily supplying the UFS device controller 2210, ranging from 1.14V to 1.26V. Voltage VCCQ2 can be a power supply voltage primarily supplying the I / O interface (e.g., MIPI M-PHY 2251) with a voltage lower than VCC and higher than VCCQ, ranging from 1.7V to 1.95V. The power supply voltages can be supplied to the corresponding components of the UFS device 2200 via regulator 2260. Regulator 2260 can be implemented as a set of unit regulators, each connected to one of the aforementioned different power supply voltages.

[0087] As described above, embodiments may involve efficient BCH decoding with low error correction capability, which can correct t and (t+1) errors in the polarity codeword. As mentioned above, an error correction capability of t=2 can be used; however, embodiments are not limited to this. In embodiments, at least some of the polarity codewords (e.g., which may be stored in a storage device) can be decoded using a BCH decoder instead of a polarity decoder, thus improving overall throughput. In some embodiments, one or more polarity parity checks can be used to check or verify polarity frames and perform smart chase decoding, examples of which will be discussed in more detail below.

[0088] Figures 6A to 6C This is a diagram of the shape factor of a UFS card 4000. (Refer to...) Figure 5 When the described UFS device 2200 is implemented as a UFS card 4000, the appearance of the UFS card 4000 can be as follows: Figures 6A to 6C As shown.

[0089] Figure 6A This is a top view of a UFS card 4000 according to an example embodiment. Figure 6A This demonstrates that the UFS Card 4000 adopts a completely shark-shaped design. Figure 6A As an example, the UFS card 4000 can have the dimensions shown in Table 1 below.

[0090] [Table 1]

[0091]

[0092] Figure 6B This is a side view of a UFS card 4000 according to an example embodiment. Figure 6B As an example, the UFS card 4000 can have the dimensions shown in Table 2 below.

[0093] [Table 2]

[0094]

[0095] Figure 6C This is a bottom view of a UFS card 4000 according to an example embodiment. (Reference) Figure 6C Multiple pins for electrical contact with the UFS slot can be formed on the bottom surface of the UFS card 4000. The function of each pin is described below. Based on the symmetry between the top and bottom surfaces of the UFS card 4000, refer to... Figure 6A The information about the dimensions described in Table 1 (e.g., T1 to T5 and T9) can also be applied. Figure 6C The image shows a bottom view of the UFS card 4000.

[0096] Multiple pins for electrical connection with the UFS host can be formed on the bottom surface of the UFS card 4000. (Reference) Figure 6C The total number of pins can be 12. Each pin can have a rectangular shape, and the signal name corresponding to the pin can be as follows: Figure 6C As shown. For detailed information on each pin, please refer to Table 3 below and the references above. Figure 5 To understand the description.

[0097] [Table 3]

[0098]

[0099] Figure 7 This is a block diagram of a memory system 20 according to an embodiment. (See reference...) Figure 7 The memory system 20 may include a memory device 300 and a memory controller 400. The memory device 300 may correspond to one of the NVM devices NVM11 to NVMmn, which are based on... Figure 3One of the multiple channels CH1 to CHm communicates with the memory controller 400. The memory controller 400 can communicate with... Figure 3 The storage controller 210 corresponds to this.

[0100] The memory device 300 may include first pins P11 to eighth pins P18, memory interface circuitry 310, control logic circuitry 320, and memory cell array 330.

[0101] The memory interface circuit 310 can receive the chip enable signal nCE from the memory controller 400 via the first pin P11. In response to the chip enable signal nCE, the memory interface circuit 310 can send signals to and receive signals from the memory controller 400 via the second pin P12 to the eighth pin P18. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the memory interface circuit 310 can send signals to and receive signals from the memory controller 400 via the second pin P12 to the eighth pin P18.

[0102] The memory interface circuit 310 can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the memory controller 400 via pins P12 to P14. The memory interface circuit 310 can receive or send the data signal DQ from the memory controller 400 via pin P17. Command CMD, address ADDR, and data can be transmitted via the data signal DQ. For example, the data signal DQ can be transmitted via multiple data signal lines. In this case, pin P17 may include multiple pins corresponding to the multiple data signals DQ.

[0103] The memory interface circuit 310 can obtain the command CMD from the data signal DQ received in the enable portion (e.g., high-level state) of the command latch enable signal CLE based on the switching time of the write enable signal nWE. The memory interface circuit 310 can also obtain the address ADDR from the data signal DQ received in the enable portion (e.g., high-level state) of the address latch enable signal ALE based on the switching time of the write enable signal nWE.

[0104] In the example embodiment, the write enable signal nWE can be held statically (e.g., high or low) and toggled between high and low levels. For example, the write enable signal nWE can be toggled during the transmission of command CMD or address ADDR. Therefore, the memory interface circuit 310 can obtain command CMD or address ADDR based on the switching time of the write enable signal nWE.

[0105] The memory interface circuit 310 can receive the read enable signal nRE from the memory controller 400 via its fifth pin P15. The memory interface circuit 310 can receive the data strobe signal DQS from the memory controller 400 or send the data strobe signal DQS to the memory controller 400 via its sixth pin P16.

[0106] In the data (DATA) output operation of memory device 300, memory interface circuit 310 can receive a read enable signal nRE switched via pin 5 P15 before outputting data DATA. Memory interface circuit 310 can generate a data strobe signal DQS that switches based on the switching of the read enable signal nRE. For example, memory interface circuit 310 can generate data strobe signal DQS based on the switching start time of the read enable signal nRE, and the data strobe signal DQS starts switching after a predetermined delay (e.g., tDQSRE). Memory interface circuit 310 can send a data signal DQ including data DATA based on the switching time point of the data strobe signal DQS. Therefore, data DATA can be aligned with the switching time point of the data strobe signal DQS and sent to memory controller 400.

[0107] In the data (DATA) input operation of memory device 300, when a data signal DQ including data DATA is received from memory controller 400, memory interface circuit 310 can receive a data strobe signal DQS that switches along with the data DATA from memory controller 400. Memory interface circuit 310 can obtain data DATA from data signal DQ based on the switching time of data strobe signal DQS. For example, memory interface circuit 310 can sample data signal DQ and obtain data DATA at the rising and falling edges of data strobe signal DQS.

[0108] The memory interface circuit 310 can send a ready / busy output signal nR / B to the memory controller 400 via pin 8 P18. The memory interface circuit 310 can also send status information of the memory device 300 to the memory controller 400 via the ready / busy output signal nR / B. When the memory device 300 is in a busy state (i.e., when an operation is being performed in the memory device 300), the memory interface circuit 310 can send a ready / busy output signal nR / B indicating the busy state to the memory controller 400. When the memory device 300 is in a ready state (i.e., when no operation is being performed or completed in the memory device 300), the memory interface circuit 310 can send a ready / busy output signal nR / B indicating the ready state to the memory controller 400. For example, when the memory device 300 reads data DATA from the memory cell array 330 in response to a page read command, the memory interface circuit 310 can send a ready / busy output signal nR / B indicating the busy state (e.g., a low level) to the memory controller 400. For example, when memory device 300 programs data DATA into memory cell array 330 in response to a programming command, memory interface circuit 310 can send a ready / busy output signal nR / B indicating a busy state to memory controller 400.

[0109] Control logic circuit 320 can control all operations of memory device 300. Control logic circuit 320 can receive commands / addresses (CMD / ADDR) obtained from memory interface circuit 310. Control logic circuit 320 can generate control signals for controlling other components of memory device 300 in response to the received commands / addresses (CMD / ADDR). For example, control logic circuit 320 can generate various control signals for programming data DATA into or reading data DATA from memory cell array 330.

[0110] The memory cell array 330 can store data DATA obtained from the memory interface circuit 310 under the control of the control logic circuit 320. The memory cell array 330 can also output the stored data DATA to the memory interface circuit 310 under the control of the control logic circuit 320.

[0111] The memory cell array 330 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the inventive concept is not limited thereto, and the memory cells may be RRAM cells, FRAM cells, PRAM cells, thyristor RAM (TRAM) cells, or MRAM cells. In the following, embodiments in which the memory cells are NAND flash memory cells will be described primarily.

[0112] The memory controller 400 may include first pins P21 to eighth pins P28 and controller interface circuitry 410. First pins P21 to eighth pins P28 may correspond to first pins P11 to eighth pins P18 of the memory device 300, respectively.

[0113] The controller interface circuit 410 can send a chip enable signal nCE to the memory device 300 via the first pin P21. The controller interface circuit 410 can send and receive signals selected by the chip enable signal nCE to the memory device 300 via the second pin P22 to the eighth pin P28.

[0114] The controller interface circuit 410 can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device 300 via pins P22 to P24. The controller interface circuit 410 can send the data signal DQ to or receive the data signal DQ from the memory device 300 via pin P27.

[0115] The controller interface circuit 410 can send a data signal DQ, including a command CMD or address ADDR, along with a write enable signal nWE. The controller interface circuit 410 can also send the data signal DQ, including a command CMD, to the memory device 300 by sending a command latch enable signal CLE with an enabled state. Furthermore, the controller interface circuit 410 can send the data signal DQ, including the address ADDR, to the memory device 300 by sending an address latch enable signal ALE with an enabled state.

[0116] The controller interface circuit 410 can send the read enable signal nRE to the memory device 300 via the fifth pin P25. The controller interface circuit 410 can receive the data strobe signal DQS from the memory device 300 or send the data strobe signal DQS to the memory device 300 via the sixth pin P26.

[0117] In the data (DATA) output operation of memory device 300, controller interface circuit 410 can generate a switching read enable signal nRE and send the read enable signal nRE to memory device 300. For example, before outputting data DATA, controller interface circuit 410 can generate a read enable signal nRE that changes from a static state (e.g., high level or low level) to a switching state. Therefore, memory device 300 can generate a switching data strobe signal DQS based on the read enable signal nRE. Controller interface circuit 410 can receive a data signal DQ including data DATA and the switching data strobe signal DQS from memory device 300. Controller interface circuit 410 can obtain data DATA from data signal DQ based on the switching time of data strobe signal DQS.

[0118] During data (DATA) input operations of memory device 300, controller interface circuit 410 can generate a switching data strobe signal DQS. For example, before sending data DATA, controller interface circuit 410 can generate data strobe signal DQS, which changes from a static state (e.g., high or low) to a switched state. Controller interface circuit 410 can send a data signal DQ including data DATA to memory device 300 based on the switching time of data strobe signal DQS.

[0119] The controller interface circuit 410 can receive the ready / busy output signal nR / B from the memory device 300 via pin 8 P28. The controller interface circuit 410 can determine the status information of the memory device 300 based on the ready / busy output signal nR / B.

[0120] Figure 8 This is a diagram of a 3D V-NAND structure applicable to a UFS device according to an embodiment. When the storage module of a UFS device is implemented as 3D V-NAND flash memory, each of the plurality of memory blocks included in the storage module can be used... Figure 8 The equivalent circuit shown is illustrated.

[0121] Figure 8 The memory block BLKi shown can refer to a 3D memory block with a 3D structure formed on a substrate. For example, multiple NAND strings included in the memory block BLKi can be formed in a direction perpendicular to the substrate. In embodiments, the vertical direction can correspond to... Figure 8 The Z-axis direction is shown. In this embodiment, the vertical direction may be referred to as the column direction.

[0122] refer to Figure 8The memory block BLKi may include multiple memory NAND strings (e.g., NS11 to NS33) connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the memory NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells (e.g., MC1, MC2, ..., and MC8), and a ground select transistor GST. Figure 8 In the NAND strings NS11 to NS33, each is shown as including eight memory cells MC1, MC2, ... and MC8, but is not limited thereto.

[0123] The serial select transistor SST can be connected to its corresponding serial select lines SSL1, SSL2, and SSL3. Each of the memory cells MC1, MC2, ..., and MC8 can be connected to its corresponding gate line among the gate lines GTL1, GTL2, ..., and GTL8. Gate lines GTL1, GTL2, ..., and GTL8 can each correspond to a word line, and some of the gate lines GTL1, GTL2, ..., and GTL8 can correspond to dummy word lines. The ground select transistor GST can be connected to its corresponding ground select lines GSL1, GSL2, and GSL3. The serial select transistor SST can be connected to its corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0124] Word lines at the same level (e.g., the same line) (e.g., WL1) can be connected together, and ground select lines GSL1, GSL2, and GSL3 and string select lines SSL1, SSL2, and SSL3 can be separated from each other. Figure 8 The diagram illustrates a case where the memory block BLK is connected to eight gate lines GTL1, GTL2, ..., and GTL8, and three bit lines BL1, BL2, and BL3, but is not limited to this.

[0125] Figure 9A This is a block diagram of a storage system according to an embodiment. For example... Figure 9A As shown, the storage system 90A may include a host 100 and a storage device 900A, and the storage device 900A may include a storage controller 910A and an NVM 220. In an embodiment, the host 100 and NVM 220 may correspond to the host 100 and NVM 220 included in the host storage system 10 described above. Furthermore, the storage controller 910A may include a voltage detection module 920, an equalization module 930 (which may include multiple threshold models 931), and an ECC module 940. In an embodiment, the storage controller 910A may be similar to the storage controller 210 discussed above, and except... Figure 9AIn addition to the components shown, the storage controller 210 may also include one or more components, or components related to it. Figure 9A The component combinations shown are as follows. For example, in one embodiment, ECC module 940 may correspond to ECC engine 217, and voltage detection module may correspond to memory interface 212; however, the embodiment is not limited thereto.

[0126] In an embodiment, the equalization module 930 can be used to perform a correction operation during the read process to compensate for noise and reduce or eliminate errors caused by noise. In an embodiment, the correction operation can be referred to as a denoising operation or an equalization operation, and can be performed, for example, before applying ECC decoding. According to an embodiment, the equalization operation can be used to map the voltage read from the memory cell to... One of the possible values ​​or voltage levels, Each possible value or voltage level can correspond to All possible combinations of bits.

[0127] In some embodiments, multiple threshold models 931 can be used to decompose the equalization operation into multiple single-bit decision problems, considering only the case where the voltage read from the memory cell is close to a decision boundary between two voltage levels. In embodiments, the decision boundary can be referred to as a threshold or a voltage threshold. The memory cell corresponding to these cases can be referred to as a weak memory cell.

[0128] In an embodiment, each of the single-bit decision problems may correspond to a threshold model 931 associated with a specific threshold or decision boundary.

[0129] In an embodiment, the output of each threshold model 931 can be a single LLR value, which can be represented according to the following formula 1:

[0130] Formula 1

[0131] In Formula 1, It can represent a feature vector that includes features corresponding to memory cells, and It can represent having parameters The function.

[0132] For each unit Bit, possibly Each voltage level and A threshold model 931. In an embodiment, the equalization operation may include identifying weak memory cells, determining a corresponding threshold model 931 for each weak memory cell, and applying the threshold model 931 to the voltage read from the weak memory cell to obtain an LLR value representing the data read from the weak memory cell.

[0133] Figure 9B An example of an equalization module 930 according to an embodiment is shown. Figure 9B As shown, the equalization module 930 may include multiple threshold models 931 and a threshold selection module 932. In an embodiment, the multiple threshold models 931 may be, for example, machine learning models, such as neural network models.

[0134] In this embodiment, a neural network model can refer to a type of computer algorithm that learns specific patterns by iterating over known data without explicit programming. A neural network model can refer to a cognitive model that includes input nodes, hidden nodes, and output nodes. Nodes in a neural network model may have activation functions that calculate whether a node is activated based on the output of previous nodes. Training the system may involve providing input values ​​and modifying the edge weights and activation functions (algorithmically or randomly) until the result approximates a set of desired outputs.

[0135] An artificial neural network model can refer to a hardware or software component that includes multiple connected nodes (i.e., artificial neurons), which may roughly correspond to neurons in the human brain. Each connection or edge transmits a signal from one node to another (similar to physical synapses in the brain). When a node receives a signal, it processes it and then sends the processed signal to other connected nodes. In some embodiments, the signals between nodes include real numbers, and the output of each node is calculated as a function of the sum of its inputs. Each node and edge is associated with one or more node weights that determine how the signal is processed and sent. During training, these weights are adjusted to improve the accuracy of the results (e.g., by minimizing a loss function that corresponds to the difference between the current result and the target result). The weights of edges increase or decrease the strength of the signal transmitted between nodes. In some cases, nodes have a threshold below which no signal is transmitted. In some examples, nodes are aggregated into layers. Different layers perform different transformations on their inputs. The initial layer is called the input layer, and the last layer is called the output layer. In some cases, the signal passes through certain layers multiple times.

[0136] exist Figure 9B In the example, the equalization module 930 may include multiple threshold models 931, which may output soft symbol estimates based on input memory cell features 933. The input memory cell features may include voltages read from a target memory cell, voltages read from a first adjacent memory cell (e.g., a memory cell adjacent to the target memory cell in the upward column direction), voltages read from a second adjacent memory cell (e.g., a memory cell adjacent to the target memory cell in the downward column direction), and reference voltages (e.g., one or more hard-decision voltage thresholds). However, the embodiments are not limited thereto.

[0137] exist Figure 9B In the example, a sample (e.g., memory cell feature 933) can be processed by at least one of multiple threshold models 931, and the equalization module 930 can output a soft sign estimate, such as an LLR value. In an embodiment, one or more memory cell features 933 (e.g., target memory cell voltage and hard decision voltage threshold) can be provided to a threshold selection module 932, which can select a threshold model 931 to perform an equalization operation corresponding to the target memory cell.

[0138] Figure 10 An example of a voltage threshold according to an embodiment is shown. The example shown includes a level 1000, a hard-determining voltage threshold 1005, a strong-determining voltage range 1010, and a weak-determining voltage range 1015.

[0139] exist Figure 10 In the example, samples (e.g., read samples, detection voltage samples, etc.) can be processed by a threshold model 931 (e.g., a first threshold model 931-1, a second threshold model 931-2, a sixth threshold model 931-6, etc.), which can be selected from multiple threshold models 931 (e.g., by a threshold selection module 932). In the embodiment, the threshold model 931 for each sample is selected based on the characteristics of the sample (e.g., detection values, such as detection voltage) (e.g., by a threshold selection module 932). For example, the threshold model 931 can be selected based on the weak decision voltage range 1015 in which the sample is located (e.g., by a threshold selection module 932).

[0140] As mentioned above, in memory devices such as the NVM 220, each memory cell can use a single voltage to store data. Bit information (where, (This could be, for example, 3, 4, or 5). To read data stored in a memory device, the voltage of each memory cell can be measured, and the voltage level stored in the memory cell can be inferred (e.g., Figure 10 The indicated levels are 0, 1, ..., 7. Data stored in a memory cell, such as three bits stored in a TLC memory cell, can then be recovered.

[0141] In embodiments, a trade-off may need to be struck between the number of voltage levels and the reliability of the memory device. For example, the more bits per memory cell, the more data can be stored in the memory cell, and therefore the more data can be stored in the memory device. However, voltage levels representing different values ​​may be closer together because a greater number of distinguishable voltages can be used within the same dynamic range. Therefore, if noise is present when programming or reading a memory cell, it is more likely that a voltage with one level will be changed to another voltage representing a different level, resulting in errors when reading the memory cell. According to embodiments, various noise sources may exist in the memory device that can cause data to be read incorrectly from the memory cell, such as write noise, interference noise, device degradation noise, and read noise. Write noise can refer to variations caused by the write or programming process that may cause the voltage of the programmed memory cell to differ from the expected voltage. Interference noise can refer to voltage variations in memory cells caused by performing programming operations on different memory cells (e.g., adjacent memory cells). Device degradation noise can refer to variations in memory cell voltage that increase with the number of writes and reads to the memory cell. Read noise can refer to variations or interference in the memory cell voltage caused by the read process of reading the voltage from the memory cell.

[0142] In an embodiment, the presence of noise may cause the value of the read data to be ambiguous (e.g., the read voltage may correspond to a voltage level within a weak decision voltage range 1015 between two hard decision voltage thresholds 1005).

[0143] exist Figure 10 In the example, eight voltage levels 1000 are shown (e.g., level 0, level 1, ..., level 7). In the embodiment, the eight voltage levels 1000 can be used to represent three-bit data (e.g., data value "000" can correspond to level 0, data value "001" can correspond to level 1, and data value "111" can correspond to level 7). The hard decision threshold 1005 can be located between two adjacent levels 1000. Furthermore, the strong decision range 1010 and the weak decision range 1015 can be located within the dynamic range of level 0 to level 7. The strong decision range 1010 can refer to (e.g., via voltage detection module 920) the range in which the voltage level of the sample can be easily determined (e.g., a voltage range). The weak decision range 1015 can include the range around the hard decision threshold 1005, within which the level of the sample may not be easily determined. For example, the weak decision voltage range 1015 may include voltages immediately before and after the hard decision threshold 1005.

[0144] Typically, level 1000 can be distinguished based on a hard decision threshold 1005, and level 1000 can include portions of a strong decision range 1010 and a weak decision range 1015. Detected voltages determined to be within the strong decision range 1010 can be readily classified as the corresponding level 1000 (e.g., performed by voltage detection module 920 without using equalization module 930). Detected voltages within the weak decision voltage range 1015 can be used (e.g., performed by threshold selection module 932) to select a threshold model 931 that can be used to classify the detected voltage as one of two adjacent levels 1000. For example, as... Figure 10 As shown, the hard decision threshold 1005-b can be located between level 1000-a and level 1000-b, and the weak decision voltage range 1015 can include the range between level 1000-a and level 1000-b where the detected voltage can be further analyzed using the corresponding threshold model 931. In some embodiments, the weak decision voltage range 1015 may include the following range: within this range, the detected voltages of different channel output values ​​may overlap, and the threshold model 931 can be used to classify the detected voltages into one of two related adjacent values ​​to improve accuracy and reliability.

[0145] Accordingly, strong samples or samples within the strong decision range 1010 may have channel outputs estimated based on the voltage detection module 920 (e.g., without using the equalization module 930), since strong samples are likely within the strong decision range 1010 where the voltage detection module 920 has relatively high accuracy. However, weak samples or samples within the weak decision voltage range 1015 may have channel outputs estimated by a threshold model 931, which is selected based on equalization operations associated with the weak decision voltage range 1015, including the detected voltage.

[0146] For example, a first threshold model 931-1 can be trained on samples close to the hard decision threshold 0, a second threshold model 931-2 can be trained on samples close to the hard decision threshold 1, and so on (e.g., up to a sixth threshold model 931-6, which can be trained on samples close to the hard decision threshold 6). Each threshold model 931 can be trained to solve a binary classification task associated with the corresponding weak decision voltage range 1015. During inference, each sample can be passed through the corresponding threshold model in the threshold model 931.

[0147] In the example scenario (e.g., using voltage detection module 920), the voltage of each sample can be determined. Then, for samples whose voltages fall within the weak decision voltage range 1015, a hard decision can be determined based on the voltage level 1000 closest to the determined voltage. The features of the samples can then be provided to the corresponding thresholding model 931 (e.g., a thresholding model 931 trained and configured to perform a classification operation on the weak decision voltage range 1015 associated with the voltage of the samples determined by voltage detection module 920).

[0148] Although Figure 10 Examples of determining or estimating voltage levels are shown, but embodiments are not limited thereto, and in some embodiments, other determinations or estimates (e.g., similar to bits, soft symbols, etc.) may be used. In some embodiments, the number of threshold models 931 may be reduced, for example, by performing a classification operation on two weak decision ranges 1015 using a single threshold model 931. For example, a first threshold model 925-1 may be used for equalization operations associated with weak decision voltage ranges 1015 between levels 0 and 1 and between levels 1 and 2. As another example, a second threshold model 931-2 may be used for equalization operations associated with weak decision voltage ranges 1015 between levels 2 and 3 and between levels 3 and 4.

[0149] According to an embodiment, the multiple threshold models 931 may have two competing performance metrics: accuracy and complexity cost. Accuracy can refer to the error correction capability of the storage device 900, which includes the multiple threshold models 931. To improve the storage device 900's ability to correct errors such as bit flip errors, larger feature vectors and more parameters can be used for the multiple threshold models 931. Complexity cost can refer to the cost in terms of latency and / or gate count when using the multiple threshold models 931. A larger threshold model 931 may require more computation time (in firmware) or a larger gate count (in hardware) compared to a smaller threshold model 931. According to an embodiment, to improve the accuracy of the storage device 900, the complexity cost of the multiple threshold models 931 can be increased.

[0150] According to an embodiment, the multiple threshold models 931 may include a set of shallow machine learning models that can operate with low memory usage (e.g., less than the memory usage of ECC module 950) and low latency. Shallow models may refer to those models that prioritize reducing complexity costs over accuracy, and therefore can operate based on a relatively small number of parameters and features.

[0151] For example, in some embodiments, multiple threshold models 931 may have As a linear function. In the embodiment, as described above, the storage device 900A uses a... The balancing operation performed by multiple threshold models 931, which are linear functions, can be referred to as a linear balancing operation. In an embodiment, a linear balancing operation may refer to the balancing operation performed by the storage device 900A as described above. In an embodiment, It can have four input features, which can be, for example, the memory cell feature 933 discussed above.

[0152] Accordingly, for the total number of balancing operations Each threshold model 931 can have five parameters (e.g., four weights and bias terms corresponding to the input features). For example, the output of each threshold model 931 can be represented by Equation 2 below:

[0153] Formula 2

[0154] In formula 2 above, It can represent the first The first memory cell feature, It can represent the first The feature vector of the memory cell, and the vector of parameters of the threshold model 931, can be represented by the following formula 3:

[0155] Formula 3

[0156] In this embodiment, each threshold model 931 may be a shallow neural network, and each shallow neural network may be trained and configured for different hard-decision voltage thresholds 1005 or different weak-decision ranges 1015 for classification operations. However, the embodiments are not limited thereto; in some embodiments, other types of machine learning models, such as logistic regression models, decision trees, random forests, etc., may be used. In this embodiment, multiple threshold models 931 may be implemented using firmware, and therefore may be used by any NAND flash memory architecture.

[0157] One drawback of the above example is that it requires training a thresholding model 931 (e.g., determining and fixing functions). parameters According to an embodiment, the model can be trained offline based on data collected in a laboratory to simulate the end-of-life operating point (e.g., a situation where the error rate causes unbalanced data to fail to be decoded for ECC at a rate exceeding product specifications). For example, the number of decoding failures at the end-of-life operating point may be approximately once per million operations, but the embodiment is not limited to this.

[0158] However, setting simulated end-of-life operating points in the lab can be challenging. For example, this might involve applying thousands of program / erase cycles and exposing the chip to extremely high temperatures (e.g., exceeding 100°C). These lab-generated operating points can have several drawbacks. For instance, their creation can be cumbersome, making it difficult to incorporate the training process into mass production. Furthermore, significant differences may still exist between lab-generated operating points and real-world conditions.

[0159] Accordingly, embodiments can help address this training problem by avoiding it. For example, embodiments can allow the threshold model 931 to adjust its own parameters based on real input data without any offline training and / or labeled training data. Thus, embodiments can relate to systems, methods, and apparatus for performing a self-adjusting equalization process that allows storage devices to access the trained threshold model 931 without a time-consuming and arduous laboratory training process.

[0160] Figure 11 This is a block diagram of a storage system according to an embodiment. For example... Figure 11 As shown, storage system 90B may include host 100 and storage device 900B, and storage device 900B may include storage controller 910B and NVM 220. In embodiments, host 100 and NVM 220 may correspond to host 100 and NVM 220 included in the host storage system 10 and storage system 90A described above. Furthermore, storage controller 910B may include voltage detection module 920, equalization module 930 (which may include multiple threshold models 931), and ECC module 940. In embodiments, storage controller 910B may be similar to storage controllers 210 and 910A described above, and except... Figure 11 In addition to the components shown, it may also include one or more components of the storage controllers 210 and 910A, or related to them. Figure 11 The component combinations shown are as follows. For example, in one embodiment, the ECC module 940 may correspond to the ECC engine 217, and the voltage detection module may correspond to the memory interface 212; however, the embodiment is not limited thereto. Furthermore, the memory controller 910B may also include an adjustment module 950, which can be used to perform a self-adjustment process, also known as a self-adjustment equalization process, examples of which will be discussed in more detail below.

[0161] As mentioned above Figure 9AIn the discussion, storage device 900A may be limited to using offline versions of multiple threshold models 931, for example, multiple threshold models 931 having versions with parameters set according to a single operating point. In an embodiment, storage device 900B differs from storage device 900A in that the adjustment module 950 allows storage device 900B to adjust or train the parameters of multiple threshold models 931 during inference. This allows the equalization module 930 included in storage device 900B to implicitly use adjusted weights or parameters suitable for any operating point of the target memory cell without explicitly changing the architecture of the equalization module 930.

[0162] Typically, the input features or input data used by the threshold model 931 can be divided into three parts: the voltage read from the target memory cell (which can be called the target voltage). The corresponding hard-determining voltage threshold (which can be called the threshold voltage) The additional features include, for example, one or more of the following: adjacent cell voltages measured at hard-decision resolution, the position of the target cell along the word line, the word line index, and the number of programming / erase cycles in the word line history, but the embodiments are not limited thereto.

[0163] In some embodiments, features identical to the word line of the target memory cell (e.g., word line index or PE cycle number) may be ignored. Other additional features can be quantized into a relatively small number of groups, which may be referred to as sub-levels. According to embodiments, the number of sub-levels can be selected based on the word line size and available features. For example, in some embodiments, up to 256 sub-levels may be used to train the threshold model 931, but embodiments are not limited thereto.

[0164] Without the threshold model 931, it can be based on the target voltage. and threshold voltage The difference between the two values ​​is used to calculate the target voltage read from the target memory cell. The corresponding LLR value is shown in Formula 4 below:

[0165] Formula 4

[0166] In formula 4 above, This can represent a calibration constant or calibration parameter. The origin of this connection may stem from the binary additive white Gaussian noise (AWGN) channel model.

[0167] Figure 12AAn example voltage distribution corresponding to the AWGN channel model is shown. As illustrated in Figure 1210, the overall distribution 1211 may include two normal distributions (e.g., bell-shaped distributions). Based on the additional features discussed, the overall distribution 1211 may be decomposed into sub-distributions 1212 corresponding to sub-levels. For example, sub-distributions 1212 may include a first sub-distribution 1212A corresponding to a first sub-level, a second sub-distribution 1212B corresponding to a second sub-level, a third sub-distribution 1212C corresponding to a third sub-level, and a fourth sub-distribution 1212D corresponding to a fourth sub-level, but the embodiments are not limited thereto. Figure 12A As shown, each sub-distribution 1212 can have two bell-shaped curves, similar to the binary AWGN channel model. When the sub-distributions 1212 are combined, the overall distribution 1211 can be obtained.

[0168] According to the embodiment, the threshold model 931 can be recalculated according to the following formula 5:

[0169] Formula 5

[0170] In formula 5 above, The output of the threshold model 931, which corresponds to the hard-decision threshold, can be represented by the feature vector. It can represent an extra number of features that are not significant for word lines.

[0171] According to an embodiment, memory devices and storage devices (e.g., flash memory devices) (along with many other devices, such as communication devices) can use a scrambler to ensure that written data is uniformly distributed among symbols. This may mean that the probability of finding a true bit value of zero (“0”) in real data or benchmark truth data may be equal to the probability of finding a true bit value of one (“1”). Therefore, the expected value of the LLR value output by threshold model 931 is... It may be close to zero ("0"), as shown in Formula 6 below:

[0172] Formula 6

[0173] This could also be true for each sub-distribution 1212. The mean LLR value for each sub-level can be calculated separately. Furthermore, a search can be performed on the optimized model parameters to make all these parameters as close as possible to zero ("0"), as shown in Equation 7 below:

[0174] Formula 7

[0175] According to the embodiments, the mean squared error (MSE) can be used as the loss function for the search. When the number of sub-levels exceeds the number of model parameters, a trade-off between setting different mean LLR values ​​of the sub-levels to zero ("0") may produce a solution that is relatively close to a threshold model trained using labeled training data.

[0176] To solve optimization problems and obtain optimized model parameters, some implementations may use nonlinear optimization algorithms, such as Newton's method with trust region correction.

[0177] According to the embodiments, in the linear case, Equation 8 below may hold.

[0178] Formula 8

[0179] Formula 8 allows the optimization parameters to be expressed according to Formula 9 below. The analytical solution, for example, can correspond to linear regression:

[0180] Formula 9

[0181] Figure 12B An example of a voltage distribution that can be measured according to a limited sensing window, according to an embodiment, is shown. In the example discussed above, the mean LLR value can be calculated for each sub-level based on input data collected during runtime (e.g., based on voltage read during operation of storage device 900B). However, performing a self-adjustment process based on voltage measurements collected across the entire voltage distribution 1211 can be relatively time-consuming and resource-intensive. Therefore, according to an embodiment, the voltage used for the self-adjustment process can be measured within a limited window 1221 near a threshold voltage 1222, for example, as... Figure 12B As shown.

[0182] Since the sensing window 1221 may be finite, the relationship between the threshold model 931 and the optimization result may change. To compensate for this effect, a compensation constant can be introduced into the threshold model 931. As shown in Formula 10 below:

[0183] Formula 10

[0184] In formula 10 above, This can represent the optimized parameters, which can be obtained according to the following formula 11:

[0185] Formula 11

[0186] In some embodiments, Equation 10 may correspond to the optimization problem discussed above. Optimized parameters The parameters can be referred to as trained parameters or tuned parameters, and the threshold model 931 including these tuned parameters can be referred to as tuned threshold model 931 or self-tuning threshold model 931.

[0187] According to an embodiment, the relationship between the LLR value calculated by the adjusted threshold model 931 and the LLR value calculated by the initial threshold model 931 may include calibration parameters. In the embodiment, calibration parameters It can act as a general scaling factor, converting between voltage (which may have units, such as millivolts) and LLR values ​​(which may be unitless). Accurate conversion might require knowledge of the width of each sub-distribution 1212. However, the adjustment module 950 may not be able to obtain a measurement of this quantity based on the finite sensing window 1221. Therefore, the LLR value can be rescaled to a fixed width, which can be adjusted using scaling parameters. Configure it.

[0188] According to the embodiment, the compensation constant and scaling parameters One or two values ​​can be predetermined or set, for example, when manufacturing the storage device 900B, based on data obtained according to a mixture of operating point and chip type. According to an embodiment, the compensation constant is roughly fixed in this way. and / or scaling parameters It can produce robust results.

[0189] Based on the data used in the self-adjustment process (e.g., based on the obtained parameters used to obtain the adjusted parameters) The voltage), can be used to obtain multiple uncalibrated LLR values ​​according to Formula 12 below. :

[0190] Formula 12

[0191] In some embodiments, for example by providing data (e.g., voltage) to an adjusted threshold model 931, an uncalibrated LLR value can be obtained using an adjusted threshold model 931 corresponding to Equation 10 above. .

[0192] Based on uncalibrated LLR values The updated calibration parameters can be calculated using Formula 13 below. :

[0193] Formula 13

[0194] In Equation 13 above, std can represent the standard deviation. Accordingly, it can be based on the updated calibration parameters. Modify the adjusted threshold model 931 corresponding to Formula 10 above to obtain a calibrated threshold model 931. The calibrated threshold model 931 can be expressed according to the following Formula 14:

[0195] Formula 14

[0196] According to an embodiment, after obtaining a calibrated threshold model 931, it can be used to determine an LLR value based on the voltage read from a memory cell, thereby obtaining data stored in the storage device 900B. In some embodiments, the same voltage can be used to adjust an initial threshold model 931 to obtain an adjusted threshold model 931, and then the same voltage can be used to calibrate the adjusted threshold model 931 to obtain a calibrated threshold model 931. The same voltage is then applied to the calibrated threshold model 931 to obtain a final LLR value corresponding to the voltage, thereby obtaining or reconstructing data stored in a target memory cell from which the voltage is read. However, the embodiments are not limited to this.

[0197] In some embodiments, after obtaining the calibrated threshold model 931, the storage device 900B may read a new voltage to readjust and / or recalibrate the calibrated threshold model 931. For example, readjustment and / or recalibration may be performed each time a voltage is read, or it may be performed based on a trigger or event. For example, readjustment and / or recalibration may be performed based on determining at least one of the following: a predetermined time has elapsed, a predetermined number of operations (e.g., read and / or programming operations) have been performed, and a predetermined number of faults or errors (e.g., ECC faults) have been detected.

[0198] Figure 13A This is a flowchart of the process 1310 for controlling the storage device according to an embodiment. In some embodiments, Figure 13A One or more processing blocks can be executed by any of the aforementioned components, such as one or more storage devices 900A and 900B and any components included therein, such as storage controllers 910A and 910B, voltage detection module 920, equalization module 930, multiple threshold models 931, and ECC module 940. In an embodiment, process 1310 may correspond to the linear equalization operation described above.

[0199] like Figure 13A As shown, in operation 1311, process 1310 may include reading the voltage corresponding to the memory cell.

[0200] like Figure 13AFurther, in operation 1312, process 1310 may determine whether the voltage corresponds to a weak decision voltage range. In an embodiment, the weak decision voltage range may correspond to one or more of the aforementioned weak decision voltage ranges 1015. Based on determining that the voltage corresponds to a weak decision voltage range ("No" in operation 1312), process 1310 may include generating data corresponding to the memory cell based on a hard decision voltage threshold. Based on determining that the voltage corresponds to a weak decision voltage range ("Yes" in operation 1312), process 1310 may include selecting a threshold model from multiple threshold models based on the weak decision voltage range. In an embodiment, the multiple threshold models may correspond to multiple threshold models 931.

[0201] like Figure 13A As further shown, in operation 1315, process 1310 may include generating data by providing a voltage to the selected threshold model. For example, operation 1315 may include obtaining an LLR value output by the selected threshold model and generating or reconstructing data based on that LLR value, but the embodiments are not limited thereto.

[0202] Figure 13B This is a flowchart of a process 1320 for controlling a storage device according to an embodiment. In some embodiments, Figure 13B One or more process blocks can be executed by any of the aforementioned components, such as one or more storage devices 900B and any components included therein, such as storage controller 910B, voltage detection module 920, equalization module 930, multiple threshold models 931, ECC module 940, and adjustment module 950. In an embodiment, process 1320 may correspond to the self-adjusting process or self-adjusting equalization process described above.

[0203] like Figure 13B As shown, in operation 1321, process 1320 may include reading multiple voltages from target memory cells included in the non-volatile memory of the storage device.

[0204] like Figure 13B As further shown, in operation 1322, process 1320 may include obtaining multiple initial log-likelihood ratio (LLR) values ​​by providing multiple voltages to an initial threshold model. In an embodiment, the initial LLR values ​​may be obtained according to Formula 5.

[0205] like Figure 13B As further shown, in operation 1323, process 1320 may include generating at least one adjusted model parameter based on a plurality of initial LLR values. In an embodiment, the at least one adjusted model parameter may correspond to an optimization parameter. .

[0206] like Figure 13BAs further shown, in operation 1324, process 1320 may include adjusting the initial threshold model based on at least one adjusted model parameter to obtain an adjusted threshold model. In an embodiment, the adjusted threshold model may correspond to Formula 10.

[0207] like Figure 13B As further shown, in operation 1325, process 1320 may include obtaining multiple uncalibrated LLR values ​​by providing multiple voltages to an adjusted threshold model. In an embodiment, the multiple uncalibrated LLR values ​​may be obtained according to Formula 12.

[0208] like Figure 13B As further shown, in operation 1326, process 1320 may include calculating calibration parameters based on a plurality of uncalibrated LLR values. In an embodiment, the calibration parameters may correspond to updated calibration parameters. .

[0209] like Figure 13B As further shown, in operation 1327, process 1320 may include modifying the adjusted threshold model based on calibration parameters to obtain a calibrated threshold model. In an embodiment, the calibrated threshold model may correspond to Equation 14.

[0210] like Figure 13B As further shown, in operation 1328, process 1320 may include obtaining a final predicted LLR value by providing at least one of a plurality of voltages to a calibrated and adjusted threshold model. In an embodiment, the final predicted LLR value may be obtained according to Formula 14.

[0211] like Figure 13B As further shown, in operation 1329, process 1320 may include obtaining data based on the final predicted LLR value.

[0212] In an embodiment, multiple voltages may correspond to multiple sub-levels associated with a weak decision voltage range, the weak decision voltage range corresponding to an initial threshold model, and at least one adjusted model parameter may be generated based on multiple mean initial LLR values ​​corresponding to the multiple sub-levels.

[0213] In one embodiment, at least one adjusted model parameter can be generated by performing linear regression based on multiple initial LLR values ​​with means. In this embodiment, the linear regression can correspond to Equation 9.

[0214] In one embodiment, at least one adjusted model parameter may be obtained based on a loss function that includes the mean squared error.

[0215] In one embodiment, the calibration parameter may be calculated based on the standard deviation of multiple uncalibrated LLR values. In another embodiment, the calibration parameter may correspond to an updated calibration parameter and may be calculated according to Formula 13.

[0216] In this embodiment, multiple voltages can be read during a predetermined sensing window. In this embodiment, the predetermined sensing window may correspond to sensing window 1221.

[0217] In one embodiment, the calibrated threshold model may include a compensation constant corresponding to a predetermined sensing window. In another embodiment, the compensation constant may correspond to a compensation constant... .

[0218] In an embodiment, process 1320 may further include reading multiple new voltages from a target memory cell; and obtaining a recalibrated and readjusted threshold model based on the multiple new voltages.

[0219] In an embodiment, a recalibrated and readjusted threshold model is obtained based on determining at least one of the following: a predetermined amount of time has elapsed, a predetermined number of programming / erasing cycles have been executed, or a read error has been detected.

[0220] Although Figure 13A and Figure 13B Example blocks of processes 1310 and 1320 are shown, but in some implementations, processes 1310 and 1320 may include... Figure 13A and Figure 13B The blocks shown are compared to additional blocks, fewer blocks, different blocks, or blocks with different arrangements. Alternatively or additionally, the two or more blocks of processes 1310 and 1320 can be arranged or combined in any order, or executed in parallel.

[0221] Figure 14 This is a diagram of a data center 3000 that utilizes a memory device according to an embodiment.

[0222] refer to Figure 14 Data center 3000 can be a facility that collects various types of data and provides services, and can be referred to as a data storage center. Data center 3000 can be a system for operating search engines and databases, and can be a computing system used by a company (e.g., a bank) or government agency. Data center 3000 can include application servers 3100 to 3100n and storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m can be selected differently depending on the embodiment. The number of application servers 3100 to 3100n can differ from the number of storage servers 3200 to 3200m.

[0223] Application server 3100 or storage server 3200 may include at least one of processors 3110 and 3210 and memories 3120 and 3220. Storage server 3200 will now be described as an example. Processor 3210 may control all operations of storage server 3200, access memory 3220, and execute instructions and / or data loaded in memory 3220. Memory 3220 may be double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, and / or non-volatile DIMM (NVMDIMM). In some embodiments, the number of processors 3210 and memory 3220 included in storage server 3200 may be varied. In embodiments, processors 3210 and memory 3220 may provide processor-memory pairs. In embodiments, the number of processors 3210 may differ from the number of memories 3220. Processor 3210 may include a single-core processor or a multi-core processor. The above description of storage server 3200 can be similarly applied to application server 3100. In some embodiments, application server 3100 may not include storage device 3150. Storage server 3200 may include at least one storage device 3250. The number of storage devices 3250 included in storage server 3200 may be selected differently depending on the embodiment.

[0224] Application servers 3100 to 3100n can communicate with storage servers 3200 to 3200m via network 3300. Network 3300 can be implemented using Fibre Channel (FC) or Ethernet. In this case, FC can be used as the medium for relatively high-speed data transmission, employing high-performance and high-availability optical switches. Storage servers 3200 to 3200m can be provided as file storage, block storage, or object storage, depending on the access method of network 3300.

[0225] In one embodiment, network 3300 can be a storage-specific network, such as a storage area network (SAN). For example, the SAN can be an FC-SAN, which uses an FC network and is implemented according to the FC protocol (FCP). As another example, the SAN can be an Internet Protocol (IP)-SAN, using a Transmission Control Protocol (TCP / IP) network and implemented according to the SCSI over TCP / IP or Internet SCSI (iSCSI) protocol. In another embodiment, network 3300 can be a general-purpose network, such as a TCP / IP network. For example, network 3300 can be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fibre (NVMe-oF).

[0226] The following description will primarily focus on application server 3100 and storage server 3200. The description of application server 3100 can be applied to another application server 3100n, and the description of storage server 3200 can be applied to another storage server 3200m.

[0227] Application server 3100 can store data requested by users or clients to one of storage servers 3200 to 3200m via network 3300. Furthermore, application server 3100 can retrieve data requested by users or clients from one of storage servers 3200 to 3200m via network 3300. For example, application server 3100 can be implemented as a web server or a database management system (DBMS).

[0228] Application server 3100 can access memory 3120n or storage device 3150n included in another application server 3100n via network 3300. Alternatively, application server 3100 can access memory 3220 to 3220m or storage device 3250 to 3250m included in storage servers 3200 to 3200m via network 3300. Therefore, application server 3100 can perform various operations on data stored in application servers 3100 to 3100n and / or storage servers 3200 to 3200m. For example, application server 3100 can execute instructions to move or copy data between application servers 3100 to 3100n and / or storage servers 3200 to 3200m. In this scenario, data can be moved directly from storage devices 3250 to 3250m of storage servers 3200 to 3200m to storage devices 3120 to 3120n of application servers 3100 to 3100n, or via storage devices 3220 to 3220m of storage servers 3200 to 3200m to storage devices 3120 to 3120n of application servers 3100 to 3100n. Data moved over network 3300 can be encrypted for security or privacy purposes.

[0229] The description will now take storage server 3200 as an example. Interface 3254 provides physical connectivity between processor 3210 and controller (CTRL) 3251, and between network interface card (NIC) 3240 and controller 3251. For example, interface 3254 can be implemented using a direct-attach storage (DAS) scheme, where storage device 3250 is directly connected to a dedicated cable. For example, interface 3254 can be implemented using various interface schemes, such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB interface, SD card interface, MMC interface, eMMC interface, UFS interface, eUFS interface, and / or CF card interface.

[0230] Storage server 3200 may also include switch 3230 and NIC (Network Interconnect) 3240. Switch 3230 can selectively connect processor 3210 to storage device 3250 or selectively connect NIC 3240 to storage device 3250 through the control of processor 3210.

[0231] In an embodiment, NIC 3240 may include a network interface card and a network adapter. NIC 3240 can be connected to network 3300 via a wired interface, wireless interface, Bluetooth interface, or fiber optic interface. NIC 3240 may include internal memory, a digital signal processor (DSP), and a host bus interface, and is connected to processor 3210 and / or switch 3230 via the host bus interface. The host bus interface may be implemented as one of the examples of interface 3254 described above. In an embodiment, NIC 3240 may be integrated with at least one of processor 3210, switch 3230, and storage device 3250.

[0232] In storage servers 3200 to 3200m or application servers 3100 to 3100n, the processor can send commands to storage devices 3150 to 3150n and 3250 to 3250m or memories 3120 to 3120n and 3220 to 3220m and program or read data. In this case, the data can be data whose errors have been corrected by the ECC engine. The data can be data that has undergone Data Bus Inversion (DBI) or Data Masking (DM) operations and can include Cyclic Redundancy Check (CRC) information. The data can be encrypted for security or privacy purposes.

[0233] Storage devices 3150 to 3150n and 3250 to 3250m can send control signals and command / address signals to NAND flash memory devices 3252 to 3252m in response to read commands received from the processor. Therefore, when reading data from NAND flash memory devices 3252 to 3252m, a read enable (RE) signal can be input as a data output control signal, thereby outputting data to the DQ bus. The RE signal can be used to generate a data strobe signal DQS. Command and address signals can be latched into the page buffer based on the rising or falling edge of the write enable (WE) signal.

[0234] Controller 3251 can control all operations of storage device 3250. In embodiments, controller 3251 may include SRAM. Controller 3251 can write data to NAND flash memory device 3252 in response to a write command, or read data from NAND flash memory device 3252 in response to a read command. For example, write commands and / or read commands may be provided by processor 3210 of storage server 3200, processor 3210m of another storage server 3200m, or processors 3110 and 3110n of application servers 3100 and 3100n. DRAM 3253 may temporarily store (or buffer) data to be written to or read from NAND flash memory device 3252. In addition, DRAM 3253 may store metadata. Here, metadata may be user data or data generated by controller 3251 for managing NAND flash memory device 3252. Storage device 3250 may include a security element (SE) for security or privacy.

[0235] As is common in the art, embodiments are described and illustrated in the accompanying drawings in the form of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors, etc., they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware or as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of this invention, each block, unit, and / or module of the embodiments may be physically divided into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of this invention, the blocks, units, and / or modules of the embodiments may be physically combined into more complex blocks, units, and / or modules.

[0236] The various operations described above can be performed by any suitable device capable of performing the operations, such as various hardware and / or software components, circuits and / or modules.

[0237] Software may include an ordered list of executable instructions for implementing logical functions and may be embodied in any processor-readable medium used or in conjunction with an instruction execution system, apparatus, or device, such as a single-core or multi-core processor or a system including a processor.

[0238] The blocks or steps of the methods, algorithms, and functions described in conjunction with the embodiments disclosed herein can be implemented directly in hardware, implemented with software modules executed by a processor, or a combination of both. If implemented in software, these functions can be stored as one or more instructions or code on or through a tangible, non-transitory computer-readable medium. The software modules can reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0239] The foregoing is illustrative of certain embodiments and should not be construed as limiting them. Although some embodiments have been described, those skilled in the art will readily understand that various modifications can be made to the embodiments without departing from the scope thereof.

Claims

1. A method for reading data stored in a storage device, the method comprising: Multiple voltages are read from the target memory cells included in the non-volatile memory of the storage device; By providing the multiple voltages to the initial threshold model, multiple initial log-likelihood ratio (LLR) values ​​are obtained; Based on the multiple initial LLR values, at least one adjusted model parameter is generated; Based on the at least one adjusted model parameter, the initial threshold model is adjusted to obtain an adjusted threshold model; By providing the plurality of voltages to the adjusted threshold model, a plurality of uncalibrated LLR values ​​are obtained; Based on the multiple uncalibrated LLR values, calculate the calibration parameters; The adjusted threshold model is modified based on the calibration parameters to obtain a calibrated and adjusted threshold model; The final predicted LLR value is obtained by providing at least one of the plurality of voltages to the calibrated and adjusted threshold model; as well as Data is obtained based on the final predicted LLR value.

2. The method according to claim 1, wherein, The plurality of voltages correspond to a plurality of sub-levels associated with a weak decision voltage range, the weak decision voltage range corresponding to the initial threshold model, and The at least one adjusted model parameter is generated based on multiple mean initial LLR values ​​corresponding to the multiple sub-levels.

3. The method according to claim 2, wherein, The at least one adjusted model parameter is generated by performing linear regression based on the plurality of initial mean LLR values.

4. The method according to claim 1, wherein, The at least one adjusted model parameter is obtained based on a loss function that includes the mean squared error.

5. The method according to claim 1, wherein, The calibration parameters are calculated based on the standard deviation of the plurality of uncalibrated LLR values.

6. The method according to claim 1, wherein, The multiple voltages are read during a predetermined sensing window.

7. The method according to claim 6, wherein, The calibrated threshold model includes a compensation constant corresponding to the predetermined sensing window.

8. The method according to claim 1, further comprising: Read multiple new voltages from the target memory cell; as well as Based on the aforementioned new voltages, a recalibrated and readjusted threshold model is obtained.

9. The method according to claim 8, wherein, The recalibrated and readjusted threshold model is based on determining at least one of the following: a predetermined amount of time has elapsed, a predetermined number of programming / erase cycles have been executed, or a read error has been detected.

10. A storage device, comprising: The non-volatile memory includes multiple sectors, including a first sector and a second sector; as well as The storage controller is configured as follows: Multiple voltages are read from the target memory cells included in the non-volatile memory. By providing the multiple voltages to the initial threshold model, multiple initial log-likelihood ratio (LLR) values ​​are obtained. Based on the multiple initial LLR values, at least one adjusted model parameter is generated. The initial threshold model is adjusted based on the at least one adjusted model parameter to obtain an adjusted threshold model. By providing the plurality of voltages to the adjusted threshold model, a plurality of uncalibrated LLR values ​​are obtained. Based on the multiple uncalibrated LLR values, the calibration parameters are calculated. The adjusted threshold model is modified based on the calibration parameters to obtain a calibrated and adjusted threshold model. The final predicted LLR value is obtained by providing at least one of the plurality of voltages to the calibrated threshold model. Data is obtained based on the final predicted LLR value.

11. The storage device according to claim 10, wherein, The plurality of voltages correspond to a plurality of sub-levels associated with a weak decision voltage range, the weak decision voltage range corresponding to the initial threshold model, and The at least one adjusted model parameter is generated based on multiple mean initial LLR values ​​corresponding to the multiple sub-levels.

12. The storage device according to claim 11, wherein, The at least one adjusted model parameter is generated by performing linear regression based on the plurality of initial mean LLR values.

13. The storage device according to claim 10, wherein, The at least one adjusted model parameter is obtained based on a loss function that includes the mean squared error.

14. The storage device according to claim 10, wherein, The calibration parameters are calculated based on the standard deviation of the plurality of uncalibrated LLR values.

15. The storage device according to claim 10, wherein, The multiple voltages are read during a predetermined sensing window.

16. The storage device according to claim 15, wherein, The calibrated threshold model includes a compensation constant corresponding to the predetermined sensing window.

17. The storage device of claim 10, further comprising: Read multiple new voltages from the target memory cell; as well as Based on the aforementioned new voltages, a recalibrated and readjusted threshold model is obtained.

18. The storage device according to claim 17, wherein, The recalibrated and readjusted threshold model is based on determining at least one of the following: a predetermined amount of time has elapsed, a predetermined number of programming / erase cycles have been executed, or a read error has been detected.

19. A storage controller for controlling a storage device, the storage controller comprising: At least one processor is configured as follows: Multiple voltages are read from the target memory cells included in the non-volatile memory of the storage device; By providing the multiple voltages to the initial threshold model, multiple initial log-likelihood ratio (LLR) values ​​are obtained; Based on the multiple initial LLR values, at least one adjusted model parameter is generated; The initial threshold model is adjusted based on the at least one adjusted model parameter to obtain an adjusted threshold model; By providing the plurality of voltages to the adjusted threshold model, a plurality of uncalibrated LLR values ​​are obtained; Based on the multiple uncalibrated LLR values, calculate the calibration parameters; The adjusted threshold model is modified based on the calibration parameters to obtain a calibrated and adjusted threshold model; The final predicted LLR value is obtained by providing at least one of the plurality of voltages to the calibrated and adjusted threshold model; as well as Data is obtained based on the final predicted LLR value.

20. The storage controller according to claim 19, wherein, The plurality of voltages correspond to a plurality of sub-levels associated with a weak decision voltage range, the weak decision voltage range corresponding to the initial threshold model, and The at least one adjusted model parameter is generated based on multiple mean initial LLR values ​​corresponding to the multiple sub-levels.

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