SLC NAND array partition interference suppression method and system based on write heat map perception

Abstract

The application relates to the technical field of intelligent chips, and discloses an SLC NAND array partition interference suppression method and system based on write heat map sensing, which comprises the following steps: acquiring a write frequency to locate a write hot spot, extracting an evolution feature to predict a voltage disturbance, determining adjacent cells around the write hot spot according to the voltage disturbance, calculating the capacitance coupling strength of the two and mapping the capacitance coupling strength into a risk value, generating a programming control voltage for electrical control according to the risk value, judging data flipping through a reading verification operation, and finally executing secondary electrical control to block coupling diffusion, so that the single-layer cell flash array write interference is accurately perceived and actively suppressed in partitions, and the data retention reliability is improved. The method can realize a dynamic interference suppression mechanism of a write load.

Description

Technical Field

[0001] This invention relates to the field of smart chip technology, and in particular to a method and system for suppressing SLC NAND array partitioning interference based on write heatmap perception. Background Technology

[0002] Currently, single-layer cell flash memory arrays are important storage media in critical business scenarios such as smart chips and industrial control systems where data integrity requirements are extremely high. As the scale of data throughput increases, the write pressure they bear under long-term high-load operation is becoming more and more concentrated.

[0003] In one existing technology, programming interference suppression relies on a factory-fixed uniform programming strategy, including bootstrap programming suppression, programming in a recommended order, adjusting the pass voltage, and enhancing error correction codes, while distributing writes across multiple blocks through wear leveling. However, with process miniaturization, parasitic capacitive coupling between adjacent cells increases significantly. When hotspot blocks are repeatedly programmed, their charge changes generate continuous voltage disturbances to adjacent cells through parasitic capacitance, leading to threshold drift. Existing solutions employ indiscriminate uniform programming suppression and periodic refresh, failing to detect changes in real-time write frequency distribution or adjust electrical control of adjacent cells according to changes in the coupling state of hotspot neighborhoods. This results in data flipping in adjacent cells due to continuous hotspot programming interference, accumulating errors and exhausting error correction resources, thus affecting the data retention reliability of the flash array.

[0004] In summary, existing technologies lack a dynamic interference suppression mechanism. Summary of the Invention

[0005] This invention provides a method and system for suppressing SLC NAND array partition interference based on write heatmap awareness, so as to realize a dynamic interference suppression mechanism for memory writes.

[0006] In a first aspect, to address the aforementioned technical problems, this invention provides a method for suppressing SLCNAND array partition interference based on write heatmap awareness, comprising: Obtain the real-time write frequency and identify the highest frequency point as the write hotspot. Extract hotspot evolution features from the written hotspots and predict voltage shifts and outwardly radiated voltage disturbances; Based on the voltage disturbance, the adjacent cells around the write hotspot are determined, and the capacitive coupling strength between the write hotspot and the adjacent cells is calculated. If the capacitive coupling strength is greater than a preset coupling strength threshold, the threshold drift risk value is obtained through linear mapping. A programming control voltage is generated based on the threshold drift risk value, and the unit with the threshold drift risk value is electrically controlled by the programming control voltage to obtain the control state of the adjacent unit; After the adjacent unit enters the control state, a read verification operation is performed to determine whether the adjacent unit has experienced data flipping. If data flipping occurs in the adjacent units, the coupling diffusion is blocked by performing secondary electrical control on the adjacent units.

[0007] Secondly, the present invention provides an SLC NAND array partition interference suppression system based on write heatmap awareness, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described above.

[0008] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described above.

[0009] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention first obtains the real-time write frequency and establishes the write hotspot. This process abandons the lagging method of static division or fixed time window statistics in the prior art and realizes the real-time capture of the load distribution of the storage array. By monitoring the write operation in real time, the specific physical area currently bearing the maximum write pressure can be accurately located, thereby providing accurate spatial coordinates and data basis for subsequent fine interference management of the high-pressure area, solving the technical pain point of the prior art that cannot lock the high-frequency write area in real time.

[0010] (2) Based on the hotspots written, this invention further extracts evolution characteristics and predicts voltage shifts and outwardly radiated voltage disturbances. This mechanism breaks through the limitation of existing technologies that only passively handle interference after it occurs. By predicting the trend of electrical state changes caused by high-frequency writing in advance, the system can establish an early warning mechanism before voltage disturbances cause substantial physical damage, thus providing theoretical support for solving the problem that existing technologies lack the ability to predict in advance and can only remedy the situation afterward.

[0011] (3) This invention dynamically generates a programming control voltage based on the calculated threshold drift risk value, and uses this voltage to implement electrical control on the target unit, changing the strategy of using a uniform fixed programming voltage in the prior art. Through adaptive matching of risk value and control voltage, targeted suppression measures can be applied at key nodes of interference accumulation, thereby effectively curbing the abnormal drift trend of threshold voltage and solving the defect that the uniform control method in the prior art cannot cope with local high-risk environments.

[0012] (4) After detecting a data flip in an adjacent cell, the present invention blocks the coupling diffusion through secondary electrical control, which fills the gap in the prior art in blocking the interference chain reaction. When a cell that has experienced a data flip is detected, it can quickly intervene and implement compensatory electrical operations to prevent the local high-frequency write interference from continuing to spread to the surrounding healthy cells, thereby solving the shortcomings of the prior art in suppressing the interference diffusion chain. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the SLC NAND array partition interference suppression process based on write heatmap awareness provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the change in capacitive coupling strength between adjacent units provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the reading current superposition compensation effect provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the current distribution before and after compensation reading for secondary electrical control provided in an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Reference Figure 1 The first embodiment of the present invention provides a method for suppressing SLC NAND array partition interference based on write heatmap awareness, including the following steps: S11, obtain the real-time write frequency, and determine the highest frequency point as the write hotspot; S12, extract hotspot evolution features from the written hotspots, and predict voltage shift and outward radiated voltage disturbances; S13, determine the adjacent cells around the write hotspot based on the voltage disturbance, calculate the capacitive coupling strength between the write hotspot and the adjacent cells, and if the capacitive coupling strength is greater than a preset coupling strength threshold, obtain the threshold drift risk value through linear mapping; S14, Generate a programming control voltage based on the threshold drift risk value, and use the programming control voltage to electrically control the unit with the threshold drift risk value to obtain the control state of the adjacent unit; S15, after the adjacent unit enters the control state, a read verification operation is performed to determine whether the adjacent unit has experienced data flipping; S16, if the adjacent unit experiences data flipping, the coupling diffusion is blocked by performing secondary electrical control on the adjacent unit.

[0016] In step S11, it is necessary to obtain the real-time write frequency and determine the highest frequency point as the write hotspot, including: Obtain write operation records of storage blocks in a single-level cell flash array, and calculate the real-time write frequency of each block based on the write operation records. The real-time write frequencies are sorted, and the block address of the highest frequency is extracted as the write hotspot inside the single-layer cell flash array.

[0017] It should be noted that when acquiring write operation records of storage blocks in a single-level cell flash array and calculating the real-time write frequency of each block based on these records, the system uses a firmware-level input / output monitoring module to collect the write command issuance status of each storage block within a set time window, with a statistical period of 10 seconds. The module counts the number of write commands received for a specific block, such as the log block or data cache block. This number is used as input data, and the real-time write frequency of that block is updated by maintaining a fixed-length sliding window. For example, if a block is written 50 times in 10 seconds, this real-time statistics can accurately reflect the current load distribution of the storage array.

[0018] When ranking real-time write frequencies and extracting the block address of the highest frequency as the write hotspot within a single-layer cell flash array, the system first determines whether the real-time write frequency exceeds a preset frequency threshold. This preset threshold is determined statistically through accelerated aging tests on flash memory chips of the same batch. Specifically, during the test, increasing write pressure is applied to the sample chips, and the critical write frequency at which the bit error rate (BER) of the storage cell begins to rise significantly is recorded. The average of this critical value is used as the threshold. For example, if the test shows that the BER begins to rise when the write frequency reaches 30 times per 10 seconds, then the threshold is set to 30 times per 10 seconds. The statistically obtained 50 times is compared with 30 times. Since 50 is greater than 30, a comparison result exceeding the threshold is generated. Based on this comparison result, the corresponding block address is extracted, and the flash translation layer is used to map the logical address to the physical block address, thereby obtaining candidate hotspot markers. This mapping process ensures the physical accuracy of hotspot location and avoids logical-level misjudgments. If the real-time write frequency of all storage blocks is less than or equal to the preset frequency threshold, it is determined that there is no write hotspot in the current array. The system maintains the original unified programming strategy while continuously monitoring the real-time write frequency.

[0019] Next, the real-time write frequencies corresponding to all candidate hotspot markers are arranged in descending order to find the extreme node with the greatest current write pressure. The frequency of all blocks that have obtained candidate hotspot markers is used as input, and the magnitude of each frequency value is compared one by one. The frequency sequence arranged from high to low is output. The candidate hotspot marker at the top of this descending order is extracted to determine the write hotspot inside the single-layer cell flash array. For example, in a sequence containing multiple candidate hotspots, the highest frequency is 80 times every 10 seconds. Then the physical block corresponding to these 80 times is the write hotspot.

[0020] In step S12, hotspot evolution features are extracted from the written hotspots, and voltage offsets and outwardly radiated voltage disturbances are predicted, including: Based on the programming timestamps of the written hotspots, the historical programming frequency is statistically analyzed, and a frequency time series is constructed. Hotspot evolution features were obtained by exponentially smoothing the frequency time series. Based on the hotspot evolution characteristics, the charge trapping state is obtained, the threshold voltage drift is determined, and mapped to a voltage offset. The coupling strength of each node in the space is determined based on the voltage offset, and a spatial distribution matrix is ​​constructed. The voltage disturbance radiated outward from the hot spot is obtained by superimposing the contributions of each node in the spatial distribution matrix.

[0021] It should be noted that when the system calculates the historical programming frequency and constructs a frequency time series based on the programming timestamps of the write hotspots, it extracts the times of all programming operations that occurred in the physical block within a set historical period for the identified write hotspots in the single-layer cell flash array. For example, it collects the programming timestamps from the past 60 minutes, uses 5-minute intervals as a fixed time granularity, and counts the number of programming instructions executed in each 5-minute interval. The system then uses the integer values ​​obtained from the statistics, such as 45 times, 50 times, 62 times, etc., arranged in chronological order, as input data to construct a frequency time series reflecting the write pressure of the block.

[0022] When extracting hotspot evolution features from the frequency time series through exponential smoothing, the system uses the constructed frequency time series as input and performs calculations using exponential smoothing. A smoothing coefficient is set to perform a weighted average of historical frequency data, with more recent frequency data assigned higher weights and earlier frequency data having exponentially decreasing weights. This effectively captures short-term trend changes in write frequencies without complex calculations. For example, when the smoothing coefficient is set to 0.3, the smoothed value at the current moment is calculated by proportionally weighting the smoothed value at the previous moment and the current observation value. This allows for rapid response to sudden writes and filtering of random fluctuations, resulting in higher computational efficiency and easier deployment at the firmware level.

[0023] The smoothing coefficient was determined through backtesting of historical write frequency data. Specifically, during the development phase, a segment of historical frequency data covering a typical business cycle was selected, and exponential smoothing was performed using different smoothing coefficients. The smoothing results of each coefficient were compared with the actual observed values, and the root mean square value of the prediction error was calculated. The smoothing coefficient that minimizes the root mean square error was selected as the preset value. For example, test results showed that the prediction error was minimized when the smoothing coefficient was 0.3, so 0.3 was set as the smoothing coefficient.

[0024] After completing the exponential smoothing calculation, the system extracts hotspot evolution features from the smoothing results: First, it records the smoothed value at the current moment as the first feature, representing the current write pressure level; then, it calculates the difference between the current smoothed value and the smoothed value at the previous moment as the second feature, representing the trend of write pressure changes; finally, it calculates the absolute deviation between the current observation value and the current smoothed value as the third feature, representing the degree of fluctuation in write behavior. These three values ​​are then concatenated sequentially into a one-dimensional array to obtain the hotspot evolution feature vector for that block.

[0025] Next, the type of write hotspot is determined based on the numerical distribution characteristics of the hotspot evolution characteristics. If the second characteristic (difference) of the hotspot evolution characteristics is greater than the preset rate of change threshold and the third characteristic (absolute deviation) is greater than the preset fluctuation threshold, it is determined to be a sudden write hotspot, which indicates that the write load increases sharply in a short period of time; otherwise, it is determined to be a periodic continuous write hotspot, which indicates that the write load exhibits regular and stable fluctuations.

[0026] The preset rate of change threshold and the preset fluctuation threshold are determined by statistical analysis of the variance of the feature vectors of multiple known types of write hotspot samples. Specifically, during the development phase, historical write frequency data covering both burst and periodic modes are collected, and the difference and absolute deviation in their feature vectors are extracted to obtain the distribution sets of the two types of samples in two dimensions. A binary search method is used to traverse and search the boundary region of the set, and the variance value that can achieve the highest classification accuracy and the lowest misclassification rate is selected as the fluctuation threshold.

[0027] When determining the threshold voltage drift based on the hotspot evolution characteristics and mapping it to voltage offset, the system analyzes the electron tunneling stress induced in the floating gate oxide layer by the identified burst-type or periodic hotspot evolution characteristics in a single-layer cell flash memory array. Based on the correspondence between the hotspot evolution characteristics and the electron capture density in the floating gate oxide layer, the system calculates and outputs the charge capture state data within the current physical block's insulating layer through the physical tunneling effect, such as the electron density captured per unit area. Based on this charge capture state, the threshold voltage drift of the memory cell is calculated according to the electrostatic potential energy conversion principle. The specific calculation formula is as follows: Where q represents the charge of a single electron. This represents the electron density trapped per unit area. This represents the capacitance of the oxide layer per unit area. For example, when the trapped electron density reaches... Oxide layer capacitance is The threshold voltage drift was calculated to be 0.5 volts. Then, a linear scaling was performed on this 0.5 volt threshold voltage drift to obtain a voltage offset used to characterize the degree of local electric field distortion.

[0028] The coupling strength of each node in the space is determined based on the voltage offset, and a spatial distribution matrix is ​​constructed. Then, based on the contribution of each node in the matrix, the voltage disturbance radiating outward from the write hotspot is obtained. The system uses the acquired voltage offset data combined with the physical topology of the flash array to track the propagation trajectory of the electric field distortion along the word line and bit line directions, centered on the write hotspot, to determine the disturbance propagation path. Along the determined disturbance propagation path, the parasitic capacitance coupling effect strength of adjacent memory cells is calculated using the parallel plate capacitance formula combined with the edge field correction coefficient. Specifically, the word line spacing is read from the flash memory manufacturing process parameter table. Insulation layer thickness and the dielectric constant of the insulating layer Using the parallel plate capacitance formula Calculate the basic capacitance value, where Let A be the vacuum dielectric constant, A be the overlap area between the word line and the control gate of the adjacent cell, and d be the vertical distance between the two plates (i.e., the insulation layer thickness). Next, the basic capacitance value is multiplied by the edge field correction factor. , The value ranges from 1.2 to 1.5, which is used to compensate for the electric field edge effect caused by the finite size conductor, thereby obtaining the coupling strength value of each node. The calculated coupling strength values ​​of each node are arranged according to the physical space coordinates to generate a 5x5 spatial distribution matrix. The value at the center of the matrix is ​​the largest and shows a gradient decay distribution pattern along the word line and bit line directions.

[0029] It should be noted that the edge field correction coefficient The value of is determined based on the ratio of word line spacing to insulation layer thickness: when the word line spacing is less than twice the insulation layer thickness, the edge field effect is significant. A value of 1.4 to 1.5 is used; when the word line spacing is greater than 5 times the insulation layer thickness, the edge field effect is weaker. Take a value between 1.2 and 1.3; when it falls between these two values, The values ​​are obtained through linear interpolation. Specific values ​​can be calibrated using TCAD simulation against actual device measurement results before being finalized.

[0030] The generated spatial distribution matrix is ​​numerically calculated based on the principle of electrostatic field superposition. Specifically, the coupling strength values ​​of each node in the matrix are used as equivalent sources of point charges. The electric field contribution generated by each source point at the target location is calculated according to the inverse Coulomb square law. All contributions are vector-superimposed to obtain a two-dimensional continuous distribution of electric field disturbance in the silicon substrate, i.e., the radiation intensity distribution. Subsequently, based on this radiation intensity distribution, the electric field intensity value at the target location is read. Combined with the physical distance between this location and the write hotspot, the voltage disturbance value is calculated through the integral relationship between potential and electric field intensity. For example, by analyzing the radiation intensity distribution, the voltage disturbance radiated outward from the write hotspot is determined to be 0.15 volts. This voltage disturbance data reflects the amount of cross-coupling interference caused by the central hotspot to the surrounding adjacent memory cells during programming operations.

[0031] In step S13, neighboring cells around the write hotspot are determined based on the voltage disturbance, and the capacitive coupling strength between the write hotspot and the neighboring cells is calculated. If the capacitive coupling strength is greater than a preset coupling strength threshold, a threshold drift risk value is obtained through linear mapping, including: Based on the spatial influence range of the voltage disturbance, adjacent cells are determined, and the physical distance between the adjacent cells and the write hotspot is calculated. Based on the physical distance, the parasitic capacitance value is obtained by calling the pre-stored parasitic parameter lookup table, and the parasitic capacitance value is substituted into the capacitor voltage divider formula to calculate the capacitive coupling strength between the write hotspot and the adjacent cell. The programming interference amount is calculated based on the capacitive coupling strength. If the capacitive coupling strength is greater than a preset coupling strength threshold, the programming interference amount is calculated using a preset first mapping function to obtain a threshold drift risk value; otherwise, the threshold drift risk value is calculated using a preset second linear mapping function.

[0032] It should be noted that when determining adjacent cells based on the spatial influence range of the voltage disturbance, calculating the physical distance between the adjacent cells and the write hotspot, and constructing a feature vector, the system first uses the write hotspot as the center and, based on the attenuation curves of the voltage disturbance in the word line and bit line directions, determines the critical distance at which the disturbance amplitude drops to a preset threshold. A circular or elliptical evaluation area is then delineated with this distance as the radius. Subsequently, all memory cells within this area are traversed and marked as adjacent cells affected by the disturbance. Next, a three-dimensional coordinate system is established with the intersection of the word line and bit line where the write hotspot is located as the origin. The relative coordinates of each adjacent cell in this coordinate system are read from the physical address mapping table of the flash memory translation layer. Finally, based on the three-dimensional coordinates of the write hotspot and adjacent cells, the Euclidean distance between them in the insulating medium is calculated through coordinate analysis to obtain the physical distance value.

[0033] Based on the physical distance, the system retrieves the parasitic capacitance value from a pre-stored parasitic parameter lookup table. Substituting this parasitic capacitance value into the capacitance divider formula, the system calculates the capacitive coupling strength between the write hotspot and the adjacent cell. First, the calculated physical distance is converted into a relative position offset in the word line and bit line directions. For example, if the adjacent cell is located at the first cell position along the bit line direction of the write hotspot, the word line spacing is 0, and the bit line spacing is 1 times the process feature size. Then, using this relative position offset as an index, the system locates the corresponding entry in the parasitic parameter lookup table pre-installed in the flash controller firmware area and reads the parasitic capacitance value stored in that entry, in femtofarads (FF). For example, when the adjacent cell is adjacent to the write hotspot along the bit line direction (spacing is F, where F is the process feature size), the parasitic capacitance value retrieved from the lookup table is 5fF. When adjacent along the word line direction, the parasitic capacitance value is 3 fF. The parasitic parameter lookup table is pre-extracted and solidified during the chip design phase based on the layout structure and process parameters of the flash memory array through electromagnetic simulation. The table directly stores the corresponding parasitic capacitance values ​​using the relative positions of adjacent cells and write hotspots as indices. For positions not on the lookup table grid nodes, the parasitic capacitance value is calculated using a bilinear interpolation algorithm.

[0034] Based on the obtained parasitic capacitance value and voltage disturbance, according to the capacitance voltage divider formula... The capacitive coupling strength is calculated. This indicates the voltage disturbance amplitude caused by parasitic capacitive coupling between adjacent units, i.e., the capacitive coupling strength. This represents the parasitic capacitance value between the write hotspot and the adjacent cell; The total capacitance contained in the adjacent cell itself includes the sum of all parasitic components such as floating gate capacitance, control gate capacitance, and tunnel oxide capacitance, and is given by the process parameter table provided during the chip design stage; ΔVa represents the voltage disturbance generated by the write hotspot obtained in S12 during the programming process.

[0035] Next, based on the capacitive coupling strength and the sensitivity coefficient of the unit threshold voltage to coupling interference, the programming interference is directly calculated. Specifically, the programming interference... ,in This represents the voltage disturbance amplitude caused by parasitic capacitive coupling between adjacent cells, i.e., the capacitive coupling strength. K is the interference sensitivity correction coefficient (determined by process deviations and cell location, typically between 0.8 and 1.2, calibrated at the wafer level and stored in a lookup table). For example, when the capacitive coupling strength is 150mV and the correction coefficient is 1.0, the programming interference is ΔVd = 1.0 × 150mV = 150mV. In cases with multiple adjacent interference sources, the programming interference is the algebraic sum of the contributions from each source. The effects of temperature and erase / write cycles on interference sensitivity are reflected by the temperature factor and wear factor of the correction coefficient K, both read from a pre-stored calibration parameter table.

[0036] If the capacitive coupling strength is greater than a preset coupling strength threshold, the programming interference is used to calculate a threshold drift risk value through a preset first mapping function; otherwise, a preset second linear mapping function is used to calculate the threshold drift risk value. A fixed coupling strength threshold is preset. The currently acquired capacitive coupling strength is compared with this threshold, and the programming interference is used to determine the risk level. For example, if the preset coupling strength threshold is set to 20 picofarads, and the actual capacitive coupling strength is 21 picofarads, it is determined to be greater than the preset threshold. In this case, the 150 mV programming interference is substituted into the linear mapping function to calculate a threshold drift risk value of 85. The specific form of this linear mapping function is as follows: .

[0037] Where R represents the threshold drift risk value. The programming interference amount is represented by α and β, which are preset linear coefficients. The values ​​of α and β are determined by linear regression fitting of experimental data of adjacent units under multiple sets of different programming interference amounts. Specifically, under laboratory conditions, multiple sample particles are selected, and the critical risk score when adjacent units just happen to flip data under different programming interference amounts is measured. A univariate linear regression is performed with programming interference amount as independent variable and critical risk score as dependent variable. The slope obtained from the regression is α, and the intercept is β. For example, if the regression yields α of 0.5 and β of 10, then when the programming interference amount is 150 millivolts, the calculated risk value is 85.

[0038] If the actual capacitive coupling strength is 18 picofarads, and it is determined to be less than the preset threshold, then the programmed interference is substituted into the second linear mapping function to calculate the second threshold drift risk value as 30. The form of the second linear mapping function is as follows: The values ​​of α' and β' are also determined experimentally. However, since the interference effect is weaker in low coupling intensity scenarios, their regression coefficients are different from those in high coupling intensity scenarios. For example, the regression yields α' as 0.2 and β' as 0. Therefore, when the programmed interference is 150 millivolts, the calculated risk value is 30.

[0039] The preset coupling strength threshold was determined statistically after conducting accelerated aging tests on multiple batches of single-layer cell flash memory chips of the same specification. Specifically, during the test, incremental programming pressure was applied to the sample chips and the starting point of threshold drift in adjacent cells was monitored. The average value of the parasitic capacitance coupling strength at which the threshold voltage of adjacent cells first showed a non-negligible shift was used as the threshold. For example, the statistical results showed that when the coupling strength reached 20 picofarads, the bit error rate of adjacent cells began to rise significantly. Therefore, 20 picofarads was set as the preset coupling strength threshold.

[0040] For example, Figure 2 This diagram illustrates the variation in capacitive coupling strength between adjacent cells. As write hotspots migrate and write pressure accumulates, the capacitive coupling strength exhibits phased changes. Adjacent cells in the bit-line direction exceed the coupling strength threshold at certain times, while adjacent cells in the word-line direction maintain a lower level. This provides a basis for calculating the threshold drift risk value using different linear mappings.

[0041] In step S14, a programming control voltage is generated based on the threshold drift risk value. This programming control voltage is then used to electrically control the units exhibiting the threshold drift risk value, thereby obtaining the control state of the adjacent units. This includes: Obtain the preset reference programming voltage of the flash array, and perform compensation processing on the preset reference programming voltage according to the threshold drift risk value to obtain the programming control voltage; The programmed control voltage is applied to the adjacent units to perform electrical control and obtain a control state.

[0042] It should be noted that when obtaining the preset reference programming voltage of the flash array, and compensating the reference programming voltage according to the threshold drift risk value, the system uses the previously determined threshold drift risk value and the number of erase / write cycles of the current adjacent cell as two input parameters. According to the preset compensation calculation rules, the compensation components of the two parameters are calculated independently and then merged.

[0043] Specifically, firstly, using the reference programming voltage as a base, the threshold drift risk value is normalized by dividing it by a preset maximum risk value, resulting in a normalized risk value ranging from 0 to 1. Simultaneously, the number of erase / write cycles is normalized by dividing it by a preset maximum number of cycles, also ranging from 0 to 1. Then, the normalized risk value is multiplied by a first weighting coefficient to obtain a first compensation ratio, and the normalized wear value is multiplied by a second weighting coefficient to obtain a second compensation ratio. Both the first and second weighting coefficients are dimensionless scaling factors; for example, the first weighting coefficient is set to 0.05 and the second weighting coefficient to -0.02. The first and second compensation ratios are summed to obtain the total compensation ratio, which is then multiplied by the reference programming voltage to obtain the voltage compensation amplitude.

[0044] For example, if the normalized risk value is 0.71, the normalized wear value is 0.60, the first weighting coefficient is 0.05, and the second weighting coefficient is -0.02, then the total compensation ratio is 0.05×0.71+(-0.02)×0.60=0.0235. If the reference programming voltage is 15000 mV, then the voltage compensation amplitude is 352.5 mV, and the programming control voltage is 15352.5 mV.

[0045] It should be noted that the first and second weighting coefficients are empirical values ​​obtained by performing accelerated aging tests and programming interference experiments on flash memory chips under different process angles, with the goal of minimizing the data flip-flop rate. These values ​​are calibrated using a grid search method and then fixed to the firmware parameter area of ​​the flash memory controller before mass production of the chip.

[0046] The preset maximum risk value is determined based on the theoretical upper limit of the threshold drift risk value. Specifically, it is the upper limit of the risk value calculated using a preset linear mapping function when the capacitive coupling strength reaches its maximum possible value and the programming interference reaches its maximum amplitude. The form of this linear mapping function is as follows: Where R is the threshold drift risk value, The programming interference is denoted by α and β, which are preset linear coefficients determined by linear regression fitting of experimental data showing data flipping between adjacent cells under multiple sets of different programming interference levels. Under typical process conditions, this represents the programming interference level corresponding to the maximum value of capacitive coupling strength. Substituting this into the mapping function, the maximum risk value is calculated to be 100.

[0047] First, the programming control voltage, as the amplitude of the programming pulse, is applied to the control gate of the adjacent cell for a preset pulse width, allowing charge to be injected into the floating gate through tunneling. The preset pulse width is determined according to the flash memory manufacturing process specifications; for example, in a typical 65nm process, the standard programming pulse width for a single-layer cell flash memory is 1 microsecond, a value read from the process parameter register by the timing control module of the flash memory controller. Then, a read operation is immediately performed, directly measuring the threshold voltage of the adjacent cell through a sensing amplifier. The measured threshold voltage is compared with a preset target threshold voltage. If the target value has been reached, programming stops, and the cell is determined to be in a normal programming state. The preset target threshold voltage is determined according to the logic state division window of the single-layer cell flash memory; for example, the target threshold voltage for logic 0 is set to 1500 millivolts, a value specified by the flash memory manufacturer in the device datasheet and stored in the reference voltage register of the flash memory controller. If the target value is not reached, the programming control voltage for the next pulse is adjusted according to a pre-calibrated incremental step table based on the difference between the current threshold voltage and the target value, and the cycle of applying pulses and verification is repeated until the threshold voltage reaches the target or the maximum number of pulses is reached. For example, after applying the first programming pulse, the threshold voltage is read as 1200 millivolts, while the target threshold voltage is 1500 millivolts, a difference of 300 millivolts. Referring to the incremental step table, it is determined that the next programming control voltage needs to be increased by 200 millivolts. Then, the second pulse is applied and verified again until the threshold voltage reaches 1500 millivolts. At this point, it is determined that the adjacent unit is in normal programming state.

[0048] The pre-calibrated incremental step table was obtained through experimental calibration during the chip characteristic testing phase. The specific method is as follows: programming pulses of different amplitudes are applied to multiple sample particles, the threshold voltage increment after each pulse is measured, the optimal increment value corresponding to different gap intervals is statistically obtained, and a lookup table is constructed with the gap range as the index and the increment as the table entry. For example, when the gap is 300 millivolts, the step increment is 200 millivolts. The maximum number of pulses is set according to the programming endurance requirements of the flash memory cell. For example, under typical processes, the maximum number of programming pulses for a single-layer cell flash memory is 10 times to prevent over-programming from causing oxide layer breakdown.

[0049] After confirming that the adjacent cell is in a normal programming state, the electrical control of the adjacent cell is completed, resulting in a control state. Then, the read voltage monitoring process in step S15 begins. The control state refers to the situation where, after electrical regulation by the programming control voltage, the threshold voltage of the adjacent cell is raised to a preset target threshold voltage range. This prevents it from being misjudged as a logic state flip due to parasitic capacitance coupling interference from write hotspots during subsequent read operations. The core characteristic of this state is that the charge storage of the adjacent cell is precisely controlled within a safe range sufficient to resist preset amplitude voltage disturbances.

[0050] It should be noted that the preset target threshold voltage range is determined by the specifications of the flash memory device. Specifically, the threshold voltage distribution range corresponding to the programming verification voltage is selected as the basic range, and a voltage margin is further reserved within this basic range to resist parasitic capacitance coupling interference, thus obtaining the final preset target threshold voltage range. The upper and lower limit parameters of this range are fixed in the reference voltage register of the flash memory controller before chip mass production.

[0051] In step S15, after the adjacent unit enters the control state, a read verification operation is performed to determine whether the adjacent unit has experienced data flipping, including: After the adjacent unit enters the control state, the transient voltage change rate of the adjacent unit is obtained, and the parasitic capacitance value of the adjacent unit is read from the pre-stored register; The coupling interference current of the write hotspot coupled to the adjacent cell through the parasitic capacitance is calculated based on the transient voltage change rate and the parasitic capacitance value. A set standard read voltage is applied to the adjacent unit, the read current on the bit line is collected, and the coupling interference current is superimposed and compensated with the read current to obtain the compensated read current; The real-time logic value corresponding to the compensated read current is compared with the expected logic value when writing to the adjacent unit. If they are inconsistent, it is determined that a data flip has occurred.

[0052] It should be noted that after confirming that the adjacent unit has entered the control state in step S14, when the write hotspot executes a programming pulse due to a normal service write operation, the voltage jump of the programming pulse will be coupled to the adjacent unit through parasitic capacitance. That is, the rapid rise or fall of its voltage will induce transient voltage changes on the control gate of the adjacent unit, which may interfere with its control state. In order to monitor whether this interference causes data flipping, the high-speed voltage monitoring circuit monitors the voltage waveform on the control gate of the adjacent unit in real time at a picosecond sampling rate, and captures the voltage jump amplitude and duration during the edge of the programming pulse. For example, if the voltage rises by 0.5 volts within 1 nanosecond, the transient voltage change rate is calculated to be 0.5 volts per nanosecond, and this value is stored in the buffer register in digital form for subsequent reading.

[0053] Next, the parasitic capacitance values ​​of adjacent cells are read from the registers pre-programmed into the firmware area of ​​the flash memory controller. These parasitic capacitance values ​​are obtained by extracting parasitic parameters from the flash memory array layout once using a three-dimensional parasitic parameter extraction tool during the chip design phase and then storing them in a lookup table with the relative physical position of the adjacent cells and the write hotspot as the index. For example, the parasitic capacitance of the word line and bit line overlapping area is found to be 2 Fab.

[0054] Then, the previously stored transient voltage change rate value is retrieved from the cache register and multiplied by the parasitic capacitance value of the adjacent cell from the pre-stored register. This multiplication yields the coupling interference current. This coupling interference current represents the transient current component induced in the gate circuit of the adjacent cell when the write hotspot performs a programming operation, due to the rapid voltage change on its control gate coupled to the control gate of the adjacent cell through the parasitic capacitance. This current component, superimposed on the normal read current, interferes with the sensitive amplifier's accurate judgment of the storage state of the adjacent cell. For example, if the transient voltage change rate is 0.5 volts per nanosecond and the parasitic capacitance is 2 femtofarads, the calculated coupling interference current is 1 nanoamp. This value represents the interference intensity of the write hotspot coupled to the adjacent cell through the parasitic capacitance. After calculation, this coupling interference current value is sent to the current summing node, ready to be superimposed and compensated with the subsequently acquired read current.

[0055] It should be noted that a standard read voltage is applied to adjacent cells, the read current on the bit lines is collected, and the calculated coupling interference current is used to compensate for this read current. To obtain the compensated read current, the word line drive circuit first applies a standard read voltage to the control gate of the adjacent cell. This standard read voltage is set according to the read operation conditions specified in the device datasheet provided by the flash memory manufacturer. For example, the voltage applied in standard read mode is 5000 millivolts to ensure that the memory cell is in the saturation region during the read process and that the channel current and threshold voltage have a monotonic relationship. Simultaneously with applying the standard read voltage, the system collects the read current flowing through the bit lines of the adjacent cells through a current mirror circuit. This read current includes the channel conduction current of the adjacent cells themselves and the interference current component introduced from write hotspots through parasitic capacitance coupling. For example, the collected read current is 50 nanoamps.

[0056] Subsequently, the acquired read current and the previously calculated coupling interference current are fed into a current summing node. The two current values ​​are algebraically added using a current mirroring method, where the direction of the coupling interference current is opposite to that of the read current, to compensate for the interference component. For example, if the read current is 50 nanoamps and the coupling interference current is 1 nanoamp, the difference yields a compensated read current of 49 nanoamps. This compensated read current eliminates the interference of hotspot programming operations on the read results of adjacent cells, reflecting the true channel conduction state of adjacent cells and providing an accurate current input for the subsequent correct decision by the sensitive amplifier. After compensation, this compensated read current is fed into the input of the sensitive amplifier, ready to be compared with a reference current to output a real-time logic value.

[0057] The compensated read current is input to a sensitive amplifier and compared with a reference current. A real-time logic value is output and compared with the expected logic value when writing to the adjacent cell. If they do not match, a data flip is determined. When this occurs, the system first sends the compensated read current obtained in the previous step to the non-inverting input of the sensitive amplifier, and simultaneously connects a preset reference current to the inverting input. This reference current is pre-calibrated based on the read reference conditions of a single-layer flash memory chip, for example, set to 50 nanoamps, and is used to distinguish the critical current value between a memory cell in a logic 1 or logic 0 state. Internally, the sensitive amplifier differentially amplifies the two input currents through a current comparison circuit. When the compensated read current is greater than the reference current, the sensitive amplifier outputs a high level, representing logic 1; when the compensated read current is less than the reference current, the sensitive amplifier outputs a low level, representing logic 0, thus converting the analog current signal into a digital logic level, i.e., the real-time logic value.

[0058] Subsequently, the system reads the expected logic value written by the adjacent cell during the most recent programming operation from the page buffer or data latch. This expected logic value is the target state data issued by the upper-level controller and temporarily stored in the cache during the programming phase. The real-time logic value and the expected logic value are sent together to the XOR comparison logic unit for bit-by-bit comparison. If they match, the XOR gate outputs a low level, indicating that the read result matches the written content and no data error has occurred. If they do not match, the XOR gate outputs a high level, indicating that the read result does not match the written content, that is, the storage state of the adjacent cell has changed unexpectedly due to parasitic capacitance coupling interference from the write hotspot, and is determined to be a data flip. This determination result is sent to the control state machine, triggering subsequent secondary electrical control processes to block coupling propagation and restore data correctness.

[0059] For example, Figure 3 This is a schematic diagram illustrating the effect of read current superposition compensation. The coupling interference introduced by the programming pulse edge significantly increases the read current. After calculating and compensating for the interference current using the transient voltage change rate and parasitic capacitance, the compensated read current remains below the 50 nanoamp reference current, ensuring that the real-time logic value of the adjacent cell remains consistent with the desired logic value.

[0060] In step S16, if data flipping occurs in the adjacent units, secondary electrical control of the adjacent units is required to block coupling diffusion, including: If data flipping occurs in the adjacent cells, the initial charge distribution state of the write hotspot is extracted; Based on the initial charge distribution state, the potential gradient along the hotspot migration path is calculated to obtain the corresponding electric field intensity; The second programming control voltage is determined based on the electric field strength. The second programming control voltage is used to perform secondary electrical control on adjacent cells to block the coupling and diffusion of the write hotspot to adjacent cells.

[0061] It should be noted that if data flipping occurs between adjacent cells, when extracting the initial charge distribution state of the write hotspot, the system first calls the charge capture state data of the write hotspot in the floating gate oxide layer that was obtained when predicting voltage offset and outward radiated voltage disturbance. Then, these discrete electron density values ​​are reorganized into a three-dimensional array according to physical space coordinates. Each element of the array corresponds to the charge concentration of a storage cell, thereby obtaining the initial charge distribution state of the write hotspot. For example, the charge concentration in the center region of the hotspot is 1 x 10^19 electrons per cubic centimeter, and the charge concentration in the edge region decreases to 5 x 10^18 electrons per cubic centimeter.

[0062] Based on the initial charge distribution state, the system calculates the potential gradient along the hotspot migration path to obtain the corresponding electric field intensity. Using a three-dimensional array of the initial charge distribution state as input, the system discretizes each point in space using the finite difference method. The ratio of the potential difference to the distance between adjacent grid points is calculated along both the word line and bit line directions to obtain the potential gradient components in each direction. Then, the gradient components in the two directions are vector-synthesized to obtain the electric field intensity vector at each spatial location. For example, at the hotspot boundary, the potential gradient calculated along the word line direction is 500 mV per micrometer, and along the bit line direction it is 300 mV per micrometer. After synthesis, the electric field intensity is approximately 583 mV per micrometer, pointing towards one side of the adjacent cell.

[0063] It should be noted that the second programming control voltage is determined based on the electric field strength, and secondary electrical control is performed on adjacent cells using the second programming control voltage to block the coupling and diffusion of the write hotspot to adjacent cells, including: The second programming control voltage is determined based on the electric field strength by directly obtaining it through a preset mapping relationship between the electric field strength and the programming control voltage. The mapping relationship is pre-established using a linear function.

[0064] It should be noted that when the second programming control voltage is used to perform secondary electrical control on adjacent units to block the coupling diffusion of the writing hotspot to adjacent units, the system takes the electric field strength calculated above as input and directly obtains the second programming control voltage through the preset mapping relationship between the electric field strength and the programming control voltage.

[0065] A pre-defined scaling factor is used to calculate the reverse compensation voltage by multiplying the electric field strength by this factor. This scaling factor is determined through linear regression fitting of the reverse compensation voltages required to restore the threshold voltage of adjacent cells to the normal range under multiple sets of different electric field strengths. Specifically, under laboratory conditions, multiple sample particles are selected, and the optimal reverse compensation voltage corresponding to different electric field strengths is measured. A univariate linear regression is performed with the electric field strength as the independent variable and the reverse compensation voltage as the dependent variable. The slope obtained from the regression is the scaling factor. Subsequently, the reverse compensation voltage is added to the current programming control voltage of the adjacent cell. The sum of the two is the second programming control voltage. For example, if the current programming control voltage is 15300 mV and the reverse compensation voltage is 250 mV, then the second programming control voltage is 15550 mV. Finally, the control word line drive circuit applies a square wave pulse with an amplitude equal to the second programming control voltage to the control gate of the adjacent cell for a preset pulse width. This increases the channel electric field to counteract the parasitic capacitive coupling effect from the write hotspot, thereby pulling the threshold voltage of the adjacent cell back to the normal range and blocking the coupling diffusion path from the hotspot to the adjacent cell.

[0066] For example, Figure 4 This is a schematic diagram of the compensation read current distribution before and after secondary electrical control. After implementing secondary electrical control on 157 adjacent units that were determined to have data flipped during the read verification, the compensation read current of 151 units dropped below the reference current. However, 6 units were still determined to have data flipped, indicating that the number of data flips decreased in this simulation, but not all were recovered.

[0067] In summary, this invention discloses a method for suppressing partitioned interference in an SLC NAND array based on write heatmap awareness. The method includes acquiring the real-time write frequency and identifying the highest point as the write hotspot. Evolution features are extracted from this hotspot to predict voltage shifts and outwardly radiated voltage disturbances. The spatial distance between the voltage disturbance and the hotspot is calculated, and a feature vector is constructed. Parasitic capacitance is evaluated to obtain capacitive coupling strength; if it exceeds a preset threshold, a threshold drift risk value is obtained through linear mapping. A programming control voltage is generated based on this risk value to electrically control adjacent cells, resulting in a control state. After the adjacent cells enter the control state, a read verification operation is performed to acquire the transient voltage change rate and calculate the coupling interference current. The bit line read current is superimposed and compensated to obtain a compensated read current. The real-time logic value corresponding to the compensated read current is compared with the expected logic value; if they are inconsistent, a data flip is determined. If a data flip occurs, secondary electrical control is performed on the adjacent cells to block coupling propagation.

[0068] This invention locates write hotspots by real-time monitoring of write frequency, extracts hotspot evolution characteristics to predict voltage disturbances, assesses coupling strength based on spatial distance and parasitic capacitance and maps it to a threshold drift risk value, generates a programming control voltage to electrically control adjacent cells, and then judges data flipping through read verification operations. When a flipping occurs, secondary electrical control is executed to block coupling diffusion, thus achieving precise partitioned perception and active suppression of write interference in single-layer cell flash arrays.

[0069] The second embodiment of the present invention provides an SLC NAND array partition interference suppression system based on write heatmap awareness, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described above.

[0070] It should be noted that the SLC NAND array partition interference suppression system based on write heatmap awareness provided in this embodiment of the invention is used to execute all the process steps of the SLC NAND array partition interference suppression method based on write heatmap awareness in the above embodiment. The working principles and beneficial effects of the two are one-to-one, so they will not be described again.

[0071] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0072] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A method for suppressing partition interference in an SLC NAND array based on write heatmap awareness, characterized in that, include: Obtain the real-time write frequency and identify the highest frequency point as the write hotspot. Extract hotspot evolution features from the written hotspot, obtain charge capture state based on the hotspot evolution features, determine threshold voltage drift and map it to voltage offset, determine the coupling strength of each node in the space based on the voltage offset, construct a spatial distribution matrix, and obtain the voltage perturbation radiated outward from the written hotspot based on the superposition of the contributions of each node in the spatial distribution matrix. Based on the voltage disturbance, the adjacent cells around the write hotspot are determined, and the capacitive coupling strength between the write hotspot and the adjacent cells is calculated. If the capacitive coupling strength is greater than a preset coupling strength threshold, the threshold drift risk value is obtained through linear mapping. A programming control voltage is generated based on the threshold drift risk value, and the unit with the threshold drift risk value is electrically controlled by the programming control voltage to obtain the control state of the adjacent unit; After the adjacent unit enters the control state, the transient voltage change rate of the adjacent unit is acquired, and the parasitic capacitance value of the adjacent unit is read from the pre-stored register; the coupling interference current of the write hot spot coupled to the adjacent unit through the parasitic capacitance is calculated based on the transient voltage change rate and the parasitic capacitance value; a set standard read voltage is applied to the adjacent unit, the read current on the bit line is collected, and the coupling interference current is superimposed and compensated with the read current to obtain the compensated read current; the real-time logic value corresponding to the compensated read current is compared with the expected logic value when writing to the adjacent unit, and if they are inconsistent, it is determined that a data flip has occurred; If data flipping occurs in the adjacent units, the coupling diffusion is blocked by performing secondary electrical control on the adjacent units.

2. The SLC NAND array partition interference suppression method based on write heatmap awareness according to claim 1, characterized in that, The step of obtaining the real-time write frequency and determining the highest frequency point as the write hotspot includes: Obtain write operation records of storage blocks in a single-level cell flash array, and calculate the real-time write frequency of each block based on the write operation records. The real-time write frequencies are sorted, and the block address of the highest frequency is extracted as the write hotspot inside the single-layer cell flash array.

3. The SLC NAND array partition interference suppression method based on write heatmap awareness according to claim 1, characterized in that, The step of extracting hotspot evolution features from the written hotspots includes: Based on the programming timestamps of the written hotspots, the historical programming frequency is statistically analyzed, and a frequency time series is constructed. Hotspot evolution features are extracted from the frequency time series by exponential smoothing.

4. The SLC NAND array partition interference suppression method based on write heatmap awareness according to claim 1, characterized in that, The process involves determining adjacent cells around the write hotspot based on the voltage disturbance, calculating the capacitive coupling strength between the write hotspot and the adjacent cells, and if the capacitive coupling strength is greater than a preset coupling strength threshold, obtaining a threshold drift risk value through linear mapping, including: Based on the spatial influence range of the voltage disturbance, adjacent cells are determined, and the physical distance between the adjacent cells and the write hotspot is calculated. Based on the physical distance, the parasitic capacitance value is obtained by calling the pre-stored parasitic parameter lookup table, and the parasitic capacitance value is substituted into the capacitor voltage divider formula to calculate the capacitive coupling strength between the write hotspot and the adjacent cell. The programming interference amount is calculated based on the capacitive coupling strength. If the capacitive coupling strength is greater than a preset coupling strength threshold, the programming interference amount is calculated using a preset first mapping function to obtain a threshold drift risk value; otherwise, the threshold drift risk value is calculated using a preset second linear mapping function.

5. The SLC NAND array partition interference suppression method based on write heatmap awareness according to claim 1, characterized in that, The step of generating a programmed control voltage based on the threshold drift risk value, and then using the programmed control voltage to electrically control the unit with the threshold drift risk value to obtain the control state of the adjacent unit includes: Obtain the preset reference programming voltage of the flash array, and perform compensation processing on the preset reference programming voltage according to the threshold drift risk value to obtain the programming control voltage; The programmed control voltage is applied to the adjacent units to perform electrical control and obtain a control state.

6. The SLC NAND array partition interference suppression method based on write heatmap awareness according to claim 1, characterized in that, If a data flip occurs in the adjacent unit, the coupling diffusion is blocked by performing secondary electrical control on the adjacent unit, including: If data flipping occurs in the adjacent cells, the initial charge distribution state of the write hotspot is extracted; Based on the initial charge distribution state, the potential gradient along the hotspot migration path is calculated to obtain the corresponding electric field intensity; The second programming control voltage is determined based on the electric field strength. The second programming control voltage is used to perform secondary electrical control on adjacent cells to block the coupling and diffusion of the write hotspot to adjacent cells.

7. The SLC NAND array partition interference suppression method based on write heatmap awareness according to claim 6, characterized in that, The step of determining the second programming control voltage based on the electric field strength, and using the second programming control voltage to perform secondary electrical control on adjacent cells to block the coupling and diffusion of the write hotspot to adjacent cells, includes: The second programmed control voltage is determined based on the electric field strength by directly obtaining it through a preset mapping relationship between the electric field strength and the programmed control voltage. The mapping relationship is pre-established using a linear function.

8. A partition interference suppression system for SLC NAND arrays based on write heatmap awareness, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method described in any one of claims 1 to 7.

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