Storage device and storage system

Abstract

The present disclosure relates to a memory device and a memory system. A memory device includes: an array of memory cells including a plurality of cell groups each including adjacent cell blocks of a plurality of cell blocks and sharing a sub word line driver with an adjacent cell group; a mapping control circuit configured to generate a mapping control signal according to an output option signal and to selectively invert at least one bit of the mapping control signal based on a row address and a repair control signal including information about a repair cell group of the plurality of cell groups; and a mapping circuit configured to select one of two adjacent cell groups based on a corresponding bit of the mapping control signal and to map the selected cell group to a plurality of data pads.

Description

Cross-references to related applications

[0001] This application claims the benefit of Korean Patent Application No. 10-2025-0044516, filed on April 7, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0002] Various embodiments of this disclosure relate to semiconductor design techniques, and more specifically, to a storage system including a storage device with an ECC engine. Background Technology

[0003] In the early days of the semiconductor memory industry, most of the original good dies produced during the semiconductor on-chip manufacturing process formed defect-free memory cells. However, as the capacity of memory devices has gradually increased, it has become increasingly difficult to manufacture memory devices with completely defect-free memory cells, and currently, it can be said that it is almost impossible to manufacture memory devices with defect-free memory cells. As a solution to overcome this situation, methods such as using redundant memory cells to repair defective memory cells in memory devices or using error correction code (ECC) engines to correct errors in the data of memory cells are being used.

[0004] Currently, various methods are being discussed to manage the maximum number of error bits that may occur in a storage device within the error correction capabilities of the memory controller. Summary of the Invention

[0005] Embodiments of this disclosure relate to a storage device and a storage system that can change the mapping between data pads and cell blocks of a common subword line driver, thereby limiting the maximum number of error bits that may occur in the storage device to the error correction capability of the memory controller.

[0006] According to one embodiment of this disclosure, a storage device includes: a storage cell array including a plurality of cell groups, each cell group including adjacent cell blocks in a plurality of cell blocks and alternately sharing a subword line driver with adjacent cell groups; a mapping control circuit configured to generate a mapping control signal according to an output option signal and selectively invert at least one bit of the mapping control signal based on a row address and a repair control signal including information about a repair cell group in the plurality of cell groups; and a mapping circuit configured to select one of two adjacent cell groups based on corresponding bits of the mapping control signal and map the selected cell group to a plurality of data pads.

[0007] According to another embodiment of this disclosure, a storage device includes: a storage cell array comprising a plurality of normal cell blocks, redundant cell blocks, and error correction code (ECC) cell blocks, wherein adjacent normal cell blocks among the plurality of normal cell blocks are grouped to form a plurality of normal cell groups, the redundant cell blocks and ECC cell blocks are grouped to form additional cell groups, and each cell group alternately shares a subword line driver with an adjacent cell group; a mapping circuit comprising a plurality of mappers respectively corresponding to pairs of normal cell groups among the plurality of normal cell groups, each mapper being configured to select one of the pairs of normal cell groups based on a corresponding bit of a mapping control signal; and a mapping control circuit configured to identify a target cell group among the plurality of normal cell groups according to an output option signal, and detect that a repair cell group is included in the target cell group and that a cell group sharing a subword line driver with an additional cell group is included in the target cell group, to set the bits of the mapping control signal to have different values.

[0008] According to another embodiment of this disclosure, a storage system includes: at least one storage device; and a memory controller configured to control the operation of the at least one storage device, wherein the at least one storage device includes: a storage cell array including a plurality of cell groups, each cell group including adjacent cell blocks in a plurality of cell blocks and alternately sharing a subword line driver with adjacent cell groups; a mapping control circuit configured to generate a mapping control signal according to an output option signal and selectively invert at least one bit of the mapping control signal based on a row address and a repair control signal including information about a repair cell group in the plurality of cell groups; and a mapping circuit configured to select one of two adjacent cell groups based on a corresponding bit of the mapping control signal and map the selected cell group to a plurality of data pads.

[0009] According to embodiments of this disclosure, a storage device can prevent uncorrectable errors (UEs) and maximize error correction capabilities by limiting the maximum number of error bits, including miscorrections, to a range defined by a specification.

[0010] According to embodiments of this disclosure, the storage device can provide optimized reliability, accessibility, and maintainability (RAS) operation by improving the error mitigation capabilities of the memory controller.

[0011] These and other features and advantages of the embodiments of this disclosure will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a storage system according to an embodiment of the present disclosure.

[0013] Figure 2 It is shown Figure 1 A diagram illustrating the data input / output operations of a storage device.

[0014] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 1 A block diagram of the storage device.

[0015] Figures 4A to 4C This illustrates an embodiment according to the present disclosure. Figure 3 A diagram of a storage cell array.

[0016] Figure 5 It shows including Figure 3 A diagram illustrating an example of the data input / output path for the memory cell array and mapping circuitry.

[0017] Figure 6 It is shown Figure 3 The diagram shows a detailed block diagram of the mapping control circuit.

[0018] Figure 7 It is used to describe Figure 6 The table shown illustrates the operation of the repair group detector.

[0019] Figure 8 It is used to describe Figure 6 The flowchart shown illustrates the operation of the switching determinant.

[0020] Figure 9A and Figure 9B It is for ease of description Figure 8 The table for operations.

[0021] Figures 10A to 11C This is a diagram used to describe mapping operations according to embodiments of the present disclosure.

[0022] Figure 12 This is a block diagram illustrating a storage system including a storage module according to an embodiment of the present disclosure.

[0023] Figure 13 This is a block diagram illustrating a storage system including a stacked storage device according to embodiments of the present disclosure.

[0024] Figure 14 This is a block diagram illustrating a mobile system including a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0025] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, the embodiments of the present disclosure may take different forms and should not be construed as limited to those described herein. Rather, these embodiments are provided to make the present disclosure more comprehensive and complete, and to fully convey the scope of the disclosure to those skilled in the art. Throughout the present disclosure, the same reference numerals refer to the same parts in the various figures and embodiments.

[0026] It should be understood that when an element is referred to as "coupled" or "connected" to another element, this can mean that the two elements are directly coupled or that the two elements are electrically connected to each other, with another circuitry interposed therebetween. It should also be understood that the terms "comprising," "including," "having," etc., as used in this specification, specify the presence of the stated features, numbers, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof. In this disclosure, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0027] Figure 1 This is a block diagram illustrating a storage system 10 according to an embodiment of the present disclosure.

[0028] refer to Figure 1 The storage system 10 may include a storage device 100 and a memory controller 200. The storage system 10 can store data under the control of a host device 20 (such as a cellular phone, smartphone, MP3 player, laptop, desktop computer, game console, television, tablet, or in-vehicle infotainment system). The host device 20 may be an external device of the storage system 10.

[0029] The memory controller 200 can control the operation of the storage system 10 and control the data transfer between the host 20 and the storage device 100. The memory controller 200 can generate a command / address signal C / A based on a request REQ from the host 20 and provide the generated command / address signal C / A to the storage device 100. According to one embodiment, the memory controller 200 can provide a clock signal along with the command / address signal C / A. The memory controller 200 can provide the storage device 100 with a data DIO corresponding to the request REQ from the host 20, and provide the host 20 with data DIO read from the storage device 100. For example, during a write operation, the memory controller 200 can provide the storage device 100 with a write command, address, and data. During a read operation, the memory controller 200 can provide the storage device 100 with a read command and address, and provide the host 20 with the data read from the storage device 100.

[0030] The memory controller 200 may include an error correction code (ECC) engine 210. The ECC engine 210 can detect and correct errors in the data DIO read from the storage device 100 and provide the error correction data to the host 20. When the number of error bits in the data DIO exceeds the error correction capability of the ECC engine 210, the memory controller 200 can notify the host 20 that an uncorrectable error (UE) has occurred.

[0031] Storage device 100 can store data DIO. Storage device 100 can operate under the control of memory controller 200. Storage device 100 may include a memory cell array 110, which includes a plurality of memory cells for storing data. Storage device 100 may include dynamic random access memory (DRAM), which includes dynamic memory cells. In one embodiment, storage device 100 may be double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, Rambus dynamic random access memory (RDRAM), or other types.

[0032] Storage device 100 is configured to receive a command / address signal C / A from memory controller 200 to access a region selected from memory cell array 110. That is, storage device 100 can perform an operation instructed by a command on the region selected by address. For example, storage device 100 can perform a write operation (e.g., a programming operation) to write data DIO to the region selected by address. During a read operation, storage device 100 can read data DIO from the region selected by address.

[0033] Furthermore, the storage device 100 may include an ECC engine 132. The ECC engine 132, located within the storage device 100, may be referred to as an "on-die (or chip-based) ECC engine." During a write operation, the ECC engine 132 can generate error correction codes using data DIO and stores the data DIO and error correction codes in a selected area of ​​the memory cell array 110. During a read operation, the ECC engine 132 can read data and error correction codes from the selected area of ​​the memory cell array 110 and generate error-corrected data DIO by correcting errors in the read data using the read error correction codes. The error correction capability of the storage device 100 may be set to be less than that of the memory controller 200. That is, the error correction capability of the ECC engine 210 of the memory controller 200 may be greater than that of the ECC engine 132 of the storage device 100. For example, the ECC engine 132 may only be able to correct single-bit errors, while the ECC engine 210 may be able to correct multi-bit errors.

[0034] In the storage device 100, a command / address pad CA# for receiving command / address signals C / A and a data pad DQ# for receiving data DIO can be configured. Although Figure 1 Only one command / address pad CA# and one data pad DQ# are shown, but the number of command / address pads CA# and DQ# can be set to correspond to the number of bits of the command / address signal C / A and the number of bits of the data DIO, respectively.

[0035] Figure 2 It is shown Figure 1 A diagram illustrating the data input / output operations of the storage device 100.

[0036] refer to Figure 2 The storage device 100 can use multiple data pads (i.e., first to fourth data pads DQ0 to DQ3) corresponding to the data bus width (e.g., ×4) to input / output data DIO according to a preset data width option (e.g., 4 bits). Furthermore, the storage device 100 can perform burst operations to convert data output in parallel from the storage cell array into serially ordered data and output the converted data within a preset burst length (e.g., 16).

[0037] therefore, Figure 2 The storage device 100 can input / output 4*16=64 bits of data DIO during each burst length from BL0 to BL15, in a single read or write operation, by inputting / outputting data in 4-bit units via the first to fourth data pads DQ0 to DQ3. On the other hand, if the error correction capability of the memory controller 200 can cover erroneous bits in a consecutive 32-bit data sequence, erroneous bits transmitted via the two data pads can be corrected by the error correction operation performed by the memory controller 200.

[0038] Figure 2 The storage device 100 is shown with the data width option set to 4 and the burst length set to 16, but the embodiment is not limited to this. Data of multiple bits can be input and output according to the settings of the data width option and the burst length.

[0039] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 1 Block diagram of storage device 100. Figures 4A to 4C This illustrates an embodiment according to the present disclosure. Figure 3 A diagram of the storage cell array 110.

[0040] refer to Figure 3The storage device 100 may include a storage cell array 110, a row control circuit 120, a column control circuit 130, an error correction code (ECC) engine 132, a repair control circuit 140, a mapping control circuit 150, a mapping circuit 160, a command / address (CA) buffer 172, a command decoder 173, an address generation circuit 174, and a data input / output circuit 180.

[0041] The memory cell array 110 can be coupled to the row control circuit 120 via multiple word lines WL, and to the column control circuit 130 via multiple bit lines BL. The multiple word lines WL can extend along a first direction (e.g., the row direction) and be arranged sequentially in a second direction (e.g., the column direction). The multiple bit lines BL can extend along the column direction and be arranged sequentially in the row direction.

[0042] refer to Figure 4A The storage cell array 110 may include multiple storage blocks (hereinafter referred to as "cell blocks MB") arranged in an array along a first direction X1 and a second direction Y1 intersecting the first direction X1. Each cell block MB may include multiple storage cells MC connected between multiple word lines WL and multiple bit lines BL. In one embodiment of this disclosure, a "cell block" may be defined as a group of storage cells that share word lines WL and bit lines BL and are arranged in the same manner.

[0043] Furthermore, to reduce word line voltage transmission latency (which increases with the number of memory cells connected to the word line and the distance between word lines), a main word line can be divided into multiple sub-word lines (e.g., eight sub-word lines), and a sub-word line driver can be used to drive each sub-word line. The multiple word lines WL mentioned in this disclosure can correspond to sub-word lines.

[0044] exist Figure 4A In this embodiment, two adjacent cell blocks (MB) disposed in the first direction X1 can form a cell group (MG). That is, the cell blocks (MB) disposed in the first direction X1 can be grouped into multiple cell groups (MG). Sub-word line driver regions (SWB) can be arranged between the cell groups (MG) disposed in the first direction X1. Multiple sub-word line drivers can be disposed in the sub-word line driver regions (SWB). Bit line sense amplifier regions (BLSAB) can be arranged between the cell blocks (MB) disposed in the second direction Y1. Multiple bit line sense amplifiers can be disposed in the bit line sense amplifier regions (BLSAB).

[0045] refer to Figure 4B It shows including Figure 4A The two unit groups MG represent a portion of the MA region.

[0046] The squares between unit groups MG can represent subword line drivers SWD, while the lines extending to the left and right sides of the subword line driver SWD can represent word lines (or subword lines). In reality, there are far more subword line drivers SWD and word lines, but for simplicity, only a portion of the lines are shown to illustrate the basic structure.

[0047] Each cell group MG may include odd-numbered word lines (hereinafter referred to as "first word line WLO") and even-numbered word lines (hereinafter referred to as "second word line WLE") extending along a first direction X1 and alternating with each other in a second direction Y1. In the odd-numbered cell group MG, the first word line WLO may share a sub-word line driver SWD with adjacent cell groups located along a direction X2 opposite to the first direction X1, while the second word line WLE may share a sub-word line driver SWD with adjacent cell groups located along the first direction X1. Conversely, in the even-numbered cell group MGE, the first word line WLO may share a sub-word line driver SWD with adjacent cell groups located along the first direction X1, while the second word line WLE may share a sub-word line driver SWD with adjacent cell groups located along the direction X2. That is, since two adjacent cell groups MG0 and MGE share a sub-word line driver SWD, one sub-word line driver SWD can be allocated to four adjacent cell blocks MB located along the first direction X1.

[0048] Each cell block MB may include a first bit line BLU and a second bit line BLL extending along a second direction Y1 and alternately arranged in a first direction X1. The first bit line BLU may share a bit line sense amplifier BLSA with adjacent cell blocks arranged along the second direction Y1, while the second bit line BLL may share a bit line sense amplifier BLSA with adjacent cell blocks arranged along a direction Y2 opposite to the second direction Y1. That is, since two adjacent cell blocks MB arranged along the second direction Y1 share a bit line sense amplifier BLSA, one bit line sense amplifier BLSA can be allocated to two adjacent cell blocks MB arranged along the second direction Y1.

[0049] In the following embodiments, such as Figure 4CAs shown, the memory cell array 110 is described by way of example as including first normal cell blocks MB0 to sixteenth normal cell blocks MB15, redundant cell blocks MBRED, and error correction code (ECC) cell blocks MBECC arranged along the row direction. Since every two adjacent cell blocks form a cell group, the first normal cell blocks MB0 to sixteenth normal cell blocks MB15 can form the first to eighth normal cell groups MG0 to MG7. The redundant cell block MBRED and the ECC cell block MBECC can form a separate cell group (hereinafter referred to as the "additional cell group MGX"). Each of the cell groups MG0 to MG7 and MGX can alternately share a subword line driver SWD with the adjacent cell group. Due to the layout of nine cell groups in the row direction, five subword line drivers SWD can be arranged at the same level along the row direction.

[0050] The first normal cell blocks MB0 to the sixteenth normal cell block MB15 are used as areas for storing user data D1 and constitute storage blocks that determine the storage capacity of storage device 100. The ECC cell block MBECC can store error correction codes (ECCs) generated by the ECC engine 132 for error correction operations. The error correction codes (ECCs) may include known parity bits. The redundant cell block MBRED is used to perform repair operations on the first normal cell blocks MB0 to the sixteenth normal cell block MB15 and the ECC cell block MBECC, and may include multiple redundant cells to replace defective cells in the normal cell blocks MB0 to MB15 and the ECC cell block MBECC.

[0051] During read or write operations, each of the cell blocks MB0 through MB15, MBRED, and MBECC can input or output data in 8-bit units. That is, each cell block MB0 through MB15, MBRED, and MBECC can read 8 bits of data from or write 8 bits of data to a selected memory cell connected between the word line specified by the row address RADD and a predetermined number (e.g., 8) bit lines specified by the column address CADD. It is important to note that to select the word line specified by the row address RADD, all sub-word line drivers SWD at the same level in the row direction can be activated.

[0052] although Figure 4COnly one redundant cell block MBRED and one ECC cell block MBECC are shown in the illustration, but this disclosure is not limited to this; one or more redundant cell blocks MBRED and ECC cell blocks MBECC may be provided. Multiple normal cell blocks MB0 to MB15 may be divided into an upper group comprising the first normal cell blocks MB0 to the eighth normal cell blocks MB7, and a lower group comprising the ninth normal cell blocks MB8 to the sixteenth normal cell blocks MB15. The first normal cell blocks MB0 to the eighth normal cell blocks MB7, the redundant cell block MBRED, the ECC cell block MBECC, and the ninth normal cell blocks MB8 to the sixteenth normal cell blocks MB15 may be arranged sequentially along the row direction. However, this disclosure is not limited to this; the first normal cell blocks MB0 to the sixteenth normal cell blocks MB15, the redundant cell block MBRED, and the ECC cell block MBECC may be arranged in various configurations.

[0053] Return to reference Figure 3 CA buffer 172 can be accessed from an external device (e.g., via command / address pad CA#) using the command / address pad. Figure 1 The memory controller 200 receives the command / address signal C / A. The CA buffer 172 can buffer the command / address signal C / A to output the internal command ICMD and the internal address IADD.

[0054] Command decoder 173 can decode internal commands ICMD to generate activation command ACT, precharge command PCG, write command WT, read command RD, output option signal OUT_OP, etc. Activation command ACT is the signal input during instruction activation operation, precharge command PCG is the signal input during instruction precharge operation, write command WT is the signal input during instruction write operation, and read command RD can be the signal input during instruction read operation. Output option signal OUT_OP is used to select half of all cell blocks MB in a configuration where the data bus width is set to ×4. For example, a logic high level response to output option signal OUT_OP can specify half of all cell blocks MB, while a logic low level response to output option signal OUT_OP can specify the other half of cell blocks MB. In a configuration where the data bus width is set to ×4, storage device 100 can read data from the specified cell block to the first data pads DQ0 to the fourth data pads DQ3, or write data from the first data pads DQ0 to the fourth data pads DQ3 to the specified cell block, according to output option signal OUT_OP. In addition to the commands described above, the command decoder 173 can also generate a variety of commands required for operating the storage device; however, for the sake of focusing on the core of this disclosure, further description thereof will be omitted.

[0055] Address generation circuit 174 can classify the internal address IADD received from command decoder 173 into row address RADD and column address CADD. Row address RADD can be an address used to select one of multiple word lines WL, while column address CADD can be an address used to select some bit lines BL to which read and write operations are to be performed. Both row address RADD and column address CADD can include multiple bits. According to one embodiment, address generation circuit 174 can classify some bits of internal address IADD as row address RADD and the remaining bits as column address CADD. Alternatively, when an operation is activated as a result of instruction decoded by command decoder 173, address generation circuit 174 can classify the address as row address RADD, while when the instruction performs read or write operations, address generation circuit 174 can classify the address as column address CADD.

[0056] According to an embodiment, the memory cell array 110 may include multiple memory banks (not shown). When the memory cell array 110 is composed of multiple memory banks, the row control circuit 120 and the column control circuit 130 may be arranged in a manner corresponding to the number of memory banks. The address generation circuit 174 may classify the internal address IADD into a memory bank address, a row address RADD, and a column address CADD, and one of the multiple memory banks may be specified by its memory bank address. The number of memory banks or the number of memory cells MC may be determined based on the capacity of the storage device 100.

[0057] The row control circuit 120 can perform an activation operation to activate the word line selected by the row address RADD in response to the activation command ACT, and perform a precharge operation to precharge the activated word line in response to the precharge command PCG. The row control circuit 120 can drive the word line by controlling the sub-word line driver according to the row address RADD.

[0058] The column control circuit 130 can select some bit lines in the bit lines BL of the memory cell array 110 according to the column address CADD, and perform a read operation to read data D1 and error correction code ECC from the memory cell MC through the selected bit lines in response to the read command RD, or perform a write operation to write data D1 and error correction code ECC to the memory cell MC through the selected bit lines in response to the write command WT. It should be noted that a predetermined number of bit lines selected simultaneously can be defined as a column, and a column can be specified according to the column address CADD. The column control circuit 130 can control the bit line sensing amplifier connected to the predetermined number of bit lines based on the column address CADD.

[0059] In addition, the column control circuit 130 can perform a repair operation in response to a repair control signal C_REP specifying a cell block in which a defective column is set (hereinafter referred to as a "defective cell block"), to replace the data of the defective cell block with the data of the redundant cell block MBRED.

[0060] During a write operation, ECC engine 132 can generate an error correction code (ECC) using data D2 received from mapping circuit 160. Data D2 and the error correction code (ECC) output from ECC engine 132 can be transmitted to column control circuit 130 and written to memory cell MC. During a write operation, since only the error correction code (ECC) is generated without performing any error correction, the data D1 provided to ECC engine 132 and the data D2 output from ECC engine 132 can be the same. During a read operation, ECC engine 132 can receive data D1 and the error correction code (ECC) read from memory cell MC, and use the read error correction code (ECC) to correct errors in the read data D1 to output error-corrected data D2.

[0061] The repair control circuit 140 can store repair information R_INF for defective columns included in multiple cell blocks MB in the memory cell array 110, and generate a repair control signal C_REP based on the column address CADD and the stored repair information R_INF. The repair control circuit 140 can output the repair control signal C_REP for the specified defective cell block (i.e., the cell block containing the defective column) by comparing the column address CADD with the stored repair information R_INF. For example, when 16 cell blocks MB are arranged, and each cell block includes 128 columns, the column address CADD can consist of 14 bits, including 4 bits for specifying the cell block MB and 7 bits for specifying the column. When the repair information R_INF "00011000000" is stored and the column address CADD matching the repair information R_INF is input, the repair control circuit 140 can output a 5-bit repair control signal C_REP "1 0001", including 4 bits "0001" specifying the defective cell block and a validity bit "1" indicating that the repair control signal is valid. The repair control signal C_REP specifying the defective cell block can include information about the repair cell group.

[0062] The mapping control circuit 150 can generate a mapping control signal SEL based on the output selection signal OUT_OP, the row address RADD, and the repair control signal C_REP. The mapping control signal SEL is a signal used to select one of two adjacent normal cell groups and can consist of bits corresponding to half of the normal cell groups arranged in the memory cell array 110. The mapping control circuit 150 can generate the mapping control signal SEL based on the output selection signal OUT_OP and can selectively invert at least one bit of the mapping control signal SEL based on the repair control signal C_REP and the row address RADD. Specifically, the mapping control circuit 150 can set the bits of the mapping control signal SEL to all high bits or all low bits according to the output selection signal OUT_OP, and selectively invert the bits of the mapping control signal SEL corresponding to the repair cell group based on the repair control signal C_REP, which includes information about the repair cell group, and specific bits of the row address RADD, which specifies odd or even numbered word lines. (Refer to...) Figures 5 to 9B Describe the detailed configuration and operation of the mapping control circuit 150.

[0063] Mapping circuitry 160 can be disposed between ECC engine 132 and data input / output circuitry 180 to control the mapping between memory cell array 110 and multiple data pads DQ#. Mapping circuitry 160 can select one of two adjacent normal cell groups according to each bit of mapping control signal SEL and control the mapping between the selected cell group and the multiple data pads DQ#. For example, during a read operation, mapping circuitry 160 can map error-corrected data D2 provided from ECC engine 132 to data D3 according to mapping control signal SEL and transmit data D3 to data input / output circuitry 180. For example, during a write operation, mapping circuitry 160 can map data D3 transmitted from data input / output circuitry 180 to data D2 according to mapping control signal SEL and transmit data D2 to ECC engine 132. During a read operation, mapping circuitry 160 can map 128 bits of error-corrected data D2 to 64 bits of data D3.

[0064] Data input / output circuit 180 can receive data DIO from memory controller 200 or transmit data DIO to memory controller 200 via data pad DQ#. Data input / output circuit 180 may include data input circuit 180A and data output circuit 180B. Data input circuit 180A can receive data DIO as data D2 from memory controller 200 according to write command WT. Data input circuit 180A can transmit data D2 by converting data DIO with a burst length of 16 that is input in parallel via each data pad DQ#. Data output circuit 180B can transmit data D2 as data DIO read from memory cell array 110 according to read command RD to memory controller 200. Data output circuit 180B can transmit data DIO by serializing data D2 to a burst length of 16. Although in Figure 3 The data input / output circuit 180 is shown as one configuration, but the data input / output circuit 180 may include multiple data input / output units corresponding to the number of data pads DQ#.

[0065] Specific embodiments of this disclosure are described below with reference to the accompanying drawings.

[0066] Figure 5 It is shown Figure 3 The diagram shows an example of a data input / output path including the memory cell array 110 and the mapping circuit 160.

[0067] refer to Figure 5 In the storage cell array 110, the first normal cell blocks MB0 to the eighth normal cell blocks MB7, the redundant cell block MBRED, the ECC cell block MBECC, and the ninth normal cell blocks MB8 to the sixteenth normal cell blocks MB15 can be arranged sequentially along the row direction. During a read or write operation, each of the cell blocks MB0 to MB15, MBRED, and MBECC can input or output data in 8-bit units.

[0068] For reference Figure 4C The first normal cell block MB0 to the sixteenth normal cell block MB15 can form the first normal cell group MG0 to the eighth normal cell group MG7, while the redundant cell block MBRED and the ECC cell block MBECC can form an additional cell group MGX. However, this disclosure is not limited to this arrangement. In embodiments of this disclosure, the normal cell blocks MB8 to MB15, the redundant cell block MBRED, and the ECC cell block MBECC can be arranged in various ways, and in this case, the redundant cell block MBRED and the ECC cell block MBECC can form a single cell group.

[0069] The column control circuit 130 can perform a repair operation based on the repair control signal C_REP of a specified defective cell block. This repair operation replaces the data of the defective cell block with the data of the redundant cell block MBRED. Therefore, 128 bits of data D1 and 8 bits of error correction code ECC can be transmitted between the column control circuit 130 and the ECC engine 132. Furthermore, although the column control circuit 130 can control column selection and data direction based on the column address CADD, read command RD, and write command WT, descriptions of these operations are omitted for clarity of this disclosure.

[0070] ECC engine 132 can generate error-correcting codes (ECCs) using a parity-check matrix (also known as an H matrix), and can use the ECCs to correct errors in data D1. ECC engine 132 may include multiple parity-check matrix operation circuits (hereinafter referred to as "code operation circuits") based on cell blocks, and can perform error correction operations on a cell group basis. The code operation circuits can generate ECCs by applying known codes (such as BCH codes, Hamming codes, or Reed-Solomon (RS) codes), or they can apply other types of parity-check codes.

[0071] During a write operation, ECC engine 132 can perform matrix operations on the 64-bit data D2 received from mapping circuit 160 and a parity matrix to generate an 8-bit error-correcting code (ECC). During a read operation, ECC engine 132 can compare the matrix operation result of the 128-bit data D1 received from column control circuit 130 and the 8-bit ECC to generate a checksum, and can correct errors in data D1 based on the checksum to output 128-bit error-corrected data D2. Therefore, data D2 can be transmitted between ECC engine 132 and mapping circuit 160 in 16-bit units on a cell-group basis.

[0072] Furthermore, since the number of bits input to and output from ECC engine 132 differs between read and write operations, ECC engine 132 can use both the 64-bit data D2 received from mapping circuit 160 and the 64-bit data D1 read from memory cell array 110 to generate an error correction code (ECC) and correct errors in the 128-bit data D1 through a read-modify-write operation. Alternatively, ECC engine 132 can generate an error correction code (ECC) by performing zero-padding on the 64-bit data D2 and correct errors in data D1. Alternatively, two independent ECC engines can be deployed to independently perform error correction operations on the 64-bit data D1 output from one half of the cell group and the 64-bit data D1 output from the other half of the cell group.

[0073] The mapping circuit 160 may include first to fourth mappers 162 to 168, each corresponding to two adjacent normal cell groups. The first to fourth mappers 162 may correspond to bits of the mapping control signal SEL<3:0>, and can transmit data from one of the two adjacent cell groups based on the corresponding bit. For example, the first mapper 162 may correspond to the first normal cell group MG0 and the second normal cell group MG1 (or to the first normal cell block MB0 to the fourth normal cell block MB3), and can transmit data based on the first bit SEL of the mapping control signal SEL<3:0>. <0> One of the first normal cell group MG0 and the second normal cell group MG1 is selected to transfer data of the selected normal cell group between the ECC engine 132 and the data input / output circuit 180. Similarly, the third mapper 166 may correspond to the fifth normal cell group MG4 and the sixth normal cell group MG5 (or correspond to the ninth normal cell block MB8 to the twelfth normal cell block MB11), and may be based on the third bit SEL of the mapping control signal SEL<3:0>. <2> One of the fifth unit group MG4 and the sixth normal unit group MG5 is selected to transmit data of the selected normal unit group between the ECC engine 132 and the data input / output circuit 180. Therefore, the first mapper 162 to the fourth mapper 168 can map 128 bits of error-corrected data D2 received from the ECC engine 132 to 64 bits of data D3, thereby transmitting data D3 to the data input / output circuit 180, or can map 64 bits of data D3 received from the data input / output circuit 180 to 128 bits of data D2, thereby transmitting data D2 to the ECC engine 132.

[0074] The data input / output circuit 180 may include first data input / output units 182 to fourth data input / output units 188, each corresponding one-to-one with first mappers 162 to fourth mappers 168 and first data pads DQ0 to fourth data pads DQ3. Data input / output units 182 to 188 may, in response to a write command WT, receive data DIO from the memory controller 200 via the corresponding data pad and transmit it to the corresponding mapper; or, in response to a read command RD, they may transmit data D3 received from the corresponding mapper to the memory controller 200 via the corresponding data pad.

[0075] Figure 6 It is shown Figure 3 The detailed block diagram of the mapping control circuit 150 shown is shown. Figure 7 It is used to describe Figure 6 The table shows the operation of the repair group detector 152.

[0076] refer to Figure 6 The mapping control circuit 150 may include a repair group detector 152 and a switching determiner 154.

[0077] The repair group detector 152 can generate a preliminary control signal PRE_SEL<7:0> for a specified repair unit group based on the repair control signal C_REP<4:0> for a specified defective unit block. A repair unit group refers to a group of units that includes the defective unit block, and the repair control signal C_REP<4:0> can include information about the repair unit group. The preliminary control signal PRE_SEL<7:0> can be composed of bits corresponding to the first normal unit group MG0 to the eighth normal unit group MG7, respectively.

[0078] like Figure 7 As shown, the repair control signal C_REP<4:0> can consist of a 5-bit signal, including a block bit (MBB) specifying the defective block and a validity bit (VB) indicating whether the repair control signal is valid. When the validity bit (VB) is a low bit, the repair group detector 152 can generate a preliminary control signal PRE_SEL<7:0> with all low bits, regardless of the block bit (MBB). On the other hand, when the validity bit (VB) is a high bit, the repair group detector 152 can generate a preliminary control signal PRE_SEL<7:0> to specify a cell group that includes the block specified by the block bit (MBB). For example, if the validity bit (VB) is a high bit and the block bit (MBB) is set to "0000" (indicating that the first normal block MB0 is defective) or "0001" (indicating that the second normal block MB1 is defective), then the repair group detector 152 can generate a preliminary control signal PRE_SEL<7:0> as "0000 0001" to specify the first normal cell group MG0. For example, if the validity bit VD is a high bit and the cell block bit MBB is set to "0100" (indicating that the fifth normal cell block MB4 is defective) or "0101" (indicating that the sixth normal cell block MB5 is defective), then the repair group detector 152 can generate a preliminary control signal PRE_SEL<7:0> as "0000 0100" to specify the third normal cell group MG2.

[0079] The switching determinant 154 can generate a mapping control signal SEL<3:0> consisting of all high bits or all low bits based on the output option signal OUT_OP, and based on the preliminary control signal PRE_SEL<7:0> for the specified repair unit group or the specified odd numbered word line WLO or even numbered word line WLE of the row address RADD. <k>Selectively switch (i.e., invert) at least one bit of the mapping control signal SEL<3:0>.

[0080] In addition, although Figure 6 The repair group detector 152 is described as being included in the mapping control circuit 150, but in other embodiments, the repair group detector 152 may be included in the repair control circuit 140, and the preliminary control signal PRE_SEL<7:0> specifying the repair unit group may be provided as the repair control signal.

[0081] Figure 8 It is used to describe Figure 6 The flowchart shows the operation of the switching determinant 154. Figure 9A and Figure 9B It is for ease of description Figure 8 The table for operations.

[0082] refer to Figure 8 When the output option signal OUT_OP is logic high (H) ("Yes" in S110) and there is no repair unit group ("No" in S120), the toggle determinant 154 can set the mapping control signal SEL<3:0> to "1111" (in S130) (see Figure 9A (Case 1) For reference, when the input corresponds to the preliminary control signal PRE_SEL<7:0> with all low bits, the switching determiner 154 can determine that there is no repair unit group. The mapping circuit 160 can select even-numbered unit groups MG1, MG3, MG5 and MG7 from the first normal unit group MG0 to the eighth normal unit group MG7 based on the mapping control signal SEL<3:0> of "1111".

[0083] When the output option signal OUT_OP is logic high ("Yes" in S110) and a repair unit group exists ("Yes" in S120), the switching determiner 154 can determine, based on the preliminary control signal PRE_SEL<7:0>, whether the repair unit group is included in the odd-numbered unit groups MG0, MG2, MG4, and MG6, or in the even-numbered unit groups MG1, MG3, MG5, and MG7 (in S140). When the repair unit group is in the odd-numbered unit group ("ODD_MG" in S140), the switching determiner 154 can set the mapping control signal SEL<3:0> to "1111" (in S130) (see [link]). Figure 9A Case 2).

[0084] When the repair unit group is located in the even-numbered unit group ("EVEN_MG" in S140), the switching determiner 154 can verify a specific bit of the row address RADD. <k>This specifies whether to use odd-numbered word lines (WLO) or even-numbered word lines (WLE) (in S150). For example, when a specific bit is RADD... <k>When the bit is a high bit, the switching determinant 154 can determine the specific bit RADD. <k>Specify odd-numbered word lines WLO, while a specific bit RADD... <k>When the bit is low, the switching determinant 154 can determine the specific bit RADD. <k>Specify the even-numbered word line WLE. When the even-numbered word line WLE is specified ("EVEN_WL" in S150), the toggle determiner 154 can set the mapping control signal SEL<3:0> to "1111" (in S130) (see...). Figure 9A (The upper part of case 3 in the middle). Conversely, when the odd-numbered word line WLO is specified ("ODD_WL" in S150), the switching determinant 154 can switch (i.e., invert) the bit corresponding to the repair unit group in the bit of the mapping control signal SEL<3:0> to the low bit (in S160) (see Figure 9A (The lower part of case 3). For example, when the repair unit group is the second normal unit group MG1, the switching determinant 154 can generate the mapping control signal SEL<3:0> as "1110".

[0085] According to one embodiment, when the repair unit group is an even-numbered unit group adjacent to the additional unit group MGX, the switching determiner 154 may not invert the bits corresponding to the repair unit group. That is, when the repair unit group is the fourth normal unit group MG3, the switching determiner 154 may generate a mapping control signal SEL<3:0> as "1111" or "1101".

[0086] Furthermore, when the output option signal OUT_OP is logic low ("No" in S110) and there is no repair unit group ("No" in S122), the switching determinant 154 can set the mapping control signal SEL<3:0> to "0000" (at S132) (see [link]). Figure 9B In case 1), the mapping circuit 160 can select the odd-numbered unit groups MG0, MG2, MG4 and MG6 from the first normal unit group MG0 to the eighth normal unit group MG7 based on the mapping control signal SEL<3:0> of "0000".

[0087] When the output option signal OUT_OP is logic low ("No" in S110) and a repair unit group exists ("Yes" in S122), the switching determiner 154 can determine, based on the preliminary control signal PRE_SEL<7:0>, whether the repair unit group is included in the odd-numbered unit groups MG0, MG2, MG4, and MG6, or in the even-numbered unit groups MG1, MG3, MG5, and MG7 (in S170). When the repair unit group is in an even-numbered unit group ("EVEN_MG" in "Repair Unit Group?" in S170), the switching determiner 154 can set the mapping control signal SEL<3:0> to "0000" (in S132) (see [link]). Figure 9B Case 2). When the repair unit group is located in an odd-numbered unit group ("ODD_MG" in S170), the switching determiner 154 can determine the specific bit of the row address RADD. <k>This specifies whether to specify the odd-numbered word line WLO or the even-numbered word line WLE (in S180). When the odd-numbered word line WLO is specified ("ODD_WL" in S180), the toggle determiner 154 can set the mapping control signal SEL<3:0> to "0000" (in S132) (see...). Figure 9B (See the lower part of case 3). Conversely, when the even-numbered word line WLE is specified ("EVEN_WL" in S180), the switching determinant 154 can switch (i.e., invert) the bit corresponding to the repair unit group in the bit of the mapping control signal SEL<3:0> to the low bit (in S190) (see Figure 9B (The upper part of case 3). For example, when the repair unit group is the third normal unit group MG2, the switching determinant 154 can generate the mapping control signal SEL<3:0> as "0010".

[0088] According to one embodiment, when the repair unit group is an odd-numbered unit group adjacent to the extra unit group MGX, the switching determiner 154 may not invert the bits corresponding to the repair unit group. That is, when the repair unit group is the fifth normal unit group MG4, the switching determiner 154 may generate the mapping control signal SEL<3:0> as "0000" or "0100".

[0089] Below, for reference Figures 6 to 9B The operation of the mapping circuit 160 according to the mapping control signal SEL<3:0> will be described.

[0090] Figures 10A to 10C A diagram illustrating the mapping operation of the prior art and embodiments of this disclosure when the output option signal OUT_OP is logic high. Figures 10A to 10C The image shows an example of repairing a defective column included in the fourth normal cell block MB3 of the second normal cell group MG1 during a read operation.

[0091] refer to Figure 10A A comparative example of the prior art is shown, in which the mapping circuit 160 operates in response to the logic high level output option signal OUT_OP when the odd number word line WLO is specified by the row address RADD.

[0092] In the prior art, the mapping circuit 160 selects even-numbered cell groups MG1, MG3, MG5, and MG7 in response to a logic high-level output option signal OUT_OP. Therefore, 64 bits of error-correcting data output from even-numbered cell groups MG1, MG3, MG5, and MG7 can be output through the data pads.

[0093] At this time, if a defect occurs in the subword line driver F_SWD shared between the fourth normal unit group MG3 and the additional unit group MGX, erroneous bits may appear in the four unit blocks (e.g., MB6, MB7, MBRED, and MBECC) served by the shared defective subword line driver F_SWD. Due to the erroneous bits in the ECC unit block MBECC, miscorrection may occur in the ECC engine 132. Therefore, in addition to the erroneous bits in the data output from the fourth normal unit group MG3 (①) and the data output from the second normal unit group MG1 repaired by the redundant unit block MBRED (②), erroneous bits may also appear in the data output from the sixth normal unit group MG5 (③) due to miscorrection. These erroneous bits are output through three independent data pads and may exceed the error correction capability of the memory controller 200.

[0094] refer to Figure 10B According to an embodiment of the present disclosure, the operation of the mapping circuit 160 is shown, wherein the odd-numbered word line WLO is specified by the row address RADD, and the output option signal OUT_OP is logic high.

[0095] For reference Figures 6 to 9B As stated above, when the output option signal OUT_OP is at a logic high level and the odd-numbered word line WLO is specified, since the second normal unit group MG1 (i.e., the even-numbered group) is the repair unit group, the mapping control circuit 150 can generate the mapping control signal SEL<3:0> of "1110". Therefore, the second mapper 164 to the fourth mapper 168 can select and output data from the even-numbered unit groups MG3, MG5, and MG7. Conversely, the first mapper 162 can select and output data from the first normal unit group MG0 (which is the odd-numbered unit group), instead of the data from the second normal unit group MG1. That is, in the embodiments of this disclosure, even if a defect occurs in the sub-word line driver F_SWD shared between the fourth normal unit group MG3 and the additional unit group MGX, resulting in erroneous bits in the four unit blocks MB6, MB7, MBRED, and MBECC, the erroneous bits in the data (②) output from the repaired second normal unit group MG1 can be eliminated.

[0096] Therefore, in the embodiments of this disclosure, due to the miscorrection of the ECC engine 132, erroneous bits may only appear in the data output from the fourth normal unit group MG3 (①) and the data output from the sixth normal unit group MG5 (③). These erroneous bits are output through two independent data pads and can be covered by the error correction capability of the memory controller 200.

[0097] In addition, refer to Figure 10C This illustrates the operation of the mapping circuit 160 when the row address RADD specifies an even-numbered word line WLE and the output option signal OUT_OP is logic high.

[0098] When a defect occurs in the subword line driver F_SWD shared between the extra cell group MGX and the fifth normal cell group MG4, erroneous bits may appear in the four cell blocks MBRED, MBECC, MB8, and MB9 served by the defective shared subword line driver F_SWD. In this case, since no data is output from the fifth normal cell group MG4, which includes the ninth normal cell block MB8 and the tenth normal cell block MB9, erroneous bits may appear in the data output from the repaired second normal cell group MG1 (②) and the data output from the sixth normal cell group MG5 (③) due to miscorrection. These erroneous bits are output through two independent data pads and can be covered by the error correction capability of the memory controller 200.

[0099] Figures 11A to 11C A diagram illustrating the mapping operation of the prior art and embodiments of this disclosure when the output option signal OUT_OP is logic low. Figures 11A to 11C The image shows an example of repairing defective columns included in the second normal cell block MB1 of the first normal cell group MG0 during a read operation.

[0100] refer to Figure 11A An example of the prior art is shown, in which the mapping circuit 160 operates in response to the logic low-level output option signal OUT_OP when the even-numbered word line WLE is specified by the row address RADD.

[0101] In the prior art, the mapping circuit 160 selects the odd-numbered cell groups MG0, MG2, MG4, and MG6 in response to a logic low-level output option signal OUT_OP. As a result, 64 bits of error-corrected data can be output from the odd-numbered cell groups MG0, MG2, MG4, and MG6 via data pads.

[0102] At this point, if a defect occurs in the subword line driver F_SWD shared between the fifth normal cell group MG4 and the additional cell group MGX, erroneous bits may appear in the four cell blocks (e.g., MBRED, MBECC, MB8, and MB9) served by this defective shared subword line driver F_SWD. Due to the erroneous bits in the ECC cell block MBECC, miscorrection may occur in the ECC engine 132. Therefore, in addition to the erroneous bits in the data output from the fifth normal cell group MG4 (①) and the data output from the first normal cell group MG0 (②) repaired by the redundant cell block MBRED, erroneous bits may also appear in the data output from the third normal cell group MG2 (③) due to miscorrection. These erroneous bits are output through three independent data pads and may exceed the error correction capability of the memory controller 200.

[0103] refer to Figure 11B According to an embodiment of the present disclosure, the operation of the mapping circuit 160 is shown, wherein the even-numbered word line WLE is specified by the row address RADD, and the output option signal OUT_OP is logic low.

[0104] For reference Figures 6 to 9B As stated above, when the output option signal OUT_OP is logic low and the even-numbered word line WLE is specified, since the first normal unit group MG0 (i.e., the odd-numbered group) is the repair unit group, the mapping control circuit 150 can generate the mapping control signal SEL<3:0> of "0001". Therefore, the second mapper 164 to the fourth mapper 168 can select and output data from the odd-numbered unit groups MG2, MG4 and MG6. Conversely, the first mapper 162 can select and output data from the second normal unit group MG0 (which is the even-numbered group), instead of the data from the first normal unit group MG0. That is, in the embodiments of this disclosure, even if a defect occurs in the sub-word line driver F_SWD shared between the fifth normal unit group MG4 and the additional unit group MGX, resulting in erroneous bits in the four unit blocks MBRED, MBECC, MB8 and MB9, the erroneous bits in the data (②) output from the repaired first normal unit group MG0 can be eliminated.

[0105] Therefore, in the embodiments of this disclosure, due to the miscorrection of the ECC engine 132, erroneous bits may only appear in the data output from the fifth normal unit group MG4 (①) and the data output from the third normal unit group MG2 (③). These erroneous bits are output through two independent data pads and can be covered by the error correction capability of the memory controller 200.

[0106] In addition, refer to Figure 11C This illustrates the operation of the mapping circuit 160 when the row address RADD specifies an odd-numbered word line WLO and the output option signal OUT_OP is logic low.

[0107] When a defect occurs in the subword line driver F_SWD shared between the fourth normal cell group MG3 and the additional cell group MGX, erroneous bits may appear in the four cell blocks MB6, MB7, MBRED, and MBECC served by the defective shared subword line driver F_SWD. In this case, since no data is output from the fourth normal cell group MG3, which includes the seventh normal cell block MB6 and the eighth normal cell block MB7, erroneous bits may appear in the data output from the repaired first normal cell group MG0 (②) and the data output from the third normal cell group MG2 (③) due to miscorrection. These erroneous bits are output through two independent data pads and can be covered by the error correction capability of the memory controller 200.

[0108] As described above, in one embodiment of this disclosure, the storage device 100 may include multiple mappers corresponding to odd-numbered normal cell groups and even-numbered normal cell groups, respectively. The storage device 100 may identify the target cell group from the odd-numbered and even-numbered cell groups based on the output option signal OUT_OP. The storage device 100 may determine whether a repair cell group exists in the target cell group based on the preliminary control signal PRE_SEL<7:0>, and may determine whether any target cell group shares the subword line driver SWD with the additional cell group MGX based on the row address RADD. When a repair cell group exists in the target cell group, and the target cell group also contains cell groups that share the subword line driver SWD with the additional cell group MGX, the storage device 100 may control the mapper corresponding to the repair cell group to select a different cell group instead of the repair cell group.

[0109] For example, when the even-numbered normal cell group is targeted based on the output option signal OUT_OP, and both the repair cell group and the cell group sharing the subword line driver SWD with the additional cell group MGX are included in the even-numbered normal cell group, the mapper corresponding to the repair cell group can be controlled to select the odd-numbered normal cell group, and the remaining mappers can be controlled to select the even-numbered normal cell group. Alternatively, when the odd-numbered normal cell group is identified based on the output option signal OUT_OP, and both the repair cell group and the cell group sharing the subword line driver SWD with the additional cell group MGX are included in the odd-numbered normal cell group, the mapper corresponding to the repair cell group can be controlled to select the even-numbered normal cell group, and the remaining mappers can be controlled to select the odd-numbered normal cell group.

[0110] Therefore, the storage device 100 prevents uncorrectable errors (UEs) from occurring by limiting the maximum number of erroneous bits caused by defective subword line drivers to within the error correction capability of the memory controller 200.

[0111] Figure 12 This is a block diagram illustrating a storage system 2000 including a storage module 2100 according to an embodiment of the present disclosure.

[0112] refer to Figure 12 The storage system 2000 may include a storage module 2100 and a memory controller 2200.

[0113] The memory controller 2200 can control the operation of the storage system 2000 and control the data transmission between the host 2300 and the storage module 2100. The memory controller 2200 can generate a command / address signal C / A based on a request REQ from the host 2300, provide the command / address signal C / A to the storage module 2100, provide the data DIO corresponding to the request REQ from the host 2300 to the storage module 2100, and provide the data DIO read from the storage module 2100 to the host 2300. The memory controller 2200 may include an error correction code (ECC) engine 2210. The ECC engine 2210 can detect and correct errors in the data DIO read from the storage module 2100 and provide error-corrected data to the host 2300. When the number of error bits in the data DIO exceeds the error correction capability of the ECC engine 2210, the memory controller 2200 can notify the host 2300 that an uncorrectable error (UE) has occurred.

[0114] Storage module 2100 may include a plurality of storage devices 2100_0 to 2100_10. Each of the storage devices 2100_0 to 2100_10 may include an error correction code (ECC) engine 2110. Each of the storage devices 2100_0 to 2100_10 may correspond to Figure 3 The storage device 100 described herein. In one embodiment of this disclosure, each of the storage devices 2100_0 to 2100_10 may include components such as those described above with respect to this disclosure, including: a storage cell array comprising a plurality of normal cell blocks, redundant cell blocks, and ECC cell blocks, wherein adjacent cell blocks in the normal cell blocks form a plurality of normal cell groups, and the redundant cell blocks and ECC cell blocks form additional cell groups; a mapping circuit comprising a plurality of mappers, each mapper corresponding to a pair of normal cell groups, and selecting one of the normal cell groups included therein based on a corresponding bit of a mapping control signal; and a mapping control circuit that identifies a target cell group from which data is to be output within the normal cell groups according to (e.g., based on) an output option signal, and controls the corresponding bit of the mapping control signal to have different values ​​by detecting whether a repair cell group is included in the target cell group and whether a cell group sharing a subword line driver with the additional cell group is also included in the target cell group. Therefore, the number of error bits that may occur due to defective subword line drivers can be limited within the error correction capability of the memory controller, thereby preventing uncorrectable errors (UEs).

[0115] Figure 13 This is a block diagram illustrating a storage system 3000 including a stacked storage device 3110 according to an embodiment of the present disclosure.

[0116] refer to Figure 13 The storage system 3000 may include a packaging substrate 3140, an interposer 3130, a stacked storage device 3110, and a processor 3120.

[0117] The packaging substrate 3140 may include a printed circuit board (PCB). The packaging substrate 3140 may be electrically connected to an external system board, motherboard, or module board via bumps.

[0118] Interposer 3130 may be formed on package substrate 3140. Interposer 3130 may be a silicon substrate with only wiring formed thereon.

[0119] Stacked storage device 3110 and processor 3120 can be formed on interposer layer 3130. Stacked storage device 3110 and processor 3120 can be disposed on interposer layer 3130 spaced apart from each other. Although Figure 13 A stacked storage device 3110 is shown, but embodiments of the present disclosure are not limited thereto, and one or more stacked storage devices may be formed around the processor 3120 on the intermediary layer 3130.

[0120] Processor 3120 may include a memory controller (MC) 3121 and a physical interface circuit (PHY) 3122. The memory controller 3121 may be configured to control the stacked storage device 3110. The physical interface circuit 3122 may interface between the memory controller 3121 and the stacked storage device 3110. The physical interface circuit 3122 may be an interface circuit that converts signals transmitted from the memory controller 3121 into signals suitable for use in the stacked storage device 3110, and vice versa. Processor 3120 may be one of various processors, such as a microprocessor unit (MPU), a central processing unit (CPU), a general-purpose processing unit (GPU), and a host processing unit (HPU).

[0121] The stacked memory device 3110 may include a lower chip 3114 and one or more upper chips 3112 vertically stacked on an interposer layer 3130. As described above, an example of the stacked memory device 3110 formed by stacking multiple chips may be a high-bandwidth memory (HBM). A through-silicon via (TSV) is formed between the lower chip 3114 and the upper chip 3112, through which signals (i.e., commands, addresses, and data) can be transmitted between the chips.

[0122] The lower chip 3114 may include a physical interface circuit (PHY) 3116 for interfacing with the memory controller 3121. Each upper chip 3112 may correspond to... Figure 3 The storage device 100 described herein. Specifically, each on-chip 3112 may include: a memory cell array comprising multiple normal cell blocks, redundant cell blocks, and ECC cell blocks, wherein adjacent normal cell blocks within the normal cell blocks form multiple normal cell groups, while the redundant cell blocks and ECC cell blocks form additional cell groups; a mapping circuit comprising multiple mappers, each mapper corresponding to a pair of normal cell groups, and selecting one of the included normal cell groups based on corresponding bits of a mapping control signal; and a mapping control circuit that identifies the target cell group for output data within the normal cell groups according to an output option signal, and controls the corresponding bits of the mapping control signal to have different values ​​by detecting whether a repair cell group is included in the target cell group, and whether a cell group sharing a subword line driver with the additional cell groups is also included in the target cell group. Therefore, the number of error bits that may occur due to a defective subword line driver can be limited within the error correction capability of the memory controller, thereby preventing uncorrectable errors (UEs).

[0123] Figure 14 This is a block diagram illustrating a mobile system 4000 including a storage device 4200 according to an embodiment of the present disclosure.

[0124] refer to Figure 14 The mobile system 4000 may include an application processor (AP) 4100, a storage device 4200, a network device 4300, a memory device 4400, and a user interface 4500.

[0125] The application processor 4100 can drive components, operating systems (OS), or user programs included in the mobile system 4000. For example, the application processor 4100 can be provided as a system-on-a-chip (SoC).

[0126] Storage device 4200 can operate as main memory, operational memory, buffer memory, or cache memory of mobile system 4000. Storage device 4200 may include volatile random access memory (such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, Low Power Double Data Rate 3 Synchronous Dynamic Random Access Memory (LPDDR3 SDRAM)) or non-volatile random access memory (such as phase-change RAM (PRAM), resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric RAM (FRAM), etc.). According to one embodiment, storage device 4200 may be configured as a reference... Figure 12 The storage system described is 2000.

[0127] In one embodiment of this disclosure, the storage device 4200 may correspond to Figure 3 The storage device 100 described herein. Specifically, the storage device 4200 may include: a storage cell array comprising a plurality of normal cell blocks, redundant cell blocks, and ECC cell blocks, wherein adjacent normal cell blocks within the normal cell blocks form a plurality of normal cell groups, while the redundant cell blocks and ECC cell blocks form additional cell groups; a mapping circuit comprising a plurality of mappers, each mapper corresponding to a pair of normal cell groups, and selecting one of the included normal cell groups based on corresponding bits of a mapping control signal; and a mapping control circuit that identifies a target cell group for outputting data within the normal cell groups according to an output option signal, and controls corresponding bits of the mapping control signal to have different values ​​by detecting whether a repair cell group is included in the target cell group, and whether a cell group sharing a sub-word line driver with the additional cell group is also included in the target cell group. Therefore, the number of error bits that may occur due to a defective sub-word line driver can be limited within the error correction capability of the memory controller, thereby preventing uncorrectable errors (UEs). According to one embodiment, the storage device 4200 may be configured with a reference... Figure 12 The storage system described is 2000.

[0128] Network device 4300 can communicate with external devices. For example, network device 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), Global Microwave Access Interoperability (WiMAX), Wireless Local Area Network (WLAN), Ultra Wideband (UWB), Bluetooth, Wi-Fi, etc. For example, network device 4300 may be included in application processor 4100.

[0129] Memory device 4400 can store data. For example, memory device 4400 can store data received from application processor 4100. Alternatively, memory device 4400 can transfer stored data to application processor 4100. For example, memory device 4400 can be implemented as a non-volatile semiconductor memory device, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or NAND flash memory (e.g., 3D NAND flash memory).

[0130] Although embodiments of the present disclosure have been described in conjunction with specific examples, those skilled in the art will understand that various modifications and improvements can be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. Furthermore, these embodiments can be combined to form additional embodiments.< / k> < / k> < / k> < / k> < / k> < / k> < / k>

Claims

1. A storage device, comprising: A storage cell array comprising multiple cell groups, each cell group comprising adjacent cell blocks in multiple cell blocks and alternately sharing a subword line driver with adjacent cell groups; A mapping control circuit that: generates a mapping control signal based on an output option signal, and selectively inverts at least one bit of the mapping control signal based on a row address and a repair control signal including information about the repair unit group among the plurality of unit groups; and A mapping circuit that: selects one of two adjacent cell groups based on the corresponding bits of the mapping control signal; and maps the selected cell group to multiple data pads.

2. The storage device according to claim 1, wherein, The mapping control circuit sets the corresponding bit of the mapping control signal to all high bits or all low bits according to the output option signal, and selectively inverts the bit corresponding to the repair unit group based on the specific bit of the row address and the repair control signal, wherein the specific bit of the row address specifies the odd number word line or the even number word line.

3. The storage device according to claim 1, wherein, In a configuration where the data bus width is set to ×4, the output option signal is provided externally to identify half of the plurality of cell blocks.

4. The storage device according to claim 1, wherein, The mapping control circuit includes: Repair group detector, which: generates a preliminary control signal specifying the repair unit group based on the repair control signal; and A switching determiner that: sets the corresponding bit of the mapping control signal to all high bits or all low bits according to the output option signal, and selectively inverts the bit corresponding to the repair unit group based on a specific bit of the row address and the repair control signal, wherein the specific bit of the row address specifies an odd number word line or an even number word line.

5. The storage device according to claim 1, further comprising a repair control circuit, the repair control circuit: storing repair information regarding defect columns included in the plurality of cell blocks; and comparing column addresses with the stored repair information to generate the repair control signal.

6. The storage device according to claim 1, in, The plurality of cell blocks includes: first to fourth n normal cell blocks, redundant cell blocks, and ECC cell blocks arranged along a first direction, where n is an integer greater than or equal to 1, and ECC refers to error correction code. In this configuration, adjacent normal cell blocks in the first to the fourth n normal cell blocks are grouped to form the first to the second n normal cell groups, and the redundant cell blocks and the ECC cell blocks are grouped to form additional cell groups.

7. The storage device according to claim 6, wherein, The mapping control circuit: Based on the output option signal, n normal unit groups are identified from the first to the 2n normal unit groups; as well as Based on the repair control signal and the row address, it is detected that the repair unit group is included in the n normal unit groups, and one of the n normal unit groups shares the subword line driver with the additional unit group to invert the bit in the mapping control signal corresponding to the repair unit group.

8. The storage device according to claim 6, wherein, The mapping circuit includes: a first to an nth mapper corresponding to two adjacent normal unit groups, each mapper selecting one of the two adjacent normal unit groups based on the corresponding bit of the mapping control signal.

9. The storage device according to claim 6, wherein, The first to nth normal unit groups, the additional unit groups, and the (n+1)th to 2nth normal unit groups are arranged sequentially along the first direction.

10. The storage device according to claim 6, further comprising: A column control circuit, which, based on the repair control signal, replaces the defective columns included in the first to the 4n normal cell blocks with redundant columns of the redundant cell blocks; and The ECC engine corrects errors in the data output from the first to the 4n normal cell blocks based on the ECC output from the ECC cell block. The mapping circuit is disposed between the ECC engine and the plurality of data pads.

11. The storage device according to claim 1, wherein, Each of the plurality of unit groups includes: The first word line, which shares the first sub-word line driver among the sub-word line drivers with the adjacent unit group in the first direction; and The second word line alternates with the first word line in a second direction intersecting the first direction, and shares the second sub-word line driver among adjacent unit groups in the opposite direction to the first direction.

12. A storage device, comprising: A storage cell array comprising multiple normal cell blocks, redundant cell blocks, and ECC cell blocks, wherein adjacent normal cell blocks are grouped to form multiple normal cell groups, the redundant cell blocks and ECC cell blocks are grouped to form additional cell groups, and each cell group alternately shares a subword line driver with adjacent cell groups, where ECC refers to error correction code. A mapping circuit includes a plurality of mappers, each mapper corresponding to a pair of normal unit groups among a plurality of normal unit groups, each mapper selecting one of the paired normal unit groups based on a corresponding bit of a mapping control signal; and The mapping control circuit, which is: The target unit group is identified among the plurality of normal unit groups based on the output option signal, and The detection of a repair unit group included in the target unit group, and a unit group sharing the sub-word line driver with the additional unit group included in the target unit group, to set the bits of the mapping control signal to have different values.

13. The storage device according to claim 12, wherein, The paired normal unit groups include: odd-numbered normal unit groups and even-numbered normal unit groups arranged adjacent to each other.

14. The storage device according to claim 13, wherein, When a identifies the even-numbered normal unit group based on the output option signal, and b shares the sub-word line driver with the additional unit group, and the repair unit group is included in the even-numbered normal unit group, the mapping control circuit: Control the mapper among the plurality of mappers corresponding to the repair unit group to select the odd-numbered normal unit group; as well as Control the remaining mappers among the plurality of mappers to select the even-numbered normal unit group.

15. The storage device according to claim 13, wherein, When a identifies the odd-numbered normal unit group based on the output option signal, and b shares the unit group of the sub-word line driver and the repair unit group included in the odd-numbered normal unit group, the mapping control circuit: Control the mapper among the plurality of mappers that corresponds to the repair unit group to select the even-numbered normal unit group; as well as Control the remaining mappers among the plurality of mappers to select the odd-numbered normal unit group.

16. The storage device according to claim 12, further comprising: A column control circuit, which: based on a repair control signal, replaces defective columns included in the plurality of normal cell blocks with redundant columns of the redundant cell blocks; and The ECC engine corrects errors in the data output from the plurality of normal unit blocks based on the error correction codes output from the ECC unit blocks. The mapping circuit is located between the ECC engine and multiple data pads.

17. A storage system, comprising: At least one storage device; as well as A memory controller that controls the operation of the at least one memory device. Wherein, the at least one storage device includes: A storage cell array comprising multiple cell groups, each cell group comprising adjacent cell blocks in multiple cell blocks, and sharing a subword line driver alternately with adjacent cell groups; A mapping control circuit that: generates a mapping control signal based on an output option signal, and selectively inverts at least one bit of the mapping control signal based on a row address and a repair control signal including information about the repair unit group in the plurality of unit groups; and A mapping circuit that: selects one of two adjacent cell groups based on the corresponding bits of the mapping control signal; and maps the selected cell group to multiple data pads.

18. The storage system according to claim 17, wherein, Each of the at least one storage device and the memory controller includes an ECC engine, where ECC stands for Error Correction Code.

19. The storage system according to claim 17, in, The plurality of unit blocks includes: first to fourth n normal unit blocks, redundant unit blocks, and ECC unit blocks arranged along a first direction, where ECC refers to error correction code, n is an integer greater than or equal to 1, and In this configuration, adjacent normal cell blocks in the first to the fourth n normal cell blocks are grouped to form the first to the second n normal cell groups, and the redundant cell blocks and the ECC cell blocks are grouped to form additional cell groups.

20. The storage system according to claim 19, wherein, The mapping control circuit: Based on the output option signal, n normal unit groups are identified from the first to the 2n normal unit groups; as well as Based on the repair control signal and the row address, it is detected that the repair unit group is included in the n normal unit groups, and one of the n normal unit groups shares the subword line driver with the additional unit group to invert a bit in the mapping control signal corresponding to the repair unit group.

21. The storage system according to claim 19, wherein, The mapping circuit includes: a first to an nth mapper corresponding to two adjacent normal unit groups, each mapper selecting one of the two adjacent normal unit groups based on the corresponding bit of the mapping control signal.

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