Memory, storage system, and operating method of storage system performing training operation

Abstract

A memory, a storage system, and an operating method of a storage system performing a training operation are provided. The memory includes a first detector configured to continuously detect a logic level of a chip select signal in synchronization with a first clock, a second detector configured to continuously detect the logic level of the chip select signal in synchronization with a second clock having a phase opposite to a phase of the first clock, and a pass / fail determination circuit configured to determine the training operation as a pass when the logic level continuously detected by the first detector and the logic level continuously detected by the second detector are different from each other.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0043517, filed with the Korean Intellectual Property Office on April 3, 2025, and Korean Patent Application No. 10-2025-0105216, filed with the Korean Intellectual Property Office on July 31, 2025, which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of this disclosure relate to memory, and more particularly to a memory for performing training operations. Background Technology

[0004] For the memory to function properly, training operations related to the input and output of various signals need to be performed. These training operations are typically executed after the initial memory operations begin. Only when the training operations are executed correctly can the input and output operations of signals proceed stably in subsequent memory operations. Summary of the Invention

[0005] In one embodiment, the memory may include: a first detector configured to continuously detect the logic level of a chip select signal in synchronization with a first clock; a second detector configured to continuously detect the logic level of the chip select signal in synchronization with a second clock having a phase opposite to that of the first clock; and pass / fail (pass / fail) determination circuitry configured to determine that a training operation is pass when the logic levels continuously detected by the first detector and the logic levels continuously detected by the second detector are different from each other.

[0006] In one embodiment, the method of operating the storage system may include: transmitting a clock from a memory controller to a memory; setting the memory to a first mode; toggling a chip select signal transmitted from the memory controller to the memory; having the memory detect the logic level of the chip select signal N times on even-numbered rising edges of the clock, where N is an integer greater than or equal to 2; having the memory detect the logic level of the chip select signal N times on odd-numbered rising edges of the clock; and when the logic level of the chip select signal is detected as high N times on even-numbered rising edges and as low N times on odd-numbered rising edges, the memory determines that the training in the first mode is qualified.

[0007] In one embodiment, the storage system may include: a memory controller configured to transmit a clock and a chip select signal; and a memory configured to receive the clock and the chip select signal, and to transmit the training result to the memory controller by detecting the logic level of the chip select signal N times on the even rising edge of the clock and N times on the odd rising edge of the clock, where N is an integer greater than or equal to 2. Attached Figure Description

[0008] Figure 1 This is a structural diagram of a memory 100 according to an embodiment of the present disclosure.

[0009] Figure 2 It is based on Figure 1 The diagram shows a structural diagram of one embodiment of the first detector 110.

[0010] Figure 3 It is based on Figure 1 The diagram shows a structural diagram of one embodiment of the pass / fail determination circuit 130.

[0011] Figure 4 and Figure 5 It is based on Figures 1 to 3 The timing diagram shows the chip selection training operation of the memory 100.

[0012] Figure 6 It is based on Figure 1 A structural diagram of another embodiment of the pass / fail determination circuit 130 shown.

[0013] Figure 7 This is a timing diagram of the chip selection training operation failure area of ​​memory 100.

[0014] Figure 8 This is a structural diagram of a storage system 800 according to an embodiment of the present disclosure. Detailed Implementation

[0015] Various embodiments of the technical spirit of this disclosure will now be described in conjunction with the accompanying drawings.

[0016] The embodiments of this disclosure can provide a technique capable of stably performing training operations on a memory.

[0017] According to various embodiments of this disclosure, a technique capable of stably performing training operations on a memory can be provided.

[0018] Figure 1 This is a structural diagram of a memory 100 according to an embodiment of the present disclosure. Figure 1 The components in memory 100 related to chip selection training (CST) operation are shown.

[0019] like Figure 1 As shown, the memory 100 may include a chip selection receiving circuit 101, a clock receiving circuit 103, a frequency divider 105, a first detector 110, a second detector 120, and a pass / fail (pass / fail) determination circuit 130.

[0020] The chip select receiving circuit 101 can receive the chip select signal CS_I from the chip select terminal CS. The chip select receiving circuit 101 can determine the logic level of the chip select signal CS_I by determining whether the voltage level of the chip select terminal CS is greater than or less than the voltage level of the chip select reference voltage VREFCS.

[0021] Clock receiving circuit 103 can receive clock CLK from clock terminal CLK. Frequency divider 105 can generate a first clock RCLK and a second clock FCLK by dividing clock CLK by two. The frequency of each of the first clock RCLK and the second clock FCLK is 1 / 2 (half) of the frequency of clock CLK. The rising edge of the first clock RCLK can be aligned with the even-numbered rising edge of clock CLK. The rising edge of the second clock FCLK can be aligned with the odd-numbered rising edge of clock CLK. That is, the first clock RCLK and the second clock FCLK can have opposite phases.

[0022] The first detector 110 can continuously detect the level of the chip select signal CS_I synchronously with the first clock RCLK (e.g., repeatedly sampling and checking the logic level of the signal over multiple clock cycles). The first detector 110 can continuously detect the logic level of the chip select signal CS_I at the rising edge of the first clock RCLK and output detection results R_ALL_H and R_ALL_L. The first all-high signal R_ALL_H can be a signal indicating that the logic level of the chip select signal CS_I is detected as high N times consecutively at the rising edge of the first clock RCLK (N is an integer greater than or equal to 2). The first all-low signal R_ALL_L can be a signal indicating that the logic level of the chip select signal CS_I is detected as low N times consecutively at the rising edge of the first clock RCLK.

[0023] The second detector 120 can continuously detect the level of the chip select signal CS_I synchronously with the second clock FCLK. The second detector 120 can continuously detect the logic level of the chip select signal CS_I on the rising edge of the second clock FCLK and can output detection results F_ALL_H and F_ALL_L. The second all-high signal F_ALL_H can be a signal indicating that the logic level of the chip select signal CS_I has been detected as high N times consecutively on the rising edge of the second clock FCLK. The second all-low signal F_ALL_L can be a signal indicating that the logic level of the chip select signal CS_I has been detected as low N times consecutively on the rising edge of the second clock FCLK.

[0024] The pass / fail determination circuit 130 can determine whether the chip selection training (CST) operation is pass or fail based on the detection results R_ALL_H and R_ALL_L of the first detector 110 and the detection results F_ALL_H and F_ALL_L of the second detector 120. The activation of both the high pass signal H_PASS and the low pass signal L_PASS of the pass / fail determination circuit 130 indicates that the CST operation is pass.

[0025] The CST operation is a training operation in which the chip select signal CS_I, transmitted from the memory controller to the memory 100, is activated N times within 2N cycles of clock CLK (i.e., N cycles based on the first clock RCLK and N cycles based on the second clock FCLK), and the logic level of the chip select signal CS_I is checked to ensure accurate identification. Accordingly, if the first detector 110 detects the chip select signal CS_I as high for N consecutive times and the second detector 120 detects the chip select signal CS_I as low for N consecutive times, it can be determined as qualified. Alternatively, if the first detector 110 detects the chip select signal CS_I as low for N consecutive times and the second detector 120 detects the chip select signal CS_I as high for N consecutive times, it can be determined as qualified.

[0026] Figure 2 It is based on Figure 1 The diagram shows a structural diagram of one embodiment of the first detector 110.

[0027] like Figure 2 As shown, the first detector 110 may include D flip-flops 210_0 to 210_15, a full-high signal generation circuit 230, and a full-low signal generation circuit 250.

[0028] D flip-flops 210_0 to 210_15 are connected in series and can operate synchronously with the first clock RCLK. The chip select signal CS_I can be input to the input D of the first-stage D flip-flop 210_0, while the signal at the output Q of the previous stage D flip-flop can be input to the input D of each of the remaining D flip-flops 210_1 to 210_15. Each D flip-flop 210_1 to 210_15 can receive and store the signal at its input D on the rising edge of the first clock RCLK, and output the stored signal to its output Q.

[0029] When all output signals Q of D flip-flops 210_0 to 210_15 <0> To Q <15> When all levels are high, that is, when the logic level of the chip select signal CS_I is detected as high N times consecutively (16 times in this case) on the rising edge of the first clock RCLK, the full-high signal generation circuit 230 can activate the first full-high signal R_ALL_H to a high level. The full-high signal generation circuit 230 may include NAND gates 231 to 236 and 239, NOR gates 237 and 238, and an inverter 240.

[0030] When all output signals Q of D flip-flops 210_0 to 210_15 <0> To Q <15> When all levels are low, that is, when the logic level of the chip select signal CS_I is detected as low N times consecutively on the rising edge of the first clock RCLK (hereinafter referred to as N=16), the all-low signal generation circuit 250 can activate the first all-low signal R_ALL_L to a high level. The all-low signal generation circuit 250 may include NOR gates 251 to 256 and 259 and NAND gates 257 and 258.

[0031] The second detector 120 may have the same structure as the first detector 110. Figure 2 The first detector 110 shown can become the second detector 120 by replacing the first clock RCLK with the second clock FCLK and replacing the output signals R_ALL_H and R_ALL_L with signals F_ALL_H and F_ALL_L.

[0032] Figure 3 It is based on Figure 1 The diagram shows a structural diagram of one embodiment of the pass / fail determination circuit 130.

[0033] like Figure 3 As shown, the pass / fail determination circuit 130 may include OR gates 301 and 303.

[0034] When the first full-high signal R_ALL_H or the second full-high signal F_ALL_H is activated, OR gate 301 can activate the high pass signal H_PASS. When the first full-low signal R_ALL_L or the second full-low signal F_ALL_L is activated, OR gate 303 can activate the low pass signal L_PASS.

[0035] Figure 4 and 5 It is based on Figures 1 to 3 The timing diagram of the CST operation of the memory 100 shown.

[0036] Figure 4 The diagram illustrates a scenario where the logic level of the chip select signal CS_I is detected as high 16 times (at each of timings 0 to 15) on the rising edge of the first clock RCLK, and low 16 times on the rising edge of the second clock FCLK. In this case, the CST operation can be determined to be successful because both the high pass signal H_PASS and the low pass signal L_PASS are activated. If the CST operation is not determined to be successful, it can be re-executed by speeding up or slowing down the timing of the chip select signal CS_I (e.g., accelerating or decelerating the signal timing to ensure proper synchronization with the clock signal and pass the test).

[0037] Figure 5 The diagram illustrates a scenario where the logic level of the chip select signal CS_I is detected as low 16 times on the rising edge of the first clock RCLK, and high 16 times on the rising edge of the second clock FCLK. In this case, the CST operation can be determined to be successful because both the high pass signal H_PASS and the low pass signal L_PASS are activated.

[0038] In training operations, for example Figure 4 and 5 As shown, the CST operation is deemed successful when the logic level of the chip select signal CS_I is detected as high 16 times on the rising edge of the first clock RCLK and low 16 times on the rising edge of the second clock FCLK. Even in the opposite case, the CST operation can be deemed successful. That is, the CST operation is deemed successful when either the combination of the first clock RCLK and the second clock FCLK is satisfied. Correspondingly, the failure region of the CST operation is very narrow when the rising edge of either the first clock RCLK or the second clock FCLK overlaps with the rising or falling edge of the chip select signal CS_I. When the failure region becomes narrow as described above, it may be difficult to obtain reliable training results because it is difficult to find the optimal timing point for the chip select signal CS_I.

[0039] Figure 6 It is based on Figure 1 A structural diagram of another embodiment of the pass / fail determination circuit 130 shown.

[0040] Figure 6 The pass / fail determination circuit 130 can be used in Figure 3 The pass / fail determination circuit 130 introduces a first mode and a second mode to expand the failure zone of the training operation. That is, Figure 6 The pass / fail determination circuit 130 can improve the reliability of CST operation.

[0041] like Figure 6 As shown, the pass / fail determination circuit 130 may include a first preliminary high pass signal generation unit 601, a first preliminary low pass signal generation unit 602, a second preliminary high pass signal generation unit 603, a second preliminary low pass signal generation unit 604, a high pass signal generation unit 605, and a low pass signal generation unit 606.

[0042] The first mode signal MODE1 can be a signal that is activated to a low level when set to the first mode. The second mode signal MODE2 can be a signal that is activated to a low level when set to the second mode. The first mode can be the following: the CST operation is determined to be qualified only when the logic level of the chip select signal CS_I is detected to be high at the rising edge of the first clock RCLK and low at the rising edge of the second clock FCLK, that is, only when the first all-high signal R_ALL_H and the second all-low signal F_ALL_L are activated. The second mode can be the following: the CST operation is determined to be qualified only when the logic level of the chip select signal CS_I is detected to be high at the rising edge of the second clock FCLK and low at the rising edge of the first clock RCLK, that is, only when the first all-low signal R_ALL_L and the second all-high signal F_ALL_H are activated.

[0043] The first preliminary high pass signal generation unit 601 can activate the first preliminary high pass signal R_PRE_H in response to the activation of the first full-high signal R_ALL_H, and can fix the first preliminary high pass signal R_PRE_H to a deactivated state when set to the second mode. The first preliminary high pass signal generation unit 601 may include an AND gate, which outputs the first preliminary high pass signal R_PRE_H based on the first full-high signal R_ALL_H and the second mode signal MODE2.

[0044] The first preliminary low-qualification signal generation unit 602 can activate the first preliminary low-qualification signal R_PRE_L in response to the activation of the first all-low signal R_ALL_L, and fix the first preliminary low-qualification signal R_PRE_L to a deactivated state when set to the first mode. The first preliminary low-qualification signal generation unit 602 may include an AND gate that outputs the first preliminary low-qualification signal R_PRE_L based on (e.g., receiving) the first all-low signal R_ALL_L and the first mode signal MODE1.

[0045] The second preliminary high pass signal generation unit 603 can activate the second preliminary high pass signal F_PRE_H in response to the activation of the second full-high signal F_ALL_H, and can fix the second preliminary high pass signal F_PRE_H to a deactivated state when set to the first mode. The second preliminary high pass signal generation unit 603 may include an AND gate, which outputs the second preliminary high pass signal F_PRE_H based on the second full-high signal F_ALL_H and the first mode signal MODE1.

[0046] The second preliminary low pass signal generation unit 604 can activate the second preliminary low pass signal F_PRE_L in response to the activation of the second all-low signal F_ALL_L, and can fix the second preliminary low pass signal F_PRE_L to a deactivated state when set to the second mode. The second preliminary low pass signal generation unit 604 may include an AND gate that outputs the second preliminary low pass signal F_PRE_L based on the second all-low signal F_ALL_L and the second mode signal MODE2.

[0047] When either the first preliminary high pass signal R_PRE_H or the second preliminary high pass signal F_PRE_H is activated, the high pass signal generation unit 605 can activate the high pass signal H_PASS. The high pass signal generation unit 605 may include an OR gate, which outputs the high pass signal H_PASS based on the first preliminary high pass signal R_PRE_H and the second preliminary high pass signal F_PRE_H.

[0048] When either the first preliminary low pass signal R_PRE_L or the second preliminary low pass signal F_PRE_L is activated, the low pass signal generation unit 606 can activate the low pass signal L_PASS. The low pass signal generation unit 606 may include an OR gate, which outputs the low pass signal L_PASS based on the first preliminary low pass signal R_PRE_L and the second preliminary low pass signal F_PRE_L.

[0049] When set to the first mode Figure 6 The pass / fail determination circuit 130 can be used in the chip select signal CS_I, such as Figure 4When the input is shown, the CST operation is determined to be qualified, but the chip select signal CS_I is as follows: Figure 5 The input shown indicates that the CST operation failed.

[0050] When set to the second mode Figure 6 The pass / fail determination circuit 130 can be used in the chip select signal CS_I, such as Figure 5 When the input is shown, the CST operation is determined to be qualified, but the chip select signal CS_I is as follows: Figure 4 The input shown indicates that the CST operation failed.

[0051] Figure 7 This is a timing diagram of the failure region for the CST operation of memory 100. The CST operation can be determined as a failure when the rising edge of the chip select signal CS_I is located within the failure region.

[0052] Figure 7 This illustrates the timing determination of whether a CST operation is successful or unsuccessful based on the chip select signal CS_I. Figure 7 In this context, Tcs_shift represents the offset value of the chip select signal CS_I.

[0053] It can be seen that when no mode is set (Mode X Failure Zone), if the pass / fail determination circuit 130 follows... Figure 3 If the failure region is very narrow, then the failure region is extremely narrow (e.g., relative to one clock cycle 1tCK) when the rising edge of the first clock RCLK or the second clock FCLK overlaps with the rising or falling edge of the chip select signal CS_I. When the failure region is formed so narrowly as shown above, the memory controller may easily determine that the CST operation is qualified. As a result, the reliability of the CST operation may be difficult to guarantee.

[0054] It can be seen that when set to the first mode (first mode failure zone) or the second mode (second mode failure zone), the failure zone is wider. A wider failure zone ensures a clear failure area. Consequently, the pass / fail determination for the CST operation becomes more stringent. As a result, the reliability of the CST operation is guaranteed.

[0055] Figure 8 This is a structural diagram of a storage system 800 according to an embodiment of the present disclosure.

[0056] like Figure 8As shown, the storage system 800 may include a memory controller 810 and a memory 820. The memory controller 810 can control the memory 820 by transmitting a chip select signal CS_I, a command address CA, and a clock CLK to the memory 820. The memory 820 can execute a CST operation by controlling the chip select signal CS_I and the command address CA. A first mode and a second mode can be set.

[0057] like Figures 1 to 7 The memory 820 can perform CST operations under the control of the memory controller 810, and can transmit the pass / fail result of the CST operation to the memory controller 810. The pass / fail result may only include information indicating whether the CST operation is determined to be pass or fail, or it may include information indicating a high pass signal H_PASS and a low pass signal L_PASS. That is, the pass / fail result may include information indicating whether the CST operation is a high pass or a low pass.

[0058] The technical spirit of this disclosure has been described above in conjunction with embodiments. However, it should be noted that these descriptions are only for illustrating embodiments consistent with the concepts of this disclosure and are not intended to limit them. Those skilled in the art will understand that various embodiments can be implemented without departing from the technical spirit of this disclosure.

Claims

1. A memory, comprising: The first detector continuously detects the logic level of the chip selection signal in sync with the first clock. A second detector, which: continuously detects the logic level of the chip selection signal in synchronization with a second clock, the second clock having a phase opposite to that of the first clock; and The pass / fail determination circuit is a pass / fail determination circuit that determines the training operation as pass when the logic level continuously detected by the first detector is different from the logic level continuously detected by the second detector.

2. The memory according to claim 1, wherein, When set to the first mode, the pass / fail determination circuit determines that the training operation is pass when the first detector continuously detects a high level and the second detector continuously detects a low level.

3. The memory according to claim 2, wherein, When set to the second mode, the pass / fail determination circuit determines that the training operation is pass when the first detector continuously detects a low level and the second detector continuously detects a high level.

4. The memory according to claim 1, further comprising: Clock receiving circuit, Its: receiving clock; as well as A frequency divider, which generates the first clock and the second clock by dividing the clock frequency.

5. The memory according to claim 4, further comprising a chip select receiving circuit, wherein: Receive the chip selection signal.

6. The memory according to claim 1, wherein, The first detector includes: A plurality of first D flip-flops are connected in series and operate synchronously with the first clock, wherein the chip select signal is input to the first D flip-flop in the first stage of the plurality of first D flip-flops; A first full-high signal generation circuit, wherein: when all output signals of the plurality of first D flip-flops are at a high level, the first full-high signal is activated; and The first all-low signal generation circuit activates the first all-low signal when all the output signals of the plurality of first D flip-flops are at a low level.

7. The memory according to claim 6, wherein, The second detector includes: A plurality of second D flip-flops are connected in series and operate synchronously with the second clock, wherein the chip select signal is input to the second D flip-flop in the first stage of the plurality of second D flip-flops; The second full-high signal generation circuit activates the second full-high signal when all output signals of the plurality of second D flip-flops are at a high level; and The second all-low signal generation circuit activates the second all-low signal when all the output signals of the plurality of second D flip-flops are at a low level.

8. The memory according to claim 7, wherein, The pass / fail determination circuit also includes: When set to the first mode, the training operation is determined to be qualified when the first full-high signal and the second full-low signal are activated, and When set to the second mode, the training operation is determined to be qualified when the first all-low signal and the second all-high signal are activated.

9. The memory according to claim 7, wherein, The pass / fail determination circuit includes: The first preliminary high-pass signal generation unit: activates the first preliminary high-pass signal in response to the activation of the first full-high signal, and fixes the first preliminary high-pass signal to a deactivated state when set to the second mode; The first preliminary low pass signal generation unit: activates the first preliminary low pass signal in response to the activation of the first full low signal, and fixes the first preliminary low pass signal to a deactivated state when set to the first mode. The second preliminary high-qualification signal generation unit: activates the second preliminary high-qualification signal in response to the activation of the second full-high signal, and fixes the second preliminary high-qualification signal to a deactivated state when set to the first mode; The second preliminary low pass signal generation unit: activates the second preliminary low pass signal in response to the activation of the second full low signal, and fixes the second preliminary low pass signal to a deactivated state when set to the second mode; A high-qualification signal generation unit, wherein: when one or more of the first preliminary high-qualification signal and the second preliminary high-qualification signal are activated, the high-qualification signal is activated; and A low pass signal generation unit, wherein: when one or more of the first preliminary low pass signal and the second preliminary low pass signal are activated, the low pass signal is activated.

10. The memory according to claim 7, wherein: The number of the plurality of first D flip-flops is 16, and The number of the plurality of second D flip-flops is 16.

11. The memory according to claim 1, wherein, The training operation includes: activating the chip selection signal.

12. A method of operating a storage system, comprising: Transferring clock signals from the memory controller to the memory; Set the memory to the first mode; Toggle the chip select signal transmitted from the memory controller to the memory; The memory detects the logic level of the chip selection signal N times at the even-numbered rising edge of the clock, where N is an integer greater than or equal to 2; The memory detects the logic level of the chip select signal N times at the odd rising edges of the clock; and When the logic level of the chip selection signal is detected as high on N even-numbered rising edges and the logic level of the chip selection signal is detected as low on N odd-numbered rising edges, the memory determines that the training in the first mode is qualified.

13. The operating method according to claim 12, further comprising: Set the memory to the second mode; Flip the chip selection signal; The memory detects the logic level of the chip selection signal N times on the even-numbered rising edge; The memory detects the logic level of the chip selection signal N times on the odd rising edge; as well as When the logic level of the chip selection signal is detected as high on N odd-numbered rising edges and the logic level of the chip selection signal is detected as low on N even-numbered rising edges, the memory determines that the training in the second mode is qualified.

14. The operating method according to claim 13, wherein, N is 16.

15. A storage system, comprising: The memory controller, which transmits the clock and chip select signals; and The memory receives the clock and the chip select signal, and transmits the training result to the memory controller by detecting the logic level of the chip select signal N times on the even rising edge of the clock and N times on the odd rising edge of the clock, where N is an integer greater than or equal to 2.

16. The storage system according to claim 15, wherein, When the memory is set to the first mode, the training result is determined to be qualified when the logic level of the chip selection signal is continuously detected as high on the even-numbered rising edge and the logic level of the chip selection signal is continuously detected as low on the odd-numbered rising edge.

17. The storage system according to claim 15, wherein, When the memory is set to the second mode, the training result is determined to be qualified when the logic level of the chip selection signal is continuously detected as low on the even-numbered rising edge and the logic level of the chip selection signal is continuously detected as high on the odd-numbered rising edge.

18. The storage system according to claim 15, wherein, The training includes activating the chip selection signal.

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