A flash memory fault detection method and system based on an improved march algorithm

Abstract

The application relates to the technical field of semiconductor integrated circuit testing, and discloses a flash memory fault detection method and system based on an improved March algorithm. The system is innovated in cooperation with an algorithm and a system, and a double-track parallel detection architecture is constructed: at the algorithm level, the improved March algorithm based on the alternately written odd-even address and the forward / reverse double-cycle check architecture is adopted. At the system level, a test management subsystem and a visual interactive subsystem are integrated, and the communication / burning interface is connected to a to-be-tested board to realize detection instruction interaction and detection firmware burning. During detection, the system dynamically matches the flash memory detection firmware based on the improved March algorithm from a firmware library based on automatically recognized flash memory hardware information, burns the flash memory detection firmware into the to-be-tested board, the to-be-tested board executes the flash memory detection firmware program based on the improved March algorithm, and uploads fault information to the test management subsystem and the visual interactive subsystem for analysis and display.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit testing technology, and more specifically, to a flash memory fault detection method and system based on an improved March algorithm. Background Technology

[0002] With the increasing integration of semiconductor integrated circuits, the capacity and density of flash memory have significantly improved. However, the reduction in cell charge capacity has led to the frequent occurrence of new types of faults such as charge leakage and read / write crosstalk, posing a serious challenge to traditional testing methods. On the one hand, the mainstream March algorithm, which mostly uses fixed data patterns (such as all-0 / all-1 filling), can detect basic cell failures, but it is not sensitive enough to complex defects such as address parity-related coupling faults and dynamic interference failures, resulting in a higher false negative rate for flash memory faults. On the other hand, traditional testing systems require manual configuration of parameters to adapt to chips with different interface protocols, which is cumbersome and has a high false negative rate, making it difficult to meet the reliability verification requirements of high-density memory.

[0003] To address these issues, several technical improvements have been proposed in recent years. One approach strengthens the test intensity by overlaying a high-frequency sequence of read 0, read 1, write 0, and write 1 operations onto the March algorithm and employs a log tracking mechanism for fault feature extraction. However, its testing logic remains based on the traditional March algorithm and does not optimize test vectors for the electrical characteristics of flash memory cells, thus limiting dynamic fault detection capabilities. Another approach uses interface conversion technology to achieve concurrent testing of multiple chips. While this reduces cable interconnection complexity through protocol physical layer conversion, it is limited by the fixed hardware and software architecture, making it unable to dynamically adapt to flash memory chips with various interface protocols. Furthermore, the lack of a visual interface negatively impacts the efficiency and accuracy of flash memory fault location.

[0004] In summary, existing technologies generally suffer from three major bottlenecks: insufficient algorithm-system coordination, low automation of testing processes, and a single dimension of fault analysis. This patent constructs a dual-track parallel testing solution by deeply integrating an improved March algorithm with a modular system architecture: at the algorithm level, an improved March algorithm based on alternating odd and even address writing and a forward / reverse dual-loop verification architecture is developed to reduce the dynamic fault false negative rate; at the system level, a visual interface and automated detection mechanism are designed to automate and intelligently detect flash memory faults, providing an efficient and low-cost flash memory fault detection technology solution for the semiconductor manufacturing industry. Summary of the Invention

[0005] Existing flash memory fault detection technologies suffer from the following technical bottlenecks.

[0006] 1. Algorithm adaptability defects: The traditional March algorithm is not optimized for flash memory erasure characteristics, resulting in frequent erasure operations in the test process (increasing invalid cycles by 30%-50%). In addition, the fixed data mode (all 0 / all 1 sequential read and write) makes it difficult to detect dynamic defects such as address parity coupling faults and adjacent interference, with a dynamic fault false detection rate of over 20%.

[0007] 2. Fixed System Architecture: Traditional system hardware and software architectures adopt a non-modular design concept, lacking flexibility and unable to dynamically adapt to flash memory chips with different protocols such as NAND and NOR. Relying on manual parameter configuration leads to a cumbersome protocol switching process, averaging up to 15 minutes, severely hindering the improvement of flash memory fault detection efficiency.

[0008] 3. Limited fault analysis dimensions: Existing technologies lack real-time caching and visualization mechanisms, requiring manual extraction and analysis of fault data. This results in low location accuracy and the inability to generate multi-dimensional fault feature maps, making it difficult to meet the needs of intelligent analysis.

[0009] To overcome the aforementioned technical bottlenecks, this invention provides a flash memory fault detection method and system based on an improved March algorithm. This system employs algorithm-system co-design based on the improved March algorithm, constructs a dual-track parallel adaptive testing architecture, and integrates real-time fault visualization functionality. The aim is to reduce the dynamic fault false negative rate to below 5%, shorten the testing cycle by 40%, and improve fault location accuracy to over 95%.

[0010] The technical solution adopted by the present invention to solve its technical problem is as follows.

[0011] This invention provides a flash memory fault detection method based on an improved March algorithm. This method is a systematic optimization of the traditional March algorithm, adapted to flash memory, and upgrades the traditional March algorithm's single address traversal mode to a forward-reverse bidirectional scanning coupled verification mode. The specific improvement strategy is as follows.

[0012] 1. Dynamic Parity Check Write Strategy: Based on the fixed write mode of the traditional algorithm, a new parity check mechanism is added, alternating between writing a checkerboard background pattern based on the parity of the flash memory address (0xAA for odd addresses, 0x55 for even addresses). This mechanism utilizes the binary characteristics of the least significant bit of the flash memory address to differentiate memory cells, enabling both modes of verification to be completed with only a single full address traversal per test cycle. This reduces the number of write operations by more than 50% (the traditional algorithm requires two independent writes, while this solution reduces it to one).

[0013] 2. Bidirectional Traversal Coupling Test: Breaking through the limitations of traditional unidirectional traversal algorithms, a dual-loop test architecture of ascending and descending order is constructed. After the first erase, the flash memory address is traversed in ascending order, completing the basic test through four steps: "read 1 → parity check write → read check value → full address verification in sequence". After the second erase, the flash memory address is traversed in descending order, using a completely mirrored operation process. This mode can detect logical faults in the address decoder during ascending / descending operations, eliminating the risk of missed faults due to coupling in unidirectional testing, and increasing test coverage to over 98%.

[0014] 3. Storage Cell State Retention Verification: A state retention detection step is embedded in the bidirectional testing process. By continuously reading the alternating parity values ​​of adjacent flash memory cells (0xAA→0x55→0xAA…), the data retention capability of the flash memory cells after multiple read and write operations is verified, effectively detecting dynamic faults caused by charge leakage or interference, and making up for the shortcomings of traditional algorithms that focus on static fault detection.

[0015] 4. Algorithm complexity optimization: By reducing the frequency of write-1 operations and the number of erase operations in flash memory, the total number of operations is optimized from 10N in the traditional March C algorithm to 8N+2 (N is the number of storage units). While maintaining the fault coverage, the test time is shortened by about 20%, which significantly improves the testing efficiency of large-scale flash memory chips.

[0016] The present invention also provides a flash memory fault detection system based on an improved March algorithm, including a visualization and interaction subsystem, a test management subsystem, a communication interface, and a programming interface.

[0017] The visualization and interactive subsystem includes a fault type analysis unit and an analysis result display unit.

[0018] The fault type analysis unit is used to perform data parsing and fault type identification on the flash memory test results received by the communication interface, and transmit the classified fault type data to the analysis result display unit in real time.

[0019] The analysis results display unit automatically generates a two-dimensional storage fault density dynamic mapping map (showing the physical location distribution of fault units) and a fault type statistical pie chart (quantifying the proportion of each type of fault) based on the data received from the fault type analysis unit.

[0020] The test management subsystem includes a parameter identification unit, a firmware library, and a burning control unit.

[0021] The parameter identification unit sends a read command through the communication interface to obtain the flash memory JEDEC ID, which is then parsed and transmitted to the programming control unit.

[0022] The firmware library integrates a flash memory detection firmware set with an improved March algorithm, and supports firmware calls through a standardized API interface.

[0023] The programming control unit executes a three-level operation process.

[0024] 1. Receive the flash memory hardware-related information parsed by the parameter identification unit.

[0025] 2. Based on the parsed flash memory hardware information, call the firmware library's API interface to match the corresponding improved March algorithm detection firmware in the firmware library.

[0026] 3. Write the firmware to the board under test through the programming interface.

[0027] The communication interface is electrically connected to the communication bus and is used to transmit various commands to the board under test. A check and retransmission mechanism is used to ensure the reliability of data transmission.

[0028] The programming interface is electrically connected to the programming bus and is used to program the improved March algorithm flash memory testing firmware onto the board under test. The firmware is encrypted using an encryption algorithm, and the decryption key is dynamically distributed through the communication interface to ensure the security of firmware transmission.

[0029] The flash memory to be tested is mounted on the board under test. By executing the flash memory detection firmware with the improved March algorithm, fault detection of the flash memory under test is achieved.

[0030] The present invention proposes a flash memory fault detection method and system based on an improved March algorithm, which has the following beneficial effects.

[0031] This invention addresses the shortcomings of the traditional March algorithm in flash memory testing, including low detection efficiency, high dynamic fault miss rate, incomplete fault mode coverage, and rigid system architecture leading to inefficient fault analysis. It proposes a dual-track parallel solution that integrates the algorithm and the fault detection system: At the algorithm level, an improved March algorithm with alternating odd and even address writing and a forward / reverse dual-loop verification architecture reduces the number of erase / write cycles per memory cell by 50% while increasing address coupling fault detection coverage by over 30%, accurately identifying dynamic read / write coupling, charge leakage, and data conversion faults. At the system level, a test management subsystem supports adaptive access to flash memory chips with different protocols, and a visual interaction subsystem enables precise fault location and intelligent analysis. This solution not only overcomes the limitations of the traditional March algorithm in flash memory testing but also forms a closed-loop system of "efficient detection - intelligent analysis - lifetime optimization" through algorithm-system collaboration, improving flash memory reliability. It is compatible with mainstream flash memory protocol types and has a good detection rate for flash memory fixed-bit faults, conversion faults, coupling faults, addressing faults, and data retention faults, effectively extending flash memory lifespan and providing a systematic solution for industrial flash memory reliability testing. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a block diagram of a flash memory fault detection system based on an improved March algorithm according to the present invention.

[0034] Figure 2 This is a flowchart illustrating a flash memory fault detection method based on an improved March algorithm according to the present invention. Detailed Implementation

[0035] The technical solution of this invention will be described in detail below with reference to the accompanying drawings, aiming to provide a complete description of the technical features and implementation process. This embodiment takes a 1GB NOR flash memory as an example, but the invention is not limited to this model, and its technical solution can be extended to SPI, NAND and other flash memory chips.

[0036] Reference Appendix Figure 1 This is a block diagram of a flash memory fault detection system based on an improved March algorithm.

[0037] The analysis results display unit is implemented in the form of a display window. The left area displays a dynamic mapping map of storage fault density, and the right area displays a pie chart of fault type statistics. The display content is dynamically refreshed by detecting the data transmitted by the fault type analysis unit in real time.

[0038] The principle behind generating a dynamic fault density map is to map the physical addresses of flash memory into a two-dimensional matrix and use a graphics rendering library to implement dynamic pseudo-color encoding (red represents fault-intensive areas, and blue represents normal areas). For example, a 1GB NOR flash memory has 8192 blocks with a block size of 128KB. This is divided into a two-dimensional matrix of 64 rows and 128 columns, with each matrix cell corresponding to a physical block. The degree of color gradient of the corresponding matrix cell is determined based on the fault frequency of the faulty block.

[0039] The generation principle of the fault type statistical pie chart is based on the bit difference comparison analysis of binary data. By comparing the bit-by-bit difference characteristics between the expected system operating data and the actual collected data, fault types are identified and classified. Address mapping technology is used to count the number of fault addresses corresponding to each fault type, and the total number of fault addresses is obtained by accumulating the number of fault addresses of each type. The number of fault addresses of each type is normalized to the total number of fault addresses through ratio calculation to obtain the ratio parameters of each fault type. Based on the geometric transformation algorithm, the ratio parameters are converted into the center angle value of the pie chart.

[0040] The following is the normalization formula:

[0041] in, Let be the central angle of the i-th type of fault. This corresponds to the number of fault addresses. Finally, a graphics rendering library is used to achieve a visual representation.

[0042] The test management subsystem includes a parameter identification unit, a firmware library, and a burning control unit.

[0043] The parameter identification unit reads the JEDEC ID of the flash memory by sending a read command through the communication interface, parses the flash memory interface standard, memory type, manufacturer code, flash memory capacity and related data, and internally transmits the parsed data to the programming control unit.

[0044] The firmware library is deployed in the test management subsystem and is built using a relational database model to achieve centralized storage, dynamic retrieval, and version management of firmware.

[0045] The control process of the programming control unit is as follows: First, obtain flash memory hardware information from the parameter identification unit; second, obtain the test firmware of the board under test from the relevant directory of the firmware library based on the obtained flash memory hardware information; and finally, program the test firmware into the board under test through the programming interface.

[0046] Reference Appendix Figure 2 This is a flowchart illustrating a flash memory fault detection method based on an improved March algorithm.

[0047] S1, perform a full array erase operation on the storage space to be tested of the flash memory chip, and initialize the background pattern to all 1s.

[0048] S2, starting from the beginning address of the storage space to be tested, read and verify each address word by word after it is "1", then write the "chessboard background pattern" (0xAA for odd addresses and 0x55 for even addresses), and then read and verify the "chessboard background pattern". This operation is performed sequentially until the end address of the storage space to be tested is reached.

[0049] S3 reads and verifies the written "chessboard background pattern" data (0xAA / 0x55) cell by cell from the start address to the end address of the storage space under test.

[0050] S4, perform a full flash array erase again to clear the above positive sequence test data.

[0051] S5, Perform mirroring operation: Starting from the end address of the storage space under test, read and verify each word by address until it is "1", then write the "chessboard background pattern" (0xAA for odd addresses and 0x55 for even addresses), and then read and verify the "chessboard background pattern". This mirroring operation is performed sequentially until the starting address of the storage space under test is reached.

[0052] S6 reads and verifies the written "chessboard background pattern" cell by cell from the end address to the start address of the storage space under test.

Claims

1. A flash memory fault detection system based on an improved March algorithm, characterized in that, include: The visualization and interactive subsystem includes a fault type analysis unit and an analysis result display unit. The fault type analysis unit performs data parsing and fault type identification on the flash memory test results received from the communication interface, and transmits the classified fault type data to the analysis result display unit in real time. The analysis result display unit automatically generates a dynamic mapping map of storage fault density and a pie chart of fault type statistics based on the data received from the fault type analysis unit. The test management subsystem includes a parameter identification unit, a firmware library, and a burning control unit. The firmware library stores a set of flash memory testing firmware based on the improved March algorithm and is accessed through a standardized API interface. The communication interface and the firmware burning interface respectively implement data transmission and firmware burning through verification and retransmission mechanisms and encryption algorithms; The firmware library integration includes a flash detection firmware set with an improved March algorithm, and supports firmware calls through a standardized API interface.

2. The flash memory fault detection system based on the improved March algorithm according to claim 1, characterized in that, The visual interaction subsystem: The storage fault density dynamic mapping map maps the physical addresses of flash memory into a two-dimensional matrix of m rows × n columns, with each matrix unit corresponding to a storage block. Dynamic pseudo-color encoding is implemented using a graphics rendering library (red represents fault-intensive areas, and blue represents normal areas). The generation principle of the fault type statistical pie chart is based on the bit difference comparison analysis of binary data. By comparing the bit-by-bit difference characteristics between the expected system operation data and the actual collected data, the fault types are identified and classified. Address mapping technology is used to count the number of fault addresses corresponding to each fault type, and the total number of fault addresses is obtained by accumulating the number of fault addresses for each type. The number of various fault addresses is normalized to the total number of fault addresses by proportional calculation to obtain the proportional parameters of each fault type; the proportional parameters are converted into the center angle values ​​of the pie chart based on the geometric transformation algorithm. The following is the normalization formula: in Let be the central angle of the i-th type of fault. This corresponds to the number of fault addresses. Finally, a graphics rendering library is used to achieve a visual representation.

3. The flash memory fault detection system based on the improved March algorithm according to claim 1, characterized in that, The test management subsystem: The parameter identification unit reads the JEDEC ID of the flash memory by sending a read command through the communication interface, parses the flash memory interface standard, memory type, manufacturer code, flash memory capacity and related data, and internally transmits the parsed data to the programming control unit; The programming control unit executes a three-level operation process: (1) Receive flash memory hardware-related information parsed by the parameter identification unit; (2) Based on the parsed flash memory hardware information, call the firmware library's API interface to match the corresponding detection firmware using the improved March algorithm in the firmware library; (3) Write the firmware to the board under test through the programming interface.

4. A flash memory fault detection system based on an improved March algorithm according to claim 1, characterized in that, The firmware library is deployed in the test management subsystem and is built using a relational database model to achieve centralized storage, dynamic retrieval, and version management of firmware.

5. A flash memory fault detection method based on an improved March algorithm, characterized in that, include: (1) Dynamic parity check writing strategy: Based on the fixed writing mode of the traditional algorithm, a new verification mechanism is added to alternately write the chessboard background pattern according to the parity of the flash memory address; (2) Bidirectional Traversal Coupling Test: Breaking through the limitation of unidirectional traversal in traditional algorithms, a forward-reverse dual-loop test architecture is constructed; after the first erase, the flash address forward traversal is performed, and the basic test is completed through four steps: "read 1 → parity check write → read check value → full address verification in sequence"; after the second erase, the flash address reverse traversal is started, and a completely mirrored operation process is adopted. (3) Storage Cell State Retention Verification: A state retention detection step is embedded in the bidirectional testing process. By continuously reading the alternating parity values ​​of adjacent flash memory cells, the data retention capability of the flash memory cells after multiple read and write operations is verified. (4) Algorithm complexity optimization: By reducing the frequency of write-1 operations and the number of erase operations in flash memory, the total number of operations is optimized from 10N in the traditional March C algorithm to 8N+2.

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