FPGA-based DRAM function test system and method

Abstract

The application discloses a DRAM function test system and method based on FPGA, relates to the technical field of DRAM test, solves the problems of high cost and limited test efficiency of DRAM function test in the prior art, and the system comprises an ATE and an FPGA chip connected with the ATE through a communication interface, the ATE is used for issuing test instructions, configuration parameters and starting a test process to the FPGA chip, and receiving test result data returned by the FPGA chip, the FPGA chip is used for generating read-write timing and excitation signals for the DRAM, executing corresponding function test algorithms and formatting output response data of the DRAM into a data stream, greatly reducing system cost, improving test efficiency, quickly adapting to different types of DRAM and different test requirements, linearly improving test capacity by increasing the number of FPGA chips, and being applicable to wafer-level test and finished product test simultaneously.

Description

Technical Field

[0001] This application relates to the field of DRAM testing technology, and in particular to an FPGA-based DRAM functional testing system and method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is one of the most important storage devices in electronic systems, and its reliability and performance directly determine the operational stability of the entire system. With the continuous advancement of semiconductor technology, DRAM storage capacity continues to increase, operating frequency continues to rise, and interface protocols become increasingly complex, which places increasingly higher demands on DRAM functional testing.

[0003] Currently, DRAM functional testing primarily relies on Automatic Test Equipment (ATE). Traditional ATE testing methods determine chip functionality by applying predefined test vectors to the DRAM and analyzing its responses. The advantage of ATE testing lies in its mature test architecture and ability to observe rich test details such as electrical and timing parameters, making it an effective testing method. However, traditional ATE testing methods have the following shortcomings:

[0004] First, testing costs are high: the research and development and purchase of high-performance ATE equipment requires huge capital investment, which is difficult for small and medium-sized chip design companies and packaging and testing manufacturers to afford. As DRAM speeds continue to increase, upgrading or replacing ATE equipment to meet testing needs will further increase costs.

[0005] Second, vector storage resources are limited: traditional ATE equipment relies on a high-precision vector storage module inside the machine to store test vectors. The capacity of this storage module is limited, which makes it difficult to meet the needs of large-capacity DRAM full address space testing, thus limiting the test coverage.

[0006] Third, insufficient system flexibility: ATE equipment is usually designed for testing specific types of chips. When the DRAM interface protocol is upgraded or the test algorithm is changed, it is often necessary to replace the test hardware or carry out a complex system upgrade. The adaptation cycle is long and the cost is high, making it difficult to quickly respond to the needs of chip iteration updates.

[0007] Fourth, testing efficiency is limited: Traditional ATE typically adopts a serial testing mode, executing instructions one by one, which makes it difficult to fully utilize the potential of parallel testing, resulting in limited throughput in large-scale mass production testing scenarios.

[0008] Therefore, there is an urgent need in the field for a DRAM functional testing system and method that can balance testing efficiency and cost, and possess high flexibility and scalability. Summary of the Invention

[0009] The purpose of this application is to overcome the problems of high cost and limited testing efficiency of DRAM functional testing in the prior art, and to provide an FPGA-based DRAM functional testing system and method.

[0010] Firstly, an FPGA-based DRAM functional testing system is provided, including an ATE and an FPGA chip that is connected to it via a communication interface.

[0011] The ATE is used to send test commands, configuration parameters and start the test process to the FPGA chip, and to receive the test result data returned by the FPGA chip.

[0012] The FPGA chip is used to generate read / write timing and stimulus signals for DRAM and execute corresponding functional test algorithms. The FPGA chip is also used to acquire the output response data of DRAM and format it into a data stream that can be recognized by ATE.

[0013] In some possible implementations, the FPGA chip includes the following modules:

[0014] The communication interface module is used to communicate with the ATE, receive test commands and configuration parameters, and report test result data.

[0015] The instruction parsing module is used to receive and parse the test instructions and configuration parameters issued by the ATE;

[0016] The timing generation module is used to generate read and write timing signals that conform to the DRAM interface specification based on the parsed test instructions;

[0017] The incentive generation module is used to generate various types of test incentive data.

[0018] The address generation module is used to generate the address sequence required for testing.

[0019] The response acquisition module is used to acquire response data output by the DRAM in response to the read / write timing signals and stimulus data;

[0020] The data formatting module is used to format the collected response data into a data stream according to a preset communication protocol;

[0021] The result reporting module is used to report the formatted data stream to the ATE through the communication interface.

[0022] In some possible implementations, the data formatting module employs a three-stage pipeline architecture, including:

[0023] The input buffer unit uses an asynchronous FIFO to achieve cross-clock domain data buffering and rate matching;

[0024] A data packaging engine is used to read raw response data from the input buffer unit and assemble the data according to a preset frame format. The data packaging engine includes a data splicer, an address tag inserter, a timestamp inserter, and a channel identifier inserter. The address tag inserter is used to bind the current test address with the corresponding response data. The timestamp inserter is used to add a time value from the FPGA's internal global timer to the data. The channel identifier inserter is used to insert the test channel number to which the current data belongs in a multi-channel parallel test scenario.

[0025] The protocol encapsulation unit is used to encapsulate the data payload output by the data packaging engine into a data frame that conforms to the communication interface protocol standard.

[0026] In some possible implementations, the timing generation module internally includes a clock generation submodule based on an FPGA phase-locked loop. The clock generation submodule is used to generate a high-precision clock signal, and the timing generation module supports switching between multiple DRAM interface standards through parameterized design. The excitation generation module supports all-zero data, all-one data, checkerboard data, step data, pseudo-random sequence data, and user-defined data modes. The address generation module supports address increment mode, address decrement mode, and address jump mode.

[0027] In some possible implementations, the FPGA chip also includes a BIST control unit, which comprises:

[0028] The BIST controller, implemented using a finite state machine, is used to control the overall process of BIST testing.

[0029] An address generator is used to generate the address sequences required for the BIST test.

[0030] A vector generator, used to generate test vectors based on a preset test algorithm;

[0031] A control signal generator is used to generate the control signals required for DRAM testing.

[0032] A comparator is used to compare the response data read from DRAM with the expected data to determine if a fault exists;

[0033] The selector MUX is used to select between different test sources.

[0034] In some possible implementations, the FPGA chip establishes a temporary electrical connection with the DRAM on the wafer via a probe card for use in wafer-level testing; or, the FPGA chip establishes an electrical connection with the packaged DRAM via a test socket for use in finished product testing.

[0035] Secondly, an FPGA-based DRAM functional testing method is provided, employing a system as described in any implementation of the first aspect, the method comprising:

[0036] Configuration and startup steps: The ATE sends test configuration parameters and test startup commands to the FPGA chip through the communication interface;

[0037] Instruction parsing and mode configuration steps: The FPGA chip receives and parses the test configuration parameters and test start command, and configures the working mode of each internal module according to the configuration parameters;

[0038] Test stimulus generation steps: According to the configured test mode, the FPGA chip generates read and write timing signals that conform to the DRAM interface specification through the timing generation module, generates test stimulus data through the stimulus generation module, and generates test address sequence through the address generation module;

[0039] Test execution steps: The FPGA chip applies the read / write timing signals, test stimulus data, and address signals to the DRAM under test to perform write and read operations;

[0040] Response acquisition steps: The FPGA chip acquires the response data output by the tested DRAM in response to the read / write timing signals and stimulus data through the response acquisition module;

[0041] Data formatting steps: The FPGA chip formats the acquired response data into a data stream according to a preset communication protocol;

[0042] Result reporting step: The FPGA chip reports the formatted data stream to the ATE through the communication interface;

[0043] Results analysis steps: The ATE receives and analyzes the data stream, compares the received response data with the expected data, and generates a test result report.

[0044] In some possible implementations, the data formatting step specifically includes:

[0045] Data reception and buffering: Write the acquired DRAM response data into an asynchronous FIFO;

[0046] State machine wake-up and data reading: When the amount of data cached in the asynchronous FIFO reaches a preset threshold, the packaging engine is woken up to read data from the FIFO;

[0047] Data assembly: Parallel execution includes reading raw response data from the FIFO, obtaining the current test address and inserting it into the address tag field, obtaining the current time value and inserting it into the timestamp field, and obtaining the current channel number and inserting it into the channel number field;

[0048] Protocol encapsulation: The assembled data payload is encapsulated according to the communication protocol between the ATE and the FPGA chip, a protocol header and a verification field are added, and the data is written to the output buffer;

[0049] Data reporting trigger: The data frames in the output buffer are reported to the ATE through the communication interface.

[0050] Among the possible implementations is the BIST test pattern:

[0051] The ATE sends the BIST test start command and configuration parameters to the FPGA chip through the communication interface;

[0052] After the instruction parsing module of the FPGA chip parses the instruction, it activates the BIST control unit.

[0053] The finite state machine of the BIST control unit initiates the test process, and the control address generator, vector generator, and control signal generator work together to generate test address sequences, test vectors, and DRAM control signals.

[0054] The FPGA chip applies the above signal to the DRAM under test through the DRAM interface;

[0055] The comparator compares the response data read from DRAM with the expected data generated by the vector generator in real time.

[0056] If the comparison results are inconsistent, the BIST controller records the fault address;

[0057] After the BIST test is completed, the BIST control unit reports the test results to the ATE through the result reporting module.

[0058] In some possible implementations, during the data formatting step, when the response data from multiple consecutive addresses is completely consistent with the expected data, only the first address and the number of consecutive passes are reported; and / or, when the ATE is configured to report fault-only mode, a data frame is generated and reported only when the response data is inconsistent with the expected data.

[0059] This application has the following beneficial effects:

[0060] 1. Reduced System Costs for DRAM Functional Testing: This application employs a heterogeneous master-slave architecture with ATE as the host control unit and FPGA chip as the test function execution unit. This decouples the high-precision, high-speed DRAM read / write timing generation and test vector storage / application from the ATE hardware, entrusting the FPGA with these tasks. As a general-purpose programmable logic device, the cost of an FPGA is far lower than that of a dedicated ATE test hardware module with equivalent performance. This reduces the reliance on the high-precision vector storage depth and high-speed channel boards of traditional ATE equipment, enabling mid-to-low-end ATE equipment to perform high-performance DRAM functional testing with the FPGA, effectively reducing the hardware costs of the testing system.

[0061] 2. Improved flexibility and reconfigurability of the test system: This application integrates multiple functional modules within the FPGA chip, including a timing generation module, a stimulus generation module, and an address generation module. Each module adopts a parameterized and reconfigurable design. When the DRAM interface standard is upgraded or the test algorithm changes, the system upgrade can be completed simply by sending updated configuration parameters to the FPGA via the ATE or updating the FPGA's configuration file, without replacing any hardware. The timing generation module can flexibly switch between different DRAM interface standards through parameterized design, and the stimulus generation module supports the configuration and switching of multiple test data modes, thereby shortening the development cycle and upgrade cost of the test system and enabling rapid adaptation to different types of DRAM and different test requirements.

[0062] 3. Improved testing efficiency: This application utilizes the parallel logic resources within the FPGA to execute operations such as address generation, stimulus generation, timing drive, response acquisition, and data formatting in a hardware parallel circuit and pipeline manner, allowing multiple test steps to be processed in parallel. Simultaneously, the FPGA chip can integrate multiple functional modules to support multi-channel parallel testing, with each test channel independently configurable with different test parameters, simultaneously testing multiple DRAMs. Compared to the traditional serial instruction execution mode of ATE, this significantly improves test throughput.

[0063] 4. Reduced communication overhead between ATE and FPGA: This application incorporates a BIST control unit within the FPGA. Upon test initiation, the BIST control unit utilizes a finite state machine to control the address generator, vector generator, and control signal generator, enabling autonomous execution of test procedures such as the MARCH and GALPAT algorithms without ATE intervention. Simultaneously, the ATE retains the authority for remote real-time interruption, parameter reconfiguration, and status reading. This dual-mode control of "autonomous execution + remote controllability" balances test efficiency with debugging flexibility, reducing communication overhead between the ATE and FPGA.

[0064] 5. Reduced data processing burden on the ATE host computer: This application incorporates a data formatting module within the FPGA. This module employs a three-stage pipeline architecture, performing preprocessing operations such as response data packaging, address tag addition, timestamp insertion, and protocol encapsulation within the FPGA. The data frames received by the ATE directly contain structured information such as address tags, timestamps, and response data. Fault location and result analysis can be performed without additional data parsing and address matching by the ATE, thereby reducing the data processing burden on the ATE host computer's CPU and improving the response speed of remote real-time analysis.

[0065] 6. Reduced bandwidth usage of high-speed communication interfaces: The data formatting module in this application integrates an optional data compression mechanism. In full-match compression mode, when the response data from multiple consecutive addresses is completely consistent with the expected data, only the first address and the number of consecutive passes are reported, rather than reporting each one individually. In fault-only reporting mode, a data frame is generated and reported only when the response data is inconsistent with the expected data. Through the above compression mechanism, the data transmission volume of the high-speed communication interface is effectively reduced, enabling medium- and low-speed communication interfaces to handle the data reporting task of DRAM high-speed testing. Attached Figure Description

[0066] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an undue limitation of this application.

[0067] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0068] Figure 1 This is a connection diagram of the FPGA-based DRAM function test system according to Embodiment 1 of this application;

[0069] Figure 2 This is an architecture diagram of the FPGA-based DRAM functional testing system of Embodiment 1 of this application;

[0070] Figure 3 This is a three-stage pipeline structure diagram of the data formatting module in the FPGA-based DRAM functional test system of Embodiment 1 of this application;

[0071] Figure 4 This is an architecture diagram of the FPGA-based DRAM functional testing system of Embodiment 2 of this application;

[0072] Figure 5This is an architecture diagram of the BIST control unit in the FPGA-based DRAM functional test system of Embodiment 2 of this application;

[0073] Figure 6 This is a flowchart of the FPGA-based DRAM function testing method according to Embodiment 3 of this application;

[0074] Figure 7 This is a connection diagram of the system applied to the wafer-level testing stage in Embodiment 5 of this application;

[0075] Figure 8 This is a connection diagram of the system applied to the finished product testing stage in Embodiment 6 of this application.

[0076] Figure label:

[0077] 100. ATE; 200. FPGA chip; 201. Communication interface module; 202. Instruction parsing module; 203. Timing generation module; 204. Stimulus generation module; 205. Address generation module; 206. Response acquisition module; 207. Data formatting module; 2071. Input buffer unit; 2072. Data packing engine; 2073. Protocol encapsulation unit; 208. Result reporting module; 209. BIST control unit; 2091. BIST controller; 2092. Address generator; 2093. Vector generator; 2094. Control signal generator; 2095. Comparator; 2096. Selector MUX; 300. DRAM. Detailed Implementation

[0078] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0079] Example 1

[0080] like Figure 1As shown, the FPGA-based DRAM functional testing system involved in Embodiment 1 of this application includes an ATE100 (i.e., an automatic test device) and an FPGA chip 200. The ATE100, as a host computer control unit, is connected to the FPGA through a high-speed communication interface. It is used to send test commands, configuration parameters, and start the test process to the FPGA chip 200, and to receive the test result data returned by the FPGA chip 200 in real time. The FPGA chip 200, as a test function execution unit, is used to generate read / write timing and stimulus signals for the DRAM 300 and execute the corresponding functional test algorithm. At the same time, the FPGA chip 200 is also used to collect the output response data of the DRAM 300 and format it into data that can be recognized by the ATE100.

[0081] In this embodiment, the high-speed communication interface is a PCIe interface, and the FPGA chip 200 is connected to the DRAM 300 under test through the DRAM 300 interface. The DRAM 300 interface includes data lines (DQ), address lines (ADDR), control lines (including chip select CS, row address strobe RAS, column address strobe CAS, and write enable WE, etc.) and clock lines (CK).

[0082] The ATE100 and FPGA adopt a master-slave control mode: the ATE100 acts as the master device, responsible for issuing test commands, configuration parameters and starting the test process to the FPGA chip 200; the FPGA chip 200 acts as the slave device, responsible for executing specific test tasks and sending the test results back to the ATE100.

[0083] like Figure 2 As shown, the FPGA chip 200 integrates the following functional modules:

[0084] Communication interface module 201: Responsible for high-speed data communication with ATE100, receiving test commands and configuration parameters, and reporting test result data. Communication interface module 201 establishes the data link, sends and receives data packets, and manages the link status according to the selected high-speed interface protocol (PCIe interface).

[0085] Instruction parsing module 202: Connected to communication interface module 201, it is used to receive and parse the test instructions and configuration parameters issued by ATE100, and distribute the parsed information to the corresponding modules of FPGA chip 200. The test instructions include: test start instruction, test pause instruction, test termination instruction, and mode switching instruction, etc.; the configuration parameters include: operating frequency, data bit width, test data mode, start address, end address, and number of tests, etc.

[0086] Timing generation module 203: Connected to instruction parsing module 202, it generates read / write timing signals conforming to the DRAM300 interface specification based on the parsed test instructions. Internally, timing generation module 203 includes a clock generation submodule based on an FPGA phase-locked loop (PLL), capable of generating high-precision, low-jitter clock signals. Timing generation module 203 supports multiple DRAM300 interface standards and enables flexible switching between different interface standards through parameterized design.

[0087] Stimulus generation module 204: Connected to instruction parsing module 202, it is used to generate various types of test stimulus data. The data types supported by stimulus generation module 204 include:

[0088] (1) All 0 / All 1 data: used to detect the basic read and write functions of DRAM300 memory cells;

[0089] (2) Checkerboard data: used to detect coupling faults between storage units;

[0090] (3) Walking Pattern: Used to detect address decoding faults;

[0091] (4) Pseudo-random sequence data (PRBS): used to test the working stability of DRAM300 in random data mode;

[0092] (5) User-defined data mode: Users can send custom data modes through the ATE100 host computer.

[0093] Address generation module 205: Connected to instruction parsing module 202, it is used to generate the address sequence required for testing. Address generation module 205 supports three address generation modes:

[0094] (1) Address incrementing mode: starting from the starting address and gradually incrementing to the ending address;

[0095] (2) Address decreasing pattern: starting from the end address and gradually decreasing to the start address;

[0096] (3) Address jump mode: accesses the address space by jumping according to the preset jump step size.

[0097] It should be noted that the address generation module 205 uses an adder to perform address increment and decrement operations.

[0098] Response acquisition module 206: Connected to the DRAM300 interface, it is used to acquire data output by the DRAM300 in response to read and write operations. The response acquisition module 206 acquires data using a sampling clock that matches the output data rate of the DRAM300. The sampling clock is generated by the FPGA's internal PLL based on the clock configuration parameters issued by ATE100. The response acquisition module 206 internally includes a data buffer submodule for temporarily storing the acquired response data.

[0099] Data formatting module 207: Connected to response acquisition module 206, it is used to format the acquired response data into a data stream according to a preset communication protocol. Formatting operations include: data packaging, adding timestamps, adding channel identifiers, and data compression.

[0100] like Figure 3 As shown, the data formatting module 207 is implemented in the FPGA using a three-stage pipeline architecture, mainly including the following sub-modules:

[0101] (1) Input buffer unit 2071:

[0102] The input buffer unit 2071 is directly connected to the response acquisition module 206, using an asynchronous FIFO (First In First Out) as a data buffer. Since the operating clock of the response acquisition module 206 (a high-frequency clock matching the output data rate of the DRAM 300) and the processing clock of the data formatting module 207 (typically the operating clock of the communication interface) may belong to different clock domains, the asynchronous FIFO is used to achieve cross-clock domain data buffering and rate matching. The FIFO depth is pre-configured according to the data bit width of the DRAM 300 and the amount of test data to ensure that data overflow does not occur at high data rates.

[0103] (2) Data Packaging Engine 2072:

[0104] The data packing engine 2072 is the core computational unit of the formatting module. Controlled by a finite state machine (FSM), it is responsible for reading raw response data from the FIFO and assembling the data according to a preset frame format. The packing engine internally includes:

[0105] Data splicer: splices or splits parallel data (such as 32-bit, 64-bit, or 128-bit) from the response acquisition module 206 as needed according to bit width;

[0106] Address label inserter: Receives the current test address from address generation module 205 and binds it to the corresponding response data;

[0107] Timestamp inserter: Receives the current time value from the FPGA's internal global timer and adds timestamp information to each set of data;

[0108] Channel Identifier Inserter: In multi-channel parallel testing scenarios, inserts the test channel number to which the current data belongs.

[0109] (3) Protocol encapsulation unit 2073:

[0110] The protocol encapsulation unit 2073 encapsulates the data payload output by the packetization engine into data frames conforming to the protocol standard, according to the communication protocol (such as PCIe or Gigabit Ethernet) agreed upon between ATE100 and FPGA chip 200. The encapsulation operation includes:

[0111] Add a protocol header, which includes information such as data length, data type, and frame sequence number;

[0112] Calculate and add check fields (such as CRC checksum) to ensure the integrity of data transmission;

[0113] Data escaping or scrambling is performed when necessary to meet physical layer transmission requirements.

[0114] For example, each frame of data output by the data formatting module 207 adopts a standardized structure as shown in Table 1:

[0115] Table 1: Data Standardization Structure

[0116]

[0117] After receiving the data frame, the ATE100 host computer can directly extract the address tag, timestamp, and response data from the frame without performing additional protocol parsing or address matching, and can then perform fault location and result analysis.

[0118] Result reporting module 208: Connected to data formatting module 207 and communication interface module 201, it is used to report the formatted data stream to ATE100 through a high-speed communication interface. Result reporting module 208 supports real-time reporting mode (reporting after each read / write operation) and batch reporting mode (reporting centrally after a test block is completed).

[0119] The testing system in this embodiment has the following advantages compared with the prior art:

[0120] Cost advantage: Replacing the dedicated test hardware in the traditional ATE100 with the FPGA chip 200 significantly reduces system costs. The FPGA chip 200 is a general-purpose programmable logic device, and its cost is far lower than that of the dedicated hardware module of the ATE100 with equivalent performance.

[0121] Flexibility Advantage: The field-programmable nature of the FPGA chip 200 allows the test system to quickly adapt to different types of DRAM300 and various testing requirements. When the DRAM300 interface standard is upgraded or the test algorithm is updated, the system upgrade can be completed simply by updating the FPGA configuration file.

[0122] Efficiency advantages: The parallel processing capabilities and multi-channel test architecture of the FPGA significantly improve test throughput. The BIST test mode further reduces the communication overhead between the ATE100 and the FPGA, improving test efficiency.

[0123] Scalability advantages: Supports multi-FPGA cascading expansion, allowing for flexible expansion of the number of test channels according to testing needs. In large-scale mass production testing scenarios, testing capabilities can be linearly increased by adding 200 FPGA chips.

[0124] Full process coverage: The system of this application is applicable to both wafer-level (CP) testing and finished product (FT) testing, and can achieve full process functional testing coverage of DRAM300 from wafer to finished product.

[0125] Example 2

[0126] like Figure 4 As shown, based on Embodiment 1, this embodiment further provides a DRAM functional test system with BIST test mode. The BIST control unit 209 is an optional enhancement module, which is integrated inside the FPGA chip 200.

[0127] like Figure 5 As shown, the BIST control unit 209 includes:

[0128] (1) BIST Controller 2091: Implemented using a finite state machine, responsible for controlling the overall process of BIST testing;

[0129] (2) Address generator 2092: used to generate the address sequence required for the BIST test;

[0130] (3) Vector generator 2093: used to generate test vectors according to a preset test algorithm;

[0131] (4) Control signal generator 2094: used to generate control signals required for DRAM300 testing;

[0132] (5) Comparator 2095: Used to compare the response data read from DRAM300 with the expected data to determine whether there is a fault;

[0133] (6) Selector MUX2096: Used to select between different test sources.

[0134] Example 3

[0135] like Figure 6 As shown, Embodiment 3 of this application relates to an FPGA-based DRAM functional testing method, which uses the system as described in Embodiment 1. The testing method includes:

[0136] S100 Configuration and Startup Procedure: After the system is powered on, ATE100 and FPGA chip 200 establish a communication connection through a high-speed communication interface. ATE100 detects the online status of FPGA chip 200, and FPGA chip 200 completes internal logic initialization and self-test. ATE100 sends test configuration parameters and test start commands to FPGA chip 200 through the communication interface. The test configuration parameters include, but are not limited to:

[0137] Operating frequency: for example, 800MHz, 1066MHz, 1333MHz, 1600MHz, etc.;

[0138] Data bit width: for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.;

[0139] Test data modes: All 0s / All 1s / Checkerboard / Movement / Pseudo-random / Custom;

[0140] Address range: starting address and ending address;

[0141] Number of tests: The number of times each address is repeatedly tested;

[0142] Test algorithms: MARCH algorithm, GALPAT algorithm.

[0143] S200, Instruction Parsing and Mode Configuration Steps: The FPGA chip 200 receives and parses the test configuration parameters and test start instructions, and configures the working mode of each internal module according to the configuration parameters.

[0144] S300, Test stimulus generation steps: The instruction parsing module 202 of the FPGA chip 200 receives and parses the test configuration parameters and test start instructions issued by the ATE100. Based on the parsing results, it configures the working parameters of the timing generation module 203, the stimulus generation module 204, and the address generation module 205. Specifically, according to the configured test mode, the FPGA chip 200 generates read and write timing signals conforming to the DRAM300 interface specification through the timing generation module 203, generates test stimulus data through the stimulus generation module 204, and generates a test address sequence through the address generation module 205.

[0145] S400, Test Execution Steps: The FPGA chip 200 applies read / write timing signals, test stimulus data, and address signals to the DRAM under test 300, performing write and read operations. Specifically, the FPGA chip 200 performs DRAM functional tests according to the configured test mode:

[0146] S401, The address generation module 205 generates the current test address according to the configured address mode;

[0147] S402, The stimulus generation module 204 generates test stimulus data according to the configured data mode;

[0148] S403, Timing generation module 203 generates write timing signals that conform to the DRAM300 interface specification;

[0149] S404 and FPGA chip 200 apply test stimulus data and address signals to DRAM 300 according to the write timing sequence to perform a write operation;

[0150] S405, Timing generation module 203 switches to read timing mode;

[0151] S406 and FPGA chip 200 apply address signals to DRAM 300 according to the read timing sequence to perform the read operation.

[0152] S500, Response Acquisition Steps: The FPGA chip 200 acquires the response data output by the DRAM 300 under test in response to the read / write timing signals and stimulus data through the response acquisition module 206 at a sampling clock that matches the output data rate of the DRAM 300, and temporarily stores the acquired data in the internal buffer.

[0153] S600, Data Formatting Steps: The data formatting module 207 of the FPGA chip 200 reads the response data from the buffer and formats the read response data into a data stream according to a preset communication protocol. Specifically, this includes the following steps:

[0154] S601, Data Reception and Buffering: Write the acquired DRAM300 response data into the asynchronous FIFO;

[0155] S602, State Machine Wake-up and Data Reading: When the amount of data cached in the asynchronous FIFO reaches a preset threshold, the packing engine is woken up to read data from the FIFO;

[0156] S603, Data Assembly: Parallel execution of reading raw response data from FIFO, obtaining the current test address and inserting the address label field, obtaining the current time value and inserting the timestamp field, and obtaining the current channel number and inserting the channel number field;

[0157] S604, Protocol Encapsulation: The assembled data payload is encapsulated according to the communication protocol between ATE100 and FPGA chip 200, a protocol header and a verification field are added, and the data is written to the output buffer.

[0158] S605, Data Reporting Trigger: The data frames in the output buffer are reported to ATE100 through the communication interface.

[0159] S700, Result Reporting Steps: The result reporting module 208 of the FPGA chip 200 reports the formatted data stream to the ATE100 through the communication interface. The reporting mode can be selected as real-time reporting or batch reporting according to the test requirements.

[0160] S800, Result Analysis Steps: The ATE100 receives and analyzes the data stream reported by the FPGA chip 200, comparing the actual read data with the expected data. If they match, the memory cell is deemed to have passed the test; otherwise, the fault address and fault data are recorded. The ATE100 generates a test report based on the test results of all memory cells and displays it visually through the ATE100's display module.

[0161] Specifically, the ATE100 has comprehensive test result data analysis capabilities. After receiving the test result data reported by the FPGA, the ATE100 performs the following analysis operations:

[0162] S801, Bit-by-bit comparison: Compare the data read from each address with the expected data bit by bit, and mark the fault bits;

[0163] S802. Fault Classification: Based on the distribution characteristics of fault bits, faults are classified (such as fixed faults, coupling faults, address faults, etc.).

[0164] S803, Fault Statistics: Statistics on the total number of faults, fault type distribution, and fault address distribution for each DRAM300;

[0165] S804, Yield Calculation: Calculate the product yield of the wafer or batch based on the test results;

[0166] S805, Fault Map Generation: For wafer-level testing, a fault distribution map (Bin Map) is generated on the wafer, which intuitively displays the test results of each chip on the wafer.

[0167] After the analysis is completed, the ATE100 displays the test results through the display module and stores the result data in the memory for subsequent quality traceability and process improvement.

[0168] S900 Test Completion and Cleanup: After completing the test of all addresses, the FPGA chip 200 sends a test completion signal to the ATE100. Upon receiving the signal, the ATE100 can issue test instructions for the next chip or terminate the entire test process.

[0169] It should be noted that other specific implementations of the FPGA-based DRAM function testing method in this embodiment can be found in the specific implementations of the FPGA-based DRAM function testing system described above. To avoid redundancy, they will not be repeated here.

[0170] Example 4

[0171] Building upon Example 3, this example further provides a DRAM functional testing method with a BIST test mode. As described in Example 2, in the test system, the FPGA chip 200 integrates a BIST control unit 209 to support the BIST test mode. The test procedure in BIST test mode is as follows:

[0172] (1) ATE100 sends BIST test start command and configuration parameters to FPGA chip 200 through high-speed communication interface;

[0173] (2) After the instruction parsing module 202 of the FPGA chip 200 parses the instruction, it activates the BIST control unit 209;

[0174] (3) The BIST controller 2091 (finite state machine) starts the test process, and the control address generator 2092, vector generator 2093 and control signal generator 2094 work together;

[0175] (4) Address generator 2092 generates test address sequence, vector generator 2093 generates test vector, and control signal generator 2094 generates DRAM300 control signal;

[0176] (5) The FPGA chip 200 applies the above signal to the DRAM 300 under test through the DRAM 300 interface;

[0177] (6) The comparator 2095 compares the response data read from the DRAM 300 with the expected data generated by the vector generator 2093 in real time;

[0178] (7) If the comparison results are consistent, the test continues to the next address; if the comparison results are inconsistent, the BIST controller 2091 records the fault address and can choose to continue the test or pause the test according to the configuration.

[0179] (8) After the BIST test is completed, the BIST control unit 209 reports the test results (including pass / fail status, fault address list, etc.) to ATE100 through the result reporting module 208.

[0180] In this embodiment, the advantage of the BIST test mode is that the test process is completely controlled autonomously by the internal logic of the FPGA, without the need for real-time intervention of the ATE100, which can significantly reduce the communication overhead between the ATE100 and the FPGA and improve test efficiency.

[0181] Example 5

[0182] like Figure 7 As shown, in one embodiment of this application, the system is applied to the wafer-level (CP) testing stage.

[0183] In wafer-level (CP) testing, the wafer contains multiple DRAM 300s (i.e., dies). The FPGA chip 200 establishes a temporary electrical connection with the DRAM 300s on the wafer via a probe card. The probe card is equipped with a probe array corresponding to the pads of the DRAM 300s.

[0184] The testing process is as follows:

[0185] (1) The ATE100 controls the probe station to move the wafer so that the probes on the probe card contact the pads of the DRAM300 under test.

[0186] (2) ATE100 sends test configuration and start commands to FPGA chip 200 through high-speed communication interface;

[0187] (3) The FPGA chip 200 performs the above test method to perform functional tests on the current DRAM 300;

[0188] (4) After the test is completed, the FPGA will report the test results to ATE100;

[0189] (5) The ATE records the test results and controls the probe station to move to the next DRAM position;

[0190] (6) Repeat steps (2) to (5) above until all DRAMs on the wafer have been tested.

[0191] Example 6

[0192] like Figure 8 As shown, in one embodiment of this application, the system is applied to the finished product (FT) testing stage.

[0193] In the final product (FT) test, the packaged DRAM300 establishes an electrical connection with the FPGA chip 200 via a test socket. The test socket is equipped with contact terminals corresponding to the pins of the DRAM300.

[0194] The testing process is similar to CP testing, but the difference is that in FT testing, the DRAM300 is already packaged and tested via a test socket, eliminating the need for a probe station and probe card. FT testing can be used to screen for faults introduced during the packaging process, ensuring that the DRAM300 is fully functional upon leaving the factory.

[0195] Example 7

[0196] In a preferred embodiment of this application, the FPGA chip 200 supports multi-channel parallel testing.

[0197] The FPGA chip 200 integrates multiple timing generation modules 203, stimulus generation modules 204, address generation modules 205, and response acquisition modules 206, with each module corresponding to a test channel. Each test channel can be independently configured with different test parameters, allowing simultaneous testing of multiple DRAMs 300.

[0198] The process for multi-channel parallel testing is as follows:

[0199] (1) ATE100 sends multi-channel test configuration parameters to FPGA chip 200, and configures parameters such as working frequency and test data mode for each channel respectively;

[0200] (2) The instruction parsing module 202 of the FPGA chip 200 distributes the configuration parameters of each channel to the corresponding functional modules;

[0201] (3) Each test channel executes the test process independently without interfering with each other;

[0202] (4) The test results of each channel are reported to ATE100 through the result reporting module 208 respectively;

[0203] (5) ATE100 summarizes the test results of each channel and generates a comprehensive test report.

[0204] Multi-channel parallel testing can significantly improve test throughput, and is especially suitable for wafer-level testing scenarios that require rapid screening of a large number of chips.

[0205] Example 8

[0206] In one embodiment of this application, the FPGA chip 200 supports flexible switching between multiple testing algorithms.

[0207] The FPGA chip 200 has pre-built hardware implementations of various testing algorithms, including but not limited to:

[0208] (1) MARCH algorithm: a classic memory testing algorithm that detects fixed faults, transition faults and coupling faults by performing multiple read and write operations on each memory cell;

[0209] (2) GALPAT algorithm (Galloping Pattern): It tests memory cells one by one by "walking" to detect address decoding faults and adjacent cell coupling faults;

[0210] (3) Checkerboard algorithm: detects coupling faults between storage units by writing checkerboard data patterns;

[0211] (4) Pseudo-random test algorithm: The DRAM300 is read and written by a pseudo-random sequence, which can simulate the data pattern in the actual working scenario.

[0212] Users can issue commands via ATE100 to select the desired test algorithm. After the instruction parsing module 202 of FPGA chip 200 parses the command, the control selector MUX2096 connects the corresponding test logic to the test path. During the test, users can also dynamically switch test algorithms via ATE100 without reconfiguring FPGA chip 200.

[0213] The flexible switching of the test algorithm enables this application to adapt to the testing requirements of different DRAM300s, different test stages and different fault models, and has wide applicability.

[0214] The ATE100 possesses comprehensive test result data analysis capabilities. After receiving the test result data reported by the FPGA, the ATE100 performs the following analysis operations:

[0215] (1) Bit-by-bit comparison: Compare the data read from each address with the expected data bit by bit, and mark the fault bits;

[0216] (2) Fault classification: Based on the distribution characteristics of fault bits, faults are classified (such as fixed faults, coupling faults, address faults, etc.).

[0217] (3) Fault statistics: Statistics on the total number of faults, fault type distribution, and fault address distribution for each DRAM300;

[0218] (4) Yield calculation: Calculate the yield of wafers or batches based on the test results;

[0219] (5) Fault map generation: For wafer-level testing, a fault distribution map (Bin Map) is generated on the wafer to intuitively display the test results of each chip on the wafer.

[0220] After the analysis is completed, the ATE100 displays the test results through the display module and stores the result data in the memory for subsequent quality traceability and process improvement.

[0221] The above are merely preferred embodiments of this application; however, the scope of protection of this application is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in this application, based on the technical solution and its improved concept, should be covered within the scope of protection of this application.

Claims

1. A DRAM functional testing system based on FPGA, characterized in that, This includes the ATE (Automatic Equipment) and the FPGA chip that communicates with it via a communication interface; The ATE is used to send test commands, configuration parameters and start the test process to the FPGA chip, and to receive the test result data returned by the FPGA chip. The FPGA chip is used to generate read / write timing and stimulus signals for DRAM and execute corresponding functional test algorithms. The FPGA chip is also used to acquire the output response data of DRAM and format it into a data stream that can be recognized by ATE.

2. The FPGA-based DRAM functional testing system according to claim 1, characterized in that, The FPGA chip includes the following modules: The communication interface module is used to communicate with the ATE, receive test commands and configuration parameters, and report test result data. The instruction parsing module is used to receive and parse the test instructions and configuration parameters issued by the ATE; The timing generation module is used to generate read and write timing signals that conform to the DRAM interface specification based on the parsed test instructions; The incentive generation module is used to generate various types of test incentive data; The address generation module is used to generate the address sequence required for testing. The response acquisition module is used to acquire response data output by the DRAM in response to the read / write timing signals and stimulus data; The data formatting module is used to format the collected response data into a data stream according to a preset communication protocol; The result reporting module is used to report the formatted data stream to the ATE through the communication interface.

3. The FPGA-based DRAM functional testing system according to claim 2, characterized in that, The data formatting module includes: The input buffer unit uses an asynchronous FIFO to achieve cross-clock domain data buffering and rate matching; A data packaging engine is used to read raw response data from the input buffer unit and assemble the data according to a preset frame format. The data packaging engine includes a data splicer, an address tag inserter, a timestamp inserter, and a channel identifier inserter. The address tag inserter is used to bind the current test address with the corresponding response data. The timestamp inserter is used to add a time value from the FPGA's internal global timer to the data. The channel identifier inserter is used to insert the test channel number to which the current data belongs in a multi-channel parallel test scenario. The protocol encapsulation unit is used to encapsulate the data payload output by the data packaging engine into a data frame that conforms to the communication interface protocol standard.

4. The FPGA-based DRAM functional testing system according to claim 2, characterized in that, The timing generation module includes a clock generation submodule based on an FPGA phase-locked loop. The clock generation submodule is used to generate high-precision clock signals, and the timing generation module supports switching between multiple DRAM interface standards through parameterized design. The incentive generation module supports all-zero data, all-one data, chessboard data, move data, pseudo-random sequence data, and user-defined data modes; the address generation module supports address increment mode, address decrement mode, and address jump mode.

5. The FPGA-based DRAM functional testing system according to claim 2, characterized in that, The FPGA chip also includes a BIST control unit, which comprises: The BIST controller, implemented using a finite state machine, is used to control the overall process of BIST testing. An address generator is used to generate the address sequences required for the BIST test. A vector generator, used to generate test vectors based on a preset test algorithm; A control signal generator is used to generate the control signals required for DRAM testing. A comparator is used to compare the response data read from DRAM with the expected data to determine if a fault exists; The selector MUX is used to select between different test sources.

6. The FPGA-based DRAM functional testing system according to any one of claims 1-5, characterized in that, The FPGA chip establishes a temporary electrical connection with the DRAM on the wafer through a probe card for use in the wafer-level testing stage; or, the FPGA chip establishes an electrical connection with the packaged DRAM through a test socket for use in the finished product testing stage.

7. A DRAM functional testing method based on FPGA, employing the system as described in claim 2, characterized in that, The method includes: Configuration and startup steps: The ATE sends test configuration parameters and test startup commands to the FPGA chip through the communication interface; Instruction parsing and mode configuration steps: The FPGA chip receives and parses the test configuration parameters and test start command, and configures the working mode of each internal module according to the configuration parameters; Test stimulus generation steps: According to the configured test mode, the FPGA chip generates read and write timing signals that conform to the DRAM interface specification through the timing generation module, generates test stimulus data through the stimulus generation module, and generates test address sequence through the address generation module; Test execution steps: The FPGA chip applies the read / write timing signals, test stimulus data, and address signals to the DRAM under test to perform write and read operations; Response acquisition steps: The FPGA chip acquires the response data output by the tested DRAM in response to the read / write timing signals and stimulus data through the response acquisition module; Data formatting steps: The FPGA chip formats the acquired response data into a data stream according to a preset communication protocol; Result reporting step: The FPGA chip reports the formatted data stream to the ATE through the communication interface; Results analysis steps: The ATE receives and analyzes the data stream, compares the received response data with the expected data, and generates a test result report.

8. The FPGA-based DRAM functional testing method according to claim 7, characterized in that, The data formatting steps specifically include: Data reception and buffering: Write the acquired DRAM response data into an asynchronous FIFO; State machine wake-up and data reading: When the amount of data cached in the asynchronous FIFO reaches a preset threshold, the packaging engine is woken up to read data from the FIFO; Data assembly: Parallel execution includes reading raw response data from the FIFO, obtaining the current test address and inserting it into the address tag field, obtaining the current time value and inserting it into the timestamp field, and obtaining the current channel number and inserting it into the channel number field; Protocol encapsulation: The assembled data payload is encapsulated according to the communication protocol between the ATE and the FPGA chip, a protocol header and a verification field are added, and the data is written to the output buffer; Data reporting trigger: The data frames in the output buffer are reported to the ATE through the communication interface.

9. The FPGA-based DRAM functional testing method according to claim 7, characterized in that, Also includes the BIST test mode: The ATE sends the BIST test start command and configuration parameters to the FPGA chip through the communication interface; After the instruction parsing module of the FPGA chip parses the instruction, it activates the BIST control unit. The finite state machine of the BIST control unit initiates the test process, and the control address generator, vector generator, and control signal generator work together to generate test address sequences, test vectors, and DRAM control signals. The FPGA chip applies the above signal to the DRAM under test through the DRAM interface; The comparator compares the response data read from DRAM with the expected data generated by the vector generator in real time. If the comparison results are inconsistent, the BIST controller records the fault address; After the BIST test is completed, the BIST control unit reports the test results to the ATE through the result reporting module.

10. The FPGA-based DRAM functional testing method according to claim 7, characterized in that, In the data formatting step, when the response data of multiple consecutive addresses is completely consistent with the expected data, only the first address and the number of consecutive passes are reported; and / or, when the ATE is configured to report faults only, a data frame is generated and reported only when the response data is inconsistent with the expected data.

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