A memory, processor chip and electronic device

Abstract

The application relates to the technical field of memories, and provides a memory, a processor chip and an electronic device, which are used for improving the problem that the existing memory requires a long time for testing and writing data. The memory comprises a plurality of storage arrays and a plurality of write enable circuits, the plurality of write enable circuits correspond to the plurality of storage arrays one by one; the write enable circuit is used for receiving a storage array selection signal and a test mode signal; the write enable circuit is used for outputting a valid array enable signal to an enable end of the storage array when the test mode signal is valid; the write enable circuit is also used for outputting an array enable signal which is the same as the enable state of the storage array selection signal to the enable end of the storage array when the test mode signal is invalid; the storage array is used for writing data when the enable end is valid; and the write enable circuits corresponding to at least two storage arrays receive the same test mode signal.

Description

Technical Field

[0001] This application relates to the field of memory technology, and more particularly to a memory, processor chip, and electronic device. Background Technology

[0002] Random access memory (RAM) is a storage device in a computer used to store data and instructions. RAM includes various types such as dynamic random access memory (DRAM), static random access memory (SRAM), and graphics random access memory (GRAM).

[0003] With the development of memory technology, the storage capacity of memory is becoming larger and larger, with memory chips integrating hundreds of thousands or even more memory cells. During the chip screening process, in order to ensure the stability and reliability of the memory, all memory cells need to be tested multiple times with write and read operations to detect manufacturing defects in advance, resulting in a long testing time. Summary of the Invention

[0004] This application provides a memory, processor chip, and electronic device to improve the problem of long time required for existing memory tests to write data.

[0005] To address the aforementioned problems, the technical solution adopted in this application is as follows:

[0006] In a first aspect, embodiments of this application provide a memory including multiple memory banks and multiple write enable circuits, each corresponding to one of the memory banks. The write enable circuits receive a memory bank selection signal and a test mode signal. When the test mode signal is valid, the write enable circuit outputs a valid array enable signal to the enable terminal of the memory bank. When the test mode signal is invalid and the memory bank selection signal is valid, the write enable circuit outputs a valid array enable signal to the enable terminal of the memory bank. When the test mode signal is invalid and the memory bank selection signal is invalid, the write enable circuit outputs an invalid array enable signal to the enable terminal of the memory bank. The memory banks are used to write data when the enable terminal of the memory bank is valid. At least two write enable circuits corresponding to the memory banks receive the same test mode signal.

[0007] The memory provided in this application embodiment has at least two write enable circuits corresponding to the memory arrays receiving the same test mode signal. When the test mode signal is invalid, data can be written to the memory array according to the validity of the memory array selection signal, thus enabling two operating modes. When the test mode signal is valid, data can be written to the memory array regardless of whether the memory array selection signal is valid. These write enable circuits synchronously enable the memory arrays, thereby enabling simultaneous writing of data to multiple memory arrays, improving the efficiency of writing data during memory testing, and reducing test time.

[0008] In one possible implementation of the first aspect, the write enable circuit is further configured to receive a check enable signal; the write enable circuit is configured to output a valid array enable signal to the enable terminal of the storage array when both the check enable signal and the test mode signal are valid; and to output an array enable signal with the same enable state as the storage array selection signal to the enable terminal of the storage array when both the check enable signal and the test mode signal are invalid. In this embodiment, the check enable signal is used to control the read and write enable of the storage array, and the storage array can only perform read and write operations when the check enable signal is valid.

[0009] In one possible implementation of the first aspect, the write enable circuit is further specifically used to output an invalid array enable signal to the enable terminal of the memory array when the enable signal is checked to be invalid. Reading or writing to the memory array is not permitted when the enable signal is checked to be invalid.

[0010] In one possible implementation of the first aspect, multiple write enable circuits receive the same check enable signal. This allows for synchronous control of read and write enable of multiple memory arrays.

[0011] In one possible implementation of the first aspect, when multiple write enable circuits receive the same test mode signal, they also receive the same check enable signal, so that a group of memory arrays connected to the same test mode signal can be controlled by the same check enable signal.

[0012] In one possible implementation of the first aspect, the write enable circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is used to receive a memory array selection signal, the second input terminal is used to receive a test mode signal, the third input terminal is used to receive a check enable signal, and the output terminal is connected to the enable terminal of the corresponding memory array to output an array enable signal. The write enable circuit also includes a NOR gate and an OR gate. The first input terminal of the NOR gate is connected to the first input terminal of the write enable circuit, the second input terminal of the NOR gate is connected to the second input terminal of the write enable circuit, and the output terminal of the NOR gate is connected to the first input terminal of the OR gate. The second input terminal of the OR gate is connected to the third input terminal of the write enable circuit, and the output terminal of the OR gate is connected to the output terminal of the write enable circuit.

[0013] In one possible implementation of the first aspect, the memory further includes a memory array selection circuit for receiving an address signal and outputting a memory array selection signal.

[0014] Secondly, embodiments of this application also provide a processor chip, including a processor and a memory as provided in the first aspect and any implementation thereof, wherein the memory is electrically connected to the processor.

[0015] Thirdly, embodiments of this application also provide an electronic device, including a circuit board and a processor chip as provided in the second aspect, wherein the processor chip is electrically connected to the circuit board. Attached Figure Description

[0016] Figure 1 A schematic diagram of an electronic device provided in an embodiment of this application;

[0017] Figure 2 A schematic diagram of a memory provided for an embodiment of this application;

[0018] Figure 3 A schematic diagram of another memory provided for an embodiment of this application;

[0019] Figure 4 A schematic diagram of a storage unit provided in an embodiment of this application;

[0020] Figure 5 A schematic diagram of another memory provided for an embodiment of this application;

[0021] Figure 6 A schematic diagram of a write enable circuit provided in an embodiment of this application;

[0022] Figure 7 A schematic diagram of a storage array provided in an embodiment of this application;

[0023] Figure 8 A schematic diagram of another memory provided for an embodiment of this application;

[0024] Figure 9 A schematic diagram of a storage array selection circuit provided in an embodiment of this application;

[0025] Figure 10 A schematic diagram of a write enable circuit provided in an embodiment of this application;

[0026] Figure 11 A schematic diagram of another write enable circuit provided in an embodiment of this application;

[0027] Figure 12 A schematic diagram of the grouping of the write enable circuit provided in the embodiments of this application;

[0028] Figure 13 This is a schematic diagram of another memory provided in an embodiment of this application. Detailed Implementation

[0029] The following sections will discuss the fabrication and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this description and technology, and do not limit the scope of this application.

[0030] Unless otherwise defined, all technical terms used herein have the same meaning as known to those skilled in the art. Circuits or other components may be described or referred to as “for” performing one or more tasks. In this context, “for” is used to imply a structure (e.g., a circuit system) that includes a circuit / component performing one or more tasks during operation. Thus, a circuit / component may be referred to as “for” performing a task even when it is currently inoperable (e.g., not turned on). Circuits / components used with the term “for” include hardware, such as circuits that perform operations.

[0031] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. In addition, in the embodiments of this application, the words "first" and "second" do not limit the quantity or order.

[0032] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0033] Figure 1 An electronic device 100 provided in this application embodiment can be a terminal device, such as a mobile phone, tablet computer, smart bracelet, or other electronic devices such as a personal computer (PC), server, workstation, etc.

[0034] Electronic device 100 includes a bus 105 and a system-on-chip (SoC) 110 connected to the bus 105. SoC 110 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, SoC 110 may include an application processor (AP) 111 for processing applications, a graphics processing unit (GPU) 112 for processing image data, and a first RAM 113 for caching high-speed data.

[0035] The first RAM 113 can be static random access memory (SRAM), embedded flash (eflash), or graphics random access memory (GRAM), etc. The AP 111, GPU 112, and the first RAM 113 can be integrated into a single die or disposed in multiple dies.

[0036] The electronic device 100 may also include a second RAM 120 connected to the SoC 110 via a bus 105. The second RAM 120 may be dynamic random access memory (DRAM). The second RAM 120 can be used to store volatile data, such as temporary data generated by the SoC 110. The storage capacity of the second RAM 120 is typically larger than that of the first RAM 113, but its read speed is typically slower than that of the first RAM 113.

[0037] The electronic device 100 may also include a communication chip 130 and a power management chip 140 connected to the SoC 110 via a bus 105. The communication chip 130 may be used for protocol stack processing, or for amplifying, filtering, or performing other processing on analog radio frequency signals, or simultaneously performing the above functions. The power management chip 140 may be used to supply power to other chips. The SoC 110 and the second RAM 120 may be packaged in a single package structure, such as using 2.5D (dimension) or 3D packaging, to achieve faster inter-chip data transfer rates.

[0038] Figure 2 This is a schematic diagram of a memory provided in an embodiment of this application. The memory 200 can be as follows: Figure 1The first RAM 113 shown could also be the second RAM 120. This application does not limit the application scenario of the memory 200. Alternatively, the memory 200 could also be RAM located outside the SOC 210. This application does not limit the location of the memory 200 in the electronic device or its positional relationship with the SOC 210.

[0039] like Figure 2 As shown, the memory 200 includes multiple memory arrays 21 and a controller 22 for accessing the memory arrays 21, wherein the controller 22 controls read and write operations of the memory arrays 21. The multiple memory arrays 21 can be a single-layer memory array or a multi-layer memory array stacked perpendicular to the substrate. When two or more layers of memory arrays are included, such a memory can be referred to as a three-dimensional integrated memory structure. A three-dimensional integrated memory structure can reduce the memory footprint and increase storage density.

[0040] Reference Figure 3 and Figure 4 The storage array 21 includes multiple arrayed storage cells, each of which can store 1 bit or more bits of data. The storage array 21 may also include word lines (WL) and bit lines (BL). Each storage cell is electrically connected to a corresponding word line (WL) and bit line (BL). Different storage cells can be electrically connected via WL and BL; for example, storage cells in the same row can be connected to the same word line, and storage cells in the same column can be connected to the same bit line. Word lines can be connected to word line control circuitry (or word line resolvers), and bit lines can be connected to bit line control circuitry (or bit line resolvers).

[0041] The controller 22 may include one or more of the following circuit structures: command decoder 210, control logic circuit 220, and input / output circuit 240. In specific embodiments, it is not limited to these and may include fewer or more components.

[0042] The command decoder 210 can receive commands (CMD) and decode the received commands. For example, commands may include write commands (WR), read commands (RD), and activation commands (ACT).

[0043] Control logic circuit 220 can control components of memory 200 based on the decoding result from command decoder 210. For example, if the decoding result from command decoder 210 indicates a received command activation command, control logic circuit 220 can control word line control circuitry to activate the word line corresponding to the row address (RA) received with the activation command. In this case, data stored in the memory cell connected to the activated word line can be set (e.g., transferred, sent, output, etc.) through a sense amplifier (SA) to input / output circuit 240. For example, if the decoding result from command decoder 210 indicates a received command is a read command (RD), control logic circuit 220 can control input / output circuit 240 to output data from the bit line corresponding to the column address (CA) received with the read command. If the decoding result from command decoder 210 indicates a received command is a write command, control logic circuit 220 can set the write data received from memory controller 102 to input / output circuit 240.

[0044] The aforementioned storage array 21, command decoder 210, control logic circuit 220, and input / output circuit 240 can be integrated into one chip or into multiple chips respectively.

[0045] The memory 200 can be of various types, such as dynamic random access memory (DRAM), static random access memory (SRAM), and graphics random access memory (GRAM). This application embodiment does not limit the specific type of memory 200. Taking dynamic random access memory as an example, a memory cell of dynamic random access memory consists of a transistor and a capacitor, such as... Figure 4 As shown, Figure 4 This is a schematic diagram of a memory cell provided in an embodiment of this application. The first terminal of the transistor T in the memory cell is connected to the bit line (BL), and its second terminal is connected to the first terminal of the capacitor C. The gate of the transistor T is connected to the word line (WL), and the second terminal of the capacitor C can be connected to a voltage terminal. The voltage terminal can be connected to a voltage of a specific level (e.g., a desired voltage level) (e.g., ground voltage or half-supply voltage) through a source line (not shown). Figure 4The example shown is only one structure of a storage unit. The memory can also be other types of memory, and the embodiments of this application do not limit this.

[0046] The memory can perform read and write operations based on the received address signal. The bit width of the address is related to the number of memory arrays and the number of rows and columns of memory cells in the array. For example, if the memory includes 32 banks, the first 5 bits of the write address are used to select the target bank, and the remaining address bits are used to determine the row and column number of the target memory cell.

[0047] Now combine Figures 5-7 This section introduces the read / write principles of memory.

[0048] The memory includes multiple memory arrays. To ensure correct access timing, each memory array includes an enable pin (BEN). When the array enable signal (bank_CEN) received by the enable pin (BEN) is valid, memory cell addresses and data can be transmitted to the memory array, allowing normal read and write operations. Otherwise, if the array enable signal (bank_CEN) received by the enable pin (BEN) is invalid, the memory array cannot be read or written. This embodiment uses an example where the array enable signal (bank_CEN) is active low.

[0049] The command decoder may include a memory array selection circuit. Figure 5 Taking four memory banks as an example, the memory bank selection circuit can output memory bank selection signals (bank_sel) to the memory banks. For instance, the memory bank selection circuit outputs the selection signal bank0_sel to the write enable circuit 0 of bank 0, the selection signal bank1_sel to the write enable circuit 1 of bank 1, the selection signal bank2_sel to the write enable circuit 2 of bank 2, and the selection signal bank3_sel to the write enable circuit 3 of bank 3. In this embodiment, the example is illustrated with the selection signal being active high.

[0050] Figure 6 The schematic diagram of a write enable circuit provided in this application embodiment includes a NOT gate 211 and an OR gate 212. The input terminal of the NOT gate 211 is used to receive the memory array select signal (bank_sel), the output terminal of the NOT gate 211 is connected to the first input terminal of the OR gate 212, the second input terminal of the OR gate 212 is used to receive the check enable signal (CEN), and the output terminal of the OR gate 212 is used to output the enable signal (bank_CEN).

[0051] The storage array selection circuit receives the storage array address and selects the storage array to be accessed based on the address. The write enable circuit outputs a valid array enable signal (bank_CEN) to the storage array's enable terminal BEN when the received storage array selection signal is valid. For example, the write enable circuit receives a check enable signal (CEN) and a storage array selection signal (bank_sel). When the check enable signal is valid, it outputs an array enable signal to the storage array's enable terminal BEN with the same enable state as the storage array selection signal (bank_sel). In this embodiment, the check enable signal is active low, the storage array selection signal is active high, and the array enable signal is active low. When the check enable signal is valid, if the storage array selection signal received by the write enable circuit is high, it outputs a low-level array enable signal to the storage array's enable terminal BEN, allowing data to be written to the storage array. If the storage array selection signal received by the write enable circuit is low, it outputs a high-level array enable signal to the storage array's enable terminal BEN, preventing data from being written to the storage array.

[0052] Figure 5 Taking a four-bank storage array as an example, the address width of the storage array is 2 bits. The storage array selection circuit can select the storage array to access based on the 2-bit address. For example, the storage array address can be 00, 01, 10, or 11. When the storage array address received by the storage array selection circuit is 00, the storage array selection signal bank0_sel output by the storage array is high, and the storage array selection signals bank1_sel, bank2_sel, and bank3_sel are low-high level. When the storage array address received by the storage array selection circuit is 11, the storage array selection signal bank3_sel output by the storage array is high, and the storage array selection signals bank0_sel, bank1_sel, and bank2_sel are low. Table 1 shows the correspondence between the storage array address and the state of the storage array selection signal. In Table 1, a signal state of 1 represents a high level, and a signal state of 0 represents a low level.

[0053] After the target storage array is selected by the storage array selection circuit according to the storage array address, data reading and writing can be completed according to the address of the storage cell.

[0054] First, let's introduce the principle of data writing. Figure 7This is a schematic diagram of a storage array provided in an embodiment of this application. The storage array includes m rows and n columns of storage cells. Both m and n are positive integers, typically powers of 2. Taking writing data to a storage cell located in the second row and third column as an example, this storage cell is connected to word line WL2 and bit line BL3. The storage cell can be located via WL2 and BL3. When writing data, the word line control circuit enables WL2, activating the row of storage cells connected to WL2. Other storage cells connected to word lines are not activated. Activation of a storage cell here can be understood as the storage cell being connected to its connected bit line. After the storage cell connected to WL2 is activated, a write voltage is applied to BL3 through the bit line control circuit. This write voltage can be applied to the activated storage cell connected to BL3, completing the data writing. For other activated storage cells, since no write voltage is applied to their connected bit lines, their stored data or state remains unchanged.

[0055] When reading data, let's continue with the example of reading data from the second row of memory cells. The word line control circuit enables WL2, activating the row of memory cells connected to WL2. This activated row of memory cells discharges to the bit line, causing a change in the voltage on the connected bit line. By sensing the voltage change on the bit line through a sensitive amplifier, the data or state stored in the memory cell can be identified, thus completing the data reading.

[0056] With the development of storage technology, memory storage density is increasing and storage capacity is also expanding. However, due to limitations in semiconductor manufacturing processes, memory cells are more likely to contain defects. In practical applications, it is necessary to screen and identify defective memory chips to avoid using defective memory and related circuitry.

[0057] For example, read / write tests can be used to screen memory. To ensure the reliability and stability of memory, multiple write and read operations need to be performed on all memory cells to detect manufacturing defects in advance. However, memory consists of a large number of memory arrays, and performing multiple write operations on all memory cells individually results in a long testing time.

[0058] To reduce the time spent writing data during testing, data can be written to multiple rows of storage units in parallel to improve efficiency. Testing scenarios differ from real-world memory applications. In real-world applications, the data written to each storage unit may be different, requiring data to be written to each unit individually or row by row. However, in testing scenarios, the same data can be written to the test storage units, such as all 1s or all 0s. This allows for a reduction in the time spent writing data during testing by writing to multiple rows of storage units at once.

[0059] For example, the command decoder decodes the input address and test signal, and uses the word line control circuit to generate the write enable for the word line, thus determining the row number of the memory cell to be written to, such as rows 1 to 4, or rows 1 to 8. The bit line control circuit then selects the corresponding bit line, which is the column number of the memory cell to be written to. During writing, data can be written to multiple rows of memory cells at once, thereby reducing the writing time during testing.

[0060] The above-described multi-line parallel writing method can reduce the time required to write data during testing. However, the decoding logic for parallel writing can only be powers of 2, meaning that the selection of rows to be written must be in units of powers of 2. If the target row address of the parallel write is 2 bits wide, 4 rows can be selected. If the target row address of the parallel write is 3 bits wide, 8 rows can be selected. If the target row address of the parallel write is 4 bits wide, 16 rows can be selected.

[0061] In multi-row parallel writing, besides the row decoding logic, the impact of parallel write current also needs to be considered. During actual writing, voltage is applied to the connected memory cells via bit lines to write data. In normal read / write mode, each bit line writes data to only one connected memory cell. For example, each bit line writes data to the memory cell in the first row, thus completing the data writing to the first row. However, in test scenarios, when writing data to multiple rows of memory cells in parallel, the write current on the bit lines is not infinite; it can only support writing data to a limited number of memory cells. For example, the write current on the bit lines supports writing data to a maximum of 14 memory cells, meaning that in this memory array, each parallel write supports writing data to a maximum of 14 rows of memory cells. However, due to the limitations of the parallel write decoding logic, parallel writing requires enabling powers of 2 rows, such as 8 or 16 rows. The actual hardware circuit can only withstand the parallel write current for writing data to 14 rows of memory cells. Since 14 is greater than 8 but less than 16, this scheme can only be configured to write data to 8 rows in parallel, adding an extra 6 rows of parallel write time and hardware cost.

[0062] To address the aforementioned issues, this application provides a memory that can employ parallel writing of multiple memory arrays, and the number of memory arrays for parallel writing can be configured as needed, minimizing the data writing time during testing within the capabilities of the hardware circuitry.

[0063] See Figure 8 The memory provided in this application includes: a memory array selection circuit, multiple memory arrays (banks) and multiple write enable circuits, with each write enable circuit connected to one of the multiple memory arrays.

[0064] The memory array selection circuit receives the memory array address and outputs a memory array selection signal. The circuit decodes the received memory array address, selects the specific memory array to be read from, written to, or accessed based on the address, and switches the enable state of the corresponding memory array selection signal to a valid state.

[0065] The write enable circuit is used to receive the memory array select signal (bank_sel) and the test mode signal (TWM), and output the array enable signal (bank_CEN) to the enable terminal of the memory array.

[0066] When the received test mode signal is valid, the write enable circuit outputs a valid array enable signal to the memory array to which it is connected, so that the memory array can be accessed, for example, to write data to a target address in the memory array.

[0067] When the received test mode signal is invalid, the write enable circuit outputs an array enable signal to the connected memory array that has the same enable state as the memory array select signal (bank_sel). If the memory array select signal received by the write enable circuit is valid, it outputs a valid array enable signal, and the memory array can be accessed. If the memory array select signal received by the write enable circuit is invalid, it outputs an invalid array enable signal, and the memory array cannot be accessed.

[0068] The memory comprises multiple memory arrays, which can be divided into two or more groups. The write enable circuit for each group of memory arrays receives the same test mode signal. For example... Figure 8 As shown, bank0 and bank1 form one group, and bank2 and bank3 form another group. The write enable circuits corresponding to bank0 and bank1 receive the same test mode signal (TWM1). The write enable circuits corresponding to bank2 and bank3 receive the same test mode signal (TWM2). Taking the test mode signal TWM1 as an example, when this test mode signal is valid, all the memory arrays controlled by it can receive a valid array enable signal and can synchronously write data to this group of memory arrays.

[0069] The test mode signal is used to indicate whether the memory is in test mode, or to indicate whether a group of memory arrays controlled by the test mode signal is writing data to multiple memory arrays in parallel in test mode. When the test mode signal is valid, multiple write enable circuits receiving the test mode signal output valid array enable signals to the corresponding memory arrays. Multiple memory arrays are enabled, and memory cell addresses and data can be transmitted to these multiple memory arrays, realizing parallel writing of data to multiple memory arrays.

[0070] When the test mode signal is invalid, the memory is in non-test mode, and data is written in normal mode, that is, data is written to a target memory cell in a target memory array. The memory array selection signal received by the write enable circuit is used to indicate whether the memory array to which the write enable circuit is connected is the target memory array. When the test mode signal received by the write enable circuit is invalid, that is, the memory is operating in normal write mode, if the memory array selection signal received by the write enable circuit is valid, it indicates that the memory array is the target memory array, and the write enable circuit outputs a valid array enable signal to the memory array it is connected to, and the memory array can be accessed, for example, data can be written to the target address in the memory array. If the memory array selection signal received by the write enable circuit is invalid, the memory array is not the target memory array, and the write enable circuit outputs an invalid array enable signal to the memory array, and data cannot be written to the memory array.

[0071] The memory provided in this application embodiment can support parallel writing of data to multiple memory arrays during testing. The number of memory arrays for parallel writing can be set according to the maximum number of parallel writes supported by the memory's write current. For example, four memory arrays can be grouped together, and the write enable circuits corresponding to the four memory arrays receive the same test mode signal. This test mode signal can control the four memory arrays to be enabled. After the four memory arrays are enabled, they receive the same memory cell address and data, and write the same data in parallel to the same address in different memory arrays. For example, if the target address is address 1, data can be written in parallel to address 1 in bank0, address 1 in bank2, address 1 in bank3, and address 1 in bank4.

[0072] Alternatively, eight memory arrays can be grouped together, with the write enable circuits corresponding to the eight memory arrays receiving the same test mode signal. Alternatively, any number of memory arrays can be grouped together and data can be written in parallel. The number of memory arrays used for parallel writing in the scheme provided in this application can be set according to the write current carrying capacity, minimizing the data writing time during testing within the capacity of the hardware circuit.

[0073] Furthermore, in the solution provided in this application embodiment, when the test mode signal is invalid, the write enable circuit can output an array enable signal with the same enable state as the storage array select signal based on the received storage array select signal, and operate according to the conventional write mode. Based on the architecture provided in this application embodiment, it is possible to both conventionally select a target storage array to write data according to the storage array select signal, and effectively write data to multiple storage arrays in parallel in response to the test mode signal. The hardware structure provided in this application embodiment can achieve compatibility with both data write modes.

[0074] In this embodiment, an example is given where the memory array address width is 2 bits and the memory includes four memory arrays: bank0, bank1, bank2, and bank3. In practical applications, the memory array address width can be set according to the actual number of memory arrays.

[0075] The memory array selection circuit is used to select the memory array to be accessed based on the received memory array address. The memory array selection circuit outputs a valid memory array selection signal to the memory array to be accessed, and an invalid memory array selection signal to other memory arrays.

[0076] For example, if the memory array to be accessed is determined to be bank0 based on the memory address, the memory array selection signal bank0_sel output by the memory array selection circuit to bank0 is in a valid state, for example, a high level. The memory array selection signals bank1_sel output to bank1, bank2_sel output to bank2, and bank3_sel output to bank3 are in an invalid state, for example, a low level.

[0077] For example, if the memory array to be accessed is determined to be bank1 based on the memory address, the memory array selection signal bank1_sel output by the memory array selection circuit to bank1 is in a valid state, for example, a high level. The memory array selection signal bank0_sel output to bank0, the memory array selection signal bank2_sel output to bank2, and the memory array selection signal bank3_sel output to bank3 are in an invalid state, for example, a low level.

[0078] See Figure 9 The memory array selection circuit includes an address input terminal and a selection signal output terminal. In this embodiment, an example is given with four memory arrays and a 2-bit address width. The 2-bit bank address may contain the following values: 00, 01, 10, and 11, which can be used to select four memory arrays. Accordingly, the address input terminal of the memory array selection circuit includes a first address input terminal and a second address input terminal, and the selection signal output terminal includes a first selection signal output terminal, a second selection signal output terminal, a third selection signal output terminal, and a fourth selection signal output terminal. Specifically, the first selection signal output terminal outputs the memory array selection signal bank0_sel corresponding to bank0, the second selection signal output terminal outputs the memory array selection signal bank1_sel corresponding to bank1, the third selection signal output terminal outputs the memory array selection signal bank2_sel corresponding to bank2, and the fourth selection signal output terminal outputs the memory array selection signal bank3_sel corresponding to bank3.

[0079] The memory array selection circuit also includes NOT gate 311, NOT gate 312, AND gate 321, AND gate 322, AND gate 323, and AND gate 324. The input of NOT gate 311 is connected to the first address port, and the output of NOT gate 311 is connected to the first input of AND gate 321. The input of NOT gate 312 is connected to the second address port, and the output of NOT gate 312 is connected to the second input of AND gate 321. The output of AND gate 321 is connected to the first selection signal output terminal, used to output the memory array selection signal bank0_sel.

[0080] The first input of AND gate 322 is connected to the output of NOT gate 311, the second input of AND gate 322 is connected to the second address port, and the output of AND gate 323 is connected to the second selection signal output, which is used to output the memory array selection signal bank1_sel.

[0081] The first input of AND gate 323 is connected to the first address port, the second input of AND gate 323 is connected to the output of NOT gate 312, and the output of AND gate 323 is connected to the third selection signal output, which is used to output the memory array selection signal bank2_sel.

[0082] The first input of AND gate 324 is connected to the first address segment port, the second input of AND gate 324 is connected to the second address port, and the output of AND gate 324 is connected to the fourth selection signal output, which is used to output the memory array selection signal bank3_sel.

[0083] based on Figure 9 The structure of the memory array selection circuit is shown in Table 1, which illustrates the signal state combinations of the input and output of the memory array selection circuit.

[0084] Table 1

[0085]

[0086]

[0087] Referring to Table 1, the memory array selection circuit can output a corresponding memory array selection signal based on the received address signal. The above example uses a memory array address width of 2 bits. In practical applications, the memory array address width can also be set according to the actual number of memory arrays.

[0088] In the example above, the write enable circuit receives the memory array select signal and the test mode signal, and outputs an array enable signal to the enable terminal of the memory array. In one possible implementation, the write enable circuit also receives a check enable signal, which in some cases can also be called a read / write enable signal, used to control the read / write enable of the memory array. For example, when the write enable circuit receives a valid check enable signal, the memory array connected to the write enable circuit can read and write data. When the write enable circuit receives an invalid check enable signal, the memory array connected to the write enable circuit cannot read or write data.

[0089] In this embodiment, the write enable circuit specifically outputs a valid array enable signal to the memory array when both the enable signal and the test mode signal are valid; and outputs an array enable signal with the same enable state as the memory array selection signal when both are invalid. If the memory array selection signal is valid, a valid array enable signal is output; if the memory array selection signal is invalid, an invalid array enable signal is output. The write enable circuit is also used to output an invalid array enable signal to the memory array when the received enable signal is invalid.

[0090] This application embodiment uses the example of the storage array select signal being active high, the test mode signal being active high, and the check enable signal and array enable signal being active low as an example for illustration.

[0091] Figure 10 A schematic diagram of a write enable circuit provided in an embodiment of this application is shown. The write enable circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is used to receive a memory array select signal (bank_sel), the second input terminal is used to receive a test mode signal (TWM), the third input terminal is used to receive a check enable signal (CEN), and the output terminal is used to output an array enable signal (bank_CEN) to the memory array.

[0092] The write enable circuit also includes multiple logic gates, such as NOR gate 411 and OR gate 412. The first input of NOR gate 411 is connected to the first input of the write enable circuit, the second input of NOR gate 411 is connected to the second input of the write enable circuit, and the output of NOR gate 411 is connected to the first input of OR gate 412. The second input of OR gate 412 is connected to the third input of the write enable circuit, and the output of OR gate 412 is connected to the output of the write enable circuit. The output of the write enable circuit is connected to the enable terminal BEN of the memory array.

[0093] based on Figure 10 The structure of the write enable circuit is shown in Table 2, which illustrates the input and output signal state combinations of the write enable circuit.

[0094] Table 2

[0095]

[0096] As shown in Table 2, when the check enable signal is invalid, regardless of whether the memory array selection signal or the test signal is valid, the write enable circuit outputs an invalid array enable signal to the memory array, and the memory array cannot be read or written. The memory array can only be read and written normally when the check enable signal is valid. If the test mode signal is valid, regardless of whether the memory array selection signal is valid, the write enable circuit outputs a valid array enable signal to the memory array, and the memory array can write data. Furthermore, since the write enable circuits of multiple memory arrays receive the same test mode signal, multiple memory arrays can write data in parallel. If the test mode signal is invalid, when the memory array selection signal is valid, the write enable circuit outputs a valid array enable signal. In this case, the memory array is the selected target bank and data can be read and written. When the memory array selection signal is invalid, the write enable circuit outputs an invalid array enable signal. In this case, the memory array is not the target bank and data cannot be read or written.

[0097] Figure 11 A schematic diagram of another write enable circuit provided in an embodiment of this application is shown. The write enable circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal, transistors M1 to M6, and a resistor R.

[0098] The control terminals of transistors M1 and M2 are connected to the first input terminal. The first terminal of transistor M1 is connected to the first power supply (VDD1), and the first terminal of transistor M2 is grounded (GND). The second terminals of transistors M1 and M2 are connected to the first terminal of transistor M3. The second terminal of transistor M3 and the first terminal of transistor M4 are connected to the first terminal of transistor M5. The control terminals of transistors M3 and M4 are connected to the second input terminal. The second terminal of transistor M4 is grounded (GND). The control terminals of transistors M5 and M6 are connected to the third input terminal. The first terminal of transistor M6 is connected to the second power supply (VDD2), and the second terminals of transistors M5 and M6 are connected to the output terminal. A resistor R is connected between the output terminal and ground (GND).

[0099] Transistors M1, M3, and M5 can be PMOS transistors. Transistors M2, M4, and M6 can be NMOS transistors.

[0100] The above description is merely an exemplary illustration of the write enable circuit provided in the embodiments of this application. The write enable circuit may also be other types or other structures of circuits.

[0101] In this embodiment, the check enable signal is used to control the read and write enable of the memory array. The write enable circuits corresponding to each memory array can receive the same check enable signal. In this way, the global memory array can be controlled by a single check enable signal, simplifying the circuit structure and enabling or disabling each memory array synchronously.

[0102] Alternatively, a set of write enable circuits for a group of memory arrays controlled by the same test mode signal can receive the same check enable signal, which can then control the enabling or disabling of this set of memory arrays.

[0103] The memory provided in the embodiments of this application can operate in test mode and non-test mode.

[0104] In non-test mode, the memory can perform regular read and write logic, that is, output a valid array enable signal to the memory array according to the memory array selection signal, enable the memory array, and then transmit the memory cell address and data to the memory array, and write the data to the memory cell corresponding to the memory cell address.

[0105] In test mode, the memory can synchronously write to multiple memory arrays based on the test mode signal. For example, the memory includes multiple memory arrays, which can be divided into multiple groups. The write enable circuits in each group of memory arrays receive the same test mode signal. When the test mode signal is valid, the enable terminals of this group of memory arrays can all receive a valid array enable signal, allowing the same data to be written in parallel to the memory cells corresponding to the same memory cell address in this group of memory arrays.

[0106] For example, see Figure 12 and Figure 13 Continuing with the example of a memory comprising 24 memory banks, the memory includes banks 0 through 23. Each memory bank has the same memory address range, for example, from address 0 to address n. Correspondingly, each of the 24 memory banks has one of 24 write enable circuits. Figure 12 As shown, these 24 write enable circuits are divided into 4 groups of 6. The write enable circuits corresponding to banks 0 to 5 are connected to TWM0, the write enable circuits corresponding to banks 6 to 11 are connected to TWM1, the write enable circuits corresponding to banks 12 to 17 are connected to TWM3, and the write enable circuits corresponding to banks 18 to 23 are connected to TWM3.

[0107] In non-test mode, only one of the array enable signals bank0_CEN to bank23_CEN is low. When the array enable signal is low, the data of the write data signal will be written to the memory cell of the memory array corresponding to the memory cell address.

[0108] When the memory is running in test mode and parallel write functionality is enabled, bank0_CEN to bank23_CEN will... Figure 12 The diagram shows a grouping process where multiple array enable signals are simultaneously set low. For example, when TMW0 is active and TWM1 to TWM3 are inactive, bank0_CEN to bank5_CEN are low, allowing synchronous data writing to banks0 to banks5. In this case, the data from the write data signal can be simultaneously written to the memory cells corresponding to the addresses in banks0 to banks5, such as address 0 in banks0 to banks5, thereby reducing the data writing time during memory testing.

[0109] The memory provided in this application embodiment can achieve parallel data writing of multiple memory arrays by optimizing its write enable circuit design, thereby reducing the time required for memory testing.

[0110] This application also provides a processor chip, including a processor and the memory provided in the foregoing embodiments, wherein the memory is electrically connected to the processor. The processor chip may be... Figure 1 The SoC chip shown can also be other processor chips, such as central processing unit chips, graphics processing unit chips, etc. For example, the processor chip can be a graphics processing unit chip, which includes a graphics processor and a memory as provided in the foregoing embodiments. Specifically, the memory can be an image random access memory. Based on the solution provided in the embodiments of this application, multi-bank parallel data writing can be implemented in test mode, reducing the time required for testing.

[0111] This application also provides an electronic device, including a circuit board and a processor chip as provided in the foregoing embodiments, wherein the processor chip is electrically connected to the circuit board. This electronic device can be as follows: Figure 1 The electronic devices shown may be, for example, mobile phones, tablets, personal computers, etc., but this application does not limit them.

[0112] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, include: Multiple memory arrays and multiple write enable circuits, wherein each write enable circuit corresponds to one of the multiple memory arrays; The write enable circuit is used to receive the memory array selection signal and the test mode signal, and output the array enable signal to the enable terminal of the memory array. When the test mode signal is valid, the write enable circuit outputs a valid array enable signal to the enable terminal of the memory array. When the test mode signal is invalid and the memory array selection signal is valid, the write enable circuit outputs a valid array enable signal to the enable terminal of the memory array. When the test mode signal is invalid and the memory array selection signal is invalid, the write enable circuit outputs an invalid array enable signal to the enable terminal of the memory array. The storage array is used to write data when the enable pin of the storage array is active; At least two memory arrays have write enable circuits that receive the same test mode signal.

2. The memory according to claim 1, characterized in that, The write enable circuit is also used to receive a check enable signal; The write enable circuit is used to output a valid array enable signal to the enable terminal of the memory array when the check enable signal is valid and the test mode signal is valid. The write enable circuit is also used to output an array enable signal to the enable terminal of the memory array that is in the same enable state as the memory array selection signal when the check enable signal is valid and the test mode signal is invalid.

3. The memory according to claim 2, characterized in that, The write enable circuit is also used to output an invalid array enable signal to the enable terminal of the memory array when the check enable signal is invalid.

4. The memory according to claim 2 or 3, characterized in that, The multiple write enable circuits receive the same check enable signal.

5. The memory according to claim 2 or 3, characterized in that, When the multiple write enable circuits receive the same test mode signal, they also receive the same check enable signal.

6. The memory according to any one of claims 2 to 5, characterized in that, The write enable circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is used to receive the memory array selection signal, the second input terminal is used to receive the test mode signal, the third input terminal is used to receive the check enable signal, and the output terminal is connected to the enable terminal of the corresponding memory array to output the array enable signal. The write enable circuit also includes NOR gates and OR gates; The first input terminal of the NOR gate is connected to the first input terminal of the write enable circuit, the second input terminal of the NOR gate is connected to the second input terminal of the write enable circuit, and the output terminal of the NOR gate is connected to the first input terminal of the OR gate. The second input terminal of the OR gate is connected to the third input terminal of the write enable circuit, and the output terminal of the OR gate is connected to the output terminal of the write enable circuit.

7. The memory according to any one of claims 1 to 6, characterized in that, The memory also includes a memory array selection circuit, which receives an address signal and outputs a memory array selection signal.

8. A processor chip, characterized in that, It includes a processor and a memory as described in any one of claims 1 to 7, wherein the memory is electrically connected to the processor.

9. An electronic device, characterized in that, It includes a circuit board and a processor chip as described in claim 8, wherein the processor chip is electrically connected to the circuit board.

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