Temperature cycle test and test method for an MRAM memory under thermal vacuum conditions

Abstract

The application relates to a temperature cycle test method of MRAM memory under a thermal vacuum condition, which comprises the following steps: obtaining temperature change data of the MRAM memory under a normal service environment; performing a shift read-write function test on the measured MRAM memory, and performing in-situ standby current monitoring and cooperative verification of the shift read-write function test; and establishing a performance degradation model to obtain the life of the MRAM memory reaching a failure threshold under a normal temperature cycle working environment. The application has the beneficial effect that the failure mechanism of the MRAM memory under the double stress of vacuum and temperature can be better revealed, so that the accuracy of the reliability evaluation result is improved.

Description

Technical Field

[0001] This invention relates to the field of memory reliability testing technology, and more specifically, to a temperature cycling test and testing method for MRAM memory under thermal vacuum conditions. Background Technology

[0002] Magnetoresistive random access memory (MRAM) is a type of memory device that combines non-volatility, fast read / write speed, and high durability. Because its memory cells are magnetic tunnel junctions, it has good radiation resistance and has broad application prospects in high-reliability applications such as spacecraft.

[0003] In the spaceflight service environment, MRAM memories are not only affected by the vacuum environment during operation, but also subjected to harsh temperature environments. During the operation of geostationary satellites, the significant difference in solar radiation between the sun-facing and shaded sides causes the satellite and its internal components to be subjected to cyclic temperature stress. Due to the differences in the thermal expansion coefficients of the different materials within the memory, the internal structure is prone to failure phenomena such as cracks and interface degradation under cyclic temperature stress. Furthermore, under long-term powered operation, the memory may also experience performance degradation issues such as threshold voltage drift, leakage current changes, and read / write anomalies, thus affecting the memory's read / write functionality and reliability.

[0004] In existing technologies, temperature cycling tests for semiconductor memories are mostly conducted at room temperature and pressure, which makes it difficult to realistically simulate the environmental stress and degradation process experienced by MRAM memories under thermal vacuum conditions. Existing test methods suffer from problems such as long test cycles and low efficiency, and lack continuous monitoring methods for electrical parameters and read / write function testing methods that can be used for thermal vacuum testing of memories, making it difficult to meet the reliability assessment requirements of MRAM memories under thermal vacuum conditions. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a temperature cycling test and testing method for MRAM memory under thermal vacuum conditions.

[0006] Firstly, a temperature cycling test and testing method for MRAM memory under thermal vacuum conditions is provided, including:

[0007] S1. Obtain temperature change data of MRAM memory under normal service environment, establish equivalent temperature cycle stress profile, set benchmark test profile and multiple temperature cycle accelerated stress levels under the premise of ensuring that the failure mechanism remains unchanged, and apply vacuum environment and temperature cycle stress to the MRAM memory under test by step stress loading method.

[0008] S2. During the thermal vacuum temperature cyclic stress loading process, the in-situ standby current of the MRAM memory under test is continuously monitored, and the shift read and write function test of the MRAM memory under test is performed at the preset test time node to obtain the read and write function parameters, and to perform collaborative verification of in-situ standby current monitoring and shift read and write function test.

[0009] S3. Establish a performance degradation model based on the standby current degradation data obtained from in-situ standby current monitoring. Establish a temperature cycling stress acceleration equation and calculate the acceleration coefficient based on the degradation rate parameters under different temperature cycling accelerated stress levels. Extrapolate the degradation law under accelerated test conditions to normal working conditions based on the acceleration coefficient to obtain the lifespan of the MRAM memory reaching the failure threshold under normal temperature cycling working environment.

[0010] As a preferred embodiment, in S1, the constraint of maintaining the unchanged failure mechanism is achieved through a combination of stress design assurance and experimental criterion verification. In terms of stress design assurance, the highest temperature of each temperature cycle accelerated stress level is lower than the magnetic thermal stability threshold of the MRAM memory cell, the thermal deformation threshold of the packaging material, and the thermal breakdown temperature of the CMOS circuit, and the temperature change range and temperature change rate remain constant. In terms of experimental criterion verification, the mechanism consistency is verified during the test through failure mode consistency criteria, degradation model morphology consistency criteria, and equivalent activation energy consistency criteria.

[0011] As a preferred embodiment, in S2, the in-situ standby current monitoring is implemented in the following manner:

[0012] The MRAM memory under test is installed on the test fixture plate of the test sample and placed inside the thermal vacuum test equipment. The test control unit is located outside the thermal vacuum test equipment. The two are electrically connected through a through-wall electrical connector and a data line.

[0013] The operating voltage is applied to the MRAM memory under test by a DC power supply, and the standby current of the MRAM memory under test is continuously collected by the current detection unit.

[0014] In this test, multiple MRAM memories under test are connected in parallel to the test circuit, and the total standby current of the parallel circuit is monitored during the test. When the preset test time interval is reached, the remaining MRAM memories under test, except for the target MRAM memory under test, are disconnected in sequence to collect the standby current of each individual MRAM memory under test in a time-division manner.

[0015] Preferably, in S2, the in-situ standby current monitoring also includes a temperature compensation step:

[0016] The temperature sensor installed inside the through-wall electrical connector collects real-time temperature information of the hot vacuum side conductor and the normal temperature side conductor; based on the conductor material parameters and the collected temperature information, the equivalent resistance change of the conductor and the corresponding additional voltage drop change are calculated; the current detection results are corrected in real time based on the additional voltage drop change to eliminate the influence of conductor temperature drift on the current parameter test results.

[0017] Preferably, in S2, the shift read / write function test includes the testing and data storage of read current, write current, read rate, write rate and read / write error rate; both the test sample test fixture board and the read / write test board are equipped with detachable test sockets, and the MRAM memory under test can quickly switch between the in-situ test fixture and the read / write test fixture through the detachable test sockets.

[0018] Preferably, in S2, the collaborative verification of in-situ standby current monitoring and shift read / write function testing includes:

[0019] The continuous degradation trend of standby current obtained from in-situ standby current monitoring is used as a characterization of early degradation of MRAM memory. When the standby current shows abnormal growth or fluctuation, the shift read / write function test is triggered to confirm the health status of the memory. The read / write function parameters obtained from the shift read / write function test are used as the basis for judging the functional status of MRAM memory. When the read / write function parameters are abnormal, they are cross-validated with the standby current degradation data.

[0020] Preferably, the through-wall electrical connector includes a housing, a front electrical connection terminal and a rear electrical connection terminal respectively disposed at both ends of the housing, and a metal conductive core, a spring-type contact and an insulating support disposed in the terminal contact connection area; the spring-type contact elastically contacts the metal conductive core and forms a continuous elastic pressure on the metal conductive core to compensate for the change in contact gap caused by the thermal expansion and contraction of the material during the thermal vacuum temperature cycle.

[0021] Preferably, in S3, the performance degradation model uses standby current as the degradation characterization parameter, which is expressed as the sum of the initial standby current and the degradation increment that changes over time. The degradation increment is jointly determined by the degradation rate parameter and the degradation trend parameter. The temperature cycling stress acceleration equation couples the temperature accumulation effect and the temperature cycling fatigue effect, wherein the temperature accumulation effect is characterized by the average temperature during the temperature cycling process, and the temperature cycling fatigue effect is characterized by the temperature change rate.

[0022] Preferably, in S3, the acceleration coefficient is the ratio of the degradation rate parameter under accelerated temperature cyclic stress conditions to the degradation rate parameter under normal use conditions. Based on the acceleration coefficient, the degradation rate parameter under accelerated test conditions is converted into the degradation rate parameter under normal use conditions, thereby obtaining the standby current degradation law under normal use conditions. When the standby current reaches the preset failure threshold, the corresponding lifetime value is calculated.

[0023] In a second aspect, an MRAM memory test system for implementing the method as described in any of the first aspects is provided, comprising:

[0024] The test sample test fixture plate is set inside the thermal vacuum test equipment to support the MRAM memory under test and to cooperate in the in-situ current parameter test;

[0025] The read / write test board is located outside the thermal vacuum test equipment and is used to perform read / write function tests on the MRAM memory under test during the shift test.

[0026] Through-wall electrical connectors are installed on the tank wall of thermal vacuum testing equipment to enable the transmission of electrical signals inside and outside the thermal vacuum tank;

[0027] A DC power supply is used to provide the operating voltage for the MRAM memory under test.

[0028] The current detection unit is used to collect the standby current of the MRAM memory under test.

[0029] The host computer is used to configure test modes, control the test process, read back, display and store test data.

[0030] The beneficial effects of this invention are:

[0031] 1. This invention conducts accelerated life testing by step temperature cycling under thermal vacuum conditions. Compared with existing ambient temperature and pressure testing methods, it more realistically simulates the actual service environment and can better reveal the failure mechanism of MRAM memory under the dual stress of vacuum and temperature, thereby improving the accuracy of reliability assessment results.

[0032] 2. This invention accelerates the performance degradation process of samples by constructing multiple levels of temperature cycling stress profiles and adopting a step stress loading method, while ensuring that the failure mechanism remains unchanged. It can obtain performance degradation data and lifetime data in a shorter time, shorten the test time, reduce the test cost, and improve the test efficiency.

[0033] 3. This invention proposes a testing method combining in-situ standby current monitoring and shift read / write function testing. In-situ standby current monitoring can continuously acquire memory standby current degradation data under thermal vacuum temperature cyclic stress loading conditions, while shift read / write function testing can test the memory's read / write function at preset nodes. The two methods work together to ensure that the experimental data possesses both temporal continuity and functional integrity, overcoming the problems of single in-situ testing being insufficient to fully verify read / write functions and single shift testing being insufficient to continuously capture the degradation process.

[0034] 4. By setting a temperature compensation device on the electrical connector, the present invention can compensate for the resistance change caused by the temperature change of the conductor in real time, reduce the interference of conductor temperature drift on the current parameter test results, and improve the accuracy and stability of electrical parameter test under thermal vacuum temperature cycling conditions.

[0035] 5. This invention uses standby current as a degradation characterization quantity of MRAM memory under thermal vacuum temperature cycling stress, and combines it with shift read / write function tests to confirm the memory status. Since standby current is sensitive to leakage current in peripheral circuits, interface defects, and changes in connection status, it can reflect the degradation trend of the device earlier. Therefore, continuous degradation data can be obtained, and the lifetime extrapolation and reliability assessment under normal service conditions can be achieved by combining the temperature cycling stress acceleration equation.

[0036] 6. The independently developed testing system of this invention is a memory read / write testing platform based on FPGA and virtual instrument collaboration. This system achieves integrated linkage of "test control—power supply regulation—data analysis," improving the degree of test automation and data statistical accuracy, and possesses good scalability and flexibility. Attached Figure Description

[0037] Figure 1 This is a system for accelerated life testing and read / write testing of removable memory.

[0038] Figure 2 This is a schematic diagram of the cross-sectional structure of a temperature drift resistant contact-stable connector.

[0039] Figure 3 This is a block diagram illustrating the principle of temperature compensation.

[0040] Figure 4 This is 5-day temperature telemetry data from the GEO orbit;

[0041] Figure 5 Stress profile of temperature equivalent test (5 cycles);

[0042] Figure 6 This is a step-stress loading method based on temperature cycling;

[0043] Figure 7A schematic diagram and testing fixture for DC parameters of MRAM memory;

[0044] Figure 8 Temperature cycling test procedure;

[0045] Explanation of reference numerals in the attached diagram: 1. Room temperature environment; 2. Ammeter; 3. Hot vacuum chamber; 4. Chamber wall; 5. Power supply; 6. Temperature-compensated through-wall connector; 7. Test sample testing fixture plate; 8. Memory; 9. Test socket; 10. Read / write test board; 11. Housing; 12. Threaded connection section; 13. Sealing ring; 14. Rear end fixing support; 15. Mounting plate; 16. Front end fixing support; 17. Housing; 18. Temperature compensation circuit module; 19. Temperature sensor; 20. Insulating support; 21. Insulating support; 22. Rear end electrical connection terminal; 23. Front end electrical connection terminal. Detailed Implementation

[0046] The present invention will be further described below with reference to embodiments. The description of the embodiments below is only for the purpose of helping to understand the present invention. It should be noted that those skilled in the art can make several modifications to the present invention without departing from the principle of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0047] Example 1:

[0048] To address the challenge of simultaneously achieving continuous environmental stress loading, in-situ monitoring of electrical parameters, and complete read / write function testing in existing thermal vacuum temperature cycling tests of MRAM memories, Embodiment 1 of this application provides a temperature cycling test and testing method for MRAM memories under thermal vacuum conditions. This method utilizes the characteristic that standby current can be continuously and in-situ collected under thermal vacuum conditions and is sensitive to the degradation of peripheral circuitry, using it as a continuous characterization of the degradation process. Simultaneously, shift read / write tests are used to confirm the health status of the memory, allowing for mutual verification between the degradation trend of electrical parameters and changes in read / write function, thereby achieving a coordinated assessment of degradation monitoring, functional determination, and lifetime extrapolation.

[0049] Specifically, the method includes:

[0050] S1. Obtain temperature change data of MRAM memory under normal service environment, establish equivalent temperature cycle stress profile, and on the basis of equivalent temperature cycle stress profile, set the benchmark test profile and multiple temperature cycle accelerated stress levels with the rated operating temperature range and the highest junction temperature of the memory as the constraint boundary, while ensuring that the failure mechanism remains unchanged. Apply vacuum environment and temperature cycle stress to the MRAM memory under test by step stress loading method.

[0051] In S1, the constraint of maintaining the failure mechanism is guaranteed in two ways: First, the upper limit of stress is strictly controlled below the magnetic thermal stability threshold of MRAM memory cells, the thermal deformation threshold of packaging materials, and the thermal breakdown temperature of CMOS circuits, ensuring that acceleration only increases the degradation rate and does not introduce new failure modes such as magnetic moment instability or material melting; Second, during the experiment, the consistency of the mechanism is verified by three criteria: consistency of failure mode, consistency of degradation model morphology, and consistency of equivalent activation energy. Under each stress level, the failure modes are all manifested as leakage current growth in peripheral circuits, fatigue of interconnect interfaces, and degradation of read and write performance. The degradation trajectory all conforms to the power-law degradation characteristics and there is no significant difference in equivalent activation energy, thus confirming that the failure mechanism remains consistent during acceleration.

[0052] Specifically, S1 includes:

[0053] S101. Preparation of Test Samples. A certain type of MRAM memory was selected as the test sample. Before the test, all samples were visually inspected, requiring that the samples be intact and undamaged. Then, all samples were tested according to the predetermined test method, and the key performance index values ​​were measured. The initial values ​​of the samples were compared and analyzed, and the consistency was checked. Samples with large deviations in the initial values ​​were removed, and the samples were numbered and organized according to the test group.

[0054] S102. Determine key performance parameters and failure criteria. For example, based on the failure mechanism of MRAM memory under temperature and electrical stress conditions, select DC parameters and read / write function parameters as key performance indicators. During the test, if any key performance indicator exceeds the corresponding failure threshold, the sample is deemed to have failed, and the corresponding time is recorded as the sample's lifetime. If the sample's DC parameters are normal, but it experiences read / write failure or abnormal read / write function, and the failure is confirmed by fault analysis to be due to the test, this time is also recorded as the sample's lifetime.

[0055] S103. Establish a thermal vacuum temperature cycling stress reference profile. To facilitate testing and subsequent data analysis, a test stress profile with a constant temperature change rate is established. Parameters include the highest temperature, lowest temperature, temperature change range, average temperature change rate, and the arithmetic mean of temperatures over one cycle. Based on the highest and lowest temperatures of the measured temperature change curves, the heating and cooling times, and referring to the test requirements for high and low temperature stability in temperature cycling / temperature change environment testing, and considering the operating temperature range of the tested product, the heating and cooling capabilities of the test equipment, and the time required for subsequent electrical performance testing, the holding times at the highest and lowest temperatures are set to obtain an equivalent temperature cycling stress reference profile. Considering the errors in measured data and uncertainties such as temperature fluctuations, the upper and lower limits of the temperature are adjusted based on the above equivalent test stress profile to obtain the reference test profile. For example, the electrical storage device of a probe on a GEO orbit undergoes periodic temperature cycling stress in a vacuum environment. Based on five days of telemetry data of the surface temperature of a probe on a GEO orbit spacecraft, such as… Figure 4 As shown, the highest temperature measured was approximately 44℃, and the lowest temperature was approximately -4℃. The temperature changes exhibited periodic fluctuations with a period of 24 hours, including a temperature rise time of approximately 16 hours and a temperature drop time of approximately 8 hours. An equivalent experimental profile was obtained as shown below. Figure 5 To further consider uncertainties such as measured data errors and temperature fluctuations in the thermal vacuum equipment, the upper and lower temperature limits were adjusted by 10°C based on the equivalent test stress profile, resulting in the adjusted reference test profile. .

[0056] S104, Design stepped temperature cycling accelerated stress. Based on the aforementioned benchmark test profile, while maintaining a constant temperature range, multiple temperature cycling stress levels are created by increasing the average temperature. For example, the internal storage temperature range of an MRAM memory is -55℃ to 150℃, therefore, a maximum junction temperature not exceeding 150℃ can be used as the upper limit constraint for stress. Preferably, three temperature cycling stress levels are set:

[0057] In the first temperature cycle stress level, the highest temperature is 94℃, the lowest temperature is 26℃, the average temperature change rate is 1.33℃ / min, and the average temperature is 60℃.

[0058] In the second temperature cycle stress level, the highest temperature is 114℃, the lowest temperature is 46℃, the average temperature change rate is 1.33℃ / min, and the average temperature is 80℃.

[0059] In the third temperature cycle stress level, the highest temperature is 134℃, the lowest temperature is 66℃, the average temperature change rate is 1.33℃ / min, and the average temperature is 100℃.

[0060] The above three temperature cycle stress levels adopt a step stress loading method, such as... Figure 6 As shown, the stress levels are increased stepwise from low to high to monitor the performance degradation trend of the samples under different temperature cyclic stress levels.

[0061] Furthermore, to ensure that the failure mechanism of MRAM memory remains consistent across different accelerated stress levels, this experiment establishes the following triple criterion for mechanism consistency verification:

[0062] Failure Mode Consistency Criteria: During the test, failure samples under various stress levels were located and analyzed for failure modes. It was confirmed that the failures were all characterized by abnormally high standby current and increased read / write error rate. The failure sites were concentrated in the leakage of the gate oxide layer of the peripheral CMOS circuit, fatigue cracking of the package interconnect interface, and degradation of the pad contact resistance. The failure modes were completely consistent with those under the reference stress level. No new failure modes such as magnetic tunnel junction magnetic moment thermal disturbance instability or chip material melting and decomposition were observed.

[0063] Consistency criterion for degradation model morphology: Power-law model fitting was performed on the standby current degradation data under various temperature cyclic stress levels to examine the statistical differences in the degradation trend parameter b. If there are no significant differences in the shape parameter b under different stress levels, it indicates that the evolution law of the degradation curve is consistent and the failure physical process has not undergone essential changes.

[0064] Equivalent activation energy consistency criterion: Based on the degradation rate parameters and average temperature at each stress level, the equivalent activation energy Ea is calculated by fitting the acceleration equation. If the equivalent activation energies calculated for different stress ranges are on the same order of magnitude and the deviation is within the allowable range, it indicates that the thermal activation mechanism of the degradation process remains stable and the failure mechanism has not undergone a transition.

[0065] The three accelerated stress levels set in this invention all have a maximum temperature lower than the maximum storage junction temperature of the MRAM memory (150°C), and the temperature change range is consistent with the reference profile. Only the average temperature is increased to accelerate the thermal activation degradation process; at the same time, the temperature change rate is kept constant to avoid introducing additional thermal shock failure mechanisms due to excessively high temperature change rates, thus ensuring the consistency of the failure mechanism from the stress design level.

[0066] S2. During the thermal vacuum temperature cyclic stress loading process, the in-situ standby current of the MRAM memory under test is continuously monitored, and the shift read / write function test of the MRAM memory under test is performed at the preset test time node to obtain the read / write function parameters, and the in-situ standby current monitoring and shift read / write function test are jointly verified.

[0067] like Figure 1 As shown, during the test, the memory under test is subjected to a voltage through a DC power supply, and the real-time standby current of the memory is tested in situ. Real-time current compensation is performed considering the influence of temperature on the current parameters. During the accelerated life test of step temperature cycling, the test sample is periodically removed and then placed on the read / write test board for shift testing of read / write function parameters.

[0068] In the displacement testing method, the FPGA board cannot be placed inside the heated vacuum chamber; it must be placed outside. When the memory under test is mounted on the FPGA test board, it facilitates testing. Therefore, the environmental stress test and the test are conducted separately, i.e., the displacement read / write function test is performed on the test sample. The in-situ testing method separates the FPGA board and the test board. The test board is placed inside the heated vacuum chamber, while the FPGA board is outside. The two are connected via a data cable, enabling in-situ standby current testing of the test sample.

[0069] Specifically, in S2, the in-situ standby current monitoring is implemented in the following way:

[0070] The MRAM memory under test is installed on the test fixture plate of the test sample and placed inside the thermal vacuum test equipment. The test control unit is located outside the thermal vacuum test equipment. The two are electrically connected through a through-wall electrical connector and a data line.

[0071] The operating voltage is applied to the MRAM memory under test by a DC power supply, and the standby current of the MRAM memory under test is continuously collected by the current detection unit.

[0072] In this test, multiple MRAM memories under test are connected in parallel to the test circuit, and the total standby current of the parallel circuit is monitored during the test. Furthermore, when a preset test time interval is reached, the remaining MRAM memories under test, except for the target MRAM memory, are sequentially disconnected, allowing each MRAM memory under test to be individually connected to the test circuit, and the standby current of each individual MRAM memory is measured. This switching process can be achieved without setting a dedicated single-channel selector switch or removing the memory under test from the test fixture, avoiding the additional impact of repeated plugging and unplugging on the sample and its contact state.

[0073] In S2, the in-situ standby current monitoring also includes a temperature compensation step:

[0074] A temperature sensor installed inside the through-wall electrical connector collects real-time temperature information of the hot vacuum side conductor and the room temperature side conductor. Based on the conductor material parameters and the collected temperature information, the equivalent resistance change of the conductor and the corresponding additional voltage drop change are calculated. The current detection results are corrected in real time based on the additional voltage drop change to eliminate the influence of conductor temperature drift on the current parameter test results. The structure of the through-wall electrical connector is as follows: Figure 2 As shown, this is used to compensate for the resistance changes and current deviations caused by temperature variations in the wires connecting the memory under test and the test system. This reduces the impact of temperature drift on the current parameter test results. The compensation principle of the temperature compensation circuit module is as follows: Figure 3 As shown.

[0075] Specifically, it is used to compensate for the resistance changes and current deviations caused by temperature variations in the wires connecting the memory under test and the test system, thereby reducing the impact of temperature drift on the current parameter test results. The compensation principle of the temperature compensation circuit module is as follows: Figure 3 As shown.

[0076] In addition, in S2, the shift read / write function test includes the testing and data storage of read current, write current, read rate, write rate and read / write error rate; both the test sample test fixture board and the read / write test board are equipped with detachable test sockets, and the MRAM memory under test can quickly switch between the in-situ test fixture and the read / write test fixture through the detachable test sockets.

[0077] It should be noted that during thermal vacuum temperature cycling tests, if only the shift read / write test method is used, the test needs to be interrupted and the sample removed at each test node, making it difficult to obtain degradation data on the continuous changes of electrical parameters over time under temperature cycling. If only the in-situ electrical parameter test method is used, although the changes in DC parameters such as standby current can be obtained in real time, it is difficult to completely determine whether the memory read / write function has malfunctioned. Therefore, this invention combines in-situ standby current testing with shift read / write function testing. In-situ standby current testing is used to continuously detect the early degradation trend of MRAM memory under thermal vacuum temperature cycling stress, while shift read / write function testing is used to confirm read / write correctness, read / write rate, and read / write error rate at preset time nodes. By combining the two, the problems of discrete degradation information and omission of early anomalies caused by simple shift testing can be avoided, as well as the problem that simple in-situ current testing cannot confirm functional failure.

[0078] Specifically, in S2, the collaborative verification of in-situ standby current monitoring and shift read / write function testing includes:

[0079] The continuous degradation trend of standby current obtained from in-situ standby current monitoring is used as a characterization of early degradation of MRAM memory. When the standby current shows abnormal growth or fluctuation, the shift read / write function test is triggered to confirm the health status of the memory. The read / write function parameters obtained from the shift read / write function test are used as the basis for judging the functional status of MRAM memory. When the read / write function parameters are abnormal, they are cross-validated with the standby current degradation data.

[0080] S3. Establish a performance degradation model based on the standby current degradation data obtained from in-situ standby current monitoring. Establish a temperature cycling stress acceleration equation and calculate the acceleration coefficient based on the degradation rate parameters under different temperature cycling accelerated stress levels. Extrapolate the degradation law under accelerated test conditions to normal working conditions based on the acceleration coefficient to obtain the lifespan of the MRAM memory reaching the failure threshold under normal temperature cycling working environment.

[0081] In S3, the performance degradation model uses standby current as the degradation characterization parameter, which is expressed as the sum of the initial standby current and the degradation increment that changes over time. The degradation increment is jointly determined by the degradation rate parameter and the degradation trend parameter. The temperature cycling stress acceleration equation couples the temperature accumulation effect and the temperature cycling fatigue effect. The temperature accumulation effect is characterized by the average temperature during the temperature cycling process, and the temperature cycling fatigue effect is characterized by the temperature change rate.

[0082] In S3, the acceleration coefficient is the ratio of the degradation rate parameter under accelerated temperature cyclic stress conditions to the degradation rate parameter under normal use conditions. Based on the acceleration coefficient, the degradation rate parameter under accelerated test conditions is converted into the degradation rate parameter under normal use conditions, thereby obtaining the standby current degradation law under normal use conditions. When the standby current reaches the preset failure threshold, the corresponding lifetime value is calculated.

[0083] Example 2:

[0084] Based on Example 1, Example 2 of this application provides a more specific method for temperature cycling tests and assessments of MRAM memory under thermal vacuum conditions, including:

[0085] S1. Obtain temperature change data of MRAM memory under normal service environment, establish equivalent temperature cycle stress profile, set benchmark test profile and multiple temperature cycle accelerated stress levels, and apply vacuum environment and temperature cycle stress to the MRAM memory under test by step stress loading method.

[0086] S2. During the thermal vacuum temperature cyclic stress loading process, the in-situ standby current of the MRAM memory under test is continuously monitored, and the shift read / write function test of the MRAM memory under test is performed at the preset test time node to obtain the read / write function parameters, and the in-situ standby current monitoring and shift read / write function test are jointly verified.

[0087] Specifically, S2 includes:

[0088] S201. Perform a thermal vacuum temperature cycling test. Mount the sample to be tested on a test fixture and place it inside a thermal vacuum testing equipment for temperature cycling testing. During the test, a working voltage is continuously applied to the sample. Since the memory is an active device, its working voltage variation range is limited. Therefore, the voltage is not used as an accelerating stress, but as a working bias condition.

[0089] S202. Perform in-situ and shift tests. During the test, the DC parameters of the sample are tested in-situ online, and the read / write function parameters are tested using a shift test. During the in-situ test, the MRAM memory... Figure 7The wiring method involves connecting pins #13, #41, and #8 to 3.3V, and pins #14 and #42 to the negative terminal. Multiple MRAMs under test can be connected in parallel, and the total current of the circuit is continuously monitored using a high-precision ammeter. To further obtain the degradation state of individual MRAMs, after reaching a preset test time interval, individual current tests are performed on each MRAM. Specifically, the standby current of each MRAM is measured by connecting its power supply circuit one by one and comparing it with a preset failure threshold. When the standby current of an MRAM reaches or exceeds the corresponding failure threshold, the MRAM is determined to have experienced DC parameter failure, and the corresponding test time or number of temperature cycles is recorded as the failure time of the sample. If the total current monitoring result shows a sudden increase or abnormal fluctuation, the standby current retest of the individual sample is initiated in advance to locate the abnormal sample and confirm its failure state. During the shift test, after the predetermined test interval is reached, the test sample is taken out of the thermal vacuum equipment and installed on the read / write test board to obtain read / write function parameters such as read current, write current, read rate, write rate and read / write error rate.

[0090] This embodiment also provides a specific implementation method for shift testing of MRAM memory, as follows:

[0091] Since the test control board should not be placed directly inside the thermal vacuum test equipment during environmental stress testing, the environmental stress test and read / write function test are conducted separately. During the test, the MRAM memory under test is first installed on the test sample test fixture board and operates under thermal vacuum temperature cyclic stress. A working voltage is applied to the memory under test through a DC power supply, and the current changes in the circuit are recorded in real time to obtain the variation law of the device's DC parameters under environmental stress.

[0092] Once the preset test time interval is reached, the sample under test is removed from the thermal vacuum testing equipment and transferred to the read / write test board for read / write function testing. The read / write function test includes testing and data storage of read current, write current, read rate, write rate, read / write time, and read / write error rate. Preferably, to facilitate rapid switching between the test fixture board and the read / write test board, both the test fixture board and the read / write test board are equipped with detachable test sockets. During the test, only the memory under test needs to be moved to complete the sample transfer. In this way, the read / write function parameters of the MRAM memory at different time points can be tested without placing the complex test control circuitry in a thermal vacuum environment.

[0093] Furthermore, in the temperature cycling test method proposed in this invention, the displacement test is used in conjunction with the in-situ online test. That is, the static current is monitored in-situ during the thermal vacuum test, and the sample is removed according to the preset test interval to perform the read and write function test, thereby taking into account both the continuity of environmental stress loading and the integrity of the read and write performance test.

[0094] Furthermore, this embodiment also provides a specific implementation method for in-situ online testing of MRAM memory, as follows:

[0095] The MRAM memory under test is mounted on the test fixture plate of the test sample and placed inside the thermal vacuum testing equipment along with the test fixture plate. The test control unit is located outside the thermal vacuum testing equipment and is electrically connected to the test fixture plate of the test sample via a data cable. A through-wall electrical connector is provided on the wall of the thermal vacuum testing equipment, through which the data cable transmits electrical signals between the inside and outside of the thermal vacuum chamber. The through-wall electrical connector includes a housing, front and rear electrical connection terminals respectively located at both ends of the housing, a metal conductive core, a spring-loaded contact element, and an insulating support element located within the terminal contact area. The spring-loaded contact element makes elastic contact with the metal conductive core and forms a continuous elastic pressure on the metal conductive core to compensate for changes in contact gap caused by thermal expansion and contraction of materials during thermal vacuum temperature cycling, reducing the impact of terminal contact resistance fluctuations on the test results. The through-wall electrical connector is also equipped with a temperature sensor and a temperature compensation circuit module. The temperature sensor is used to collect temperature information of the electrical connector and its connecting wires, and the temperature compensation circuit module is used to compensate for temperature drift in the test circuit based on the collected temperature information, thereby realizing in-situ online monitoring of DC electrical parameters of the MRAM memory under test in a thermal vacuum temperature cycling environment.

[0096] Specifically, during thermal vacuum temperature cycling, the wire segments connecting the memory under test (MDT) to the test system are in different temperature fields compared to those in the thermal vacuum chamber. This causes the resistance values ​​of each wire segment to drift with temperature changes, creating additional voltage drops in the power supply and current detection circuits, thus deviating from the current test results of the MDT. Simultaneously, the contact pressure changes between the front and rear electrical connection terminals due to thermal expansion and contraction of materials during temperature cycling, leading to fluctuations in contact resistance. To mitigate these effects, a temperature compensation device and a spring-loaded contact stabilization structure are incorporated into the electrical connector. The temperature compensation device includes a temperature acquisition unit, a compensation calculation unit, and a compensation output unit. The temperature acquisition unit acquires real-time temperature information from both the thermal vacuum side and the room temperature side wires. The compensation calculation unit calculates the equivalent resistance change and the corresponding additional voltage drop change of the wires based on the wire material parameters, wire length, wire cross-sectional area, and the acquired temperature information. The compensation output unit corrects the current detection results in real time based on the change in additional voltage drop, or dynamically compensates the power supply output; the spring-loaded contact stabilization structure forms an elastic contact with the metal conductive core through contact elements to compensate for changes in contact gap caused by temperature variations. Through these methods, the impact of wire temperature drift and terminal contact resistance fluctuations on the test results of the current parameters of the memory under test can be reduced simultaneously, improving the accuracy of parameter measurement.

[0097] For example, using calibrated temperature resistance value of the lower conductor As a reference, the conductor at the current temperature The resistance value below It can be calculated using the following formula:

[0098] ;

[0099] in, is the temperature coefficient of resistance of the conductor material.

[0100] At the test current is At that time, the additional voltage drop caused by the temperature drift of the conductor It can be represented as:

[0101] ;

[0102] The actual voltage of the tested memory for:

[0103] ;

[0104] in, Set the output voltage for the DC power supply. This represents the additional voltage drop caused by the temperature drift of the conductor.

[0105] Since there is a correlation between the operating current parameters of the tested memory and its actual terminal voltage, the measured current can be corrected based on a pre-calibrated current-voltage-temperature compensation model. Preferably, the actual current parameters after conductor temperature compensation... It can be represented as:

[0106] ;

[0107] in, To eliminate the influence of conductor temperature on current parameters, The original current parameters measured by the ammeter, The sensitivity coefficient for changes in current-to-terminal voltage is obtained through pre-calibration.

[0108] Furthermore, The sensitivity coefficient can be obtained through pre-test calibration. Specifically, at the reference temperature... Under these conditions, the MRAM memory under test is brought into a stable operating state, and multiple voltage points are selected near its rated operating voltage. , , ..., The aforementioned voltages were sequentially applied to the MRAM memory under test, and the corresponding standby current was measured. , , ..., This yields the data between the standby current and the terminal voltage.

[0109] Near the rated operating voltage, the local relationship between standby current and terminal voltage can be approximated as follows:

[0110]

[0111] in, The slope of the linear fit. The intercept is used for the linear fit. The slope of the linear fit is taken as the sensitivity coefficient of the standby current to the change in terminal voltage. That is:

[0112]

[0113] Furthermore, the compensation relationship can also be expressed as:

[0114] ;

[0115] in This is a compensation function established based on conductor parameters, ambient temperature, and test system calibration results. Using this method, parasitic resistance drift, additional voltage drop error, and resulting current parameter deviations caused by conductor temperature changes can be corrected in real time.

[0116] S3. Establish a performance degradation model based on the standby current degradation data obtained from in-situ standby current monitoring. Establish a temperature cycling stress acceleration equation and calculate the acceleration coefficient based on the degradation rate parameters under different temperature cycling accelerated stress levels. Extrapolate the degradation law under accelerated test conditions to normal working conditions based on the acceleration coefficient to obtain the lifespan of the MRAM memory reaching the failure threshold under normal temperature cycling working environment.

[0117] Specifically, based on key performance data obtained from in-situ online testing and shift testing, standby current is selected as a performance degradation characterization parameter for MRAM memory under temperature cycling stress conditions. This is because MRAM memory does not perform frequent read / write operations in standby mode, and ideally, the standby current should remain at a relatively stable level. When temperature cycling stress and long-term bias cause an increase in leakage channels in the peripheral CMOS circuit, accumulation of interface defects, degradation of the insulating dielectric performance, or changes in the package interconnect contact state, this may manifest as a slow rise or abnormal fluctuation in standby current. Therefore, standby current can reflect the degradation trend of the device's internal electrical performance earlier and is suitable as a degradation-sensitive parameter for continuous in-situ monitoring. Compared to functional parameters such as read / write error rate, standby current usually exhibits a more obvious gradual change characteristic before failure, making it easier to establish degradation models and accelerated lifetime extrapolation models.

[0118] For example, suppose the standby current of the memory under temperature cycling stress is... The initial standby current is Therefore, the following performance degradation model is established:

[0119]

[0120] In the formula, t is the time of temperature cycling stress or the equivalent number of cycles; a is the degradation rate parameter, used to characterize how fast the performance of the memory device degrades; b is the degradation trend parameter, used to characterize the curve shape of the standby current as a function of time or number of cycles. When a is larger, it indicates that the memory device degrades faster under the same temperature cycling conditions; when b is different, it indicates that the degradation process can exhibit different trends such as approximately linear, accelerated growth, or slowed growth.

[0121] Furthermore, the impact of temperature cycling stress on electronic memory mainly includes two types of damage mechanisms: On the one hand, the long-term cumulative effect of temperature enhances carrier transport and interface defect evolution within the device, leading to a gradual increase in the gate oxide layer or interface traps. On the other hand, periodic temperature changes generate alternating thermal stress at material interfaces, packaging structures, or interconnect regions within the device, inducing microcracks, interface fatigue, or connection degradation. Based on the above failure mechanisms, this invention couples the temperature accumulation effect and the temperature cycling fatigue effect to establish an acceleration equation between the degradation rate parameter 'a' and the temperature cycling stress:

[0122]

[0123] In the formula, A is a constant related to the device structure, materials, and process; denoted as , where is the rate of temperature change; m is the rate of temperature change exponent, used to characterize the influence of temperature cycling fatigue on the degradation rate; T is the average absolute temperature during temperature cycling, in K; and B is a temperature-sensitive parameter, which can be expressed as the ratio of activation energy to Boltzmann constant, i.e.:

[0124]

[0125] in, For equivalent activation energy, is the Boltzmann constant. In the above acceleration equation, Used to describe the fatigue acceleration effect caused by the rate of temperature change during temperature cycling. Used to describe the accelerating effect of thermal activation energy caused by the cumulative effect of temperature.

[0126] After obtaining standby current degradation data under different temperature cyclic stress conditions, the standby current data at each stress level were fitted to obtain the corresponding degradation rate parameters. Subsequently, based on the average temperature under different stress levels... and rate of temperature change The parameters of the above acceleration equations are identified, yielding model parameters A, m, and B. For accelerated stress conditions and normal operating conditions, the temperature change rate and mean absolute temperature are assumed to be... and Then, the acceleration factor AF under temperature cyclic stress conditions can be expressed as the ratio of the degradation rate under accelerated stress to the degradation rate under normal use conditions:

[0127]

[0128] Substituting the equation for accelerating the degradation rate, we get:

[0129]

[0130] In the formula, To accelerate the degradation rate parameters under temperature cyclic stress conditions; The degradation rate parameter is given under normal operating conditions. To accelerate the rate of temperature change during the experiment; The rate of temperature change under normal operating conditions; To accelerate the mean absolute temperature during the experiment; The average absolute temperature under normal operating conditions;

[0131] Therefore, based on the degradation data obtained under accelerated testing conditions, the degradation law of the memory under normal temperature cycling conditions can be extrapolated. Specifically, when the degradation model under accelerated testing conditions is known:

[0132]

[0133] The degradation rate under normal use conditions can be obtained by the following formula:

[0134]

[0135] Thus, the standby current degradation model under normal operating conditions is obtained:

[0136]

[0137] Furthermore, when the preset standby current failure threshold is The lifespan of an electrical storage device (ESD) under normal operating conditions when it reaches its failure threshold can be calculated using the following formula:

[0138]

[0139] Through the aforementioned degradation model, acceleration equation, and acceleration coefficient, this invention can establish a quantitative mapping relationship between temperature cycling accelerated test data and the reliability degradation process under normal use conditions, thereby enabling rapid assessment of the lifespan and reliability of electrical storage devices under temperature cycling conditions.

[0140] Furthermore, when a fault occurs during the test, a fault mode and fault mechanism analysis is performed to determine the fault location and cause. If the fault is confirmed to be non-responsible, the test time is restarted from the previous detection point after the fault is repaired. If the fault is confirmed to be responsible, the test is interrupted and subsequent processing is carried out. The time spent troubleshooting is not included in the total effective test time. After the test resumes, improvement measures are taken for the exposed problems, and the test continues only after verification that the problems have been resolved. In addition, the temperature cycling test flowchart is as follows: Figure 8 As shown.

[0141] It should be noted that the parts in this embodiment that are the same as or similar to those in Embodiment 1 can be referred to each other, and will not be repeated in this application.

[0142] Example 3:

[0143] Based on Embodiment 2, Embodiment 3 of this application provides an MRAM testing system for implementing the above-described thermal vacuum temperature cycling test and testing method. The testing system includes a DUT, a test sample testing fixture, a read / write test board, a host computer, a DC regulated power supply, and high-precision ammeters and voltmeters. The test sample testing fixture is used to carry the MRAM memory under test and to perform in-situ current parameter testing in conjunction with the thermal vacuum test.

[0144] The read / write test board is used to perform read / write tests on the MRAM memory under test during the shift test; the host computer is used to configure the test mode, start and stop the test, read back, display and store the test data.

[0145] A DC regulated power supply is used to provide the operating voltage for the memory under test; a high-precision ammeter and voltmeter are used to collect the DC parameters of the memory under test.

[0146] The read / write test board generates clock signals, configures and controls the read / write operations of the memory, monitors and records the memory output data, and statistically analyzes data flipping information. The host computer communicates with the read / write test board via a serial port to configure test modes, control the test process, start and stop the test, and read back, display, and store test data. Preferably, the DC power supply can also be controlled by the host computer to achieve integrated management of test power supply and data acquisition.

[0147] Furthermore, both the test sample testing fixture and the read / write test board are equipped with detachable test seats, so that multiple samples can be quickly switched between the in-situ test fixture and the read / write test fixture by simply moving the MRAM memory under test during the test, thereby improving the efficiency of sample rotation testing.

[0148] The test system includes a self-developed test system for reading and writing function parameters, a high-precision ammeter and voltmeter for DC parameters, and a DC regulated power supply. This test system enables hierarchical testing, automatic data acquisition, and unified management of MRAM memory DC parameters and read / write function parameters.

[0149] It should be noted that the system provided in this embodiment is the same as the system corresponding to the method provided in embodiment 2. Therefore, the parts that are the same or similar to those in embodiment 2 in this embodiment can be referred to each other, and will not be described again in this application.

Claims

1. A temperature cycling test and testing method for MRAM memory under thermal vacuum conditions, characterized in that, include: S1. Obtain temperature change data of MRAM memory under normal service environment, establish equivalent temperature cycle stress profile, set benchmark test profile and multiple temperature cycle accelerated stress levels under the premise of ensuring that the failure mechanism remains unchanged, and apply vacuum environment and temperature cycle stress to the MRAM memory under test by step stress loading method. S2. During the thermal vacuum temperature cyclic stress loading process, the in-situ standby current of the MRAM memory under test is continuously monitored, and the shift read and write function test of the MRAM memory under test is performed at the preset test time node to obtain the read and write function parameters, and to perform collaborative verification of in-situ standby current monitoring and shift read and write function test. S3. Establish a performance degradation model based on the standby current degradation data obtained from in-situ standby current monitoring. Establish a temperature cycling stress acceleration equation and calculate the acceleration coefficient based on the degradation rate parameters under different temperature cycling accelerated stress levels. Extrapolate the degradation law under accelerated test conditions to normal working conditions based on the acceleration coefficient to obtain the lifespan of the MRAM memory reaching the failure threshold under normal temperature cycling working environment.

2. The temperature cycling test and testing method for MRAM memory under thermal vacuum conditions according to claim 1, characterized in that, In S1, the constraint of maintaining the invariant failure mechanism is achieved through a combination of stress design assurance and experimental criterion verification. In terms of stress design assurance, the highest temperature of each temperature cycle accelerated stress level is lower than the magnetic thermal stability threshold of the MRAM memory cell, the thermal deformation threshold of the packaging material, and the thermal breakdown temperature of the CMOS circuit, and the temperature change range and temperature change rate remain constant. In terms of experimental criterion verification, the mechanism consistency is verified during the test through failure mode consistency criteria, degradation model morphology consistency criteria, and equivalent activation energy consistency criteria.

3. The temperature cycling test and testing method for MRAM memory under thermal vacuum conditions according to claim 2, characterized in that, In S2, in-situ standby current monitoring is implemented in the following way: The MRAM memory under test is installed on the test fixture plate of the test sample and placed inside the thermal vacuum test equipment. The test control unit is located outside the thermal vacuum test equipment. The two are electrically connected through a through-wall electrical connector and a data line. The operating voltage is applied to the MRAM memory under test by a DC power supply, and the standby current of the MRAM memory under test is continuously collected by the current detection unit. In this test, multiple MRAM memories under test are connected in parallel to the test circuit, and the total standby current of the parallel circuit is monitored during the test. When the preset test time interval is reached, the remaining MRAM memories under test, except for the target MRAM memory under test, are disconnected in sequence to collect the standby current of each individual MRAM memory under test in a time-division manner.

4. The temperature cycling test and testing method for MRAM memory under thermal vacuum conditions according to claim 3, characterized in that, In S2, the in-situ standby current monitoring also includes a temperature compensation step: The real-time temperature information of the hot vacuum side wire and the normal temperature side wire is collected by a temperature sensor installed in the through-wall electrical connector; based on the wire material parameters and the collected temperature information, the equivalent resistance change of the wire and the corresponding additional voltage drop change are calculated. The current detection results are corrected in real time based on the change in additional voltage drop to eliminate the influence of conductor temperature drift on the current parameter test results.

5. The temperature cycling test and testing method for MRAM memory under thermal vacuum conditions according to claim 4, characterized in that, In S2, the shift read / write function test includes the testing and data storage of read current, write current, read rate, write rate and read / write error rate; both the test sample test fixture board and the read / write test board are equipped with detachable test sockets, and the MRAM memory under test can quickly switch between the in-situ test fixture and the read / write test fixture through the detachable test sockets.

6. The temperature cycling test and testing method for MRAM memory under thermal vacuum conditions according to claim 5, characterized in that, In S2, the collaborative verification of in-situ standby current monitoring and shift read / write function testing includes: The continuous degradation trend of standby current obtained from in-situ standby current monitoring is used as a characterization of early degradation of MRAM memory. When the standby current shows abnormal growth or fluctuation, the shift read / write function test is triggered to confirm the health status of the memory. The read / write function parameters obtained from the shift read / write function test are used as the basis for judging the functional status of MRAM memory. When the read / write function parameters are abnormal, they are cross-validated with the standby current degradation data.

7. The temperature cycling test and testing method for MRAM memory under thermal vacuum conditions according to claim 6, characterized in that, The through-wall electrical connector includes a housing, a front electrical connection terminal and a rear electrical connection terminal respectively disposed at both ends of the housing, and a metal conductive core, a spring-loaded contact and an insulating support disposed in the terminal contact connection area; the spring-loaded contact elastically contacts the metal conductive core and forms a continuous elastic pressure on the metal conductive core to compensate for the change in contact gap caused by the thermal expansion and contraction of the material during the thermal vacuum temperature cycle.

8. The temperature cycling test and testing method for MRAM memory under thermal vacuum conditions according to claim 7, characterized in that, In S3, the performance degradation model uses standby current as the degradation characterization parameter, which is expressed as the sum of the initial standby current and the degradation increment that changes over time. The degradation increment is jointly determined by the degradation rate parameter and the degradation trend parameter. The temperature cycling stress acceleration equation couples the temperature accumulation effect and the temperature cycling fatigue effect. The temperature accumulation effect is characterized by the average temperature during the temperature cycling process, and the temperature cycling fatigue effect is characterized by the temperature change rate.

9. The temperature cycling test and testing method for MRAM memory under thermal vacuum conditions according to claim 8, characterized in that, In S3, the acceleration coefficient is the ratio of the degradation rate parameter under accelerated temperature cyclic stress conditions to the degradation rate parameter under normal use conditions. Based on the acceleration coefficient, the degradation rate parameter under accelerated test conditions is converted into the degradation rate parameter under normal use conditions, thereby obtaining the standby current degradation law under normal use conditions. When the standby current reaches the preset failure threshold, the corresponding lifetime value is calculated.

10. An MRAM memory testing system for implementing the method according to any one of claims 1 to 9, characterized in that, include: The test sample test fixture plate is set inside the thermal vacuum test equipment to support the MRAM memory under test and to cooperate in the in-situ current parameter test; The read / write test board is located outside the thermal vacuum test equipment and is used to perform read / write function tests on the MRAM memory under test during the shift test. Through-wall electrical connectors are installed on the tank wall of thermal vacuum testing equipment to enable the transmission of electrical signals inside and outside the thermal vacuum tank; A DC power supply is used to provide the operating voltage for the MRAM memory under test. The current detection unit is used to collect the standby current of the MRAM memory under test. The host computer is used to configure test modes, control the test process, read back, display and store test data.

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