A high-speed high-power on-chip light source and a preparation method thereof

Abstract

The application relates to the technical field of semiconductor devices, in particular to a high-speed high-power on-chip light source and a preparation method thereof. The high-speed high-power on-chip light source comprises a laser chip and an SOI substrate; the laser chip comprises a laser region, and the laser region comprises, from bottom to top, a substrate, an n-type cladding layer, an active region, an ultrathin InP layer, a p-type heavily doped graphene layer and a light confinement layer; the SOI substrate comprises, from bottom to top, an intrinsic graphene layer and a passivation layer, and the substrate is bonded to the passivation layer; wherein the p-type heavily doped graphene layer provides holes, the high mobility of the graphene material is utilized to improve the hole migration rate, and the holes are combined with electrons provided by the n-type cladding layer to emit light in the active region; meanwhile, the high thermal conductivity of the graphene material is utilized to quickly conduct the heat generated by the combined light emission out through the intrinsic graphene layer. The application can improve the laser light output power and the modulation bandwidth by improving the hole injection efficiency and the substrate heat dissipation efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a high-speed, high-power on-chip light source and its fabrication method. Background Technology

[0002] With the rapid development of artificial intelligence, big data, and intelligent computing centers, information systems are placing unprecedented demands on high-speed, high-capacity, and low-power on-chip optical interconnects. Silicon-based optoelectronic integration, with its advantages such as compatibility with Complementary Metal Oxide Semiconductor (CMOS) processes and its ability to be mass-produced, is considered a core supporting technology for realizing on-chip optical interconnects. However, silicon is an indirect bandgap material with extremely low luminous efficiency, making the development of high-performance silicon-based on-chip light sources a highly challenging problem.

[0003] Due to the flexible gain characteristics of III-V compound semiconductor materials, most mainstream silicon-based on-chip light sources are currently based on silicon-III / V heterogeneous integration. However, silicon-III / V heterogeneous integrated on-chip light sources still face performance bottlenecks such as low output power and low modulation bandwidth.

[0004] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0005] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention proposes a high-speed, high-power on-chip light source and its fabrication method, which can improve the output power and modulation bandwidth of the laser by improving the hole injection efficiency and the substrate heat dissipation efficiency.

[0006] The embodiments of the present invention adopt the following technical solutions: In a first aspect, the present invention provides a high-speed, high-power on-chip light source, comprising a laser chip and an SOI substrate; The laser chip includes a laser region, which includes a substrate, an n-type cladding layer, an active region, an ultrathin InP layer, and an optical confinement layer stacked sequentially from bottom to top. A p-type heavily doped graphene layer is inserted between the ultrathin InP layer and the optical confinement layer. The SOI substrate comprises an intrinsic graphene layer and a passivation layer stacked sequentially from bottom to top, with the substrate bonded to the passivation layer. Holes provided by the p-type heavily doped graphene layer recombine with electrons provided by the n-type cladding layer in the active region to emit light. The high mobility of the graphene material in the p-type heavily doped graphene layer enhances hole injection efficiency, thereby increasing the effective radiative recombination of holes and electrons in the active region. Simultaneously, the high thermal conductivity of the graphene material in the intrinsic graphene layer rapidly dissipates the heat generated by recombination through the intrinsic graphene layer, improving the substrate's heat dissipation efficiency.

[0007] Preferably, the active region is a multi-quantum well structure, which includes multiple alternating layers of wells and barrier layers.

[0008] Preferably, both the well layer and the barrier layer are made of In material. 1-x Ga x As y P 1-y .

[0009] Preferably, the on-chip light source further includes an oxide layer disposed on the substrate and surrounding the n-type cladding, the active region, the ultrathin InP layer, the p-type heavily doped graphene layer, and the light confinement layer.

[0010] Preferably, the on-chip light source further includes a P-side electrode disposed on the ultrathin InP layer and an N-side electrode disposed on the oxide layer; wherein the P-side electrode and the N-side electrode are used to inject current into the active region.

[0011] Preferably, the laser chip further includes a passive feedback region, which is disposed together with the laser region on the substrate, wherein the passive cavity thickness of the passive feedback region is the same as the active cavity thickness of the laser region.

[0012] Secondly, the present invention provides a method for fabricating a high-speed, high-power on-chip light source, used to fabricate the high-speed, high-power on-chip light source described in the first aspect. The fabrication method includes fabricating an active region on a substrate and performing p... + Graphene transfer is used to obtain a p-type heavily doped graphene layer, resulting in a fabricated laser chip. An intrinsic graphene layer is formed on an SOI substrate and a passivation layer is deposited. The prepared laser chip is bonded to the passivation layer; An oxide layer is deposited on the substrate, and electrode channels are etched and electrodes are fabricated on the oxide layer to obtain an on-chip light source.

[0013] Preferably, the method further includes: An n-type cladding layer and an active region are deposited on the substrate; An ultrathin InP layer is deposited on the active region, and p is transferred after deposition. + Graphene, resulting in a p-type heavily doped graphene layer; Graphene patterning and grating etching are performed on the p-type heavily doped graphene layer. After etching, a light confinement layer is deposited and the substrate is thinned to obtain the fabricated laser chip.

[0014] Preferably, the method further includes: Achieving graphene growth and patterning on metal and Si substrates; Graphene was selected and extracted from a Si substrate using a transfer carrier. The transfer substrate is aligned with the ultrathin InP layer, and the graphene is heated to make it adhere tightly to the target position of the ultrathin InP layer. After the adhesion is completed, the transfer substrate is dissolved by cleaning to complete the transfer of p+ graphene.

[0015] Preferably, the method further includes: Deep Si is etched onto an SOI substrate; A metal layer and a solid carbon source layer are sequentially deposited on a Si substrate. Carbon atoms are induced to diffuse directionally in the metal film by heating, and graphene is precipitated in an orderly manner at the interface of the Si substrate. After the graphene is precipitated, the metal is removed to obtain the intrinsic graphene layer. A passivation layer is deposited on the intrinsic graphene layer to protect the bottom intrinsic graphene layer.

[0016] Compared with existing technologies, the beneficial effects of this invention are as follows: It introduces graphene materials with excellent properties such as high mobility and high thermal conductivity to compensate for the shortcomings of current on-chip light sources, thereby overcoming power and bandwidth bottlenecks by improving hole injection efficiency and substrate heat dissipation efficiency. Specifically, the increased hole injection efficiency leads to increased effective radiative recombination of holes and electrons in the active region, while the improved substrate heat dissipation efficiency reduces hole and electron leakage. These two factors work together to promote increased quantum efficiency and reduced threshold current in the laser, thus increasing the laser's output power. Furthermore, the increased hole injection efficiency and substrate heat dissipation efficiency lead to increased effective radiative recombination and reduced carrier leakage, resulting in increased differential gain and quantum efficiency, and reduced threshold current, thereby increasing the relaxation oscillation frequency and ultimately improving the laser's modulation bandwidth. Therefore, this invention improves both the laser's output power and modulation bandwidth by enhancing hole injection efficiency and substrate heat dissipation efficiency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0018] Figure 1 This is an internal side view of the DFB laser region provided in an embodiment of the present invention; Figure 2 This is a top view of the DFB laser region provided in an embodiment of the present invention; Figure 3 This is a schematic cross-sectional view of a DFB laser provided in an embodiment of the present invention; Figure 4 This is a side view of the high-speed, high-power on-chip light source provided in an embodiment of the present invention; Figure 5 This is a flowchart of a method for fabricating a high-speed, high-power on-chip light source provided in an embodiment of the present invention; Figure 6 This is a flowchart of a method for fabricating a laser chip in a high-speed, high-power on-chip light source provided in an embodiment of the present invention; Figure 7 This is a flowchart of a method for obtaining a p-type heavily doped graphene layer in a high-speed, high-power on-chip light source fabrication method provided in an embodiment of the present invention; Figure 8 This is a method for fabricating a high-speed, high-power on-chip light source provided in an embodiment of the present invention. + Flowchart of graphene transfer printing; Figure 9 This is a flowchart of the SOI substrate processing method in a high-speed, high-power on-chip light source fabrication method provided in an embodiment of the present invention; Figure 10 This is a flowchart of the laser fabrication process in a method for fabricating a high-speed, high-power on-chip light source provided in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0020] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0021] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0022] In the description of this invention, the expression “A and / or B” (where A and B are used to formally represent specific features) will be used. The corresponding expression includes the following three combinations: only A, only B, and a combination of A and B.

[0023] As used in this invention, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from a particular value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0024] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0025] Example 1: Existing on-chip light sources employ a structure where an SOI substrate is bonded to a laser chip. The laser chip, from bottom to top, comprises a silicon dioxide passivation layer, a substrate, an n-type cladding, an active region, and a relatively thick p-type heavily doped InP layer. The n-type cladding is used for electron injection, while the p-type heavily doped InP layer is responsible for hole injection and confining the light field. In the active region, electrons from the n-type cladding and holes from the p-type heavily doped InP layer recombine to emit light via carrier radiation (where carriers include both holes and electrons). However, due to the large effective mass of holes in the p-type heavily doped InP layer, the hole mobility is extremely low, making efficient radiative recombination of holes and electrons in the active region difficult. This reduces the output power of the on-chip light source and limits the modulation bandwidth. Furthermore, the heat generated during laser chip operation is conducted downwards to the silicon dioxide passivation layer for dissipation. However, the poor thermal conductivity of the silicon dioxide passivation layer limits its heat dissipation capacity, making it difficult to effectively dissipate the generated heat. Consequently, the heat accumulates continuously in the active region, causing an increase in the active region temperature. This temperature increase, in turn, leads to problems such as increased threshold current, increased carrier leakage, and decreased differential gain. Ultimately, this reduces the output power of the on-chip light source and limits the modulation bandwidth. In summary, existing on-chip light sources suffer from bottlenecks such as low hole injection efficiency and difficult heat dissipation, which further restricts the improvement of the output power and modulation bandwidth of on-chip light sources.

[0026] To address this, the present invention provides a high-speed, high-power on-chip light source, which includes a laser chip and an SOI substrate; the laser chip includes a laser region, which includes a substrate, an n-type cladding layer, an active region, an ultrathin InP layer, and an optical confinement layer stacked sequentially from bottom to top, with a p-type heavily doped graphene layer inserted between the ultrathin InP layer and the optical confinement layer; The SOI substrate comprises an intrinsic graphene layer and a passivation layer stacked sequentially from bottom to top, with the substrate bonded to the passivation layer. Holes provided by the p-type heavily doped graphene layer recombine with electrons provided by the n-type cladding layer in the active region to emit light. The high mobility of the graphene material in the p-type heavily doped graphene layer enhances hole injection efficiency, thereby increasing the effective radiative recombination of holes and electrons in the active region. Simultaneously, the high thermal conductivity of the graphene material in the intrinsic graphene layer rapidly dissipates the heat generated by recombination through the intrinsic graphene layer, improving the substrate's heat dissipation efficiency.

[0027] Among them, p-type heavily doped graphene layer refers to a layer that uses graphene and other materials, and the doping concentration is heavily doped. Heavy doping usually refers to a carrier concentration of 10. 18 cm 3 In the above examples, the doping material is silicon or tin. An intrinsic graphene layer refers to a layer made solely of graphene, without any other doping.

[0028] In one embodiment, the laser region is a distributed feedback laser (DFB). In another embodiment, the substrate is an n-type InP substrate, meaning the substrate material is InP and the substrate's conductivity type is electronic conductivity.

[0029] In one embodiment, the n-type cladding is an n-type heavily doped InP layer, meaning the material of the n-type cladding is InP, the conductivity type of the n-type cladding is electronic conductivity, and the doping concentration of the n-type cladding is heavily doped, typically referring to a carrier concentration of 10. 18 cm 3 The doping materials mentioned above are silicon or tin.

[0030] In one embodiment, the active region is a multi-quantum-well structure, which includes multiple alternately stacked well layers and barrier layers, wherein the well layers and the barrier layers are both made of In. 1-x Ga x As y P 1-y The emission wavelength and efficient confinement of charge carriers can be controlled by changing the composition ratio (x,y) of Group III (In / Ga) and Group V (As / P) components in the two-layer material.

[0031] In one embodiment, the ultrathin InP layer is made of InP, and the light confinement layer is not p-type doped, being intrinsic InP. In another embodiment, the light confinement layer is an InP light confinement layer, meaning the light confinement layer is made of InP and is not p-type doped, being intrinsic InP. In one embodiment, the passivation layer is a silicon dioxide passivation layer.

[0032] The following description uses a DFB laser region as an example to illustrate the structure of the high-speed, high-power on-chip light source provided by this invention. The high-speed, high-power on-chip light source includes an SOI substrate and a DFB laser region. Figure 1 This is an internal side view of the DFB laser region, as shown below. Figure 1 As shown, the DFB laser region includes, from bottom to top, an intrinsic graphene layer, a silicon dioxide passivation layer, a substrate, an n-type cladding layer, an active region, an ultrathin InP layer, a p-type heavily doped graphene layer, and an optical confinement layer.

[0033] This invention addresses the shortcomings of current on-chip light sources by introducing graphene, a material with excellent properties such as high mobility and high thermal conductivity. It aims to overcome power and bandwidth bottlenecks by improving hole injection efficiency and substrate heat dissipation efficiency. Specifically, increased hole injection efficiency leads to increased effective radiative recombination of holes and electrons in the active region, while improved substrate heat dissipation efficiency reduces hole and electron leakage. These two factors work together to improve laser quantum efficiency and reduce threshold current, thereby increasing laser output power. Furthermore, improved hole injection efficiency and substrate heat dissipation efficiency increase effective radiative recombination and reduce carrier leakage, leading to increased differential gain and quantum efficiency, and reduced threshold current. This increases the relaxation oscillation frequency, further enhancing the laser modulation bandwidth. Therefore, this invention improves laser output power and modulation bandwidth by enhancing hole injection efficiency and substrate heat dissipation efficiency.

[0034] On the one hand, the present invention replaces the thick p-type heavily doped InP layer in the existing on-chip laser chip with a p-type heavily doped graphene layer, an ultrathin InP layer and an optical confinement layer. The p-type heavily doped graphene layer is used as a hole source. By utilizing the high carrier mobility of graphene material, the effective mass of holes provided by the p-type heavily doped graphene layer is extremely small, thereby improving the hole mobility.

[0035] Furthermore, p-type heavy doping in the graphene contact region can significantly reduce the band mismatch between graphene and InP, compressing the barrier height (where a lower barrier height results in higher hole injection efficiency, and a higher barrier height results in lower hole injection efficiency). After adding an intrinsic ultrathin InP layer to the laser region (where intrinsic means no p-type doping is required), the presence of the ultrathin InP layer further reduces the barrier thickness. At this point, the ultrathin InP layer combined with p-type heavy-doped graphene can achieve efficient tunneling hole injection, effectively solving the problem of difficult hole injection and improving hole injection efficiency. Simultaneously, an optical confinement layer is placed on the upper surface of the p-type heavy-doped graphene layer to confine the optical field.

[0036] On the other hand, this invention introduces intrinsic graphene at the bottom of the silicon dioxide passivation layer as a lateral heat dissipation channel. Heat generated during the operation of the active region is transferred through the silicon dioxide passivation layer to the intrinsic graphene layer via the substrate. Utilizing the high thermal conductivity of graphene, the heat generated during the operation of the active region can be rapidly diffused horizontally, thereby quickly dissipating the heat and improving thermal stability, thus enhancing the substrate's heat dissipation efficiency. Although the thermal conductivity of the silicon dioxide passivation layer is low, its thickness is very thin. The heat generated during the operation of the active region only needs to pass through the silicon dioxide passivation layer; the high thermal conductivity of the graphene material allows the heat to be rapidly dissipated horizontally for quick heat dissipation.

[0037] In one embodiment, the modulation bandwidth of the laser is determined by the relaxation oscillation frequency of the DFB laser region. This invention increases the relaxation oscillation frequency by increasing effective radiative recombination and reducing carrier leakage, thereby increasing the differential gain and quantum efficiency and decreasing the threshold current. This, in turn, enhances the modulation bandwidth of the laser. The expression for the relaxation oscillation frequency is as follows: ; in, The frequency of relaxation oscillation. The group velocity of light in the laser medium. , , These represent the gain, carrier density, and differential gain of the DFB laser, respectively. This is the gain saturation coefficient. Photon density, For internal quantum efficiency, The light field confinement factor, For electron charge, For the volume of the active region, For the current injected into the DFB laser region, This is the threshold current of the DFB laser.

[0038] The following describes the function of each layer in the DFB laser region provided by this invention. The intrinsic graphene layer serves as a lateral heat dissipation channel, utilizing the ultra-high thermal conductivity of graphene to rapidly diffuse the heat generated during active region operation horizontally. A silicon dioxide passivation layer is disposed on the upper surface of the intrinsic graphene layer, providing a bonding interface and protecting the bottom intrinsic graphene layer. The substrate is disposed on the upper surface of the silicon dioxide passivation layer, acting as a heat dissipation carrier, transferring the heat generated during active region operation downwards through the passivation layer to the intrinsic graphene layer, where the ultra-high thermal conductivity of graphene rapidly dissipates the heat. An n-type cladding layer is disposed on the upper surface of the substrate, confining the light field within the active region and providing a carrier injection channel, injecting generated electrons into the active region through this channel. The active region is disposed on the upper surface of the n-type cladding, where electrons and holes recombine to generate gain luminescence. An InP layer is disposed on the upper surface of the active region to confine the light field and transport holes to the active region. A p-type heavily doped graphene layer is disposed on the upper surface of the InP layer to form a hole source and inject the generated holes into the active region through the InP layer. An optical confinement layer is disposed on the upper surface of the p-type heavily doped graphene layer to confine the light field within the active region.

[0039] In summary, this invention replaces the thicker p-type heavily doped InP layer in the original structure with a p-type heavily doped graphene layer, an ultrathin InP layer, and an optical confinement layer. The high mobility of graphene, combined with the ultrathin InP layer, facilitates tunneling hole injection, accelerating hole injection efficiency. The optical confinement layer restricts the optical field, thereby improving hole injection efficiency while maintaining the original structure. Furthermore, the intrinsic graphene layer introduced at the bottom utilizes its high thermal conductivity to rapidly dissipate heat generated during active region operation, improving substrate heat dissipation efficiency and consequently enhancing laser output power and modulation bandwidth.

[0040] The on-chip light source also includes a P-side electrode, an N-side electrode, and an oxide layer. The oxide layer is disposed on the substrate and surrounds an n-type cladding layer, an active region, an ultrathin InP layer, a p-type heavily doped graphene layer, and a light confinement layer. The P-side electrode is disposed on the ultrathin InP layer, and the N-side electrode is disposed on the oxide layer. The P-side electrode and the N-side electrode are used to inject current into the active region.

[0041] The optical microcavity consists of an n-type cladding layer, an active region, an ultrathin InP layer, a p-type heavily doped graphene layer, and an optical confinement layer. The optical microcavity is surrounded by an SOI oxide layer on both sides, with trenches around the SOI oxide layer. The p-side electrode contacts the p-type heavily doped graphene through an external electrode channel and is placed on the InP layer. The n-side electrode forms an electrical connection with the n-type InP substrate and is led out from the trench and placed on the SOI oxide layer.

[0042] In one embodiment, the oxide layer is an SOI oxide layer.

[0043] Figure 2 This is a top view of the DFB laser region. The G layer (ground electrode) is located on the top and bottom sides of the DFB laser region, serving as the grounding terminal of the coplanar waveguide structure. It forms a complete current loop and provides electromagnetic shielding to reduce high-frequency signal interference. The S layer, located between the two G layers, is the input channel for high-frequency electrical signals, responsible for injecting driving current into the active region to excite carrier recombination and emission. The optical resonant cavity (Cavity) is located in the central region of the DFB laser region, providing optical feedback so that the light oscillates and amplifies within the cavity, ultimately forming the laser output. The external electrodes do not directly participate in the formation of the optical cavity, ensuring uniform current injection into the gain region. The Oxide or BCB layer covers the outermost layer of the DFB laser region, used for isolating electrodes and protecting the device structure. BCB is a commonly used polymer dielectric with good planarization and insulation properties.

[0044] Figure 3 This is a schematic diagram of a cross-section of a DFB laser, as shown below. Figure 3As shown, the light emission process of the DFB laser combined with the SOI substrate provided by this invention is as follows: The external electrode, through a GSG electrode structure, injects a driving current into the DFB laser region via the p-side and n-side electrodes. The current flows in from the p-side electrode, stimulating the p-type heavily doped graphene layer to release holes, and simultaneously flows out through the n-side electrode, stimulating the n-type cladding layer to release electrons. Positively charged holes and negatively charged electrons, driven by the driving current, are transported to the active region and recombine. During recombination, electrons transition from a high energy level to a low energy level, releasing energy as photons. The resulting heat is transmitted through the substrate and the silicon dioxide passivation layer to the intrinsic graphene layer, which then rapidly conducts the heat horizontally. Simultaneously, the optical confinement layer in the DFB laser region effectively confines the light field, ensuring directional output of stimulated emission.

[0045] To further improve the 3dB bandwidth, the laser chip also includes a passive feedback region, which is disposed on the substrate together with the laser region. The passive cavity thickness of the passive feedback region is the same as the active cavity thickness of the laser region.

[0046] In one implementation, the passive feedback region is a distributed Bragg reflector laser (DBR), and the laser region is a DFB laser. See also... Figure 4 The DBR laser and DFB laser are jointly disposed on the substrate. The passive cavity thickness of the DBR laser is the same as the active cavity thickness of the DFB laser, i.e., the orange and blue portions in the figure have the same thickness. In other words, this invention also provides an on-chip light source, the structure of which includes a laser chip and an SOI substrate. The laser chip includes a DFB laser and a DBR laser, with the DFB laser serving as the active light-emitting region and the DBR laser serving as the passive feedback region. The DFB laser and DBR laser work together to excite the PPR effect, thereby effectively extending the 3dB modulation bandwidth of the device.

[0047] Specifically, in a DFB laser, the grating provides the main mode lasing, ensuring stable single-longitudinal-mode output; in a DBR laser, the grating acts as an external cavity reflection structure, introducing a side-mode resonance within the cavity with a frequency appropriately spaced from the main lasing mode. When the frequency difference between the two matches the carrier-photon relaxation oscillation frequency, a strong photon-photon resonance effect is excited. This allows the high-frequency modulation signal to gain additional gain through energy exchange between photons, rather than relying solely on traditional carrier relaxation oscillation. This resonance mechanism significantly enhances the response to high-frequency modulation components, forming a resonance peak on the frequency response curve, thereby pushing the 3dB cutoff frequency to a higher frequency band and thus greatly increasing the modulation bandwidth of the laser.

[0048] This invention also provides a method for fabricating a high-speed, high-power on-chip light source, solving the problems of device consistency and large-scale fabrication, such as... Figure 5 As shown, the on-chip light source fabrication method includes: Step 101: Fabricate the active region on the substrate and perform p... + Graphene transfer is used to obtain a p-type heavily doped graphene layer, resulting in a fabricated laser chip.

[0049] Step 102: Form an intrinsic graphene layer and deposit a passivation layer on the SOI substrate.

[0050] In one embodiment, the passivation layer is a silicon dioxide passivation layer.

[0051] Step 103: Bond the prepared laser chip to the passivation layer.

[0052] Essentially, the process involves bonding the substrate in the laser region to the passivation layer on the SOI substrate. Specifically, bumps are fabricated at the substrate bonding points. The chip with the bumps is flipped and aligned with the pads on the SOI substrate passivation layer. Heating and pressure are then used to bond the bumps to the SOI substrate pads. The bumps are typically made of materials such as gold, tin, or copper.

[0053] Step 104: Deposit an oxide layer on the substrate, and perform electrode trench etching and electrode fabrication on the oxide layer to obtain an on-chip light source.

[0054] See Figure 6 The process of fabricating laser chips includes the following steps: Step 201: Deposit an n-type cladding layer and an active region on the substrate.

[0055] The substrate is an n-type InP substrate. The n-type cladding is an n-type heavily doped InP layer. The active region is a multiple quantum well structure. Specifically, the thickness of the n-type InP substrate is 350 ± 25 μm. An n-type heavily doped InP layer with a thickness of 0.2~0.5 μm can be deposited on the n-type InP substrate. A multiple quantum well structure with a thickness of 0.15~0.3 μm can be deposited on the n-type heavily doped InP layer.

[0056] It should be noted that before depositing the heavily doped n-type InP layer on the n-type InP substrate, the n-type InP substrate should be organically cleaned and acid-washed to remove the native oxide layer on its surface. MOCVD epitaxy can be used to deposit the heavily doped n-type InP layer on the n-type InP substrate to prevent substrate defect propagation. MOCVD epitaxy can also be used to alternately deposit barriers and wells on the heavily doped n-type InP layer.

[0057] Step 202: Deposit an ultrathin InP layer on the active region, and transfer p after deposition. + Graphene was used to obtain a p-type heavily doped graphene layer.

[0058] The active region is a multi-quantum-well structure. It should be noted that after depositing an ultrathin InP layer on the multi-quantum-well structure and then transferring p-type heavily doped graphene, the graphene is used as a hole source. Utilizing the high carrier mobility of graphene, the effective hole mass provided by the p-type heavily doped graphene layer is extremely small, which can improve hole mobility. Simultaneously, the p-type heavy doping in the graphene contact region can significantly reduce the band mismatch between graphene and InP, compressing the barrier height. The presence of the ultrathin InP layer results in a very small barrier thickness, which, combined with the p-type heavily doped graphene, enables efficient tunneling hole injection, solving the problem of difficult hole injection.

[0059] In addition, this invention introduces an InP light confinement layer to confine the light field. Therefore, this invention uses a p-type heavily doped graphene layer, an ultrathin InP layer, and a light confinement layer to replace the thicker p-type heavily doped InP layer in the original structure. The high mobility of graphene material, combined with the ultrathin InP layer, forms tunneling hole injection, accelerating the hole injection efficiency, and the light confinement layer confines the light field.

[0060] Step 203: Graphene patterning and grating etching are performed on the p-type heavily doped graphene layer. After etching, a light confinement layer is deposited and the substrate is thinned to obtain the fabricated laser chip.

[0061] In one embodiment, the patterning here is intended to allow InP to continue to adhere as InP deposition proceeds.

[0062] See Figure 7 , transfer p + To obtain a p-type heavily doped graphene layer, the specific steps include the following: Step 301: Graphene growth and patterning are achieved on metal and Si substrates.

[0063] In this fabrication process, patterning involves dividing a large area of ​​graphene into several graphene sizes required for individual laser chips, and then transferring them onto multiple laser chips on a wafer.

[0064] Specifically, a metal layer and a solid carbon source layer are sequentially deposited on a Si substrate. Carbon atoms are induced to diffuse directionally in the metal film by heating, and graphene is precipitated in an orderly manner at the interface between the metal and the Si substrate. After precipitation, the metal is removed, and the graphene is retained.

[0065] Step 302: Select graphene using a transfer carrier and extract it from the Si substrate.

[0066] Among them, single-layer graphene that meets the quality requirements is selected, and its size and shape match the electrode area required by a single laser chip. It is free from damage or folding and has good cleanliness.

[0067] Step 303: Align the transfer substrate with the ultrathin InP layer, and heat it to make the graphene adhere tightly to the target position of the ultrathin InP layer. After the adhesion is completed, the transfer substrate is dissolved by cleaning to complete the transfer of p+ graphene.

[0068] Figure 8 For p + Graphene transfer process, such as Figure 8 As shown, the p-type heavily doped graphene transfer process is as follows: A metal layer and a solid carbon source layer are sequentially deposited on a Si substrate. Carbon atoms are induced to diffuse directionally in the metal film by heating, and ordered precipitation is achieved at the metal-Si substrate interface. After precipitation, the metal is removed. Then, graphene patterning is performed: first, a photoresist coating is applied, followed by photolithography and development, then etching, and finally, the resist is removed and the substrate is cleaned. Next, a transfer carrier is used to select graphene and extract it from the original substrate. Finally, the transfer carrier is aligned with the target substrate, and heating is used to make the graphene adhere tightly to the target position. The carrier is then cleaned and dissolved to complete the p+ graphene transfer. In this process, the graphene electrode is responsible for injecting charge carriers. The graphene electrode is connected to the metal, which serves as the interface for external electrical signals. The graphene is the one that actually performs the function of charge carrier injection inside the device.

[0069] An intrinsic graphene layer is formed on an SOI substrate, and a passivation layer is deposited, such as... Figure 9 As shown, the specific steps include the following: Step 401: Etch deep Si on the SOI substrate.

[0070] Step 402: Sequentially deposit a metal layer and a solid carbon source layer on a Si substrate. Induce carbon atoms to diffuse directionally in the metal film by heating, and achieve ordered precipitation of graphene at the Si substrate interface. After the graphene is precipitated, remove the metal to obtain the intrinsic graphene layer.

[0071] Specifically, the process of depositing metal mass transfer to achieve graphene precipitation is as follows: after deep Si etching, a metal thin film layer and a solid carbon source layer are deposited. Carbon atoms are induced to diffuse directionally in the metal thin film by heating and achieve orderly precipitation at the interface between the metal and the Si substrate. Finally, the metal is removed.

[0072] It should be noted that in this invention, graphene is deposited on an SOI substrate. In this case, the graphene serves as a bottom lateral heat dissipation channel to utilize the high thermal conductivity of graphene material to quickly dissipate the generated heat in the horizontal direction, thereby improving the heat dissipation efficiency of the substrate.

[0073] Step 403: Deposit a passivation layer on the intrinsic graphene layer to protect the bottom intrinsic graphene layer.

[0074] In one embodiment, a silicon dioxide passivation layer is deposited on the intrinsic graphene layer to protect the underlying intrinsic graphene layer.

[0075] Figure 10 It refers to the laser manufacturing process, such as... Figure 10 As shown, an n-type heavily doped InP layer and a multiple quantum well structure are deposited on an n-type InP substrate. An ultrathin InP layer is then deposited on top of this. After deposition, p-type heavily doped graphene is transferred, followed by graphene patterning, grating etching, and deposition of an InP light confinement layer. Finally, the substrate is thinned. The p-type heavily doped graphene transfer process is as follows: graphene growth and patterning are achieved on a metal and Si substrate. Graphene is selected using a transfer carrier and transferred in batches onto the laser chip. Before bonding the laser chip to the graphene SOI chip, the SOI chip undergoes deep Si etching. After etching, metal mass transfer is deposited to achieve graphene precipitation, followed by the deposition of a SiO2 passivation layer. The laser chip is then bonded to the SOI chip. Finally, oxide layer deposition, electrode channel and oxide layer etching, and electrode fabrication are performed.

[0076] In summary, this invention fabricates the laser chip separately during the on-chip light source preparation process, then bonds it to the SOI substrate. During the laser chip fabrication process, graphene is injected to form a p-type heavily doped graphene layer, which serves as a hole source. The high mobility of graphene enhances the hole migration rate, and its combination with an ultrathin InP layer enables tunneling hole injection, effectively increasing the relaxation oscillation frequency and hole injection efficiency, thereby significantly improving the output power and modulation bandwidth. Simultaneously, before bonding the SOI substrate to the laser chip, graphene is precipitated on the surface of the SOI substrate to obtain an intrinsic graphene layer. This intrinsic graphene layer serves as a lateral heat dissipation channel, utilizing the ultra-high thermal conductivity of graphene to improve thermal stability. This reduces the degradation of light source performance caused by high temperatures, such as increased threshold current, decreased differential gain, and carrier leakage, thus ensuring high output power and modulation bandwidth.

[0077] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-speed, high-power on-chip light source, characterized in that, Including laser chips and SOI substrates; The laser chip includes a laser region, which includes a substrate, an n-type cladding layer, an active region, an ultrathin InP layer, and an optical confinement layer stacked sequentially from bottom to top. A p-type heavily doped graphene layer is inserted between the ultrathin InP layer and the optical confinement layer. The SOI substrate comprises an intrinsic graphene layer and a passivation layer stacked sequentially from bottom to top, with the substrate bonded to the passivation layer. Holes provided by the p-type heavily doped graphene layer recombine with electrons provided by the n-type cladding layer in the active region to emit light. The high mobility of the graphene material in the p-type heavily doped graphene layer enhances hole injection efficiency, thereby increasing the effective radiative recombination of holes and electrons in the active region. Simultaneously, the high thermal conductivity of the graphene material in the intrinsic graphene layer rapidly dissipates the heat generated by recombination through the intrinsic graphene layer, improving the substrate's heat dissipation efficiency.

2. The high-speed, high-power on-chip light source according to claim 1, characterized in that, The active region is a multi-quantum well structure, which includes multiple alternating stacked well layers and barrier layers.

3. The high-speed, high-power on-chip light source according to claim 2, characterized in that, Both the well layer and the barrier layer are made of In. 1-x Ga x As y P 1-y .

4. The high-speed, high-power on-chip light source according to claim 1, characterized in that, The on-chip light source further includes an oxide layer disposed on the substrate and surrounding the n-type cladding, the active region, the ultrathin InP layer, the p-type heavily doped graphene layer, and the light confinement layer.

5. The high-speed, high-power on-chip light source according to claim 4, characterized in that, The on-chip light source further includes a P-side electrode disposed on the ultrathin InP layer and an N-side electrode disposed on the oxide layer; wherein the P-side electrode and the N-side electrode are used to inject current into the active region.

6. The high-speed, high-power on-chip light source according to claim 1, characterized in that, The laser chip also includes a passive feedback region, which is disposed on the substrate together with the laser region. The passive cavity thickness of the passive feedback region is the same as the active cavity thickness of the laser region.

7. A method for fabricating a high-speed, high-power on-chip light source, used to fabricate the high-speed, high-power on-chip light source according to any one of claims 1-6, characterized in that, include: The active region was fabricated on the substrate, and p-type processing was performed. + Graphene transfer is used to obtain a p-type heavily doped graphene layer, resulting in a fabricated laser chip. An intrinsic graphene layer is formed on an SOI substrate and a passivation layer is deposited. The prepared laser chip is bonded to the passivation layer; An oxide layer is deposited on the substrate, and electrode channels are etched and electrodes are fabricated on the oxide layer to obtain an on-chip light source.

8. The method for fabricating a high-speed, high-power on-chip light source according to claim 7, characterized in that, The method further includes: An n-type cladding layer and an active region are deposited on the substrate; An ultrathin InP layer is deposited on the active region, and p is transferred after deposition. + Graphene, resulting in a p-type heavily doped graphene layer; Graphene patterning and grating etching are performed on the p-type heavily doped graphene layer. After etching, a light confinement layer is deposited and the substrate is thinned to obtain the fabricated laser chip.

9. The method for fabricating a high-speed, high-power on-chip light source according to claim 8, characterized in that, The method further includes: Achieving graphene growth and patterning on metal and Si substrates; Graphene was selected and extracted from a Si substrate using a transfer carrier. The transfer substrate is aligned with the ultrathin InP layer, and the graphene is heated to make it adhere tightly to the target position of the ultrathin InP layer. After the adhesion is completed, the transfer substrate is dissolved by cleaning to complete the transfer of p+ graphene.

10. The method for fabricating a high-speed, high-power on-chip light source according to claim 7, characterized in that, The method further includes: Deep Si is etched onto an SOI substrate; A metal layer and a solid carbon source layer are sequentially deposited on a Si substrate. Carbon atoms are induced to diffuse directionally in the metal film by heating, and graphene is precipitated in an orderly manner at the interface of the Si substrate. After the graphene is precipitated, the metal is removed to obtain the intrinsic graphene layer. A passivation layer is deposited on the intrinsic graphene layer to protect the bottom intrinsic graphene layer.

Images