Semiconductor laser element and light emitting device

Abstract

The application relates to the technical field of lasers, in particular to a semiconductor laser element and a light emitting device. The semiconductor laser element comprises a substrate, the substrate having opposite first and second surfaces; a semiconductor stack arranged on the first surface; a back electrode layer arranged on the second surface; the back electrode layer comprising a first electrode layer and a second electrode layer; the first electrode layer being located between the second electrode layer and the substrate; the first electrode layer completely covering the second surface of the substrate; a projection edge of the second electrode layer on the second surface being located within the range of a projection edge of the first electrode layer on the second surface, and the projection edge of the second electrode layer on the second surface and the projection edge of the first electrode layer on the second surface having a minimum spacing L; and the thickness d1 of the first electrode layer being smaller than the thickness d2 of the second electrode layer. The above arrangement effectively improves the light emitting performance and reliability of the semiconductor laser element.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor laser element and a light emitting device. Background Technology

[0002] Semiconductor lasers are light source devices widely used in communications, sensing, medical, and industrial processing. Their core working principle relies on the refractive index difference between the waveguide layer and the confinement layer in their internal structure to limit the lasing mode, thereby ensuring the stability of the laser's far-field spot characteristics and output power.

[0003] In traditional semiconductor laser design, cleaving along cleaving lines is typically required to form the resonant cavity surface. To avoid peeling defects caused by tearing of the back metal electrode during cleaving, current processes generally design the back electrode as a patterned structure, i.e., removing the metal layer along the cleaving path. However, patterned back electrodes can significantly affect the device's operational stability and long-term reliability under high current. Summary of the Invention

[0004] In view of at least one deficiency of the prior art, the purpose of this application is to provide a semiconductor laser element to effectively solve the problem of back electrode design and improve the reliability of the laser element.

[0005] This application provides a semiconductor laser element, which includes at least a substrate having a first surface and a second surface opposite to each other; a semiconductor stack disposed on the first surface; and a back electrode layer disposed on the second surface. The back electrode layer includes a first electrode layer and a second electrode layer. The first electrode layer is located between the second electrode layer and the substrate. The first electrode layer completely covers the second surface of the substrate. The projected edge of the second electrode layer on the second surface is located within the range of the projected edge of the first electrode layer on the second surface, and the projected edge of the second electrode layer on the second surface and the projected edge of the first electrode layer on the second surface have a minimum distance L. The thickness d1 of the first electrode layer is less than the thickness d2 of the second electrode layer.

[0006] In addition, this application also provides a light emitting device, which employs a semiconductor laser element as described in the above embodiments.

[0007] Based on the above, compared with the prior art, the semiconductor laser element provided in this application avoids metal tearing and peeling during the cleaving process by using a thinner first electrode layer that completely covers the back side of the substrate. At the same time, by using a thicker second electrode layer with a minimum spacing L, the eutectic bonding area is increased and the heat dissipation path is improved while maintaining the compatibility of the cleaving process, thereby improving the reliability of the laser element.

[0008] Other features and beneficial effects of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing this application. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a top view of the semiconductor laser element provided in the embodiments of this application; Figure 2 yes Figure 1 Sectional view of AA; Figure 3 This is a top view of another modified example of the semiconductor laser element provided in the embodiments of this application; Figure 4 yes Figure 3 Sectional view of BB; Figure 5 yes Figure 3 A bottom view of the semiconductor laser element provided in the embodiment; Figure 6 yes Figure 3 Sectional view of CC; Figure 7 This is a cross-sectional view of a semiconductor laser element provided in another embodiment of this application.

[0011] Figure label: 10. Substrate; 10a. First surface; 10b. Second surface; 20. Semiconductor stack; 21. First semiconductor layer; 22. Active layer; 23. Second semiconductor layer; 30. Back electrode layer; 31. First electrode layer; 32. Second electrode layer; d1. Thickness of the first electrode layer; d2. Thickness of the second electrode layer; L. Minimum distance between the projected edge of the second electrode layer on the second surface and the projected edge of the first electrode layer on the second surface; 40. Front electrode layer; 51. First cavity surface coating layer; 52. Second cavity surface coating layer; 60. Insulating layer; 70. Ohmic contact layer. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings; the technical features designed in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0013] This application provides a semiconductor laser element, which includes at least a substrate 10 having opposing first surfaces 10a and second surfaces 10b; a semiconductor stack 20 disposed on the first surface 10a; and a back electrode layer 30 disposed on the second surface 10b. The back electrode layer 30 includes a first electrode layer 31 and a second electrode layer 32. The first electrode layer 31 is located between the second electrode layer 32 and the substrate 10. The first electrode layer 31 completely covers the second surface 10b of the substrate 10. The projected edge of the second electrode layer 32 on the second surface 10b is located within the range of the projected edge of the first electrode layer 31 on the second surface 10b, and there is a minimum distance L between the projected edge of the second electrode layer 32 on the second surface 10b and the projected edge of the first electrode layer 31 on the second surface 10b. The thickness d1 of the first electrode layer 31 is less than the thickness d2 of the second electrode layer 32.

[0014] The aforementioned dual-layer back electrode structure ensures compatibility with the dicing process by using a thinner, full-coverage first electrode layer 31, avoiding metal tearing and peeling during the dicing process, and suppressing light leakage at the bottom of the substrate 10 by utilizing its light-shielding effect. The thicker, recessed second electrode layer 32 increases the eutectic area of ​​the package and ensures heat dissipation. The two work together to resolve the contradiction between insufficient eutectic area of ​​the patterned electrode and dicing peeling of the full-coverage thick electrode, while improving the light leakage phenomenon of the substrate 10 at the bottom of the light-emitting side cavity surface, thereby enhancing the reliability and beam quality of the semiconductor laser device.

[0015] Furthermore, 5 ≤ d2 / d1 ≤ 20. This limitation ensures that the second electrode layer 32 has a sufficiently large thickness advantage relative to the first electrode layer 31. This avoids both insufficient eutectic bonding strength or wire bonding reliability due to an excessively small ratio and the impact of an excessively large ratio on the functional integrity of the first electrode layer 31 as a seed layer or barrier layer, thus balancing die-cut compatibility and packaging reliability.

[0016] Furthermore, 100 Å ≤ d1 ≤ 1000 Å. This ensures that the first electrode layer 31 provides good conductivity and adhesion, while preventing metal tearing during wafer cleaving. More preferably, 400 Å ≤ d1 ≤ 600 Å.

[0017] Furthermore, 2000 Å ≤ d2 ≤ 10000 Å. This limitation provides sufficient metal volume for eutectic bonding and wire bonding, ensuring adequate wetting and mechanical strength at the bonding interface, while guaranteeing good longitudinal conductivity and lateral heat dissipation, avoiding excessive thinness leading to eutectic solder penetration or excessive thickness leading to increased film stress. More preferably, 2500 Å ≤ d2 ≤ 5000 Å.

[0018] Furthermore, 0 < L ≤ 10 μm is used to ensure a clearly defined uncovered area between the second electrode layer 32 and the edge of the substrate 10, so that only a thin layer of the first electrode layer 31 is present along the dicing path, while maximizing the coverage area of ​​the second electrode layer 32 to maximize the eutectic bonding area. This upper limit is compatible with the process capabilities of conventional laser dicing or dicing. More preferably, 3 μm ≤ L ≤ 7 μm.

[0019] Furthermore, the material of the first electrode layer 31 does not contain Au, thereby avoiding the generation of slag or splashing contamination of the cavity surface by gold-containing materials in processes involving local high temperatures, such as laser scribing, making the first electrode layer 31 more compatible with back scribing operations, while reducing material costs.

[0020] Furthermore, the material of the first electrode layer 31 includes at least one of Ti, Pt, Ni, Cr, and Al.

[0021] Furthermore, the second electrode layer 32 includes an outermost layer located on the side furthest away from the first electrode layer 31, the outermost layer comprising Au or an alloy thereof; and the thickness of the outermost layer is greater than the thickness of any of the other layers in the second electrode layer 32.

[0022] Furthermore, the thickness of the outermost layer is greater than the thickness d1 of the first electrode layer 31. The thicker outermost layer can withstand the mechanical push-pull forces and thermal stresses during eutectic bonding and wire bonding processes, protecting the reliability of the device.

[0023] Furthermore, the thickness of the outermost layer is between 2000 angstroms and 5000 angstroms to avoid the outermost layer being completely consumed during the eutectic process due to being too thin, thus affecting the bonding strength, and also to avoid stress problems caused by being too thick.

[0024] Furthermore, the substrate 10 and the semiconductor stack 20 have cavity surfaces on opposite sides; the semiconductor laser element further includes a first cavity surface coating layer 51 and / or a second cavity surface coating layer 52; the first cavity surface coating layer 51 includes at least a high reflectivity layer, and the second cavity surface coating layer 52 includes at least an antireflection layer; the first cavity surface coating layer 51 and / or the second cavity surface coating layer 52 are located on the cavity surface.

[0025] Furthermore, the first cavity surface coating layer 51 and / or the second cavity surface coating layer 52 extend from the cavity surface to the sidewall of the first electrode layer 31.

[0026] Furthermore, the first cavity surface coating layer 51 and / or the second cavity surface coating layer 52 do not contact the second electrode layer 32, so as to effectively reduce the eutectic void ratio, improve the uniformity and reliability of the bonding interface, and ensure the packaging quality.

[0027] Furthermore, the semiconductor stack 20 is a GaN-based semiconductor material, and the substrate 10 is a GaN substrate. The use of a GaN-based material system achieves lattice matching and reduces epitaxial defect density, making it suitable for lasers in the visible light bands such as blue and green light.

[0028] This application also provides a light emitting device that employs a semiconductor laser element as described in any of the above embodiments, so as to effectively improve the photoelectric performance and process reliability of the light emitting device.

[0029] The technical solution of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application and through various specific implementation methods.

[0030] Example 1 Please see Figure 1 , Figure 2 In order to achieve at least one or more of the advantages mentioned above, an embodiment of this application provides a semiconductor laser element that includes at least a substrate 10, a semiconductor stack 20 and a back electrode layer 30.

[0031] The substrate 10 serves as the basic support structure for the semiconductor laser element and has a first surface 10a and a second surface 10b disposed opposite to each other. Preferably, the substrate 10 is a GaN substrate. In this embodiment, the substrate 10 can be a growth substrate or a support substrate.

[0032] A semiconductor stack 20 is disposed on the first surface 10a of the substrate 10 (i.e., the surface of the substrate 10 facing away from the back electrode layer 30) for generating and conducting laser light. In this embodiment, the stack can be formed on the substrate 10 by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD), or ion plating. In this embodiment, the semiconductor stack 20 is preferably made of a nitride semiconductor material, more preferably a GaN-based semiconductor material, to meet the emission requirements of short-wavelength lasers such as blue or green light.

[0033] The semiconductor stack 20 includes at least an active layer 22, a first semiconductor layer 21 disposed between the active layer 22 and the substrate 10, and a second semiconductor layer 23 disposed on the side of the active layer 22 facing away from the substrate 10. In this embodiment, the first semiconductor layer 21 may include, but is not limited to, a lower confinement layer, a lower waveguide layer, and a buffer layer (not shown in the figure), and the second semiconductor layer 23 may include, but is not limited to, an upper waveguide layer, an upper confinement layer, an electron blocking layer, and a contact layer (not shown in the figure). The specific functional layers should be reasonably set according to actual needs, and this embodiment does not limit them.

[0034] Specifically, the upper confinement layer is made of P-type doped material to confine the light field in the direction away from the substrate 10; the lower confinement layer is made of N-type doped material to confine the light field in the direction towards the substrate 10. The upper waveguide layer is made of P-type doped material and the lower waveguide layer is made of N-type doped material to increase the confinement of charge carriers, increase the distribution of charge carriers in the active layer 22, improve the optical confinement factor, reduce the threshold current, and improve the luminous efficiency. Preferably, the lower waveguide layer, upper waveguide layer, upper confinement layer, and lower confinement layer are any one or any combination of GaN, InGaN, InN, AlInN, AlGaN, AlInGaN, AlN, GaAs, GaP, InP, AlGaAs, AlInGaAs, AlGaInP, InGaAs, InGaAsN, AlInAs, AlInP, AlGaP, InGaP, GaSb, InSb, InAs, InAsSb, AlGaSb, AlSb, InGaSb, AlGaAsSb, InGaAsSb, SiC, Ga2O3, and BN.

[0035] The active layer 22 can be a single quantum well layer composed of indium gallium nitride / gallium nitride, or a multiple quantum well layer composed of indium gallium nitride / gallium nitride grown in multiple alternating periods, to provide optical gain.

[0036] Please continue reading. Figure 2 The back electrode layer 30 is disposed on the second surface 10b (i.e., the surface of the substrate 10 facing away from the semiconductor stack 20) ​​and is used to realize electrical connection and heat conduction between the chip and external circuits. In addition, the semiconductor laser element also includes a front electrode layer 40, which is disposed on the surface of the semiconductor stack 20 facing away from the substrate 10. The back electrode layer 30 is an N-type electrode and is electrically connected to the first semiconductor layer 21, while the front electrode layer 40 is a P-type electrode and is electrically connected to the second semiconductor layer 23.

[0037] In practical implementation, the back electrode layer 30 and the front electrode layer 40 are typically made of metal as electrodes to electrically connect with the outside world in order to control the conduction of the semiconductor laser. The material of the back electrode layer 30 may include any one of Pd, Pt, Ni, Au, Ti, W, Cu, Ag, Zn, Sn, In, Al, Ir, Rh, or ITO. The material of the front electrode layer 40 may include any one or a combination of two or more of Ni, Ti, Pd, Pt, Au, Al, TiN, ITO, and IGZO, and is not limited thereto.

[0038] In addition, please see Figure 6 The semiconductor laser element also includes an insulating layer 60, which can selectively cover the surface of the semiconductor stack 20 away from the substrate 10 as needed. The material of the insulating layer 60 includes, but is not limited to, silicon oxide or silicon nitride.

[0039] In the manufacturing process of traditional semiconductor lasers, cleaving along cleaving lines is typically required to form the resonant cavity surface. To avoid peeling defects caused by tearing of the back metal electrode during cleaving, current processes generally design the back electrode as a patterned structure, i.e., removing the metal layer along the cleaving path. However, patterned back electrodes significantly reduce the effective bonding area of ​​the chip in eutectic packaging, resulting in limited heat dissipation paths, increased thermal resistance, and consequently affecting the device's operational stability and long-term reliability under high current. Simultaneously, as the operating wavelength of GaN-based lasers shortens, the optical confinement capability of existing semiconductor lasers deteriorates significantly due to the gradually decreasing refractive index difference between the waveguide layer and the confinement layer. Some lasing modes couple to the substrate to form substrate modes, causing severe light leakage, which in turn affects the far-field and near-field beam characteristics of the laser, resulting in unstable output power and a large far-field divergence angle.

[0040] Based on this, in this embodiment, as Figure 2 , Figure 4 As shown, the back electrode layer 30 includes a first electrode layer 31 and a second electrode layer 32; the first electrode layer 31 is located between the second electrode layer 32 and the substrate 10; the first electrode layer 31 completely covers the second surface 10b of the substrate 10; the projected edge of the second electrode layer 32 on the second surface 10b is located within the range of the projected edge of the first electrode layer 31 on the second surface 10b, and there is a minimum distance L between the projected edge of the second electrode layer 32 on the second surface 10b and the projected edge of the first electrode layer 31 on the second surface 10b; the thickness d1 of the first electrode layer 31 is less than the thickness d2 of the second electrode layer 32.

[0041] In specific implementation, "the projected edge of the first electrode layer 31 on the second surface 10b" refers to the contour boundary formed by projecting the edge of the first electrode layer 31 onto the second surface 10b in a direction perpendicular to the second surface 10b; similarly, "the projected edge of the second electrode layer 32 on the second surface 10b" refers to the contour boundary formed by projecting the edge of the second electrode layer 32 onto the second surface 10b in a direction perpendicular to the second surface 10b. "Complete coverage" means that the first electrode layer 31 extends continuously on the second surface 10b of the substrate 10, so that there is no exposed portion of the second surface 10b within the coverage area. In this embodiment, the first electrode layer 31 is a continuous metal layer that covers the entire second surface 10b of the substrate 10, and its thickness d1 is relatively small. Because the first electrode layer 31 is relatively thin, in the subsequent dicing process, when splitting along the cleavage lines, this thin metal layer will not produce significant ductile tearing, thereby effectively avoiding metal peeling defects and ensuring the smooth progress of the dicing process and the integrity of the chip. More importantly, although the first electrode layer 31 is thin, it has a certain light absorption or blocking ability because it continuously covers the entire surface. It can effectively block the light that leaks from the active layer 22 through the substrate 10 to the second surface 10b side of the substrate 10. In particular, it significantly improves the light leakage phenomenon of the bottom substrate 10 of the cavity surface near the anti-reflection layer (AR) side (or near the second cavity surface coating layer 52 side), and avoids stray light from escaping from the back of the substrate 10 and affecting the beam quality, thereby improving the symmetry and clarity of the far-field light spot.

[0042] The second electrode layer 32, serving as the primary functional layer for eutectic bonding or wire bonding with external circuitry, has a relatively thick thickness d2, where d1 < d2. This thicker second electrode layer 32 provides ample eutectic bonding area and excellent electrical and thermal conductivity, ensuring low contact resistance and efficient heat dissipation after packaging. Simultaneously, the projected edge of the second electrode layer 32 on the second surface 10b lies within the range of the projected edge of the first electrode layer 31 on the second surface 10b, and has a minimum spacing L. This minimum spacing L refers to the minimum distance between the sidewalls of the second electrode layer 32 and the first electrode layer 31 on the second surface 10b. In other words, the second electrode layer 32 is recessed inwards at its edge relative to the coverage of the first electrode layer 31, without extending to the edge region of the second surface 10b. This design ensures that the edge region of the substrate 10 where the cleavage path is located is only covered by the thinner first electrode layer 31, while the thicker second electrode layer 32 does not extend near the cleavage line. In this way, during the dicing process, the thicker metal layer will not be directly subjected to splitting stress, thus avoiding tearing or peeling. This increases the effective eutectic area while remaining fully compatible with existing dicing and scribing processes. Furthermore, the reserved minimum spacing L provides a process window for the alignment tolerances of laser scribing or dicing wheel scribing, preventing the scribing tool from directly contacting the thicker metal layer.

[0043] In other embodiments, the first electrode layer 31 does not completely cover the second surface 10b of the substrate 10; it may only cover the edge region of the substrate 10. That is, the first electrode layer 31 only covers the edge region of the second surface 10b, thereby exposing the second surface 10b in the central region; the second electrode layer 32 is located on a portion of the surface of the first electrode layer 31 and extends to cover the exposed second surface 10b; the outer edge of the second electrode layer 32 is recessed inward relative to the outer edge of the first electrode layer 31 by the minimum spacing L. Specifically, as follows... Figure 7 As shown, the first electrode layer 31 can be continuously distributed in a ring or border shape around the periphery of the second surface 10b, with its outer edge close to the sidewall of the substrate 10 and its inner edge defining a voided central region. The second electrode layer 32 is stacked on the region near the inner edge of the first electrode layer 31 and extends from the stacking point towards the central region until it fills the exposed second surface 10b; thus, the second electrode layer 32 is in direct contact with the substrate 10 in the central region, and is connected to the substrate 10 through the first electrode layer 31 in the edge region. Because the outer edge of the second electrode layer 32 is recessed inward relative to the outer edge of the first electrode layer 31 with the minimum spacing L, only the thinner first electrode layer 31 is distributed in the outer peripheral region of the substrate where the cleaving path is located, while the thicker second electrode layer 32 avoids the cleaving line, thus preventing metal peeling during cleaving; at the same time, the thick metal direct bonding in the central region ensures sufficient eutectic area and heat dissipation efficiency, while the thin layer at the edge continues to block light leakage at the substrate edge.

[0044] Through the above-described double-layer back electrode structure, this embodiment uses a thin first electrode layer 31 covering the entire surface to ensure compatibility of the die-cutting process while eliminating or reducing light leakage. The thick second electrode layer 32 with recessed edges can effectively increase the eutectic area of ​​the package and ensure heat dissipation capacity. This effectively solves the contradiction between insufficient eutectic area of ​​the patterned electrode and die-cutting of the entire thick electrode, and improves the beam quality problem caused by light leakage from the substrate 10.

[0045] Optionally, the thickness d1 of the first electrode layer 31 and the thickness d2 of the second electrode layer 32 satisfy: 5≤d2 / d1≤20.

[0046] In practice, the d2 / d1 ratio is limited to between 5 and 20 to ensure that the second electrode layer 32 has a sufficiently large thickness advantage relative to the first electrode layer 31. When the ratio is less than 5, the first electrode layer 31 is relatively too thick, increasing the risk of metal extension and tearing during the dicing process. At the same time, the second electrode layer 32 is relatively thin, which may lead to insufficient eutectic bonding strength or decreased wire bonding reliability. When the ratio is greater than 20, the second electrode layer 32 is too thick, increasing film stress, which may lead to electrode detachment and easily cause incomplete gold removal, leaving metal wire residue.

[0047] As an example, the thickness d1 of the first electrode layer 31 satisfies: 100 Å ≤ d1 ≤ 1000 Å. For example, 100 Å, 200 Å, 500 Å, 600 Å, 800 Å, 1000 Å, etc. By limiting the thickness d1, on the one hand, it ensures that the first electrode layer 31 forms a continuous and dense thin film, providing good conductivity and adhesion; on the other hand, the metal layer within this thickness range hardly produces perceptible stretching deformation during dicing, minimizing metal tearing problems. Simultaneously, this thickness provides an effective light-shielding effect, blocking light leaking from the substrate 10. If d1 is less than 100 Å, film continuity is difficult to guarantee; if d1 is greater than 1000 Å, metal ductility increases, and the risk of peeling during dicing rises accordingly.

[0048] As an example, the thickness d2 of the second electrode layer 32 satisfies: 2000 Å ≤ d2 ≤ 10000 Å. Examples include 2000 Å, 4000 Å, 5000 Å, 6000 Å, 8000 Å, and 10000 Å. If d2 is less than 2000 Å, the eutectic solder may penetrate the electrode layer, affecting reliability; if d2 is greater than 10000 Å, the film stress increases, material costs increase, and process efficiency decreases. Therefore, by limiting the thickness of d2, sufficient metal volume can be provided for eutectic bonding and wire bonding, ensuring adequate wetting and mechanical strength at the bonding interface, while also guaranteeing good longitudinal conductivity and lateral heat dissipation.

[0049] For further information, please refer to [link / reference]. Figure 2 , Figure 4 The minimum distance between the projected edge of the second electrode layer 32 on the second surface 10b and the projected edge of the first electrode layer 31 on the second surface 10b is L, wherein the minimum distance L satisfies: 0 < L ≤ 10 μm.

[0050] In specific implementation, L is the minimum distance between the projected edge of the second electrode layer 32 and the projected edge of the first electrode layer 31. L > 0 ensures a clear non-covered area between the second electrode layer 32 and the edge of the substrate 10, resulting in only a thin layer of the first electrode layer 31 along the dicing path. The limitation of L ≤ 10 μm maximizes the coverage area of ​​the second electrode layer 32 to maximize the eutectic bonding area. This upper limit also matches the process capabilities of conventional laser scribing or dicing, ensuring that the dicing alignment accuracy meets the requirements.

[0051] Optionally, the material of the first electrode layer 31 does not contain Au.

[0052] In practice, the first electrode layer 31 does not contain gold. This is because in processes involving localized high temperatures, such as laser scribing, gold-containing materials are prone to producing slag or spatter under laser ablation, which may contaminate the cavity surface or affect subsequent processes. By excluding the use of Au, the first electrode layer 31 can be better compatible with back scribing operations, avoid slag problems during scribing, reduce material costs, and prevent potential reactions between Au and the substrate 10 material at high temperatures.

[0053] Optionally, the material of the first electrode layer 31 includes at least one of Ti, Pt, Ni, Cr, and Al.

[0054] In specific implementations, the material of the first electrode layer 31 can be Ti, Pt, Ni, Cr, Al, or a combination thereof, such as a Ti monolayer, a Pt monolayer, or a Ti / Pt stacked structure. Ti, Ni, Cr, and Al have good adhesion to the substrate 10, which can reduce film stress and improve the bonding strength between the first electrode layer 31 and the substrate 10; Pt has excellent barrier protection, which can improve the high temperature resistance and aging resistance of the electrode structure and prevent the diffusion of outer metal to the substrate 10 in subsequent processes.

[0055] Optionally, the second electrode layer 32 includes an outermost layer located on the side furthest away from the first electrode layer 31, the outermost layer comprising Au or an alloy thereof; and the thickness of the outermost layer is greater than the thickness of any of the other layers in the second electrode layer 32.

[0056] In a specific implementation, the second electrode layer 32 is a multilayer metal structure, including an outermost layer located on the side furthest from the first electrode layer 31. This outermost layer contains Au or its alloy, such as Au or AuSn, and its thickness is greater than the thickness of any other layer in the second electrode layer 32. This outermost layer directly participates in eutectic bonding or wire bonding, and its relatively large thickness within the second electrode layer 32 provides sufficient metal volume for the bonding interface, ensuring adequate wetting of the eutectic solder and the mechanical strength of the interface. Preferably, the second electrode layer 32 also includes at least one conductive layer located between the outermost layer and the first electrode layer 31. The conductive layer can be a metal material with good adhesion to both the first electrode layer 31 and the outermost layer, and can also be a multilayer structure, including at least one layer selected from Pt, Ti, and Ni layers, to enhance interlayer bonding, provide diffusion barrier effects, and improve conductive pathways. As an example, the second electrode layer 32 can adopt a Ti / Pt / Au stacked structure, where the Au layer is the outermost layer, and the Pt and Ti layers together serve as conductive layers; or it can adopt a Ti / Ni / AuSn stacked structure, where the AuSn layer is the outermost layer, and the Ni and Ti layers together serve as conductive layers. Through the cooperation of the outermost layer and the conductive layer, the second electrode layer 32 can meet the requirements of eutectic bonding and wire bonding for Au-based materials, while utilizing the conductive layer to optimize the overall stress distribution and reliability of the electrode.

[0057] Optionally, the thickness of the outermost layer is greater than the thickness d1 of the first electrode layer 31.

[0058] In practice, the outermost layer of the second electrode layer 32 is designed to be thicker than the overall thickness of the first electrode layer 31. This is because the outermost layer needs to bear the mechanical push-pull force and thermal stress during eutectic bonding and wire bonding processes. A thicker outermost layer can provide greater material redundancy, ensuring the stability and reliability of the bonding interface during long-term use.

[0059] As an example, the thickness of the outermost layer is between 2000 angstroms and 5000 angstroms. For example, 2000 angstroms, 3000 angstroms, 4000 angstroms, 5000 angstroms, etc. By limiting the thickness of the outermost layer, the requirements for bonding layer thickness in conventional eutectic packaging and wire bonding processes can be met. If the outermost layer is less than 2000 angstroms, it may be consumed during the eutectic process, affecting bonding strength; if the outermost layer is greater than 5000 angstroms, the stress problems caused by the excessive thickness of the outermost layer may affect chip reliability and increase material costs.

[0060] Example 2 Based on Example 1, please refer to Figures 3-5The semiconductor laser element further includes a first cavity surface coating layer 51 and / or a second cavity surface coating layer 52. Specifically, the substrate 10 and the semiconductor stack 20 have cavity surfaces on opposite sides; the first cavity surface coating layer 51 includes at least a high-reflection layer, and the second cavity surface coating layer 52 includes at least an anti-reflection layer; the first cavity surface coating layer 51 and / or the second cavity surface coating layer 52 are located on the cavity surfaces.

[0061] In specific implementation, the cavity surfaces are two parallel and opposite end faces formed after cleaving along the cleavage plane, serving as the reflecting surface and emitting surface of the laser resonant cavity, respectively. A first cavity surface coating layer 51 is formed on one cavity surface, and a second cavity surface coating layer 52 is formed on the other cavity surface. The cavity surface coating layers can be single-sided or double-sided as required. When the semiconductor stack 20 has a protruding ridge on the side facing away from the substrate 10, the ridge extends between the two cavity surfaces. Preferably, an ohmic contact layer 70 is provided on the ridge to make ohmic contact with the front electrode layer 40. The material of the ohmic contact layer 70 includes, but is not limited to, ITO, ZnO, IZO, Ga2O3, etc.

[0062] The first cavity surface coating layer 51 includes at least a high reflectivity coating (HR), and the second cavity surface coating layer 52 includes at least an antireflection coating (AR). The high reflectivity coating primarily reflects light within the laser element to form effective optical feedback, maintain laser oscillation, effectively increase the light intensity within the cavity, and improve output power. The antireflection coating primarily reduces surface reflection at the laser output end face, effectively reducing mode competition and power loss within the laser, increasing the laser's output power, and also protecting the end face from contamination and physical damage. As an example, the materials of the high reflectivity coating include, but are not limited to, Ag, Au, Al, or other semiconductor materials such as GaAs, AlAs, etc., and can be multilayer or single-layer structures. The materials of the antireflection coating include, but are not limited to, silicon dioxide, titanium dioxide, silicon nitride, magnesium fluoride, etc. In this embodiment, the high reflectivity coating is preferably a multi-period structure containing aluminum oxide and tantalum oxide, and the antireflection coating is a single-period structure containing aluminum nitride and aluminum oxide. Of course, the first cavity surface coating layer 51 and the second cavity surface coating layer 52 may also include functional layer structures such as a confinement layer, a contact layer, a protective layer, and a wavelength selection layer. The specific design is based on actual needs, and this embodiment is not limited thereto.

[0063] Optionally, the first cavity surface coating layer 51 and / or the second cavity surface coating layer 52 extend from the cavity surface to the sidewall of the first electrode layer 31.

[0064] In specific implementation, during the cavity surface coating process, the coating material not only covers the cavity surface but also extends along the edge of the cavity surface to cover the exposed surface of the first electrode layer 31 at the sidewall of the substrate 10. Since the first electrode layer 31 is relatively thin and covers the entire surface, the sidewall area covered by the cavity surface coating layer can further enhance the protection of the edge of the substrate 10, especially protecting the substrate 10 area at the bottom of the cavity surface from mechanical damage and environmental corrosion.

[0065] Optionally, the first cavity surface coating layer 51 and / or the second cavity surface coating layer 52 do not contact the second electrode layer 32.

[0066] In practice, when the cavity surface coating layer extends to cover the sidewall of the first electrode layer 31, its coverage area does not contact the second electrode layer 32. Therefore, the upper surface and sidewalls of the second electrode layer 32 maintain a clean metal surface, uncontaminated by the coating medium. This is particularly important for subsequent eutectic bonding, as it does not affect the eutectic bonding, effectively reduces the eutectic void ratio, improves the uniformity and reliability of the bonding interface, and ensures packaging quality.

[0067] Example 3 This application also provides a light emitting device, which includes at least one semiconductor laser element as described in any of the above embodiments, which can effectively improve the light emission performance and can be applied to light emitting devices using semiconductor laser elements in various industries.

[0068] In summary, the semiconductor laser device provided in this embodiment introduces a double-layer back electrode structure composed of a first electrode layer and a second electrode layer. The thinner, full-surface-covering first electrode layer ensures compatibility with the dicing process, avoids metal tearing and peeling, and utilizes its light-shielding effect to suppress substrate leakage and improve stray light at the bottom of the cavity surface on the light-emitting side. The thicker, recessed second electrode layer ensures sufficient eutectic bonding area and heat dissipation capacity. Simultaneously, the design of the cavity surface coating layer not contacting the second electrode layer improves the eutectic void ratio. This structure effectively solves the heat dissipation and reliability bottlenecks caused by patterned back electrodes, improving beam quality while balancing dicing yield and packaging reliability, thus enhancing the overall operational stability and long-term reliability of the semiconductor laser device.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor laser element, characterized in that, include: Substrate, the substrate having opposing first and second surfaces; A semiconductor stack is disposed on the first surface; A back electrode layer is disposed on the second surface; The back electrode layer includes a first electrode layer and a second electrode layer; the first electrode layer is located between the second electrode layer and the substrate; the first electrode layer completely covers the second surface of the substrate; the projected edge of the second electrode layer on the second surface is within the range of the projected edge of the first electrode layer on the second surface, and there is a minimum distance L between the projected edge of the second electrode layer on the second surface and the projected edge of the first electrode layer on the second surface; the thickness d1 of the first electrode layer is less than the thickness d2 of the second electrode layer.

2. The semiconductor laser element according to claim 1, characterized in that: 5≤d2 / d1≤20.

3. The semiconductor laser element according to claim 1, characterized in that: 100 angstroms ≤ d1 ≤ 1000 angstroms.

4. The semiconductor laser element according to claim 1, characterized in that: 2000 angstroms ≤ d2 ≤ 10000 angstroms.

5. The semiconductor laser element according to claim 1, characterized in that: 0 < L ≤ 10 μm.

6. The semiconductor laser element according to claim 1, characterized in that: The material of the first electrode layer does not contain Au.

7. The semiconductor laser element according to claim 1, characterized in that: The material of the first electrode layer includes at least one of Ti, Pt, Ni, Cr, and Al.

8. The semiconductor laser element according to claim 1, characterized in that: The second electrode layer includes an outermost layer located on the side furthest away from the first electrode layer, the outermost layer comprising Au or an alloy thereof; and the thickness of the outermost layer is greater than the thickness of any of the other layers in the second electrode layer.

9. The semiconductor laser element according to claim 8, characterized in that: The thickness of the outermost layer is greater than the thickness d1 of the first electrode layer.

10. The semiconductor laser element according to claim 8, characterized in that: The thickness of the outermost layer is between 2000 angstroms and 5000 angstroms.

11. The semiconductor laser element according to claim 1, characterized in that: The substrate and the semiconductor stack have cavity surfaces on opposite sides; the semiconductor laser element further includes a first cavity surface coating layer and / or a second cavity surface coating layer; the first cavity surface coating layer includes at least a high reflectivity layer, and the second cavity surface coating layer includes at least an antireflection layer; the first cavity surface coating layer and / or the second cavity surface coating layer are located on the cavity surface.

12. The semiconductor laser element according to claim 11, characterized in that: The first cavity surface coating layer and / or the second cavity surface coating layer extend from the cavity surface to the sidewall of the first electrode layer.

13. The semiconductor laser element according to claim 11, characterized in that: The first cavity surface coating layer and / or the second cavity surface coating layer do not contact the second electrode layer.

14. The semiconductor laser element according to claim 1, characterized in that: The semiconductor stack is a GaN-based semiconductor material, and the substrate is a GaN substrate.

15. A light emitting device, characterized in that: Includes a semiconductor laser element as described in any one of claims 1 to 14.

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