A compensation circuit

Abstract

The embodiment of the application provides a compensation circuit, and the embodiment of the application inputs the currents input by a first current generation circuit, a second current generation circuit and a third current generation circuit to a first current mirror through a current analog multiplier, and then outputs a compensation current to a positive input end of a comparator through the first current mirror, so that the voltage of the positive input end of the comparator also changes with the change of the inductor current, thereby realizing that the overcurrent protection threshold is fixed and unchanged, and the problem that in the prior art, the output current needs to be increased to trigger overcurrent protection when the inductor current ripple is small is solved.

Description

Technical Field

[0001] This application relates to the field of overcurrent protection circuit technology, and in particular to a compensation circuit. Background Technology

[0002] Figure 1 This is a circuit diagram for a buck converter, where Q1 and Q2 are switches, L is an inductor, VIN is the input signal, VOUT is the output signal, CVIN and COUT are the voltage regulating capacitors for VIN and VOUT respectively, and Rload is the load equivalent resistance of the output VOUT.

[0003] Figure 2 This is a waveform diagram of the main signals during the operation of the buck converter, combined with... Figure 1 and Figure 2 Describe the working process of the buck converter: When switch Q1 is on, switch Q2 is off. The voltage on the left side of the inductor is VIN, and the voltage on the right side is approximately VOUT (the on-resistance of Q1 / Q2 is very small and can be ignored). At this time, the inductor current charges, such as... Figure 2 As shown, when the inductor current rises and the SW voltage approaches VIN, this stage is called Ton. When switch Q1 is open and switch Q2 is open, the left side of the inductor is 0, and the right side becomes VOUT. At this time, the inductor current discharges, the inductor current decreases, and the SW voltage approaches 0. This stage is called Toff. By continuously switching between Ton and Toff, the input energy is converted into the output energy, realizing the voltage conversion function. During the Ton stage, when the inductor current rises to the current limit value, Q1 needs to be turned off to prevent damage to the protection device; this is overcurrent protection.

[0004] Figure 3 This is a circuit with overcurrent protection, consisting of a reference current generation circuit, an inductor current sampling circuit, and a comparator. Rsns is the sampling resistor, meaning the resistance values ​​at the positive and negative input terminals of the comparator are the same. Kcs is the sampling gain at the negative terminal of the comparator, Kref is the sampling gain at the positive terminal of the comparator, and Iocp_th is the overcurrent protection threshold.

[0005] The comparator's positive input voltage Vref,

[0006] Vref=Ibias*Kref*Rsns EQ[1]

[0007] The comparator's negative input voltage Vsns,

[0008] Vsns=Ipeak*Kcs*Rsns EQ[2]

[0009] When the inductor current rises to a certain threshold, Vsns = Vref, the comparator output Q1_OCP goes high, Q1 is disconnected, and Ton ends. At this time, the peak inductor current is the overcurrent protection threshold, as shown in Formula 3:

[0010] Ibias*Kref=Iocp_th*Kcs EQ[3]

[0011]

[0012] As shown in equations 1, 2, 3, 4, and 5, Vsns is the input voltage at the negative terminal of the comparator, which is related to VIN and VOUT; Ibias is the bias current, and Ts is... Figure 2 In the period, the voltage Vref at the positive input terminal of the comparator is a fixed reference voltage. In order to ensure that the maximum output capability is met in all cases, the overcurrent protection threshold Iocp_th needs to be designed according to the peak value of the maximum inductor current. However, this will cause the output current to rise before triggering the overcurrent protection when the inductor current ripple is small. Summary of the Invention

[0013] To solve or alleviate the technical problems existing in the prior art, this application provides an optimization method that compensates the change in inductor current for the voltage Vref at the positive input terminal of the comparator, so that Vref also changes with the change in inductor current ripple, thereby achieving a fixed overcurrent protection threshold.

[0014] This application provides a compensation circuit, characterized in that it includes: a first current mirror, a current analog multiplier, a first current generating circuit, a second current generating circuit, and a third current generating circuit.

[0015] The output terminal of the current analog multiplier is connected to the input terminal of the first current mirror, and the input terminal of the current analog multiplier is connected to the output terminals of the first current generating circuit, the second current generating circuit, and the third current generating circuit.

[0016] The output terminal of the first current mirror is connected to the positive input terminal of the comparator. The positive input terminal of the comparator receives the bias current, and the negative input terminal of the comparator receives the inductor current value.

[0017] The positive input terminal of the comparator is also connected to a first sampling circuit, and the negative input terminal of the comparator is also connected to a second sampling circuit.

[0018] As a preferred embodiment of this application, the first current generating circuit includes: a first resistor, a second resistor, a third resistor, a first NMOS transistor, and a second current mirror;

[0019] The common terminal between the first resistor and the second resistor is connected to the gate of the first NMOS transistor, and the source of the first NMOS transistor is connected to one end of the third resistor.

[0020] The resistance values ​​of the first resistor and the second resistor are equal;

[0021] The drain of the first NMOS transistor is connected to the input terminal of the second current mirror, and the output terminal of the second current mirror is connected to the input terminal of the current analog multiplier.

[0022] The end of the first resistor furthest from the second resistor is connected to the voltage output terminal, and the end of the second resistor furthest from the first resistor and the end of the third resistor furthest from the source of the first NMOS transistor are both grounded;

[0023] Among them, the first NMOS transistor is a power dissipation transistor.

[0024] In a preferred embodiment of this application, the second current generating circuit includes: a fourth resistor, a fifth resistor, a sixth resistor, a second NMOS transistor, and a third current mirror;

[0025] The common terminal between the fourth and fifth resistors is connected to the gate of the second NMOS transistor, and the source of the second NMOS transistor is connected to one end of the sixth resistor.

[0026] The resistance values ​​of the fourth resistor and the fifth resistor are equal;

[0027] The drain of the second NMOS transistor is connected to the input terminal of the third current mirror, and the output terminal of the third current mirror is connected to the input terminal of the current analog multiplier.

[0028] The end of the fourth resistor furthest from the fifth resistor is connected to the voltage output terminal, and the end of the fifth resistor furthest from the fourth resistor and the end of the sixth resistor furthest from the source of the second NMOS transistor are both grounded.

[0029] Among them, the second NMOS transistor is a power dissipator.

[0030] As a preferred embodiment of this application, the third current generating circuit includes a seventh resistor, an eighth resistor, a ninth resistor, a third NMOS transistor, a fourth current mirror, a tenth resistor, an eleventh resistor, a first PMOS transistor, and a current source.

[0031] The common terminal between the seventh and eighth resistors is connected to the gate of the third NMOS transistor, and the source of the third NMOS transistor is connected to one end of the ninth resistor.

[0032] The seventh and eighth resistors have the same resistance value, and the tenth and eleventh resistors have the same resistance value.

[0033] The drain of the third NMOS transistor is connected to the input terminal of the fourth current mirror, and the output terminal of the fourth current mirror is connected to the input terminal of the current analog multiplier.

[0034] The common terminal between the tenth and eleventh resistors is connected to the gate of the first PMOS transistor, and the source of the first PMOS transistor is connected to the other end of the ninth resistor.

[0035] The end of the seventh resistor furthest from the eighth resistor is connected to the voltage input terminal, the end of the tenth resistor furthest from the eleventh resistor is connected to the voltage output terminal, and the ends of the eighth resistor furthest from the seventh resistor, the ends of the eleventh resistor furthest from the tenth resistor, and the drain of the first PMOS transistor are all grounded.

[0036] The current source is connected to the output terminal of the fourth current mirror;

[0037] Among them, the third NMOS transistor is a power dissipation transistor.

[0038] Compared with the prior art, the embodiments of this application provide a compensation circuit. The embodiments of this application process the currents input from the first current generation circuit, the second current generation circuit, and the third current generation circuit through a current analog multiplier, and then input them into the first current mirror. The compensation current is then output to the positive input terminal of the comparator through the first current mirror, so that the voltage at the positive input terminal of the comparator also changes with the inductor current. This achieves a fixed overcurrent protection threshold and solves the problem in the prior art that the output current needs to increase to trigger overcurrent protection when the inductor current is small. Attached Figure Description

[0039] Non-limiting and non-exhaustive embodiments of the invention are described by way of example with reference to the following figures, wherein:

[0040] Figure 1 This is a circuit diagram of a buck converter in the prior art;

[0041] Figure 2 for Figure 1 Waveforms of the main signals during the operation of the buck converter;

[0042] Figure 3 This is a circuit diagram with overcurrent protection function in the existing technology;

[0043] Figure 4 A compensation circuit provided in this application embodiment is applied to Figure 3 The circuit diagram shown in the circuit diagram;

[0044] Figure 5 A circuit diagram of a compensation circuit provided in an embodiment of this application;

[0045] Figure 6 A circuit diagram of the first current generating circuit provided in the embodiments of this application;

[0046] Figure 7 A circuit diagram of the second current generating circuit provided in the embodiments of this application;

[0047] Figure 8 A circuit diagram of the third current generating circuit provided in an embodiment of this application. Detailed Implementation

[0048] To make the above and other features and advantages of the present invention clearer, the invention will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explanation to those skilled in the art and are exemplary only, not restrictive.

[0049] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0051] In the embodiments of this application, such as Figure 4 As shown, this application embodiment provides a compensation circuit that converts the current generated by the compensation circuit (which is...) Figure 1 The change in inductor current is compensated to the positive input of the comparator, so that the voltage at the positive input of the comparator changes with the change in inductor current, thereby keeping the overcurrent protection threshold constant.

[0052] like Figure 5As shown, this application embodiment provides a compensation circuit, including: a first current mirror 2, a current analog multiplier 1, a first current generating circuit, a second current generating circuit, and a third current generating circuit; wherein, the first current generating circuit, the second current generating circuit, and the third current generating circuit are used to generate the input current of the current analog multiplier 1; the current at the output terminal of the current analog multiplier 1 is copied to the output terminal of the first current mirror 2 through the first current mirror 2, and then compensated to the positive input terminal of the comparator;

[0053] The output terminal of the current analog multiplier 1 is connected to the input terminal of the first current mirror 2, and the input terminal of the current analog multiplier 1 is connected to the output terminals of the first current generating circuit, the second current generating circuit, and the third current generating circuit.

[0054] The output terminal of the first current mirror 2 is connected to the positive input terminal of the comparator. A bias current is input to the positive input terminal of the comparator, and an inductor current value is input to the negative input terminal of the comparator. The inductor current value is as follows: Figure 2 The peak inductor current Ipeak.

[0055] The positive input terminal of the comparator is also connected to a first sampling circuit, and the negative input terminal of the comparator is also connected to a second sampling circuit. Both the first and second sampling circuits are resistors. After the current bias Ibias at the positive input terminal of the comparator increases, it is multiplied by the resistance value of the first sampling circuit to obtain the input voltage Vref at the positive input terminal of the comparator. When the positive input terminal of the comparator is compensated by the compensation current generated by the compensation circuit provided in this application embodiment, the voltage at the positive input terminal of the comparator is Vref_Vvar.

[0056] After the current Ipeak at the negative input terminal of the comparator increases, it is multiplied by the resistance value of the second sampling circuit to obtain the input voltage Vsns at the negative input terminal of the comparator.

[0057] like Figure 6 As shown, the first current generating circuit includes: a first resistor R11, a second resistor R12, a third resistor R13, a first N MOS transistor, and a second current mirror 3;

[0058] The common terminal between the first resistor R11 and the second resistor R12 is connected to the gate of the first NMOS transistor MN11, and the source of the first NMOS transistor MN11 is connected to one end of the third resistor R13.

[0059] The resistance values ​​of the first resistor R11 and the second resistor R12 are equal;

[0060] The drain of the first NMOS transistor MN11 is connected to the input terminal of the second current mirror 3, and the output terminal of the second current mirror 3 is connected to the input terminal of the current analog multiplier 1.

[0061] The end of the first resistor R11 furthest from the second resistor R12 is connected to the voltage output terminal, and the end of the second resistor R12 furthest from the first resistor R11 and the end of the third resistor R13 furthest from the source of the first NMOS transistor MN11 are both grounded.

[0062] Among them, the first NMOS transistor MN11 is a power dissipator.

[0063] It should be noted that the voltage at the voltage output terminal is divided by the voltage divider effect of the first resistor R11 and the second resistor R12 to obtain the voltage VOUT_0p5. Then, after the voltage flows into the first NMOS transistor MN11, the current obtained through the third resistor R13 passes through the first current mirror 2 to obtain the current I1. Therefore, the current I1 is related to the voltage output terminal, that is, I1 = VOUT_0p5 / R13.

[0064] like Figure 7 As shown, the second current generating circuit includes: a fourth resistor R21, a fifth resistor R22, a sixth resistor R23, a second NMOS transistor MN22, and a third current mirror 4;

[0065] The common terminal between the fourth resistor R21 and the fifth resistor R22 is connected to the gate of the second NMOS transistor MN22, and the source of the second NMOS transistor MN22 is connected to one end of the sixth resistor R23.

[0066] The resistance values ​​of the fourth resistor R21 and the fifth resistor R22 are equal;

[0067] The drain of the second NMOS transistor MN22 is connected to the input terminal of the third current mirror 4, and the output terminal of the third current mirror 4 is connected to the input terminal of the current analog multiplier 1.

[0068] The end of the fourth resistor R21 that is away from the fifth resistor R22 is connected to the voltage output terminal, and the end of the fifth resistor R22 that is away from the fourth resistor R21 and the end of the sixth resistor R23 that is away from the source of the second NMOS transistor MN22 are both grounded.

[0069] Among them, the second NMOS transistor MN22 is a power dissipator.

[0070] It should be noted that the voltage at the input terminal is divided by the voltage divider effect of the fourth resistor R21 and the fifth resistor R22 to obtain the voltage VIN_0p5. Then, the voltage flows into the second NMOS transistor MN22, and the current obtained through the sixth resistor R23 is obtained through the second current mirror 3 to obtain the current I2. Therefore, the current I2 is related to the voltage input terminal, that is, I2 = VIN_0p5 / R23.

[0071] like Figure 8 As shown, the third current generating circuit includes: a seventh resistor R31, an eighth resistor R32, a ninth resistor R33, a third NMOS transistor MN33, a fourth current mirror 5, a tenth resistor R34, an eleventh resistor R35, a first PMOS transistor MP0, and a current source IC3.

[0072] The common terminal between the seventh resistor R31 and the eighth resistor R32 is connected to the gate of the third NMOS transistor MN33, and the source of the third NMOS transistor MN33 is connected to one end of the ninth resistor R33.

[0073] The resistance values ​​of the seventh resistor R31 and the eighth resistor R32 are equal, and the resistance values ​​of the tenth resistor R34 and the eleventh resistor R35 are equal.

[0074] The drain of the third NMOS transistor MN33 is connected to the input terminal of the fourth current mirror 5, and the output terminal of the fourth current mirror 5 is connected to the input terminal of the current analog multiplier 1.

[0075] The common terminal between the tenth resistor R34 and the eleventh resistor R35 is connected to the gate of the first PMOS transistor MP0, and the source of the first PMOS transistor MP0 is connected to the other end of the ninth resistor R33.

[0076] The end of the seventh resistor R31 away from the eighth resistor R32 is connected to the voltage input terminal, the end of the tenth resistor R34 away from the eleventh resistor R35 is connected to the voltage output terminal, and the ends of the eighth resistor R32 away from the seventh resistor R31, the ends of the eleventh resistor R35 away from the tenth resistor R34, and the drain of the first PMOS transistor MP0 are all grounded.

[0077] The current source IC3 is connected to the output terminal of the fourth current mirror 5;

[0078] Among them, the third NMOS transistor MN33 is a power dissipation transistor.

[0079] It should be noted that the voltage at the input terminal is divided by the voltage divider effect of the seventh resistor R31 and the eighth resistor R32 to obtain the voltage VIN_0p5, which then flows into the third NMOS transistor MN33. The voltage at the output terminal is divided by the voltage divider effect of the tenth resistor R34 and the eleventh resistor R35 to obtain the voltage VOUT_0p5, which then flows into the first PMOS transistor MP0. The current in the circuit containing the ninth resistor R33 is (VIN_0p5 - VOUT_0p5 - VthMP0) / R33, where VthMP0 is the threshold voltage of the first PMOS transistor MP0. Because the first PMOS transistor MP0 has a threshold voltage, the current generated by the third current generation circuit needs to be compensated by the current source IC3. Therefore, the current I3 is related to the voltage input and output terminals, that is, the current I3 is (VIN_0p5 - VOUT_0p5) / R33.

[0080] In this embodiment, the currents I1, I2, and I3 generated by the first current generating circuit, the second current generating circuit, and the third current generating circuit are input into the current analog multiplier 1. After processing, current I4 is input into the first current mirror 2. The current I4 outputs a compensation current Ivar after passing through the first current mirror 2. The compensation current Ivar is input to the positive input terminal Vref of the comparator, so that Vref also changes with the inductor current, thereby achieving a fixed overcurrent protection threshold.

[0081] like Figure 6 , Figure 7 and Figure 8 As shown, the first, second, and third current generation circuits are used to generate the current of the input current model multiplier. The first NMOS transistor MN11, the second NMOS transistor MN22, and the third NMOS transistor MN33 are all power dissipators. The first NMOS transistor is an LVT PMOS transistor, where LVT is an abbreviation for Low Threshold Voltage and PMOS is an abbreviation for P-type Metal-Oxide-Semiconductor.

[0082] The current analog multiplier 1 in this embodiment can multiply currents I1, I2 and I3 to obtain current I4. The calculation formula of I4 is shown in formula

[12] , and the specific calculation is as follows:

[0083]

[0084] Where I1 is the current generated by the first current generating circuit, I2 is the current generated by the second current generating circuit, I3 is the current generated by the third current generating circuit, n1 is the number of Q1 / Q4, n2 is the number of Q2 / Q3, IS0 is the reverse saturation region current of the PN junction, VBE1 is the base voltage of Q1 / Q2, VBE3 is the base voltage of Q3 / Q4, VT is the thermal voltage, and VN is the emitter voltage of Q2 / Q3 (MN1 leakage voltage).

[0085] exist Figure 5 In this process, the current I4 obtained from the current simulation multiplier 1 is input to the first current mirror 2 to obtain the compensation current Ivar. Specifically:

[0086]

[0087] Where Ivar is the compensation current generated by the supplementary circuit, iload is the load current, R33 is the resistance of the ninth resistor R33, R23 is the resistance of the sixth resistor R23, R13 is the resistance of the third resistor R13, Lind is the inductance of inductor L, and deltaIL is the change in inductor current. According to formula 4 in the background art, deltaIL = .

[0088] As can be seen from formulas 18 and 19, after the compensation circuit compensates the positive input terminal of the comparator, both the current Iref_var and the comparator switching current Iocp_th after compensation contain the inductor current variable deltaIL. In this embodiment, the overcurrent protection threshold is kept constant by compensating the change in inductor current deltaIL at the positive input terminal of the comparator through the compensation circuit. That is, as long as formula 20 is satisfied, the overcurrent protection threshold Iocp_th is only related to the DC current.

[0089] The technical features of the above implementation schemes can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above implementation schemes are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] Although the invention has been described in conjunction with embodiments, those skilled in the art will understand that the above description and drawings are exemplary and not restrictive, and the invention is not limited to the disclosed embodiments. Various modifications and variations are possible without departing from the spirit of the invention.

Claims

1. A compensation circuit, characterized in that, include: The circuit consists of a first current mirror, a current analog multiplier, a first current generating circuit, a second current generating circuit, and a third current generating circuit. The output terminal of the current analog multiplier is connected to the input terminal of the first current mirror, and the input terminal of the current analog multiplier is connected to the output terminals of the first current generating circuit, the second current generating circuit, and the third current generating circuit. The output terminal of the first current mirror is connected to the positive input terminal of the comparator. The positive input terminal of the comparator receives the bias current, and the negative input terminal of the comparator receives the inductor current value. The positive input terminal of the comparator is also connected to a first sampling circuit, and the negative input terminal of the comparator is also connected to a second sampling circuit.

2. The compensation circuit as described in claim 1, characterized in that, The first current generating circuit includes: a first resistor, a second resistor, a third resistor, a first N MOS transistor, and a second current mirror; The common terminal between the first resistor and the second resistor is connected to the gate of the first NMOS transistor, and the source of the first NMOS transistor is connected to one end of the third resistor. The resistance values ​​of the first resistor and the second resistor are equal; The drain of the first NMOS transistor is connected to the input terminal of the second current mirror, and the output terminal of the second current mirror is connected to the input terminal of the current analog multiplier. The end of the first resistor furthest from the second resistor is connected to the voltage output terminal, and the end of the second resistor furthest from the first resistor and the end of the third resistor furthest from the source of the first NMOS transistor are both grounded; Among them, the first NMOS transistor is a power dissipation transistor.

3. The compensation circuit as described in claim 1, characterized in that, The second current generating circuit includes: a fourth resistor, a fifth resistor, a sixth resistor, a second NMOS transistor, and a third current mirror; The common terminal between the fourth and fifth resistors is connected to the gate of the second NMOS transistor, and the source of the second NMOS transistor is connected to one end of the sixth resistor. The resistance values ​​of the fourth resistor and the fifth resistor are equal; The drain of the second NMOS transistor is connected to the input terminal of the third current mirror, and the output terminal of the third current mirror is connected to the input terminal of the current analog multiplier. The end of the fourth resistor furthest from the fifth resistor is connected to the voltage output terminal, and the end of the fifth resistor furthest from the fourth resistor and the end of the sixth resistor furthest from the source of the second NMOS transistor are both grounded. Among them, the second NMOS transistor is a power dissipator.

4. The compensation circuit as described in claim 3, characterized in that, The third current generating circuit includes a seventh resistor, an eighth resistor, a ninth resistor, a third NMOS transistor, a fourth current mirror, a tenth resistor, an eleventh resistor, a first PMOS transistor, and a current source. The common terminal between the seventh and eighth resistors is connected to the gate of the third NMOS transistor, and the source of the third NMOS transistor is connected to one end of the ninth resistor. The seventh and eighth resistors have the same resistance value, and the tenth and eleventh resistors have the same resistance value. The drain of the third NMOS transistor is connected to the input terminal of the fourth current mirror, and the output terminal of the fourth current mirror is connected to the input terminal of the current analog multiplier. The common terminal between the tenth and eleventh resistors is connected to the gate of the first PMOS transistor, and the source of the first PMOS transistor is connected to the other end of the ninth resistor. The end of the seventh resistor furthest from the eighth resistor is connected to the voltage input terminal, the end of the tenth resistor furthest from the eleventh resistor is connected to the voltage output terminal, and the ends of the eighth resistor furthest from the seventh resistor, the ends of the eleventh resistor furthest from the tenth resistor, and the drain of the first PMOS transistor are all grounded. The current source is connected to the output terminal of the fourth current mirror; Among them, the third NMOS transistor is a power dissipation transistor.

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