A surge current suppression method based on current feedback and impedance switching

Abstract

The application discloses an impulse current suppression method based on current feedback and impedance switching, belongs to the field of power electronic protection and AC power impulse current suppression, and aims at solving the problems of bidirectional impulse current generated by random input of single-phase AC load in operation, difficulty of repeated response of traditional current limiting measures, and power switch leakage source overvoltage caused by inductive shutdown. The application realizes the technical effects of repeated current limiting in operation, controlled normal power-on loss and limited single-tube leakage source voltage stress by bidirectional current isolation sampling, direction hysteresis over-limit comparison, hardware retriggerable hold and window release, control of back-to-back power MOSFET switching between bypass fixed current limiting impedance and shutdown string into fixed current limiting impedance, and acceptance of shutdown peak energy by a discrete absorption branch.

Description

Technical Field

[0001] This invention relates to the field of power electronic protection and AC power supply inrush current suppression, and particularly to an inrush current suppression method based on current feedback and impedance switching. Background Technology

[0002] In single-phase AC power supply systems, transformers, motors, rectifier filter input stages, and large-capacity capacitor loads may experience inrush currents when connected to the power supply or restarted during operation, due to flux linkage establishment, phase conditions, or charging of energy storage components. Existing solutions often employ negative temperature coefficient thermistors, series inductors, or power-on soft-start circuits to limit inrush currents.

[0003] Negative temperature coefficient thermistors experience a rise in temperature and a decrease in resistance after the first operation, making it difficult to maintain the same current-limiting capability when the load is briefly disconnected and then reconnected; series inductors increase the normal operating voltage drop and may cause magnetic saturation under high current; soft-start circuits based on power-on delay typically only respond to the initial power-on process and are difficult to identify positive or negative instantaneous over-limits that occur at any time during system operation.

[0004] Using back-to-back power MOSFETs with current-limiting impedances can reduce normal conduction losses. However, when inductive loads or parasitic line inductance are present, the switching of the power MOSFET from on to off will release stored energy and create a voltage spike across the drain and source of a single power MOSFET. If directional feedback, hold-release logic, and corresponding spike absorption paths are lacking, the bypass branch may recover prematurely before the surge ends or repeatedly switch near the threshold.

[0005] Therefore, there is a need for an inrush current suppression method based on current feedback and impedance switching that can overcome the shortcomings of the existing technology. Summary of the Invention

[0006] One objective of this invention is to propose an inrush current suppression method based on current feedback and impedance switching. Addressing the limitations of existing technologies in continuously and repeatedly limiting current in response to random positive and negative impacts during single-phase AC system operation, and the difficulty in balancing normal power loss and power switch turn-off voltage stress, this invention proposes a bidirectional bypass bridging the fixed current-limiting impedance in series with a fixed current-limiting impedance connected to the single-phase AC power supply circuit. Positive and negative current characteristics are used for directional threshold comparison. Upon impact triggering, the bypass is shut off, allowing the load current to flow through the fixed current-limiting impedance. The bypass is restored after the release condition is met. Furthermore, the invention improves control and protection stability through isolated sampling, re-triggerable holding, window release, and single-tube absorption branches in the subordinate implementation. This invention achieves the technical advantages of repeatable bidirectional impact detection during operation, continuous current limiting with a fixed impedance when limits are exceeded, restoration of the bypass after the release condition is met, and separate absorption of peak energy.

[0007] This invention provides an inrush current suppression method based on current feedback and impedance switching, applicable to single-phase AC power supply circuits, comprising:

[0008] S1. A fixed current-limiting impedance is connected in series in the single-phase AC power supply circuit, and a bidirectional bypass branch is provided across the fixed current-limiting impedance. The bidirectional bypass branch includes a first power switching device and a second power switching device connected back to back.

[0009] S2. Collect the bidirectional instantaneous current flowing through the load and generate positive current characterization and negative current characterization.

[0010] S3. Compare the positive current characterization and the negative current characterization with the corresponding trigger thresholds respectively, and generate an impact trigger signal when either current characterization reaches the corresponding trigger threshold.

[0011] S4. Drive the two power switching devices to conduct to bypass the fixed current limiting impedance, and turn off the two power switching devices when the impulse trigger signal is generated, so that the load current passes through the fixed current limiting impedance.

[0012] S5. After the two power switching devices are turned off, they remain in the off state. When the impulse trigger signal is generated again during the off period, the off state is maintained. When the preset release condition is met, the two power switching devices are turned on again. Steps S4 and S5 are repeated when the impulse trigger signal is generated again thereafter.

[0013] Optionally, S1 includes: determining the impedance value and pulse withstand capability of the fixed current limiting impedance based on the peak value of the AC power supply, the target current limiting current, the impedance of the load in the connected state, and the pulse energy during the turn-off of the two power switching devices.

[0014] Both the first power switching device and the second power switching device are power MOSFETs. The sources of the two power MOSFETs are connected together and their body diodes are in opposite directions.

[0015] The two ends of the bidirectional bypass branch are respectively connected to the two ends of the fixed current limiting impedance, so that the bypass branch impedance when the two power MOSFETs are turned on at the same time is less than the fixed current limiting impedance, and the load current when the two power MOSFETs are turned off at the same time flows through the fixed current limiting impedance.

[0016] Optionally, S2 includes: acquiring the bidirectional instantaneous current using a current sampling element connected in series in the single-phase AC power supply circuit;

[0017] The sampling signal output by the current sampling element is converted into a bipolar voltage signal centered on the control side reference by an isolation differential amplifier;

[0018] The switching noise in the bipolar voltage signal is attenuated by a low-pass filter;

[0019] Based on the offset direction and offset magnitude of the filtered bipolar voltage signal relative to the control side reference, the positive current characterization quantity and the negative current characterization quantity are formed respectively, and the two current characterization quantities are sent to the corresponding hysteresis comparison channels respectively.

[0020] Optionally, S3 includes: setting the trigger threshold and a release threshold that is less than the trigger threshold in the same direction for the positive hysteresis comparison channel and the negative hysteresis comparison channel, respectively;

[0021] The threshold conversion parameter is composed of the target impact current value in the corresponding direction, the conversion coefficient of the current sampling element, and the isolation differential amplification gain. Each trigger threshold is determined according to the threshold conversion parameter, and each release threshold is determined according to the feedback ratio of the corresponding hysteresis comparison channel.

[0022] Adjust the thresholds of the two hysteresis comparison channels separately to compensate for the deviation between the positive and negative signal chains;

[0023] Furthermore, it also includes: merging the over-limit outputs of the positive hysteresis comparison channel and the negative hysteresis comparison channel through hardware logic circuitry, and generating the impulse trigger signal when any over-limit output is valid;

[0024] The module is configured to be retriggered to hold and release a window. The module includes a latch unit set by the impact trigger signal, a shortest hold timing unit started by the latch unit and restarted by a subsequent impact trigger signal, and a window confirmation unit for generating a bypass permission signal. The module also generates a shutdown control signal based on the state of the latch unit.

[0025] Optionally, S4 includes: both the first power switching device and the second power switching device are power MOSFETs;

[0026] The enable terminal of the isolation gate driver is controlled by the shutdown control signal;

[0027] When the shutdown control signal is valid, the isolated gate driver synchronously outputs a negative shutdown voltage to the gate and source terminals of the two power MOSFETs.

[0028] When the bypass signal is active, the isolated gate driver synchronously outputs a forward conduction voltage to the gate and source terminals of the two power MOSFETs.

[0029] The control priority of the shutdown control signal is higher than that of the bypass permission signal. When both signals are active at the same time, the isolation gate driver maintains the negative shutdown voltage.

[0030] An interlocking switching interval is set between the forward turn-on voltage and the negative turn-off voltage to keep the two power MOSFETs in a synchronized switching state;

[0031] Furthermore, it also includes: an absorption branch consisting of a resistor and a capacitor connected in series is provided in parallel between the drain and source of each power MOSFET;

[0032] The capacitance value of the corresponding absorption branch is determined based on the energy released by the inductive load and the parasitic inductance of the line when the two power MOSFETs are turned off, as well as the drain-source breakdown voltage of each power MOSFET. The resistance value of the corresponding absorption branch is determined based on the peak voltage decay time and the allowable peak current, so that each absorption branch limits the drain-source voltage of the power MOSFET connected in parallel.

[0033] Furthermore, the control-side supply voltage, output-side supply voltage, and gate-source voltage of the two power MOSFETs of the isolated gate driver are detected;

[0034] When any supply voltage is less than the corresponding undervoltage lockout threshold, the switching states corresponding to the two gate-source voltages are inconsistent, or the difference in the timing of the two power MOSFETs performing the same switching state transition is greater than the preset synchronization tolerance, it is determined to be an abnormal state and the output of the allow bypass signal is prohibited, so that the two power MOSFETs remain off and the fixed current limiting impedance remains connected in series with the single-phase AC power supply circuit.

[0035] Optionally, S5 includes: disabling the bypass enable signal output during the latch unit set period;

[0036] The impact trigger signal is detected during the timing of the shortest hold timer unit, and the shortest hold timer unit is restarted when the impact trigger signal is detected.

[0037] After the shortest holding time expires, the window confirmation unit detects whether both current indicators are within their respective release thresholds, and after maintaining the preset confirmation time in this state, resets the latch unit and generates the bypass permission signal.

[0038] If any current characterization quantity is detected to reach the corresponding trigger threshold before the preset confirmation time expires, the current window confirmation is cancelled, the bypass permission signal is prohibited from being output, and the shortest hold time unit is restarted.

[0039] Furthermore, a zero-crossover detection circuit is set up, and after the window confirmation unit generates the bypass permission signal, the zero-crossover detection circuit is used to detect the absolute value of the current and the absolute value of the voltage of the single-phase AC power supply circuit.

[0040] A zero-current crossing window signal is generated when the absolute value of the current is less than a preset zero current threshold, or a zero-voltage crossing window signal is generated when the absolute value of the voltage is less than a preset zero voltage threshold;

[0041] The bypass enable signal is transmitted to the isolated gate driver for driving the first power switch and the second power switch only when either crossover window signal is valid, so that the first power switch and the second power switch are turned on synchronously.

[0042] The beneficial effects of this invention are:

[0043] 1. By comparing the positive and negative current characteristics separately and generating impulse trigger signals, the instantaneous impulses in both positive and negative AC directions can enter the same hardware control chain, avoiding actions that only target the moment of power-on or a single current direction.

[0044] 2. By using the re-triggerable holding and window release module, the current limiting state is maintained when the limit is exceeded again, and the back-to-back power MOSFETs are turned on after the release condition is met. This allows the infeed time of the fixed current limiting impedance to cover the continuous process of the impact series, while reducing premature recovery and repeated switching near the threshold.

[0045] 3. By setting absorption branches at both ends of the drain and source of each power MOSFET, the peak energy released by the inductive load and the parasitic inductance of the line when the bypass branch is turned off has a corresponding receiving path, thereby limiting the drain and source voltage of a single power MOSFET, and reducing the voltage drop caused by the fixed current limiting impedance by the conduction bypass during normal operation. Attached Figure Description

[0046] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0047] Figure 1 This is a control flowchart of the inrush current suppression method based on current feedback and impedance switching according to the present invention.

[0048] Figure 2 This is a control flowchart for the re-triggerable retention and window release in S5 of the present invention. Detailed Implementation

[0049] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0050] refer to Figures 1-2A method for suppressing inrush current based on current feedback and impedance switching, comprising:

[0051] S1. A fixed current-limiting impedance is connected in series in the single-phase AC power supply circuit, and a bidirectional bypass branch is provided across the fixed current-limiting impedance. The bidirectional bypass branch includes a first power switching device and a second power switching device connected back to back.

[0052] S2. Collect the bidirectional instantaneous current flowing through the load and generate positive current characterization and negative current characterization.

[0053] S3. Compare the positive current characterization and the negative current characterization with their respective trigger thresholds, and generate an impact trigger signal when either current characterization reaches the corresponding trigger threshold.

[0054] S4. Drive the two power switching devices to conduct to bypass the fixed current limiting impedance, and turn off the two power switching devices when the impulse trigger signal is generated, so that the load current passes through the fixed current limiting impedance.

[0055] S5. After the two power switching devices are turned off, they remain in the off state. When the impulse trigger signal is generated again during the off period, the off state is maintained. When the preset release condition is met, the two power switching devices are turned on again. Steps S4 and S5 are repeated when the impulse trigger signal is generated again thereafter.

[0056] In this specific embodiment, S1 includes:

[0057] This specific implementation takes a single-phase AC power supply circuit with a rated frequency of 50Hz and a rated voltage of 220V as the object. A fixed current-limiting impedance is connected in series between the AC power supply and the load, and a bidirectional bypass branch is connected in parallel across the fixed current-limiting impedance. The controller establishes a current-limiting configuration record for each connection process. The record fields include AC power peak value, target current-limiting current, load connection complex impedance envelope, fixed current-limiting impedance value, pulse energy rating, bypass conduction impedance upper limit, load phase category, and configuration version number. Subsequent sampling, comparison, and drive circuits all read the same configuration version.

[0058] In this specific embodiment, the peak value of the AC power supply is obtained by multiplying the rated effective value by the square root of 2, and is verified by sampling the peak value of voltage over five consecutive power frequency cycles. The complex impedance envelope of the load connection is obtained by the cold connection test of the load. During the test, steady-state voltage, current and phase difference between the two are simultaneously collected at three low-voltage points of 10%, 20% and 30% of the rated voltage. The real and imaginary parts of the impedance at each measurement point are calculated respectively, and the real and imaginary parts after the measurement error expansion are combined and written into the operating condition set. When the sampling is invalid, the phase cannot be reliably obtained or the impedance is lower than the measurement resolution, the operating condition is added to the set as the most unfavorable case with no load impedance contribution where both the real and imaginary parts are 0.

[0059] For each operating condition in the set of operating conditions, the controller follows... Calculate the total series impedance and select the appropriate impedance that satisfies the requirements for each operating condition. The minimum standard resistor specification; Indicates the first The total series impedance under each operating condition is expressed in Ω. This represents the operating condition index, and its values ​​cover all operating conditions in the rate limiting configuration record. This represents the equivalent resistance value of the fixed current-limiting impedance, expressed in Ω, and implemented using a non-inductive resistor. Indicates the first The real part of the load impedance under each operating condition, in Ω; Indicates the first The imaginary part of the load impedance under each operating condition, in Ω; Represents the imaginary unit; Indicates the first The magnitude of the total complex series impedance under each operating condition, in Ω; This represents the peak value of the AC power supply, in volts (V), and is sourced from current limiting configuration records. The peak value of the target current limiting current is expressed in amperes (A). It is derived from the minimum of the load's allowable inrush current and the rated current of the power supply circuit, and must be greater than 0. If any operating condition does not meet the inequality, the standard resistor specification is selected upwards until all operating conditions are met or the load configuration is marked as inapplicable due to steady-state voltage drop constraints.

[0060] The fixed current-limiting impedance is implemented using a non-inductive wire-wound pulse resistor group, with each resistor distributing voltage and pulse energy according to a series-parallel relationship. In this specific embodiment, the assessment period after each shutdown is set to 40ms, and the controller calculates based on the load current collected at 2μs intervals during this period. ; This represents the pulse energy absorbed by the fixed current-limiting impedance during a single test period, expressed in J, and originates from the accumulation of discrete energy. This represents the number of sampling points during the assessment period. It is a dimensionless positive integer and is obtained by dividing 40ms by the sampling period. Indicates the first The load current at each sampling point is expressed in amperes (A), and the source is the current sampling chain of S2. Indicates the sampling point index, with a value ranging from 1 to... ; The equivalent resistance component of the fixed current-limiting impedance is expressed in Ω and is derived from device data and four-wire method measurements. The sampling period is expressed in seconds (s), and in this specific implementation, it is 2 μs.

[0061] The rated energy of a single pulse of the resistor group is not less than 1.5 times the aforementioned calculated energy, and the accumulated heat during repeated triggering during the shortest holding period is checked; the temperature sensor is attached to the center of the resistor group, and is configured to record and save the 80℃ alarm temperature and the 100℃ lockout temperature. When the alarm temperature is reached, bypass restoration is prohibited. When the lockout temperature is reached, the two power switching devices are kept off and the output is in an over-temperature state; when the resistor group temperature is below 70℃ for 10 seconds and there is no new impact trigger signal, the alarm blocking is released. The lockout state must be released by the maintenance reset command after power-off inspection, so that the pulse withstand capability selection result participates in the release judgment of S5;

[0062] Both the first and second power switching devices use N-channel power MOSFETs with a drain-source withstand voltage of not less than 650V. The sources of the two power MOSFETs are connected together, and the drains are respectively connected to the two ends of the bidirectional bypass branch, so that the two body diodes are in opposite directions. The gate of each MOSFET is connected to the two synchronous output channels of the same isolated gate driver through an independent gate resistor. The source connection point serves as a common detection reference for the two gate-source voltages.

[0063] The two ends of the bidirectional bypass branch are respectively connected to the two ends of the fixed current limiting impedance. The equivalent bypass impedance in the conducting state consists of the on-resistance of the two MOSFETs, the copper foil resistance, and the connector contact resistance. Four-wire method test is performed at two temperature points of 25℃ and 100℃, and the maximum test value is taken as the bypass on-resistance. Only when this impedance is less than 5% of the fixed current limiting impedance is the configuration record marked as ready to be put into operation, so as to ensure that the load current mainly flows through the bidirectional bypass branch when both are conducting.

[0064] When both power MOSFETs are turned off simultaneously, at least one of the body diodes in opposite directions is in reverse cutoff state, and the bidirectional bypass branch is thus cut off for both the positive and negative half-cycles of AC, and the load current is redirected through the fixed current limiting impedance; if the drain-source leakage current of any device exceeds the upper limit specified in the device data at the rated bus peak, or if the difference in static leakage current between the two devices exceeds 20%, the controller will record the configuration as faulty and prohibit the bypass from being engaged.

[0065] The fixed current-limiting impedance, current sampling element, and bidirectional bypass branch are arranged in order from the power supply side to the load side. The high-voltage circuit and the control side adopt electrical clearance and creepage distance that meet the working voltage requirements. The power circuits of the two MOSFETs adopt symmetrical copper busbars to control the parasitic inductance difference between the two commutation circuits. The Kelvin lead of the current sampling element is returned separately to the isolation differential amplifier to avoid the voltage drop of the power circuit entering the sampling signal of S2.

[0066] When the set of operating conditions includes the most unfavorable operating condition where both the real and imaginary parts are 0, the controller starts by selecting a standard resistor specification that is not less than the peak AC power divided by the target current limiting current and re-performs all operating condition checks. When the selected standard resistor causes the steady-state voltage of the load to be lower than 90% of the rated value, the load configuration is marked as unsuitable and kept in bypass disabled state, without circumventing the complex impedance check or pulse energy requirement by reducing the resistance.

[0067] After completing the verification of impedance value, pulse capability, MOSFET connection relationship and bypass impedance, the controller writes the current limiting configuration record into the non-volatile memory and transmits the fixed current limiting impedance value, target current limiting current, sampling conversion coefficient reference identifier and configuration version number to S2 and S3. If the record check code is incorrect, the pulse energy rating is insufficient or the bypass impedance verification fails when powered on, the bypass permission signal will not be generated, and the fixed current limiting impedance will be continuously connected in series with the single-phase AC power supply circuit.

[0068] In this specific embodiment, S2 includes:

[0069] S2 reads the current limiting configuration record written by S1 and uses a low-inductance shunt connected in series in the single-phase AC power supply circuit as the current sampling element. The rated current of the shunt covers twice the peak value of the target current limiting current. The four-terminal sampling terminal is connected to the input terminal of the isolation differential amplifier, and the power terminal is connected in series to the load circuit. Thus, the same physical sampling reference is used for the load current in the positive and negative half-cycles of AC.

[0070] The shunt converts the bidirectional instantaneous current into a differential sampling voltage, and the conversion relationship is as follows: ; Indicates time The differential sampling voltage, in V, originates from the four sampling terminals of the shunt. This represents continuous time, measured in seconds, and covers the current power frequency cycle. The conversion factor of the current sampling element is expressed in V / A and is derived from the nominal resistance of the shunt and the calibration results of the four-wire method. Indicates time The bidirectional instantaneous current flowing through the load, measured in amperes (A). Positive values ​​correspond to the conventional direction from the power source to the load, while negative values ​​correspond to the opposite direction.

[0071] The isolation differential amplifier transforms the differential sampling voltage with a 2.5V control-side reference as the center, and the output satisfies... ; This represents the bipolar voltage signal output by the isolation differential amplifier, measured in volts (V). This represents the control-side reference voltage, in volts (V). In this specific embodiment, it is 2.5V and is provided by a precision reference source. This represents the isolation differential amplifier gain, which is a dimensionless positive number and originates from the amplifier gain resistor network. Indicates time The differential sampling voltage, in V, is derived from the shunt conversion relationship and its complete explanation mentioned in this step. This represents continuous time, measured in seconds, and covers the current power frequency cycle. This represents the offset voltage referred to the output terminal when the input current of the signal chain is zero. The unit is V, and the source is the power-on zero current calibration.

[0072] Zero-current calibration is performed with both power MOSFETs off and no load connected. The controller continuously collects 2048 amplifier output samples, removes 1% outliers before and after, and takes the average as the offset voltage. If the absolute value of the offset voltage exceeds 30mV, the sampling chain is considered abnormal and the bypass is blocked. If it does not exceed 30mV, the offset voltage and calibration temperature are written into the sampling calibration record. Zero-current calibration is performed again every time the temperature changes by 20°C.

[0073] The output of the isolation differential amplifier is connected to a second-order passive low-pass filter. In this specific embodiment, the cutoff frequency is set to 20kHz, so that the leading edge of the 50Hz power frequency current and inrush current is in the passband, while attenuating the high-frequency switching noise generated by the isolation drive and MOSFET commutation. Each stage of the filter uses 1% precision resistors and 5% precision capacitors, and the same filter network is used in both directions to avoid different group delays in the positive and negative directions.

[0074] The controller monitors the filtered bipolar voltage signal with a 2μs sampling period and uses... Digital deburring is performed on the monitoring data; Indicates the first The filtered voltage at each sampling point is expressed in V. This represents the filtered voltage at the previous sampling point, in units of V; Indicates the first The amplifier output voltage at each sampling point is expressed in volts (V). The filter weight is a dimensionless number between 0 and 1, and in this specific embodiment, it is calibrated to 0.35 through a 20kHz analog filter step test. This represents the sampling point index, which is a non-negative integer; the first valid amplifier output sample is written upon power-on, completion of zero-current calibration, or calibration version switch. Later Starting from 0, recursively calculate This indicates the initial filter voltage for recursion, in V; recursion is not started if calibration fails or the first sample is invalid, and the two current characterization quantities are sent to S3 in an over-limit state;

[0075] Based on the offset direction of the filter voltage relative to the sum of the control-side reference and offset voltage, generate and ; Indicates the first The positive current characterization of each sampling point, in V and not less than 0; Indicates the first The negative current characterization of each sampling point, in units of V and not less than 0; This function returns the upper bounds of the two voltage values ​​within the parentheses. Indicates the first The filtered voltage at each sampling point is in V, and its source is the digital deburring formula and its complete explanation mentioned above in this step. This represents the control-side reference voltage, in volts (V), derived from the amplifier transformation formula and its complete explanation mentioned earlier in this step. This represents the signal chain output offset voltage, in volts (V), derived from the amplifier transformation formula and its complete explanation mentioned earlier in this step. The sampling point index is a non-negative integer; the two parameters correspond to the positive and negative amplitudes of the bidirectional instantaneous current, respectively.

[0076] The analog hardware path does not wait for the controller's sampling results. The filtered bipolar voltage signal is simultaneously sent to the positive amplitude extraction circuit and the negative amplitude extraction circuit. The two extraction circuits form an analog voltage consistent with the two aforementioned characterization quantities using the same control-side reference and calibration offset. When the filtered voltage exceeds the effective range of 0.1V to 4.9V, the sampling chain generates a saturation flag and directly requests S3 to set the impulse latch to avoid amplifier saturation causing missed triggering.

[0077] The 2048 samples for zero-current calibration are first sorted by voltage amplitude from smallest to largest. The first and last 20 samples in the sorting and the samples with a deviation from the median value of more than 15mV are filtered out. Then, the mean of the remaining samples is calculated. When two samples have the same amplitude and are in parallel, they are retained according to the sampling time. If the number of retained samples is less than 90% of the total, the calibration is considered to be interfered with, the calibration result is discarded, and S4 is kept off. Thus, the sample selection, parallel processing, and failure branch are all determined by fixed rules.

[0078] To verify the consistency of amplitude in the positive and negative directions, the calibration current source is injected with 10%, 50%, and 90% of the target current limiting current, respectively. The controller compares the positive current characterization with the negative current characterization at each injection level. When the amplitude difference at the same level exceeds 2% of the theoretical characterization of that level, the gain adjustment codes of the positive amplitude extraction circuit and the negative amplitude extraction circuit are corrected respectively. If the correction is still unqualified, the inconsistency fault is written and bypass is prohibited.

[0079] The first 100μs of data after filter startup or calibration version switching is marked as setup data. Setup data still enters the hardware comparison channel but is not written to the steady-state statistics field. When the difference between the digital filtering result and the analog amplitude extraction result exceeds 25mV for five consecutive sampling points, the sampling chain consistency fault is set and the two characterization quantities are sent to S3 in an over-limit state to avoid the protection being deactivated when the digital monitoring path and the analog protection path are inconsistent.

[0080] The cyclic sampling buffer uses 4096 fixed-length records. Each record stores a timestamp, positive current characterization, negative current characterization, filter voltage, saturation flag, establishment period flag, and calibration version. When the buffer is full, the earliest record that does not belong to the 2ms window before and after the fault is overwritten in chronological order. The fault window record is copied to the non-volatile event area for S3 to check the trigger direction and for maintenance personnel to reproduce the impact.

[0081] S2 connects the positive current characterization and the negative current characterization to the positive hysteresis comparison channel and the negative hysteresis comparison channel, respectively, and writes the two characterizations, saturation flag, offset calibration version and timestamp of each 2μs sampling point into the cyclic sampling buffer; the two current characterizations and their calibration versions are used as direct inputs to S3. S3 receives the two characterizations in real time from the analog comparison input terminal and reads the same version sampling calibration record to determine the comparison threshold, thus maintaining the continuous traceability relationship of current direction, amplitude and calibration parameters.

[0082] In this specific embodiment, S3 includes:

[0083] S3 receives the positive and negative current characteristics generated by S2 and sets independent hysteresis comparison channels for the two directions respectively; the threshold configuration record includes the positive target impact current, the negative target impact current, the current sampling conversion coefficient, the isolation differential amplification gain, the positive compensation amount, the negative compensation amount, the two release ratios, and the configuration version number. The record version is consistent with the current limiting configuration version used by S1 and S2.

[0084] The positive trigger threshold and negative trigger threshold are respectively based on as well as Sure; This represents the trigger threshold for the positive hysteresis comparator channel, expressed in V. This represents the trigger threshold for the negative hysteresis comparator channel, expressed in V. This represents the positive target impact current value, in A, and is greater than 0; This represents the negative target impact current value, in A and greater than 0; This represents the positive signal chain compensation amount, in V; This represents the compensation amount for the negative signal chain, in V. and The isolation differential amplification gain and current sampling conversion coefficient defined in S2 are used respectively;

[0085] The two target inrush current values ​​are jointly determined by the allowable peak value given by the load manufacturer and the target current limiting current of S1. In this specific embodiment, the minimum value of the two is taken. The positive compensation amount and the negative compensation amount are obtained when the calibration current source is injected with 0.25 times, 0.5 times and 0.75 times the target inrush current in the positive and negative directions respectively, so that the maximum deviation between the actual flip current of the comparison channel and the calibration current does not exceed 2% of the target inrush current. The compensation amount is written into the dual-channel digital potentiometer and updated with the temperature calibration version.

[0086] The release threshold in each direction is based on set up; Indicates direction The release threshold, in V; Indicates direction The hysteresis feedback ratio is a dimensionless number between 0 and 1. In this specific embodiment, it is calibrated to 0.8 in both the positive and negative directions. Indicates direction The trigger threshold, in V; Indicates the current direction index, taking either positive or negative; therefore, the release threshold is less than the trigger threshold in the same direction, forming a clear hysteresis interval;

[0087] The positive hysteresis comparison channel outputs a positive over-limit valid when the positive current characterization is greater than or equal to the positive trigger threshold, and cancels the positive over-limit when the positive characterization drops to within the positive release threshold; the negative hysteresis comparison channel processes the negative current characterization using the same rules, and the propagation delay of both comparison channels is no greater than 1μs. After directional compensation, the thresholds are adjusted separately, and the compensation value of one direction is not used to replace the other direction.

[0088] The hardware logic circuit performs OR logic on the positive over-limit output, the negative over-limit output, and the sampling saturation flag of S2. A surge trigger signal is generated when any input is valid. To suppress single-point electromagnetic interference, the positive or negative comparison input is only confirmed by the over-limit channel for a duration of not less than 2μs. The sampling saturation flag and the gate drive fault signal do not pass through this de-glitch delay to ensure that real large surges and drive abnormalities trigger shutdown first.

[0089] The asynchronous setting of the impact trigger signal can trigger the latch unit in the holding and window release module. The latch unit's set output directly forms the shutdown control signal. The latch unit adopts the power-on set fault-safe logic. It remains set when the control side reset is not completed, the threshold configuration verification fails, or the output state of any comparator is uncertain. Therefore, S4 only receives shutdown commands when the control system is not ready.

[0090] When the latch unit changes from unset to set, the shortest hold timer unit is activated. In this specific embodiment, the shortest hold time is set to 40ms. During the timing period, each time a new impact trigger signal is detected, the timing unit clears the current count and restarts the timing from 40ms. The timing value and the last trigger timestamp are written to the hold status register so that adjacent or consecutive impacts cannot be released prematurely by accumulating old timing.

[0091] After the shortest hold time expires, the window confirmation unit enters the confirmation state, but does not cancel the shutdown control signal; the window confirmation unit reads the over-limit status of the two hysteresis comparison channels, the comparison results of the two current indicators with their respective release thresholds, the temperature status of the S1 resistor group, and the gate drive fault status of the S4. Only when all these inputs are in the allowed state will the confirmation time begin to accumulate.

[0092] In this specific embodiment, the preset confirmation time is 4ms. During the confirmation period, if the characterization quantity in any direction reaches the corresponding trigger threshold, any comparison channel exceeds the limit again, the resistor group temperature reaches the alarm temperature, or the gate drive fault is valid, the window confirmation unit immediately cancels the current accumulation and restarts the shortest hold time unit. After the confirmation time expires continuously, the window confirmation unit only generates an internal release ready flag, and the actual reset of the latch unit and the output of the bypass signal are controlled by the cross-window rule of S5.

[0093] Before the comparison channel is put into operation, the programmable voltage source is used to scan incrementally from below the release threshold to above the trigger threshold, and then scan in reverse incrementally. When the positive characterization reaches the positive trigger threshold, the positive over-limit output must be valid within 1μs. When it drops to within the positive release threshold, the positive over-limit output must be canceled. The negative channel is verified independently according to the same rules. The scan results and the threshold configuration version are written together into the comparison channel verification record.

[0094] The input states of the hardware or logic sequentially cover four combinations: positive limit only, negative limit only, positive and negative limit simultaneously, and no limit exceeded. When any limit exceeded output is valid, the impulse trigger signal is valid. When both limit exceeded outputs are invalid and the sampling saturation flag is invalid, the impulse trigger signal is invalid. If the logic feedback is inconsistent with the truth rule, the logic fault is set and the latch unit is directly kept set.

[0095] The shortest hold timer unit uses an independent clock counter, and the error of the clock source after power frequency cycle verification does not exceed 1%. When the latch unit changes from reset to set, the corresponding count value for 40ms is loaded. If a subsequent impact trigger signal occurs during the hold period, the complete count value is reloaded instead of the remaining value is accumulated. If the counter self-test fails, a release ready flag is not generated.

[0096] The status fields of the window confirmation unit include Holding, Pending Confirmation, Confirmation, and Release Ready; the action fields include Clear Holding Count, Start Confirmation Count, Cancel Confirmation, and Set Release Ready. If the two current indicators do not simultaneously enter the release threshold, the action field remains Cancel Confirmation. If both the holding timer and the confirmation timer are satisfied and there is no temperature or drive fault, the action field is updated to Set Release Ready. The status change takes effect at the base edge at the next 1μs.

[0097] S3 writes the shutdown control signal, latch state, hold timer remaining value, release ready flag, positive and negative direction trigger and release thresholds, and threshold configuration version into the impulse control state record, and sends the shutdown control signal to the isolated gate driver enable logic of S4 via a dedicated hardware line. This record serves as the direct input for S4's synchronous shutdown and S5's continuous hold and controlled release. S4 performs high-priority synchronous shutdown based on this record, and S5 reads the same state record to complete subsequent state transitions.

[0098] In this specific embodiment, S4 includes:

[0099] S4 uses two matched output channels of the same isolated gate driver to drive the first power MOSFET and the second power MOSFET respectively. The two channels share the isolation side power supply and enable logic, but each has a gate resistor, gate-source clamp and gate-source voltage feedback terminal. The driver control side receives the turn-off control signal of S3 and the bypass enable signal of S5. The default state after power-on is to output a negative turn-off voltage.

[0100] The input fields of S4 include the shutdown control signal, bypass enable signal, control side supply voltage, output side supply voltage, first gate-source voltage, second gate-source voltage, and transition timestamp. The status fields include shutdown, conduction, interlock, and fault. The action fields include output negative shutdown voltage, output positive conduction voltage, and drive disable. The drive logic selects actions based on safety priority rather than scoring results. If any input field fails, the drive disable action is executed.

[0101] When there is no initial impact and the release condition has been confirmed by S5, the isolated gate driver drives the two power switching devices to conduct to bypass the fixed current limiting impedance. After both MOSFETs reach the conduction confirmation threshold, the bypass confirmation field is set to valid. When the impulse trigger signal is generated, the two power switching devices are turned off, so that the load current passes through the fixed current limiting impedance. If any turn-off confirmation is missing, it is considered a fault and the bypass will not be restored.

[0102] The drive enable logic executes a defined priority rule: when the shutdown control signal is valid, both output channels output a negative shutdown voltage regardless of the state of the bypass signal; only when the shutdown control signal is invalid, the bypass signal is valid, and the drive fault state is invalid, do both output channels output a positive conduction voltage; all other combinations maintain a negative shutdown voltage, logically ensuring that the shutdown control signal has a higher priority than the bypass signal.

[0103] In this specific embodiment, the forward conduction voltage is set to 12V and the negative turn-off voltage is set to -5V. When the impulse trigger signal makes the turn-off control signal effective, the driver closes the source current path and opens the matching gate discharge path. The gate-source voltages of the two MOSFETs drop synchronously until they are both below the turn-off confirmation threshold of -2V. Then, they are maintained at -5V to cut off the bidirectional bypass branch and allow the load current to pass through the fixed current limiting impedance.

[0104] When switching from a negative turn-off voltage to a positive turn-on voltage or vice versa, the drive logic first turns off the current polarity output, then inserts a 2μs interlocking switching interval, and finally turns on the target polarity output. The interlocking interval is generated by an independent monostable circuit and does not depend on software delay. The switching start-up edges of the two output channels are distributed by the same flip-flop, keeping the two MOSFETs in a synchronized switching state.

[0105] Each power MOSFET has an absorption branch connected in parallel between its drain and source, consisting of a pulse resistor and a thin-film capacitor connected in series. The loop area of ​​the absorption branch is less than 10% of the area of ​​the main power commutation loop. The turn-off test is conducted under the maximum load current and the longest line configuration. The drain-source voltage, spike voltage and decay time before turn-off are recorded using a differential high voltage probe. The energy released by the inductive load and the parasitic inductance of the line is estimated by the current probe and the parasitic inductance.

[0106] According to the absorption capacitor Select; This represents the capacitance value of a single MOSFET absorption branch, expressed in F and greater than 0. This represents the inductive energy allocated to the absorption branch when the two power MOSFETs are turned off, expressed in J. The source is the measurement results of inductor current and equivalent parasitic inductance during the turn-off test. This indicates the allowable drain-source clamping voltage, in volts (V), and is taken as 80% of the MOSFET's rated drain-source withstand voltage. This indicates the drain-source voltage of the MOSFET before it is turned off, in volts (V). This configuration is only accepted if the clamping voltage is greater than the drain-source voltage before it is turned off.

[0107] Absorption resistor according to Select; This indicates the resistance value of a single absorption branch, in Ω. This indicates the allowable peak current of the absorption branch, in amperes (A), and is derived from the minimum of the pulse current ratings of the pulse resistor and capacitor. This indicates the allowable decay time of the peak voltage, in seconds (s), which is 15μs in this specific embodiment. This indicates the permissible drain-source clamping voltage, in volts (V). The capacitance value of a single MOSFET absorption branch is expressed in F. Both are derived from the preceding formula and its complete explanation in this step. When the lower limit of the resistance is greater than the upper limit and the calculation interval is empty, first reduce the capacitance within the range that still meets the lower limit of absorption energy and recalculate. If the lower limit of capacitance energy has been reached and there is still no intersection, then recalibrate by shortening the power loop, reducing the measured parasitic energy, or selecting an absorption device that allows a higher peak current. Do not simply increase the capacitance. If there is still no feasible intersection after recalibration, mark the configuration as inapplicable and keep both MOSFETs off.

[0108] After selecting the absorption parameters, ten maximum current turn-off tests are performed during the positive and negative half-cycles of AC. The test is passed only if the drain-source peak value of each MOSFET does not exceed the allowable clamping voltage, the absorption current does not exceed the allowable peak current, and the spike drops to within 110% of the voltage before turn-off within the allowable decay time. The absorption branch parameters, test waveform hash, and device batch number are written into the drive configuration record and recalibrated when the device batch or line length changes.

[0109] The health monitoring circuit of the isolated gate driver detects the control-side supply voltage, the output-side supply voltage, and the gate-source voltage of the two MOSFETs in a 10μs cycle. When the control-side supply voltage is lower than 4.5V and the output-side supply voltage is lower than 10V, the corresponding undervoltage lockout is triggered. The drive logic sets the transition state flag each time the turn-on or turn-off transition is initiated. After the first MOSFET crosses the 8V turn-on confirmation threshold or the -2V turn-off confirmation threshold, a 1μs hardware synchronization tolerance window is started. Within this tolerance window, only the transient state difference is recorded, and the inconsistency between the two switching states is not determined.

[0110] The timestamps of the two gate-source voltages crossing the same target state confirmation threshold are latched by a 100ns resolution counter; when the other MOSFET crosses the same target threshold within a 1μs hardware synchronization tolerance window, the transition state flag is cleared and synchronization is determined to be successful; if the threshold is not crossed after the tolerance window is exceeded, the two MOSFETs are in different confirmation states after the transition state ends, or any MOSFET crosses a non-target threshold in the reverse direction during the transition, the state is determined to be inconsistent and the synchronization is abnormal; any undervoltage lockout, state inconsistency, or synchronization abnormality will set the drive fault latch, the drive fault latch will prevent the bypass signal from entering the driver, and force the two output channels to maintain a negative turn-off voltage, so that the fixed current limiting impedance is kept in series with the single-phase AC power supply circuit;

[0111] The drive fault latch will not be automatically reset due to the instantaneous recovery of the supply voltage or gate-source voltage. The maintenance reset command is allowed to clear the fault only when the two supply voltages are continuously higher than their respective recovery thresholds for 100ms, both gate-source voltages are within the turn-off confirmation range, and the S3 turn-off control signal is still valid. After clearing, S5 will still complete the hold, confirmation, and crossover window judgment again, and will not directly restore the MOSFET to conduction.

[0112] When the shutdown control signal is valid, the negative shutdown action takes effect immediately in the hardware path and clears any pending conduction actions; when the bypass signal is valid but the shutdown control signal is invalid, the drive fault status and the two power supply voltages are checked first, and the interlocking state is only entered after all thresholds are met; when both signals are valid at the same time, the negative shutdown action is always selected and the priority overwrite reason is written in the status record.

[0113] If the first gate-source voltage and the second gate-source voltage still correspond to different switching states after the transition state ends, or if the first MOSFET crosses the target confirmation threshold and the other MOSFET still does not cross the same target threshold when the 1μs hardware synchronization tolerance window expires, then the drive fault latch and synchronization anomaly fields are both set; transient state differences within the tolerance window do not set the fault, and any reverse threshold crossing will immediately set the fault; the above determinations are all completed by independent combinational logic and monostable tolerance window, without waiting for controller polling, thereby directly converting steady-state inconsistency and synchronization deviation into a safety action with a fixed current-limiting impedance continuously inserted;

[0114] After shutdown, the drain-source voltage of the two MOSFETs is collected every 2μs and continuously recorded until twice the peak decay time. When either drain-source voltage exceeds the allowable clamping voltage, the current absorption branch verification is marked as a failure and both MOSFETs are kept off. When the peak value is qualified but the decay time exceeds the limit, the current absorption parameter version is prohibited from being put into use again. Maintenance personnel can only adjust the absorption capacitor or absorption resistor under the condition that the lower limit of absorption energy and the feasible range of resistance are met at the same time, and re-perform the positive and negative half-cycle shutdown test.

[0115] The power switch status record uses double buffer storage, one copy to save the current status and the other copy to save the most recent complete transition; the write fields also include control action source, interlock start time, two threshold crossing time, power supply undervoltage bit, status inconsistency bit, synchronization error bit and absorption branch check bit. S5 only reads records with valid check codes and consecutive transition sequence numbers, and keeps the switch off when the record is mismatched.

[0116] S4 writes the switching confirmation status, gate-source voltage, switching timestamp, drive fault status, and absorption branch configuration version of the two MOSFETs into the power switch status record, and feeds back the bypass turned-off status to S5; when there is no fault and a bypass permission signal is received from S5 through the crossover window, the driver synchronously outputs the forward conduction voltage according to the same interlocking rules, and S5 ends the current impulse suppression cycle after the bypass conduction is confirmed.

[0117] In this specific embodiment, S5 includes:

[0118] S5 takes the impact control state record of S3 and the power switch state record of S4 as inputs, and executes the state machine according to four states: turn-off holding, release confirmation, waiting for crossover and bypass operation. After the latch unit is set, it immediately enters the turn-off holding state and prohibits the output of the bypass signal. The turn-off action is recorded as completed only when both MOSFETs reach the turn-off confirmation threshold according to the feedback of S4. However, the turn-off command will not be revoked if no confirmation is received.

[0119] In the off-hold state, the shortest hold timer unit counts the 40ms shortest hold time with a 1μs time base and continuously detects the impulse trigger signal; each time an impulse trigger signal is detected, the count is cleared, the last trigger timestamp is updated, and the off control signal is maintained. Therefore, repeated impulses in the same or opposite direction during the off period can regain the complete shortest hold time.

[0120] After the shortest hold timer expires, the state machine enters the release confirmation state. The window confirmation unit simultaneously compares the positive current characterization with the positive release threshold and the negative current characterization with the negative release threshold. Only when both characterizations are less than their respective release thresholds, both comparison channels are within limits, the resistor group temperature alarm blocking state is invalid, and the drive fault is invalid, will the 4ms preset confirmation timer continuously increase. The temperature alarm blocking state is only cleared when the resistor group temperature is below 70°C for 10 consecutive seconds and there is no new impact trigger signal. The state record synchronously saves the current temperature, alarm latch bit, low temperature duration timer, and clearing reason. Any mismatch in any field will keep the state off.

[0121] Before the 4ms confirmation time expires, if any current characterization reaches the corresponding trigger threshold, any over-limit output or sampling saturation flag is valid, the window confirmation unit immediately cancels the current confirmation, disables the bypass signal, and restarts the 40ms minimum hold time. When the resistor group temperature reaches the alarm temperature or the drive fault is valid, the state machine remains in the off hold state and records the corresponding blocking reason, without replacing the safety condition with the expiration of the time.

[0122] After the confirmation time expires continuously, the window confirmation unit generates a release ready flag, the state machine enters the waiting crossover state and continues to keep the latch unit set; the zero crossover detection circuit simultaneously receives the load current sampling signal of S2 and the AC power supply voltage output by the isolation voltage sampler. The two sampling channels use the same 2μs time base and timestamp to avoid combining current and voltage at different times into crossover conditions.

[0123] The zero-crossover detection circuit calculates the absolute value of the load current and the absolute value of the AC power supply voltage. The preset zero current threshold is set to 2% of the peak value of the rated load current, and the preset zero voltage threshold is set to 3% of the peak value of the AC power supply. The thresholds are converted from the rated current record and the peak value of the AC power supply in S1 and written into the crossover configuration record. Both are greater than three times the peak value of the corresponding sampling chain noise to prevent noise from forming a false crossover window.

[0124] A zero-current crossover window signal is generated when the absolute value of the load current is less than the preset zero-current threshold for 20 μs consecutively. For load configurations that have been confirmed as approximately resistive through connection tests and have passed the zero-voltage conduction stress test, a zero-voltage crossover window signal is generated only when the absolute value of the AC power supply voltage is less than the preset zero-voltage threshold for 20 μs consecutively. For inductive loads or loads with unknown phases, the zero-voltage window is prohibited from being effective alone. The window is only marked as a qualified zero-voltage window when both the zero-voltage condition and the absolute value of the load current are lower than the upper limit of the current determined by the device safety conduction test. Only the zero-current window is allowed when phase classification or stress calibration has not been completed. The effective width of any window is limited to 200 μs. If conduction is not performed after the timeout, the window is canceled and the system waits for the next real crossover.

[0125] Crossover combined signal satisfies The hardware output that allows bypassing satisfies ; This represents a crossover combination signal, which is a binary logic value. This represents a zero-current crossover window signal, which is a binary logic value. This represents a qualified zero-voltage crossover window signal generated according to the load phase category and conduction stress test rules; it is a binary logic quantity. This represents the bypass enable signal transmitted to the isolated gate driver, and is a binary logic value. This indicates the release ready flag and is a binary logic value. This represents the shutdown control signal, which is a binary logic value. It represents the drive fault state and is a binary logic value. , and These represent logical AND, logical OR, and logical NOT operations, respectively. Crossover combination signals only provide a two-to-one crossover condition; the three safety conditions of release ready, shutdown invalid, and drive fault-free must still be met simultaneously.

[0126] When any crossover window signal is valid and the other allowable conditions are met simultaneously, the window confirmation unit first resets the impulse latch and then transmits the allow bypass signal to the isolated gate driver; S4 synchronously outputs forward conduction voltage to the two MOSFETs at a 2μs interlocking switching interval. Only when both gate-source voltages reach the conduction confirmation threshold and the synchronization time difference is not greater than 1μs, the state machine switches to the bypass operation state.

[0127] If an impulse trigger signal is generated again during the waiting for crossover or conduction process, the hardware or logic immediately makes the shutdown control signal valid again, and its priority overrides the bypass signal. The state machine cancels the current crossover window and release ready flag and returns to the shutdown holding state. Then, the synchronous shutdown of S4 and the shortest hold, window confirmation and crossover recovery process of S5 are repeated.

[0128] The crossover wait timer starts counting when the release ready flag is generated. In this specific embodiment, the waiting limit is 40ms. If no valid zero-current crossover window signal or a qualified zero-voltage crossover window signal generated according to the load phase category appears within the waiting limit, the state machine cancels the release ready flag, continues to maintain the two power switching devices off, and re-executes the 4ms release confirmation without directly turning on the bypass due to timeout.

[0129] When the crossover window arrives, the state machine reads the two supply voltages, two gate source voltages and fault latch status of S4 again. When the supply voltage is higher than the recovery threshold, the two gate source voltages are within the turn-off confirmation range and the fault latch is invalid, the bypass signal is allowed to be valid in the crossover window. If any condition is not met, the reason for the crossover rejection is recorded and the machine waits for the next crossover window after the condition is restored.

[0130] After the bypass signal is transmitted to the isolated gate driver, the isolated gate driver synchronously turns on the first power switch and the second power switch. The confirmation conditions for the synchronous turn-on of the first power switch and the second power switch are that the gate-source voltages of both devices are not lower than 8V, the time difference between the two turn-on confirmation edges is not greater than 1μs, and the four-wire measured bypass conduction impedance in the S1 configuration record is still less than 5% of the equivalent resistance value of the fixed current limiting impedance. The controller does not compare the actual voltage across the parallel bypass branch with the fixed current limiting impedance. If the configuration record check code is incorrect, the impedance test temperature or device batch is mismatched, or any gate condition is not met, the bypass signal is revoked and the controller returns to the off-hold state.

[0131] Each record in the state machine transition table includes the current state, input conditions, next state, output action, and rejection reason. When impulse triggering and crossover window occur at the same timestamp, impulse triggering is processed first according to priority and enters the shutdown holding state. When zero current window and zero voltage window occur at the same timestamp, they are both recorded as composite crossover, but only one synchronous turn-on command is executed to avoid repeated driving.

[0132] In bypass operation mode, the state machine continuously monitors two current characteristics, comparator over-limit output, sampling saturation flag, drive fault status, and resistor group temperature. Under normal conditions, the two power MOSFETs maintain synchronous conduction and bypass the fixed current limiting impedance. When any impulse trigger or fault occurs, the latch unit is reset and the machine enters the off-hold state. Each state transition writes the trigger direction, threshold version, last trigger time, number of hold restarts, crossover type, MOSFET synchronization result, and blocking reason into the loop event record, forming the determining input for the next repeated steps S4 and S5.

[0133] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

[0134] This invention uses bidirectional current feedback to directly drive hardware hold and impedance switching, forming a continuous control chain from sampling, over-limit judgment, bypass shutdown, fixed impedance current limiting, release recovery, and subsequent re-triggering. Thresholds are set for the positive and negative comparison channels respectively, allowing independent calibration of signal chain deviations in the two AC directions.

[0135] The re-triggerable hold and window release structure changes the recovery method that relies solely on a fixed power-on delay, enabling the turn-off current-limiting state to continue to be maintained when the impact exceeds the limit again, and the bypass is restored only after the current characteristics in both directions meet the release conditions; the discrete absorption branch provides corresponding peak energy carrying paths for both power MOSFETs, thus taking into account repetitive current limiting, normal power-on and inductive turn-off protection.

Claims

1. A method for suppressing inrush current based on current feedback and impedance switching, applied to a single-phase AC power supply circuit, characterized in that, include: S1. A fixed current-limiting impedance is connected in series in a single-phase AC power supply circuit, and a bidirectional bypass branch is set up to bridge the fixed current-limiting impedance. The bidirectional bypass branch includes a first power switching device and a second power switching device connected back to back. S2. Collect the bidirectional instantaneous current flowing through the load and generate positive current characterization and negative current characterization. S3. Compare the positive current characterization and negative current characterization with the corresponding trigger thresholds respectively, and generate an impact trigger signal when either current characterization reaches the corresponding trigger threshold. S4. Drive the two power switching devices to conduct to bypass the fixed current limiting impedance, and turn off the two power switching devices when the impulse trigger signal is generated, so that the load current passes through the fixed current limiting impedance. S5. After the two power switching devices are turned off, they remain in the off state. When an impulse trigger signal is generated again during the off period, the off state is maintained. When the preset release condition is met, the two power switching devices are turned on again. Steps S4 and S5 are repeated when an impulse trigger signal is generated again thereafter.

2. The inrush current suppression method based on current feedback and impedance switching according to claim 1, characterized in that, S1 includes: according to The impedance value and pulse withstand capability of the fixed current limiting impedance are determined by the peak AC power supply, the target current limiting current, the impedance of the load in the connected state, and the pulse energy during the turn-off of the two power switching devices. The first power switching device and the second power switching device are both power MOSFETs. The sources of the two power MOSFETs are connected together and their body diodes are in opposite directions. The two ends of the bidirectional bypass branch are respectively connected to the two ends of the fixed current limiting impedance, so that the bypass branch impedance when the two power MOSFETs are turned on at the same time is less than the fixed current limiting impedance, and the load current when the two power MOSFETs are turned off at the same time flows through the fixed current limiting impedance.

3. The inrush current suppression method based on current feedback and impedance switching according to claim 1, characterized in that, S2 includes: acquiring the bidirectional instantaneous current using a current sampling element connected in series in the single-phase AC power supply circuit; converting the sampling signal output by the current sampling element into a bipolar voltage signal centered on the control side reference using an isolation differential amplifier; attenuating the switching noise in the bipolar voltage signal using a low-pass filter; forming the positive current characterization and the negative current characterization respectively based on the offset direction and offset amplitude of the filtered bipolar voltage signal relative to the control side reference, and sending the two current characterizations into the corresponding hysteresis comparison channels respectively.

4. The inrush current suppression method based on current feedback and impedance switching according to claim 3, characterized in that, S3 includes: setting the trigger threshold and the release threshold (which is less than the trigger threshold in the same direction) for the positive hysteresis comparison channel and the negative hysteresis comparison channel respectively; constructing threshold conversion parameters based on the target impact current value in the corresponding direction, the conversion coefficient of the current sampling element, and the isolation differential amplification gain; determining each trigger threshold based on the threshold conversion parameters; determining each release threshold based on the feedback ratio of the corresponding hysteresis comparison channel; and adjusting the thresholds of the two hysteresis comparison channels respectively to compensate for the deviation between the positive signal chain and the negative signal chain.

5. The inrush current suppression method based on current feedback and impedance switching according to claim 4, characterized in that, Step S3 further includes: merging the over-limit outputs of the positive hysteresis comparison channel and the negative hysteresis comparison channel through hardware logic circuits, and generating the impulse trigger signal when any over-limit output is valid; setting a re-triggerable hold and window release module, the re-triggerable hold and window release module including a latch unit set by the impulse trigger signal, a shortest hold timing unit started by the latch unit and restarted by a subsequent impulse trigger signal, and a window confirmation unit for generating an allow bypass signal, and generating a shutdown control signal according to the state of the latch unit.

6. The inrush current suppression method based on current feedback and impedance switching according to claim 5, characterized in that, S4 includes: Both the first power switching device and the second power switching device are power MOSFETs; The enable terminal of the isolation gate driver is controlled by the shutdown control signal; When the shutdown control signal is valid, the isolated gate driver synchronously outputs a negative shutdown voltage to the gate and source terminals of the two power MOSFETs; when the bypass enable signal is valid, the isolated gate driver synchronously outputs a positive conduction voltage to the gate and source terminals of the two power MOSFETs; the shutdown control signal has a higher control priority than the bypass enable signal, and when both signals are valid, the isolated gate driver maintains the negative shutdown voltage; an interlocking switching interval is set between the positive conduction voltage and the negative shutdown voltage to keep the two power MOSFETs in a synchronous switching state.

7. The inrush current suppression method based on current feedback and impedance switching according to claim 2, characterized in that, Step S4 further includes: setting up an absorption branch consisting of a resistor and a capacitor connected in series in parallel between the drain and source of each power MOSFET; determining the capacitance value of the corresponding absorption branch based on the energy released by the inductive load and the parasitic inductance of the line when the two power MOSFETs are turned off and the drain-source withstand voltage of each power MOSFET; determining the resistance value of the corresponding absorption branch based on the peak voltage decay time and the allowable peak current, so that each absorption branch limits the drain-source voltage of the power MOSFET connected in parallel.

8. The inrush current suppression method based on current feedback and impedance switching according to claim 5, characterized in that, S5 includes: disabling the bypass enable signal output during the latch unit setting period; detecting the impulse trigger signal during the shortest hold timer period and restarting the shortest hold timer when the impulse trigger signal is detected; after the shortest hold timer expires, the window confirmation unit detects whether both current parameters are within their respective release thresholds, and after maintaining this state for the preset confirmation time, resets the latch unit and generates the bypass enable signal; if any current parameter reaches the corresponding trigger threshold before the preset confirmation time expires, cancels the current window confirmation, disables the bypass enable signal output, and restarts the shortest hold timer.

9. The inrush current suppression method based on current feedback and impedance switching according to claim 8, characterized in that, A zero-crossover detection circuit is set up, and after the window confirmation unit generates the allow bypass signal, the zero-crossover detection circuit is used to detect the absolute value of the current and the absolute value of the voltage of the single-phase AC power supply circuit; a zero-current crossover window signal is generated when the absolute value of the current is less than a preset zero current threshold, or a zero-voltage crossover window signal is generated when the absolute value of the voltage is less than a preset zero voltage threshold; the allow bypass signal is transmitted to the isolated gate driver for driving the first power switching device and the second power switching device only when either crossover window signal is valid, so that the first power switching device and the second power switching device are synchronously turned on.

10. The inrush current suppression method based on current feedback and impedance switching according to claim 6, characterized in that, The control-side supply voltage, output-side supply voltage, and gate-source voltage of the two power MOSFETs of the isolated gate driver are detected. When any supply voltage is less than the corresponding undervoltage lockout threshold, the switching states corresponding to the two gate-source voltages are inconsistent, or the difference in the timing of the two power MOSFETs performing the same switching state transition is greater than the preset synchronization tolerance, an abnormal state is determined and the output of the bypass signal is prohibited, so that the two power MOSFETs remain off and the fixed current limiting impedance remains connected in series in the single-phase AC power supply circuit.

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