ESD circuit suitable for high power supply voltage

Abstract

The application discloses an ESD circuit suitable for high power voltage and belongs to the field of integrated circuits. The application introduces an additional voltage clamping mechanism, so that the ESD clamping circuit composed of low-voltage devices can be suitable for the working condition of high power voltage.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an ESD circuit suitable for high power supply voltages. Background Technology

[0002] As semiconductor process dimensions continue to shrink and gate oxide layers become thinner, ESD (Electro-Static Discharge) poses an increasingly greater threat to semiconductor integrated circuits and devices. If a chip lacks ESD protection circuitry, an ESD event will generate a momentary high voltage and large current. If this exceeds the device's tolerance, it will damage the chip. Common ESD types include HBM (Human Body Model), MM (Machine Model), and CDM (Charged Device Model).

[0003] To ensure chip reliability and stability, a full-chip protection strategy based on power rails is typically employed. This involves introducing protective structures on the power rails to guide ESD current to ground or power supply, thereby reducing its impact on the chip's internal circuitry. Depending on the method of electrostatic discharge, these can be categorized as PS (I / O to ground), PD (I / O to power supply), NS (ground to I / O), ND (power supply to I / O), or DS (power supply to ground), SD (ground to power supply).

[0004] ESD protection standards are typically 2kV HBM. In the ESD discharge path, the most crucial component is the clamping circuit from power supply to ground. A typical ESD clamping circuit suitable for the 2kV HBM standard is as follows: Figure 1 As shown, PMOS transistor P0 and NMOS transistor N0 form an inverter. When there is no ESD event, the potential at point A is VCC, causing P0 to turn off and N0 to turn on. This makes the gate potential of N1 GND, turning off NMOS transistor N1 and preventing interference with normal circuitry. When an ESD event occurs, due to the hysteresis effect of the RC circuit, point A will temporarily remain at its original potential. When the power supply VCC potential rises to a certain value, P0 turns on, causing the potential at the inverter output point B to rise, turning on NMOS transistor N1 to discharge the ESD current.

[0005] As manufacturing processes advance, the rated operating voltage of transistors becomes increasingly lower. For chips using advanced process technologies, if they support traditional I / O levels, their I / O power supply levels are typically higher than the rated operating voltage of the transistors. Therefore, for... Figure 1The typical ESD clamping circuit shown has a fatal flaw when used in advanced process chips. During normal operation, if the power supply voltage is higher than the transistor's withstand voltage, it will cause overvoltage breakdown of drain and source in P0 and N1, and overvoltage breakdown of gate and source in N0, thus creating a low-resistance path from power supply to ground, affecting the normal operation of the circuit, and also losing the ability to protect against ESD. Summary of the Invention

[0006] The purpose of this invention is to provide an ESD protection circuit suitable for high power supply voltages, so as to solve the problems in the prior art.

[0007] To address the aforementioned technical problems, this invention provides an ESD clamping circuit suitable for high power supply voltages, such as... Figure 2 As shown, it includes a resistor divider network, two delay units, an inverter with voltage clamping, and a current discharge channel with voltage clamping. The resistor voltage divider network consists of two resistors, R1 and R2. One end of resistor R1 is connected to the power supply VCC, and one end of resistor R2 is grounded GND. The other ends of both are connected to point A, which is the output of the resistor voltage divider network. The first delay unit consists of a resistor R0 and a capacitor C0. One end of the resistor R0 is connected to VCC, and the other end is connected to the upper plate of the capacitor C0 at point B, which is the output of the first delay unit. The lower plate of the capacitor C0 is connected to the output point A of the voltage divider network. The second delay unit consists of a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the output point A of the resistor divider network, and the other end is connected to the upper plate of the capacitor C1 at point C, which is the output of the second delay unit. The lower plate of the capacitor C1 is connected to ground GND. The voltage-clamped inverter consists of two PMOS transistors and one NMOS transistor. The source of P0 is connected to the power supply VCC, and the gate of P0 is connected to the output point B of the first delay unit, which is the first input terminal of the inverter. The drain of P0 is connected to the source of P1 at point D, and the drains of P1 and N1 are connected to point E, which is the output of the inverter. The gate of N1 is connected to the output point B of the second delay unit, which is the second input terminal of the inverter. The voltage-clamped current discharge channel consists of two NMOS transistors. The drain and gate of N0 are connected to the power supply VCC and node D, respectively. The source of N0 is connected to the drain of N2. The gate and source of N2 are connected to the output point E of the inverter and ground GND, respectively.

[0008] exist Figure 2In one embodiment of the ESD clamping circuit shown, when working normally, the output voltage at point A of the voltage divider network is lower than the withstand voltage of the MOSFET but higher than the turn-on voltage of the MOSFET; point B is connected to the power supply VCC through resistor R0, so that P0 is in the off state and the drain potential of P0 is floating; point C is connected to point A through resistor R1, so that N1 is in the on state and the gate of N2 is connected to ground GND, thereby turning off the discharge channel N2 without affecting the normal operation of the circuit. The gate of P1 is connected to point A, clamping the potential at point D to prevent the drain-source voltage and gate-source voltage of P0, N0, and N1 from exceeding the withstand voltage of the MOSFET; the gate of N0 is connected to point D, clamping the drain potential of N2 so that the drain-source voltage of N2 does not exceed the withstand voltage.

[0009] exist Figure 2 In one embodiment of the ESD clamping circuit shown, when an ESD event occurs, the potential rise at points B and C lags behind that of VCC. When the potential of VCC rises to a certain value, P0 is turned on, and the power supply VCC raises the gate potential of N2 through P0 and P1, causing N2 to turn on and begin to discharge ESD current through N0 and N2.

[0010] The second type of ESD clamping circuit suitable for high power supply voltage provided by this invention, such as Figure 3 As shown, it includes a resistor divider network, a delay unit, a common source stage with voltage clamping, and a current discharge channel with voltage clamping. The resistor voltage divider network consists of two resistors, R1 and R2. One end of resistor R1 is connected to the power supply VCC, and one end of resistor R2 is grounded GND. The other ends of both are connected to point A, which is the output of the resistor voltage divider network. The delay unit consists of a resistor R0 and a capacitor C0. One end of the resistor R0 is connected to VCC, and the other end is connected to the upper plate of the capacitor C0 at point B, which is the output of the first delay unit. The lower plate of the capacitor C0 is connected to the output point A of the voltage divider network. The common-source stage with voltage clamping consists of two PMOS transistors and a load Z0. The source terminal of P0 is connected to the power supply VCC, the gate terminal of P0 is connected to the output point B of the first delay unit, the drain terminal of P0 is connected to the source terminal of P1 at point D, the drain terminal of P1 and one end of Z0 are connected to point E, which is the output of the common-source stage, and the other end of Z0 is connected to ground GND. The voltage-clamped current discharge channel consists of two NMOS transistors. The drain and gate of N0 are connected to the power supply VCC and node D, respectively. The source of N0 is connected to the drain of N2. The gate and source of N2 are connected to the output C point of the common source stage and ground GND, respectively.

[0011] exist Figure 3In one embodiment of the ESD clamping circuit shown, when working normally, the output voltage at point A of the voltage divider network is lower than the withstand voltage of the MOSFET but higher than the turn-on voltage of the MOSFET; point B is connected to the power supply VCC through resistor R0, so that P0 is in the off state and the drain potential of P0 is floating; point C is connected to point A through resistor R1, so that N1 is in the on state and the gate of N2 is connected to ground GND, thereby turning off the discharge channel N2 without affecting the normal operation of the circuit. The gate of P1 is connected to point A, clamping the potential at point D to prevent the drain-source voltage and gate-source voltage of P0, N0, and N1 from exceeding the withstand voltage of the MOSFET; the gate of N0 is connected to point D, clamping the drain potential of N2 so that the drain-source voltage of N2 does not exceed the withstand voltage.

[0012] exist Figure 3 In one embodiment of the ESD clamping circuit shown, when an ESD event occurs, the potential at point B rises lagging behind VCC. When the potential of VCC rises to a certain value, P0 and P1 are turned on. The power supply VCC raises the gate potential of N2 through P0 and P1, causing N2 to turn on and begin to discharge ESD current through N0 and N2.

[0013] This invention provides two ESD clamping circuits suitable for high power supply voltages. By introducing an additional voltage clamping mechanism, the ESD clamping circuits composed of low-voltage devices can be adapted to high power supply voltage operating conditions. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a typical ESD clamping circuit structure.

[0015] Figure 2 This is a schematic diagram of the ESD clamping circuit structure of the present invention.

[0016] Figure 3 This is a schematic diagram of the ESD clamping circuit variant circuit 1 of the present invention.

[0017] Figure 4 This is a schematic diagram of the ESD clamping circuit variant circuit 2 of the present invention.

[0018] Figure 5 This is a schematic diagram of the ESD clamping circuit variant circuit 3 of the present invention. Detailed Implementation

[0019] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of an ESD clamping circuit suitable for high power supply voltages proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0020] Figure 2 This is a circuit diagram of the present invention, including resistors R0, R1, R2, R3, capacitors C0, C1, PMOS transistors P0, P1, and NMOS transistors N0, N1, N2.

[0021] exist Figure 2 In the ESD clamping circuit shown, during normal operation, point B is connected to VCC through resistor R0, meaning the gate potential of P0 is VCC. At this time, the gate-source voltage of P0 is 0, and P0 is in the off state. The potential of its drain point D is in the floating state. The voltage divider network formed by R2 and R3 outputs a potential at point A that is greater than the turn-on level of the MOSFET but lower than the withstand voltage of the transistor. Point C is connected to point A through resistor R1, meaning the gate potential of N1 is the same as that of point A. At this time, the gate-source voltage of N1 is greater than the turn-on voltage, and N1 is in the on state. Point E is connected to ground through N1, meaning the potential of the gate of N2 and the drain of P1 is 0. At this time, the gate-source voltage difference of N2 is 0, and N2 is in the off state. The discharge channel is closed, which does not affect the normal operation of the circuit. The gate terminal of P1 is connected to point A. Since P0 is turned off, no current flows through P1. Therefore, the potential at point D will approach the potential at point A under the clamping effect of P1. Similarly, the potential at the source terminal of N0 will also approach the potential at point A under the clamping effect of the gate terminal potential of N0. At this time, the gate-source voltage, gate-drain voltage, and drain-source voltage of P0, P1, N0, N1, and N2 do not exceed the withstand voltage value, thus avoiding overvoltage breakdown of the MOS when operating at high power supply voltage.

[0022] exist Figure 2 In the ESD clamping circuit shown, when the circuit is not powered, it is assumed that no charge has accumulated at any node, i.e., the potential is 0. When an ESD event occurs, points B and C temporarily maintain a constant potential of 0 due to the RC hysteresis effect. At this time, P0, P1, N0, N1, and N2 are in the off state. When the power supply VCC potential rises above the turn-on voltage of P0, P0 turns on, and the potential at point D is charged to VCC. When the power supply VCC potential rises to the point where the voltage difference between points A and D is greater than the turn-on voltage of P1, P1 turns on. Because N1 is in the off state at this time, the potential at point E is rapidly charged to VCC, causing N2 to turn on. After N2 turns on, it pulls down the source potential of N0. When the gate-source voltage difference of N0 is greater than the turn-on voltage, the ESD current discharge path opens.

[0023] exist Figure 2In the ESD clamping circuit shown, under normal operating conditions, when an ESD event occurs, points B and C temporarily maintain their original potentials due to the hysteresis effect of the RC circuit. P0, P1, N0, and N2 are off, while N1 is on. When the power supply VCC potential rises above the turn-on voltage of P0, P0 turns on, and the potential at point D is charged to VCC. At this time, the gate-source voltage difference of P1 is the voltage across resistor R2, which is greater than the turn-on voltage of P1, so P1 also turns on. When the power supply VCC potential continues to rise, causing the charging current at point E to exceed the discharging current, the potential at point E rises, N2 turns on, and the source potential of N0 decreases, causing N0 to turn on, thus opening the ESD current discharge path.

[0024] Figure 3 This is a schematic diagram of the first variant circuit of the present invention, including resistors R0, R1, R2, R3, capacitors C0, C1, PMOS transistors P0, P1, and NMOS transistors N0, N1, N2. Its specific implementation is similar to... Figure 2 The circuit shown is consistent.

[0025] Figure 4 This is a schematic diagram of the second variant circuit of the present invention, including resistors R0, R2, R3, capacitor C0, PMOS transistors P0, P1, NMOS transistors N0, N2, and a passive resistive load Z0 (a resistor or a large-size NMOS transistor with its gate and source grounded).

[0026] exist Figure 4 In the ESD clamping circuit shown, during normal operation, point B is connected to VCC through resistor R0, meaning the gate potential of P0 is VCC. At this time, the gate-source voltage of P0 is 0, and P0 is in the off state. Its drain point D is in a floating state. The voltage divider network formed by R2 and R3 outputs a potential at point A that is lower than the transistor's withstand voltage. Point C is connected to ground potential through resistive load Z0, meaning the gate potential of N2 and the drain potential of P1 are 0. At this time, the gate-source voltage difference of N2 is 0, and N2 is in the off state. The discharge path is closed, which does not affect the normal operation of the circuit. The gate terminal of P1 is connected to point A. Since P0 is turned off, no current flows through P1. Therefore, the potential at point D will approach the potential at point A under the clamping effect of P1. Similarly, the potential at the source terminal of N0 will also approach the potential at point A under the clamping effect of the gate terminal potential of N0. At this time, the gate-source voltage, gate-drain voltage, and drain-source voltage of P0, P1, N0, N1, and N2 do not exceed the withstand voltage value, thus avoiding overvoltage breakdown of the MOS when operating at high power supply voltage.

[0027] exist Figure 4In the ESD clamping circuit shown, when the circuit is not connected to a power source, it is assumed that no charge has accumulated at any node, i.e., the potential is 0. When an ESD event occurs, point B temporarily maintains a constant potential of 0 due to the RC hysteresis effect. At this time, P0, P1, N0, and N2 are all in the off state. When the power supply VCC potential rises above the turn-on voltage of P0, P0 turns on, and the potential at point D is charged to VCC, causing N0 to turn on. When the power supply VCC potential rises to the point where the voltage difference between points A and D is greater than the turn-on voltage of P1, P1 turns on. Current flows through P0, P1, and Z0, generating a voltage drop across the resistive load, thereby raising the potential at point C. When the potential at point C rises above the turn-on voltage of N2, N2 turns on, thereby lowering the source potential of N0, causing N0 to turn on and opening the ESD current discharge path.

[0028] exist Figure 4 In the ESD clamping circuit shown, under normal operating conditions, when an ESD event occurs, point B temporarily maintains its original potential due to the hysteresis effect of the RC circuit, and P0, P1, N0, and N2 are in the off state. When the power supply VCC potential rises above the turn-on voltage of P0, P0 turns on, and the potential at point D is charged to VCC. At this time, the gate-source voltage difference of P1 is the voltage across resistor R2, which is greater than the turn-on voltage of P1, so P1 also turns on. As the power supply VCC potential continues to rise, the current flowing through P0, P1, and Z increases, the potential at point E rises, N2 turns on, and the source potential of N0 decreases, causing N0 to turn on and opening the ESD current discharge path.

[0029] Figure 5 This is a schematic diagram of the third variant circuit of the present invention, including resistors R0, R2, R3, capacitor C0, PMOS transistors P0, P1, and NMOS transistors N0, N1, N2, wherein NMOS transistor N1 serves as the active load of the common source stage.

[0030] exist Figure 5 In the ESD circuit shown, during normal operation, point B is connected to VCC through resistor R0, meaning the gate potential of P0 is VCC. At this time, the gate-source voltage difference of P0 is 0, and P0 is in the off state. The potential at its drain point D is in a floating state. The voltage divider network formed by R2 and R3 outputs a potential at point A that is lower than the transistor's withstand voltage but higher than the transistor's turn-on voltage. The gate of N1 is connected to point A, and its gate-source voltage difference is greater than the turn-on voltage, so N1 is turned on. Point C is connected to ground potential through N1, meaning the potential at the gate of N2 and the drain of P1 is 0, and N2 is in the off state. The discharge channel is closed, which does not affect the normal operation of the circuit. The gate terminal of P1 is connected to point A. Since P0 is turned off, no current flows through P1. Therefore, the potential at point D will approach the potential at point A under the clamping effect of P1. Similarly, the potential at the source terminal of N0 will also approach the potential at point A under the clamping effect of the gate terminal potential of N0. At this time, the gate-source voltage, gate-drain voltage, and drain-source voltage of P0, P1, N0, N1, and N2 do not exceed the withstand voltage value, thus avoiding overvoltage breakdown of the MOS when operating at high power supply voltage.

[0031] exist Figure 5 In the ESD clamping circuit shown, when the circuit is not powered on, it is assumed that no charge has accumulated at any node, i.e., the potential is 0. When an ESD event occurs, point B temporarily remains at 0 potential due to the hysteresis effect of the RC circuit. At this time, P0, P1, N0, N1, and N2 are in the off state. When the power supply VCC potential rises above the turn-on voltage of P0, P0 turns on, and the potential at point D is charged to VCC. When the power supply VCC potential rises to the point where the gate-source voltage difference of P1 is greater than the turn-on voltage, P1 turns on. Because the gate of N1 is connected to point A, when the power supply VCC potential rises, the potential at point A also rises. When the potential at point A rises to the turn-on voltage of N1, N1 turns on. Current flows through P0, P1, and N1. By designing the dimensions of N1, P0, and P1, when all three MOSFETs are turned on, the current of P-MOSFET is larger, thus raising the potential at point C. When the potential at point C rises above the turn-on voltage of N2, N2 turns on. After N2 is turned on, the source potential of N0 is reduced. When the gate-source voltage difference of N0 is greater than the turn-on voltage, the ESD current discharge channel is opened.

[0032] exist Figure 5 In the ESD circuit shown, under normal operating conditions, when an ESD event occurs, point B temporarily maintains its original potential due to the hysteresis effect of the RC circuit. P0, P1, N0, and N2 are in the off state, while N1 is in the on state. When the power supply VCC potential rises above the turn-on voltage of P0, P0 turns on, and the potential at point D is charged to VCC. At this time, the gate-source voltage difference of P1 is the voltage across resistor R2, which is greater than the turn-on voltage of P1, so P1 also turns on. As the power supply VCC potential continues to rise, the current flowing through P0 and P1 increases, the potential at point C rises, N1 turns on, and the source potential of N0 decreases, causing N0 to turn on and opening the ESD current discharge path.

[0033] Compared with typical ESD clamping circuits, this invention adds a resistor divider network and a voltage clamping MOSFET. By utilizing the voltage clamping mechanism, it enables the circuit to operate at power supply voltages exceeding the transistor's withstand voltage, providing a solution for ESD circuit design under high power supply voltage conditions.

[0034] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An ESD clamping circuit suitable for high power supply voltages, characterized in that, It includes a resistor divider network, two delay units, an inverter with voltage clamping, and a current discharge channel with voltage clamping. The resistor voltage divider network consists of two resistors, R1 and R2. One end of resistor R1 is connected to the power supply VCC, and one end of resistor R2 is grounded GND. The other ends of both are connected to point A, which is the output of the resistor voltage divider network. The first delay unit consists of a resistor R0 and a capacitor C0. One end of the resistor R0 is connected to VCC, and the other end is connected to the upper plate of the capacitor C0 at point B, which is the output of the first delay unit. The lower plate of the capacitor C0 is connected to the output point A of the voltage divider network. The second delay unit consists of a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the output point A of the resistor divider network, and the other end is connected to the upper plate of the capacitor C1 at point C, which is the output of the second delay unit. The lower plate of the capacitor C1 is connected to ground GND. The voltage-clamped inverter consists of two PMOS transistors P0 and P1 and one NMOS transistor N1. The source of the first PMOS transistor P0 is connected to the power supply VCC, and the gate of P0 is connected to the output point B of the first delay unit, which is the first input terminal of the inverter. The drain of P0 is connected to the source of the second PMOS transistor P1 at point D. P1 and the drain of NMOS transistor N1 are connected to point E, which is the output of the inverter. The gate of N1 is connected to the output point B of the second delay unit, which is the second input terminal of the inverter. The voltage-clamped current discharge channel consists of two NMOS transistors, N0 and N2. The drain of N0 is connected to the power supply VCC, the source of N0 is connected to the drain of N2, and the gate and source of N2 are connected to the output point E of the inverter and ground GND, respectively.

2. The ESD circuit as described in claim 1, wherein the gate terminal of the NMOS transistor N0 is connected to node D.

3. The ESD circuit as described in claim 1, wherein the gate terminal of the NMOS transistor N0 is connected to node A.

4. The ESD circuit as described in claim 1, characterized in that, During normal operation, the output voltage at point A of the voltage divider network is lower than the withstand voltage of the MOSFET but higher than the turn-on voltage of the MOSFET. Point B is connected to the power supply VCC through resistor R0, which puts P0 in the off state. At this time, the drain potential of P0 is floating. Point C is connected to point A through resistor R1, which puts N1 in the on state and connects the gate of N2 to ground GND, thereby turning off the discharge channel N2 without affecting the normal operation of the circuit. The gate of P1 is connected to point A, clamping the potential at point D to prevent the drain-source voltage and gate-source voltage of P0, N0, and N1 from exceeding the withstand voltage of the MOSFET; the gate of N0 is connected to point D, clamping the drain potential of N2 so that the drain-source voltage of N2 does not exceed the withstand voltage.

5. The ESD circuit as described in claim 4, characterized in that, When an ESD event occurs, the potential rise at points B and C lags behind that of VCC. When the potential of VCC rises to a certain value, P0 and P1 are turned on. The power supply VCC raises the gate potential of N2 through P0 and P1, causing N2 to turn on and begin to discharge the ESD current through N0 and N2.

6. An ESD clamping circuit suitable for high power supply voltages, characterized in that, It includes a resistor divider network, a delay unit, a common source stage with voltage clamping, and a current discharge channel with voltage clamping. The resistor voltage divider network consists of two resistors, R1 and R2. One end of resistor R1 is connected to the power supply VCC, and one end of resistor R2 is grounded GND. The other ends of both are connected to point A, which is the output of the resistor voltage divider network. The delay unit consists of a resistor R0 and a capacitor C0. One end of the resistor R0 is connected to VCC, and the other end is connected to the upper plate of the capacitor C0 at point B, which is the output of the first delay unit. The lower plate of the capacitor C0 is connected to the output point A of the voltage divider network. The common-source stage with voltage clamping consists of two PMOS transistors P0 and P1 and a load Z0. The source terminal of P0 is connected to the power supply VCC, the gate terminal of P0 is connected to the output point B of the first delay unit, the drain terminal of P0 is connected to the source terminal of P1 at point D, the drain terminal of P1 and one end of Z0 are connected to point E, which is the output of the common-source stage, and the other end of Z0 is connected to ground GND. The voltage-clamped current discharge channel consists of two NMOS transistors, N0 and N2. The drain and gate of N0 are connected to the power supply VCC and node D, respectively. The source of N0 is connected to the drain of N2. The gate and source of N2 are connected to the output point C of the common source stage and ground GND, respectively.

7. The ESD circuit as described in claim 6, wherein the load Z0 is composed of a resistor.

8. The ESD circuit as described in claim 6, wherein the load Z0 is composed of an NMOS transistor N1 with its gate-source grounded.

9. The ESD circuit as described in claim 6, wherein the load Z0 is composed of a biased NMOS transistor N1, and the gate bias of N1 is provided by the potential at point A.

10. The ESD circuit as described in claim 6, characterized in that, During normal operation, the output voltage at point A of the voltage divider network is lower than the withstand voltage of the MOSFET; point B is connected to the power supply VCC through resistor R0, which puts P0 in the off state, and at this time the drain potential of P0 is floating; point C is connected to ground GND through resistor R1, which makes the gate-source voltage difference of N2 zero, thereby turning off the discharge channel and not affecting the normal operation of the circuit. The gate of P1 is connected to point A, clamping the potential at point D to prevent the drain-source voltage and gate-source voltage of P0, N0, and N1 from exceeding the withstand voltage of the MOSFET; the gate of N0 is connected to point D, clamping the drain potential of N2 so that the drain-source voltage of N2 does not exceed the withstand voltage.

11. The ESD circuit as described in claim 10, characterized in that, When an ESD event occurs, the potential at point B rises lagging behind VCC. When the potential of VCC rises to a certain value, P0 and P1 are turned on. The power supply VCC raises the gate potential of N2 through P0 and P1, causing N2 to turn on and begin to discharge ESD current through N0 and N2.

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