A fast response voltage clamping protection surge protection chip circuit

Abstract

The application discloses a quick-response voltage clamping protection surge protection chip circuit, which comprises a detection / clamping circuit, a quick-response circuit, a driving circuit and a discharge circuit. The detection / clamping circuit is provided with a Zener diode string, is used for monitoring a power voltage in real time, and provides a starting signal after a trigger voltage is reached, so that the power voltage of a system is clamped to prevent overvoltage breakdown. The trigger voltage and the clamping voltage can be flexibly adjusted by adopting the structure of the Zener diode string with different numbers and connection modes. The quick-response circuit is used for quick response and signal transmission through the current amplification of three MOS tubes. The driving circuit is provided with an array of multiple triodes and multiple resistors, is used for providing sufficient driving current after receiving the working signal, and improves the response speed of the chip. The BIGFET of the discharge circuit forms a low-resistance path from the positive electrode of the power supply to the ground terminal after being turned on, so that the surge current is fully discharged.

Description

Technical Field

[0001] This invention relates to the field of circuit protection technology, specifically to a fast-response voltage clamping surge protection chip circuit, which is a technical solution for voltage clamping type fast-response protection circuit specifically designed for electrical over-stress events such as EOS / ESD. Background Technology

[0002] Currently, common methods for protecting against surges and other electrical overstress events in circuit systems mainly include passive discrete devices (such as varistors and gas discharge tubes) and RC networks. Passive discrete devices often have a single function, only capable of triggering conduction or discharging energy due to overvoltage, and their trigger voltage is usually fixed and unadjustable, making it difficult to adapt to the refined protection requirements under different circuit operating voltages. For example, while varistors have a certain surge absorption capability, their trigger voltage threshold is fixed, and their performance is prone to degradation after repeated surges; gas discharge tubes have a slow response speed (in the microsecond range), and after conduction, there is a follow current problem, which may cause secondary impacts on the system. On the other hand, although RC circuits are simple in structure and low in cost, they can only achieve current discharge or delayed conduction through the charging and discharging path of the capacitor, completely lacking voltage clamping function and unable to limit surge voltage within a safe range. More importantly, these two traditional protection methods generally have slow response speeds (usually in the microsecond or even millisecond range), making it difficult to act quickly in the early stages of nanosecond-level transient surge events. Therefore, they cannot meet the increasingly stringent protection requirements of modern highly integrated, low-voltage-tolerant electronic systems.

[0003] As the complexity of electrical and electronic systems continues to rise, the electrical interference and overvoltage problems faced by circuits are becoming increasingly severe. The need for protection against electrical overstress events such as surges (EOS) and electrostatic discharge (ESD) is also increasing significantly. Therefore, there is an urgent need in this field for a protection circuit specifically designed for electrical overstress events such as EOS / ESD and with fast response capabilities. Summary of the Invention

[0004] To effectively address circuit protection issues caused by electrical overstress events such as EOS and ESD, this invention aims to provide a fast-response voltage clamping surge protection chip circuit. It not only possesses a nanosecond (several nanoseconds) fast response capability, rapidly dissipating surge current, but also achieves stable voltage clamping. Furthermore, by employing a structure with different numbers and connection methods of Zener diode strings, the trigger voltage and clamping voltage can be easily and flexibly adjusted, achieving efficient surge protection at a lower cost. This provides efficient and reliable dual protection for the circuit system. Thanks to the fast switching characteristics of Zener diodes, the circuit response speed of this invention reaches the nanosecond level and can adapt to the system requirements of different operating voltages, significantly broadening the product's application scenarios. It can be widely used in power interfaces, signal ports, and various electronic devices.

[0005] To achieve the above objectives, the present invention provides a fast-response voltage clamping protection surge protection chip circuit, comprising:

[0006] The detection / clamping circuit includes a resistor R1, a Zener diode string, a reverse-connected diode D1 and resistor R2 connected in series across the power supply terminals of the system under test. It is used to monitor the power supply voltage in real time and provide a start signal after the trigger voltage is reached. At the same time, the detection / clamping circuit can clamp the power supply voltage of the system to prevent overvoltage breakdown.

[0007] A fast response circuit includes three MOSFETs electrically connected to the detection / clamping circuit. It receives the start signal from the detection / clamping circuit upon reaching the trigger voltage. Utilizing the current amplification of the MOSFETs, it performs a fast response and transmits the operating signal. The three MOSFETs are a first MOSFET, a second MOSFET, and a third MOSFET. The gates of all three MOSFETs are connected between the Zener diode string and diode D1. The drain of the second MOSFET is connected to the collector of transistor Q2. The base of transistor Q2 is connected between diode D1 and resistor R2. The emitter of transistor Q2 is connected to ground.

[0008] A driving circuit, including multiple transistors and multiple resistors, and electrically connected to the fast response circuit, is used to provide driving current after receiving an operating signal transmitted by the fast response circuit. The driving circuit includes:

[0009] Transistor Q1 has its base connected between diode D1 and resistor R2, its collector connected to the drain of the first MOSFET, and its emitter connected to ground.

[0010] Resistor R3 is connected in series between the source of the first MOSFET and the positive terminal of the power supply;

[0011] The base of transistor Q4 is connected between resistor R3 and the source of the first MOSFET, the emitter is connected to the positive power supply, and the collector is connected to the ground terminal through resistor R4.

[0012] The base of transistor Q3 is connected between the collector of transistor Q4 and resistor R4, the collector is connected to the drain of the third MOSFET, and the emitter is connected to ground.

[0013] Resistor R5 is connected in series between the source of the third MOSFET and the positive terminal of the power supply; and

[0014] Transistor Q5 has its base connected between resistor R5 and the source of the third MOSFET, its emitter connected to the positive power supply, and its collector connected to ground via resistor R6. The source of the second MOSFET is also connected between resistor R5 and the source of the third MOSFET.

[0015] The discharge circuit, electrically connected to the drive circuit, is used to conduct after the chip is powered on, so as to form a low-resistance path from the positive terminal of the power supply to the ground terminal, thereby discharging the surge current.

[0016] In one embodiment of the present invention, the discharge circuit includes a bipolar insulated gate field-effect transistor, whose gate is connected between the collector of transistor Q5 and resistor R6, its source is connected to the positive terminal of the power supply, and its drain is connected to the ground terminal.

[0017] In one embodiment of the present invention, a diode D2 is further included, which is reverse-connected between the gate of the bipolar insulated gate field-effect transistor and the ground terminal to prevent the gate voltage of the bipolar insulated gate field-effect transistor from being too high.

[0018] In one embodiment of the present invention, the clamping voltage value for ,in, Let R1 be the voltage drop across resistor R1. The voltage drop across the Zener diode string. The voltage drop across diode D1, Let R2 be the voltage drop across resistor R2.

[0019] In one embodiment of the present invention, the clamping voltage value is adjusted by changing the connection method and number of the Zener diode strings. Make adjustments.

[0020] In one embodiment of the present invention, the Zener diode string includes N forward Zener diodes and M reverse Zener diodes, where M and N are positive integers. The clamping voltage value is adjusted by changing the values ​​of N and M. Make adjustments.

[0021] The present invention further provides a fast-response voltage clamping protection surge protection chip circuit, comprising:

[0022] The detection / clamping circuit includes a resistor R1, a Zener diode string, a reverse-connected diode D1, and a resistor R2 connected in series across the power supply terminals of the system under test.

[0023] The driving circuit includes multiple transistors and resistors electrically connected to the detection / clamping circuit. The driving circuit includes:

[0024] Transistor Q1 has its base connected between diode D1 and resistor R2, its collector connected to the positive terminal of the power supply through resistor R3, and its emitter connected to the ground terminal.

[0025] Transistor Q4 has its base connected between resistor R3 and the collector of transistor Q1, its emitter connected to the positive terminal of the power supply, and its collector connected to the ground terminal through resistor R4.

[0026] Transistor Q3 has its base connected between the collector of transistor Q4 and resistor R4. The collector is connected to the positive terminal of the power supply via resistor R5, and the emitter is connected to ground.

[0027] Transistor Q5 has its base connected between resistor R5 and the collector of transistor Q3, its emitter connected to the positive terminal of the power supply, and its collector connected to ground via resistor R6; and

[0028] The discharge circuit is electrically connected to the driving circuit. The discharge circuit includes a bipolar insulated gate field-effect transistor, whose gate is connected between the collector of transistor Q5 and resistor R6, its source is connected to the positive terminal of the power supply, and its drain is connected to the ground terminal.

[0029] In one embodiment of the present invention, it further includes: a diode D2, which is reverse-connected between the gate of the bipolar insulated gate field-effect transistor and the ground terminal to prevent the gate voltage of the bipolar insulated gate field-effect transistor from being too large; a transistor Q2, whose base is connected between the diode D1 and the resistor R2, whose collector is connected to the base of the transistor Q4, and whose emitter is connected to the ground terminal.

[0030] In one embodiment of the present invention, the Zener diode string includes N forward Zener diodes and M reverse Zener diodes, where M and N are positive integers, and the clamping voltage value is adjusted by adjusting the values ​​of N and M.

[0031] The fast-response voltage clamping surge protection chip circuit provided by this invention, compared with the prior art, can adjust the detection / clamping voltage value over a wide range by adjusting the connection method and number of Zener diode strings, significantly improving the chip's application scenarios and protection range. The designed fast-response circuit utilizes the current amplification characteristics of transistors for rapid conduction, enabling rapid signal transmission in the circuit and increasing the chip's response speed to the nanosecond level, providing good protection against EOS / ESD events. By setting up a BIGFET discharge circuit, a low-resistance path is introduced between the power supply and ground after conduction to fully discharge surge current and avoid circuit damage. Optimized board layout design reduces area, improves efficiency, and lowers costs. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic block diagram of a circuit structure according to an embodiment of the present invention;

[0034] Figure 2 This is a circuit diagram of an embodiment of the present invention when the clamping voltage value is high;

[0035] Figure 3 This is a circuit diagram of an embodiment of the present invention when the clamping voltage value is low.

[0036] Figure labeling: 10 - Detection / clamping circuit; 20 - Fast response circuit; 30 - Drive circuit; 40 - Discharge circuit; N*Diode - Zener diode string; N1 - First MOSFET; N2 - Second MOSFET; N3 - Third MOSFET; AVDD - Positive power supply; AVSS - Ground terminal; BIGFET - Bipolar insulated gate field-effect transistor. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] Figure 1 This is a schematic block diagram of a circuit structure according to an embodiment of the present invention. Figure 2This is a circuit diagram of an embodiment of the present invention when the clamping voltage value is high, as shown below. Figures 1-2 As shown, this embodiment provides a fast-response voltage clamping protection surge protection chip circuit, which includes:

[0039] The detection / clamping circuit 10 includes a resistor R1, a Zener diode string N*Diode, a reverse-connected diode D1, and a resistor R2 connected in series across the power supply terminals (between AVDD and AVSS) of the system under test. It is used to monitor the power supply voltage in real time and provide a start signal after the trigger voltage is reached. At the same time, the detection / clamping circuit 10 can clamp the power supply voltage of the system to fix the voltage and prevent overvoltage breakdown.

[0040] The fast response circuit 20 includes multiple metal-oxide-semiconductor field-effect transistors (hereinafter referred to as MOS transistors) and is electrically connected to the detection / clamping circuit 10. It is used to receive the start signal of the detection / clamping circuit 10 after the trigger voltage is reached. It uses the current amplification effect of the MOS transistors to perform fast response and transmit the signal. This embodiment has been tested and its chip response speed is improved to the nanosecond level, which can provide good protection against EOS / ESD events.

[0041] Among them, such as Figure 2 As shown, the fast response circuit 20 includes three MOSFETs, namely the first MOSFET N1, the second MOSFET N2 and the third MOSFET N3. The gates of the three MOSFETs are all connected between the Zener diode string N*Diode and the diode D1 (node ​​A).

[0042] In this embodiment, a transistor Q2 is also included, with its base connected between diode D1 and resistor R2 (node ​​B), its collector connected to the drain of the second MOS transistor N2, and its emitter connected to the ground terminal AVSS.

[0043] The driving circuit 30 includes multiple transistors and resistors electrically connected to the fast response circuit 20. After receiving the operating signal from the fast response circuit 20, it provides sufficient drive current to turn on the subsequent BIGFET. The driving circuit 30 includes:

[0044] Transistor Q1 has its base connected between diode D1 and resistor R2 (node ​​B), its collector connected to the drain of the first MOSFET N1, and its emitter connected to the ground terminal AVSS.

[0045] Resistor R3 is connected in series between the source of the first MOSFET N1 and the positive power supply AVDD;

[0046] The base of transistor Q4 is connected between resistor R3 and the source of the first MOSFET N1 (node ​​C), the emitter is connected to the positive power supply AVDD, and the collector is connected to the ground terminal AVSS through resistor R4.

[0047] Transistor Q3 has its base connected between the collector of transistor Q4 and resistor R4 (node ​​E), its collector connected to the drain of third MOSFET N3, and its emitter connected to ground AVSS.

[0048] Resistor R5 is connected in series between the source of the third MOSFET N3 and the positive power supply AVDD; and

[0049] Transistor Q5 has its base connected between resistor R5 and the source of the third MOSFET N3 (node ​​D), its emitter connected to the positive power supply AVDD, and its collector connected to the ground terminal AVSS through resistor R6. The source of the second MOSFET N2 is also connected between resistor R5 and the source of the third MOSFET N3 (node ​​D).

[0050] The discharge circuit 40 is electrically connected to the drive circuit 30. It is used to turn on after the chip is started to form a low-resistance path from the power supply to ground, thereby discharging the surge current and protecting other modules of the chip and other circuits in the subsequent stage of the system.

[0051] In this embodiment, the discharge circuit 40 includes a bipolar insulated-gate field-effect transistor (BIGFET), whose gate is connected between the collector of transistor Q5 and resistor R6 (node ​​F), its source is connected to the positive power supply AVDD, and its drain is connected to the ground terminal AVSS.

[0052] In this embodiment, a diode D2 is also included, which is reverse-connected between the gate (node ​​F) of the bipolar insulated gate field-effect transistor (BIGFET) and the ground terminal AVSS, to prevent the gate voltage of the BIGFET from being too high.

[0053] In a preferred embodiment of the present invention, resistors R1 and R2 are current-limiting resistors to prevent excessive current in the N*Diode branch of the Zener diode from burning out before the subsequent discharge circuit 40 is turned on; diode D1 is a Zener diode to limit the gate voltages of the first MOSFET N1, the second MOSFET N2, and the third MOSFET N3 after they are turned on, preventing breakdown between the gate and source of the MOSFETs; the MOSFETs are NMOS transistors, and diode D2 is a Zener diode. In other embodiments, other similar components may be used in the circuit, and the present invention is not limited thereto.

[0054] Figure 2This illustrates that when the clamping voltage is high, due to the voltage requirements of the manufacturing process, the NPN transistor Q1 in the circuit is limited by the voltage difference between node C and node B. However, there is a risk of breakdown, necessitating the use of high-voltage NMOS transistors for voltage isolation. To clearly understand this invention, the following is combined with... Figure 2 The working process of this invention will be described in detail below:

[0055] When a surge event occurs in the circuit system, the voltage at the positive terminal AVDD of the power supply will rise rapidly in the early stage of the surge event. The chip system will not respond until it reaches the turn-on voltage of the Zener diode string N*Diode.

[0056] When the voltage at the positive terminal AVDD of the power supply exceeds the turn-on voltage of the Zener diode string N*Diode, the Zener diode string N*Diode turns on. After turning on, the voltage at node A is rapidly pulled up, that is, the gate voltages of the first MOSFET N1, the second MOSFET N2, and the third MOSFET N3 are pulled high and turned on. At the same time, the voltage drop across resistor R2... Provide sufficient bias voltage for forward bias conduction between the base and emitter of transistors Q1 and Q2;

[0057] After transistor Q2 and MOSFET N2 are turned on, they will first pull down the base voltage of transistor Q5, causing forward bias conduction between the emitter and base of transistor Q5. Resistor R5 acts as a current-limiting resistor, limiting the current after transistors Q2 and N2 are turned on. This current, after being amplified by transistor Q5, is used to charge the gate capacitance of the bipolar junction field-effect transistor (BIGFET), thereby raising the voltage at node F. At this time, the voltage at node F is... This allows the bipolar insulated-gate field-effect transistor (BIGFET) to turn on faster in the early stages of a surge event, thus achieving a fast response function. This is the collector current of transistor Q5.

[0058] After transistor Q1 and the first MOSFET N1 are turned on, they will pull down the voltage at node C, causing the emitter and base of transistor Q4 to be forward-biased and conduct. The base current of transistor Q4, after being amplified, acts on node E, pulling up the voltage at node E. At this time, the voltage at node E is... ,in This is the collector current of transistor Q4. The voltage rise at node E causes transistor Q3 to conduct forward-biased between its base and emitter. Meanwhile, MOSFET N3 was already conducting during the initial voltage rise at node A. Therefore, after transistor Q3 conducts, it, along with MOSFET N3, further pulls down the voltage at node D. At this point, the current through resistor R5 is... ,in This is the collector current of transistor Q2. This is the collector current of transistor Q3.

[0059] At this time, the base current of transistor Q5 The voltage at node F is further increased after current amplification via transistor Q5, thus driving the bipolar junction field-effect transistor (BIGFET) to fully conduct, forming a low-resistance path from power supply to ground to discharge charge. Combined with the clamping effect of the preceding Zener diode string N*Diode, this achieves complete protection for the chip circuit design. The clamping voltage value of the chip is... .in, Let R1 be the voltage drop across resistor R1. The voltage drop across the Zener diode string. The voltage drop across diode D1, Let R2 be the voltage drop across resistor R2.

[0060] Resistor R6 is also a current-limiting resistor, and is also used to boost the voltage at node F, as mentioned earlier, the voltage at node F is... To protect the gate voltage of the bipolar insulated gate field-effect transistor (BIGFET), diode D2 is provided to prevent gate-source breakdown caused by excessive gate voltage.

[0061] At the end of the surge event, the voltage on the power supply is lower than the chip design clamping value. The Zener diode string N*Diode turns off, and transistors Q1, Q2, Q3, the first MOSFET N1, the second MOSFET N2, and the third MOSFET N3 turn off. This leads to transistor Q5 turning off, and the voltage at node F is pulled down to 0V by resistor R6. The bipolar insulated gate field-effect transistor (BIGFET) turns off and stops discharging.

[0062] In one embodiment of the present invention, the detection / clamping voltage value of the chip can be adjusted over a wide range by adjusting the connection method and number of Zener diode strings N*Diodes.

[0063] Since a Zener diode is a simple PN junction when forward-biased, the voltage drop across it when forward-biased is... It has a clamping function when conducting in reverse, and the clamping voltage is If a branch circuit is configured with a Zener diode string of N*Diodes, containing N forward Zener diodes and M reverse Zener diodes, then when a surge occurs, and the voltage at the positive terminal AVDD of the power supply is higher than N*Diodes... + M* When the Zener diode string N*Diode is turned on, it will clamp the voltage at the positive terminal AVDD of the power supply. Resistors R1 and R2 in the branch are current-limiting resistors to prevent excessive current in this branch from burning out the diode. After the Zener diode string N*Diode is turned on, the current in this branch is... The actual clamping voltage value of the circuit is ;

[0064] By modifying the values ​​of the forward and reverse Zener diodes N and M at the circuit level, the clamping voltage of the circuit can be adjusted. Make the necessary modifications.

[0065] Figure 3 This is a circuit diagram of an embodiment of the present invention when the clamping voltage value is low, as shown below. Figure 3 As shown, in one embodiment of the present invention, since the clamping voltage requirement is low and there is no risk of transistor breakdown, the first MOSFET N1, the second MOSFET N2, and the third MOSFET N3 can be further reduced to decrease the chip circuit area and lower the cost. Specifically, the fast-response voltage clamping protection surge protection chip circuit of this embodiment includes:

[0066] The detection / clamping circuit includes a resistor R1 connected in series between the power supply terminals of the system under test (between AVDD and AVSS), a Zener diode series N*Diode, a reverse-connected diode D1, and a resistor R2.

[0067] The driving circuit includes multiple transistors and resistors electrically connected to the detection / clamping circuit. The driving circuit includes:

[0068] Transistor Q1 has its base connected between diode D1 and resistor R2 (node ​​A), its collector connected to the positive power supply AVDD through resistor R3, and its emitter connected to the ground terminal AVSS.

[0069] Transistor Q4 has its base connected between resistor R3 and the collector of transistor Q1 (node ​​B), its emitter connected to the positive power supply AVDD, and its collector connected to the ground terminal AVSS through resistor R4.

[0070] Transistor Q3 has its base connected between the collector of transistor Q4 and resistor R4 (node ​​C). The collector is connected to the positive power supply AVDD through resistor R5, and the emitter is connected to the ground terminal AVSS.

[0071] Transistor Q5 has its base connected between resistor R5 and the collector of transistor Q3 (node ​​D), its emitter connected to the positive power supply AVDD, and its collector connected to the ground terminal AVSS through resistor R6.

[0072] The bleeder circuit, electrically connected to the drive circuit, is used to conduct after the chip is powered on to form a low-resistance path from the power supply to ground, thereby discharging surge current and protecting other modules of the chip and other circuits in the subsequent stages of the system. The bleeder circuit includes a bipolar isolated-gate field-effect transistor (BIGFET), whose gate is connected between the collector of transistor Q5 and resistor R6 (node ​​E), the source is connected to the positive power supply AVDD, and the drain is connected to the ground terminal AVSS.

[0073] In this embodiment, a diode D2 is also included, which is reverse-connected between the gate (node ​​E) of the bipolar insulated gate field-effect transistor (BIGFET) and the ground terminal AVSS, to prevent the gate voltage of the BIGFET from being too high.

[0074] In this embodiment, a transistor Q2 is also included, with its base connected between diode D1 and resistor R2 (node ​​A), its collector connected to the base of transistor Q4 (node ​​B), and its emitter connected to ground terminal AVSS.

[0075] When a surge event occurs at the system power supply terminal, the voltage at the positive terminal AVDD of the power supply rises rapidly. Once the voltage rises to a preset detection threshold, the voltage detection / clamping circuit turns on first and transmits a start signal. The drive circuit then starts working, raising the gate voltage of the BIGFET and turning it on. After the BIGFET turns on, a stable low-impedance path is formed between the positive terminal AVDD of the power supply and the ground terminal AVSS, thereby discharging the huge surge current. Throughout the discharge process, the front-end clamping circuit always clamps the power supply voltage within a safe range, ensuring that the entire chip and subsequent circuit systems always operate at a safe voltage level, effectively preventing the subsequent circuits from burning out due to excessive surge current. When the surge event ends and the power supply voltage drops below the chip clamping voltage value, the clamping circuit turns off, and the subsequent discharge circuit turns off. In addition, the solution in this embodiment also supports a wide range of adjustment of the detection / clamping voltage value by adjusting the connection method and number of Zener diode strings, thereby significantly expanding the protection range of the chip and adapting to diverse application scenarios.

[0076] The fast-response voltage clamping surge protection chip circuit provided by this invention has at least the following beneficial effects:

[0077] 1) By using different connection methods and numbers of Zener diode strings, the detection / clamping voltage value of the chip can be adjusted over a wide range, greatly improving the application scenarios and protection range of the chip.

[0078] 2) The fast response circuit utilizes the current amplification characteristics of the transistor to enable rapid conduction and realize the rapid transmission of signals in the circuit, thereby improving the chip response speed to the nanosecond level and providing good protection against EOS / ESD events.

[0079] 3) Includes a BIGFET discharge circuit, which introduces a low-resistance path between the power supply and ground after conduction to fully discharge surge current and avoid circuit damage. By optimizing the board layout design, the area is reduced, efficiency is improved, and costs are lowered.

[0080] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of one embodiment, and the modules or processes shown in the drawings are not necessarily essential for implementing the present invention.

[0081] Those skilled in the art will understand that the modules in the apparatus of the embodiments can be distributed in the apparatus of the embodiments as described in the embodiments, or they can be located in one or more devices different from this embodiment with corresponding changes. The modules of the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fast-response voltage clamping protection surge protection chip circuit, characterized in that, include: The detection / clamping circuit includes a resistor R1, a Zener diode string, a reverse-connected diode D1 and resistor R2 connected in series across the power supply terminals of the system under test. It is used to monitor the power supply voltage in real time and provide a start signal after the trigger voltage is reached. At the same time, the detection / clamping circuit can clamp the power supply voltage of the system to prevent overvoltage breakdown. A fast response circuit includes three MOSFETs electrically connected to the detection / clamping circuit. It receives the start signal from the detection / clamping circuit upon reaching the trigger voltage. Utilizing the current amplification of the MOSFETs, it performs a fast response and transmits the operating signal. The three MOSFETs are a first MOSFET, a second MOSFET, and a third MOSFET. The gates of all three MOSFETs are connected between the Zener diode string and diode D1. The drain of the second MOSFET is connected to the collector of transistor Q2. The base of transistor Q2 is connected between diode D1 and resistor R2. The emitter of transistor Q2 is connected to ground. A driving circuit, including multiple transistors and multiple resistors, and electrically connected to the fast response circuit, is used to provide driving current after receiving an operating signal transmitted by the fast response circuit. The driving circuit includes: Transistor Q1 has its base connected between diode D1 and resistor R2, its collector connected to the drain of the first MOSFET, and its emitter connected to ground. Resistor R3 is connected in series between the source of the first MOSFET and the positive terminal of the power supply; The base of transistor Q4 is connected between resistor R3 and the source of the first MOSFET, the emitter is connected to the positive power supply, and the collector is connected to the ground terminal through resistor R4. The base of transistor Q3 is connected between the collector of transistor Q4 and resistor R4, the collector is connected to the drain of the third MOSFET, and the emitter is connected to ground. Resistor R5 is connected in series between the source of the third MOSFET and the positive terminal of the power supply; and Transistor Q5 has its base connected between resistor R5 and the source of the third MOSFET, its emitter connected to the positive power supply, and its collector connected to ground via resistor R6. The source of the second MOSFET is also connected between resistor R5 and the source of the third MOSFET. The discharge circuit, electrically connected to the drive circuit, is used to conduct after the chip is powered on, so as to form a low-resistance path from the positive terminal of the power supply to the ground terminal, thereby discharging the surge current.

2. The fast-response voltage clamping protection surge protection chip circuit according to claim 1, characterized in that, The discharge circuit includes a bipolar insulated gate field-effect transistor, whose gate is connected between the collector of transistor Q5 and resistor R6, its source is connected to the positive terminal of the power supply, and its drain is connected to the ground terminal.

3. The fast-response voltage clamping protection surge protection chip circuit according to claim 2, characterized in that, It also includes a diode D2, which is reverse-connected between the gate of the bipolar insulated gate field-effect transistor and the ground terminal to prevent the gate voltage of the bipolar insulated gate field-effect transistor from being too high.

4. The fast-response voltage clamping protection surge protection chip circuit according to claim 1, characterized in that, Clamping voltage value for ,in, Let R1 be the voltage drop across resistor R1. Let be the voltage drop across the Zener diode string. The voltage drop across diode D1, Let R2 be the voltage drop across resistor R2.

5. The fast-response voltage clamping protection surge protection chip circuit according to claim 4, characterized in that, By adjusting the connection method and number of the Zener diode strings, the clamping voltage value can be adjusted. Make adjustments.

6. The fast-response voltage clamping protection surge protection chip circuit according to claim 5, characterized in that, The Zener diode string includes N forward-biased Zener diodes and M reverse-biased Zener diodes, where M and N are positive integers. The clamping voltage is adjusted by changing the values ​​of N and M. Make adjustments.

7. A fast-response voltage clamping protection surge protection chip circuit, characterized in that, include: The detection / clamping circuit includes a resistor R1, a Zener diode string, a reverse-connected diode D1, and a resistor R2 connected in series across the power supply terminals of the system under test. The driving circuit includes multiple transistors and resistors electrically connected to the detection / clamping circuit. The driving circuit includes: Transistor Q1 has its base connected between diode D1 and resistor R2, its collector connected to the positive terminal of the power supply through resistor R3, and its emitter connected to the ground terminal. Transistor Q4 has its base connected between resistor R3 and the collector of transistor Q1, its emitter connected to the positive terminal of the power supply, and its collector connected to the ground terminal through resistor R4. Transistor Q3 has its base connected between the collector of transistor Q4 and resistor R4. The collector is connected to the positive terminal of the power supply via resistor R5, and the emitter is connected to ground. Transistor Q5 has its base connected between resistor R5 and the collector of transistor Q3, its emitter connected to the positive terminal of the power supply, and its collector connected to ground via resistor R6; and The discharge circuit is electrically connected to the driving circuit. The discharge circuit includes a bipolar insulated gate field-effect transistor, whose gate is connected between the collector of transistor Q5 and resistor R6, its source is connected to the positive terminal of the power supply, and its drain is connected to the ground terminal.

8. The fast-response voltage clamping protection surge protection chip circuit according to claim 7, characterized in that, Also includes: Diode D2 is reverse-connected between the gate of the bipolar insulated gate field-effect transistor and the ground terminal to prevent the gate voltage of the bipolar insulated gate field-effect transistor from being too high. Transistor Q2 has its base connected between diode D1 and resistor R2, its collector connected to the base of transistor Q4, and its emitter connected to ground.

9. The fast-response voltage clamping protection surge protection chip circuit according to claim 7, characterized in that, The Zener diode string includes N forward Zener diodes and M reverse Zener diodes, where M and N are positive integers. The clamping voltage value is adjusted by adjusting the values ​​of N and M.

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