A surge suppressor-based anti-oscillation circuit system and design method

Abstract

The embodiment of the application discloses a surge suppressor-based anti-oscillation circuit system and a design method. The system comprises a first voltage monitoring unit receiving an input voltage signal, judging whether the input voltage signal is greater than or equal to a first preset value, and outputting a first control signal if the input voltage signal is greater than or equal to the first preset value; a first surge suppression unit receiving the first control signal, receiving the input voltage signal at a first preset speed, judging whether the input voltage signal is greater than or equal to a second preset value, outputting a first intermediate voltage signal if the input voltage signal is greater than or equal to the second preset value, and outputting a second intermediate voltage signal if the input voltage signal is less than the second preset value; a second voltage monitoring unit judging whether the first intermediate voltage signal or the second intermediate voltage signal is greater than a third preset value, and outputting a second control signal if the first intermediate voltage signal or the second intermediate voltage signal is greater than the third preset value; and a second surge suppression unit receiving the second control signal, receiving the first intermediate voltage signal or the second intermediate voltage signal at a second preset speed, judging whether the first intermediate voltage signal or the second intermediate voltage signal is greater than or equal to a fifth preset value, outputting a first voltage signal if the first intermediate voltage signal or the second intermediate voltage signal is greater than or equal to the fifth preset value, and outputting a second voltage signal if the first intermediate voltage signal or the second intermediate voltage signal is less than the fifth preset value.

Description

Technical Field

[0001] This invention relates to the field of 28V DC power supply for aircraft. More specifically, it relates to an anti-oscillation circuit system and design method based on a surge suppressor. Background Technology

[0002] The electrical equipment in an aircraft's electrical system requires a stable and reliable power input. However, due to the characteristics of aircraft power supplies, extreme power output conditions exist, such as voltage distortion, voltage pulsation, voltage spikes, surge voltages, and transient power outages. Therefore, an aircraft power supply processing module is designed between the aircraft power supply and the electrical equipment to ensure that the equipment adapts to the characteristics of the aircraft power supply. For example... Figure 1 As shown, this illustrates the connection relationship between the aircraft power supply processing module and the aircraft power supply, power cables, and electrical equipment.

[0003] During the aircraft power output startup process, once the output voltage reaches a value not lower than the operating voltage threshold of the aircraft power supply processing module, the module powers on the downstream electrical equipment. If the current supplied to the electrical system, the resistance of the power supply cable, or the aircraft power output are mismatched (e.g., the aircraft power output voltage is too low, the current supplied to the electrical system is too high, or the resistance of the power supply cable is too high), the voltage at the power supply input of the aircraft power supply processing module drops below the operating voltage threshold. This causes the module to shut down its output, cutting off power to the electrical equipment. After the equipment stops working, the current in the power supply circuit drops significantly, and the voltage at the power supply input of the module rises back to a value not lower than the operating voltage threshold, allowing the module to power on the downstream electrical equipment again. This repeated fluctuation and oscillation of the power supply status of the equipment can lead to malfunctions or even damage. Summary of the Invention

[0004] The purpose of this invention is to provide an anti-oscillation circuit system and design method based on a surge suppressor, so as to solve at least one of the problems existing in the prior art.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: The first aspect of this invention provides an anti-oscillation circuit system based on a surge suppressor, the system comprising: The first voltage monitoring unit is used to receive the input voltage signal, determine whether the input voltage signal is greater than or equal to a first preset value, and if so, output a first control signal. The first surge suppression unit is used to receive a first control signal, receive an input voltage signal at a first preset speed according to the first control signal, determine whether the input voltage signal is greater than or equal to a second preset value, if yes, output a first intermediate voltage signal, the first intermediate voltage signal being the voltage signal corresponding to the second preset value; if no, output a second intermediate voltage signal, the second intermediate voltage signal following the input voltage signal. The second voltage monitoring unit is used to determine whether the first intermediate voltage signal or the second intermediate voltage signal is greater than the third preset value. If so, it outputs the second control signal. If not, it determines whether the first intermediate voltage signal or the second intermediate voltage signal is less than or equal to the third preset value and greater than or equal to the fourth preset value. If so, it maintains the current control signal. The second surge suppression unit is used to receive a second control signal, receive a first intermediate voltage signal or a second intermediate voltage signal at a second preset speed according to the second control signal, and determine whether the first intermediate voltage signal or the second intermediate voltage signal is greater than or equal to a fifth preset value. If yes, it outputs a first voltage signal, which is the voltage signal corresponding to the fifth preset value. If no, it outputs a second voltage signal, which follows the first intermediate voltage signal or the second intermediate voltage signal.

[0006] Optionally, determining whether the input voltage signal is greater than or equal to a first preset value includes: If not, a third control signal is output so that the first surge suppression unit stops outputting the first intermediate voltage signal or the second intermediate voltage signal in response to the third control signal at a third preset speed.

[0007] Optionally, determining whether the first intermediate voltage signal or the second intermediate voltage signal is less than or equal to a third preset value and greater than or equal to a fourth preset value includes: If not, a fourth control signal is output so that the second surge suppression unit stops outputting the first voltage signal or the second voltage signal in response to the fourth control signal at a fourth preset speed.

[0008] Optionally, the absolute value of the third preset value is different from the absolute value of the fourth preset value.

[0009] Optionally, the first voltage monitoring unit includes: a first transistor, a second transistor, a third transistor, a first capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a first chip; The second terminal of the first transistor is connected to the first terminal of the first capacitor, the first terminal of the first resistor, the first terminal of the third resistor, and the first terminal of the fourth resistor. The second terminal of the first capacitor is connected to the second terminal of the second resistor, the third terminal of the first chip, and the second terminal of the third transistor. The second end of the first resistor is connected to the first end of the second resistor and the second end of the first chip; The second end of the third resistor is connected to the first end of the first chip and the first end of the fifth resistor; The second terminal of the fourth resistor is connected to the first terminal of the second transistor; The second terminal of the fifth resistor is connected to the second terminal of the second transistor; The third terminal of the second transistor is connected to the first terminal of the third transistor and the first terminal of the sixth resistor; The first terminal of the first transistor receives the positive input signal of the input voltage signal; The second terminal of the first capacitor receives the negative input signal of the input voltage signal; The second terminal of the sixth resistor outputs the first control signal.

[0010] Optionally, the first surge suppression unit includes: a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a seventh resistor, an eighth resistor, a ninth resistor, a fourth transistor, and a second chip; The first terminal of the second capacitor is connected to the first terminal of the fourth transistor and the first terminal of the second chip; The first terminal of the third capacitor is connected to the second terminal of the second chip and the second terminal of the seventh resistor; The first terminal of the fourth capacitor is connected to the seventh terminal of the second chip; The first terminal of the fifth capacitor is connected to the fifth terminal of the second chip; The first terminal of the ninth resistor is connected to the second terminal of the eighth resistor and the fourth terminal of the second chip; The first terminal of the seventh resistor is connected to the second terminal of the fourth transistor; The first terminal of the eighth resistor is connected to the third terminal of the fourth transistor and the third terminal of the second chip; The second terminal of the second capacitor, the second terminal of the third capacitor, the second terminal of the fourth capacitor, the sixth terminal of the second chip, the second terminal of the fifth capacitor, and the second terminal of the ninth resistor are grounded; The first terminal of the fourth capacitor receives the first control signal; The first terminal of the eighth resistor outputs either the first intermediate voltage signal or the second intermediate voltage signal.

[0011] Optionally, the second voltage monitoring unit includes: a sixth capacitor, a seventh capacitor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a third chip; The first terminal of the sixth capacitor is connected to the first terminal of the tenth resistor and the first terminal of the third chip; The first terminal of the eleventh resistor is connected to the second terminal of the tenth resistor and the fifth terminal of the third chip; The first terminal of the seventh capacitor is connected to the first terminal of the twelfth resistor and the second terminal of the third chip; The first terminal of the thirteenth resistor is connected to the second terminal of the twelfth resistor and the third terminal of the third chip; The second terminal of the sixth capacitor, the second terminal of the eleventh resistor, the fourth terminal of the third chip, the second terminal of the thirteenth resistor, and the second terminal of the seventh capacitor are grounded; The first terminal of the sixth capacitor receives either the first intermediate voltage signal or the second intermediate voltage signal.

[0012] Optionally, the second voltage monitoring unit further includes: a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a fourth chip, and a fifth chip; The second terminal of the fourteenth resistor is connected to the first terminal of the fifteenth resistor and the first terminal of the nineteenth resistor; The first terminal of the sixteenth resistor is connected to the second terminal of the fifth chip; The second terminal of the sixteenth resistor is connected to the first terminal of the fourth chip, the first terminal of the seventeenth resistor, and the first terminal of the fifth chip; The second terminal of the seventeenth resistor is connected to the second terminal of the fourth chip and the first terminal of the eighteenth resistor; The second terminal of the nineteenth resistor is connected to the fifth terminal of the fifth chip and the first terminal of the twentieth resistor; The second terminal of the twentieth resistor is connected to the third terminal of the fifth chip and the first terminal of the twenty-first resistor; The second terminal of the fifteenth resistor, the third terminal of the fourth chip, the second terminal of the eighteenth resistor, and the fourth terminal of the fifth chip are grounded; The first terminal of the fourteenth resistor receives either the first intermediate voltage signal or the second intermediate voltage signal. The second control signal is output from the second terminal of the twenty-first resistor; The first terminal of the seventh capacitor is connected to the first terminal of the sixteenth resistor.

[0013] Optionally, the second surge suppression unit includes: an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a sixth chip, and a fifth transistor; The first terminal of the eighth capacitor is connected to the first terminal of the sixth chip and the first terminal of the fifth transistor; The first terminal of the ninth capacitor is connected to the second terminal of the sixth chip and the second terminal of the twenty-second resistor; The first terminal of the tenth capacitor is connected to the seventh terminal of the sixth chip; The first terminal of the eleventh capacitor is connected to the fifth terminal of the sixth chip; The first terminal of the twenty-fourth resistor is connected to the fourth terminal of the sixth chip and the second terminal of the twenty-third resistor; The first terminal of the twenty-second resistor is connected to the second terminal of the fifth transistor; The first terminal of the twenty-third resistor is connected to the third terminal of the fifth transistor and the third terminal of the sixth chip; The second terminal of the eighth capacitor, the second terminal of the ninth capacitor, the second terminal of the tenth capacitor, the sixth terminal of the sixth chip, the second terminal of the eleventh capacitor, and the second terminal of the twenty-fourth resistor are grounded. The first terminal of the eighth capacitor receives either the first intermediate voltage signal or the second intermediate voltage signal. The first terminal of the tenth capacitor receives the second control signal; The first terminal of the twenty-third resistor outputs either a first voltage signal or a second voltage signal.

[0014] A second aspect of the present invention provides a method for designing an anti-oscillation circuit based on a surge suppressor, the method comprising: The first voltage monitoring unit receives the input voltage signal and determines whether the input voltage signal is greater than or equal to a first preset value. If so, the first control signal is output. Using a first surge suppression unit, a first control signal is received, and an input voltage signal is received at a first preset speed according to the first control signal. It is determined whether the input voltage signal is greater than or equal to a second preset value. If so, a first intermediate voltage signal is output, which is the voltage signal corresponding to the second preset value. If not, a second intermediate voltage signal is output, which follows the input voltage signal. Using the second voltage monitoring unit, determine whether the first intermediate voltage signal or the second intermediate voltage signal is greater than the third preset value. If yes, output the second control signal. If no, determine whether the first intermediate voltage signal or the second intermediate voltage signal is less than or equal to the third preset value and greater than or equal to the fourth preset value. If yes, maintain the current control signal. Using a second surge suppression unit, a second control signal is received, and a first intermediate voltage signal or a second intermediate voltage signal is received at a second preset speed according to the second control signal. It is determined whether the first intermediate voltage signal or the second intermediate voltage signal is greater than or equal to a fifth preset value. If so, a first voltage signal is output, which is the voltage signal corresponding to the fifth preset value. If not, a second voltage signal is output, which follows the first intermediate voltage signal or the second intermediate voltage signal.

[0015] The beneficial effects of this invention are as follows: The technical solution described in this invention provides an anti-oscillation circuit system based on surge suppressors, achieving a highly simplified and integrated design. Based on a two-stage surge suppressor chip in the aircraft power supply processing module, the system controls the shutdown control inputs of the two-stage surge suppressor chips to enable or disable the output of the aircraft power supply processing module at different voltage thresholds. By combining the control of the on / off times of the two-stage surge suppressor chips, the system ensures that the output voltage of the aircraft power supply processing module stabilizes after voltage build-up when the current supplied to the electrical system and the resistance of the power supply cable match the aircraft power output. Conversely, if the current supplied to the electrical system and the resistance of the power supply cable do not match the aircraft power output, the aircraft power supply processing module has no output. This avoids repeated fluctuations and oscillations in the output state of the aircraft power supply processing module (power input to the electrical equipment), which could lead to malfunctions or even damage to the electrical equipment. Attached Figure Description

[0016] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0017] Figure 1 This diagram illustrates the external connection relationships of the carrier power supply processing module in the relevant technology.

[0018] Figure 2 A schematic diagram of an anti-oscillation circuit system based on a surge suppressor provided in an embodiment of the invention is shown.

[0019] Figure 3 The diagram shows a schematic of the first voltage monitoring unit circuit in an anti-oscillation circuit system based on a surge suppressor provided in an embodiment of the invention.

[0020] Figure 4 The diagram shows a schematic of the first surge suppression unit circuit in the anti-oscillation circuit system based on a surge suppressor provided in the embodiment of the invention.

[0021] Figure 5 The diagram shows a linear voltage regulator unit circuit in the second voltage monitoring unit circuit of the anti-oscillation circuit system based on a surge suppressor provided in the embodiment of the invention.

[0022] Figure 6 The diagram shows a schematic of a hysteresis comparator circuit in an anti-oscillation circuit system based on a surge suppressor provided in an embodiment of the invention.

[0023] Figure 7 The diagram shows a schematic of the second surge suppression unit circuit in the anti-oscillation circuit system based on a surge suppressor provided in the embodiment of the invention. Detailed Implementation

[0024] To more clearly illustrate the present invention, the following description, in conjunction with embodiments and accompanying drawings, further explains the invention. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of the present invention.

[0025] During the aircraft power output startup process, once the output voltage reaches a value not lower than the operating voltage threshold of the aircraft power supply processing module, the module powers on the downstream electrical equipment. If the current supplied to the electrical system, the resistance of the power supply cable, or the aircraft power output are mismatched (e.g., the aircraft power output voltage is too low, the current supplied to the electrical system is too high, or the resistance of the power supply cable is too high), the voltage at the power supply input of the aircraft power supply processing module drops below the operating voltage threshold. This causes the module to shut down its output, cutting off power to the electrical equipment. After the equipment stops working, the current in the power supply circuit drops significantly, and the voltage at the power supply input of the module rises back to a value not lower than the operating voltage threshold, allowing the module to power on the downstream electrical equipment again. This repeated fluctuation and oscillation of the power supply status of the equipment can lead to malfunctions or even damage.

[0026] In view of this, one embodiment of the present invention provides an anti-oscillation circuit system based on a surge suppressor. The system includes: a first voltage monitoring unit, configured to receive an input voltage signal, determine whether the input voltage signal is greater than or equal to a first preset value, and if so, output a first control signal; a first surge suppression unit, configured to receive the first control signal, receive the input voltage signal at a first preset speed according to the first control signal, determine whether the input voltage signal is greater than or equal to a second preset value, and if so, output a first intermediate voltage signal, wherein the first intermediate voltage signal is the voltage signal corresponding to the second preset value; otherwise, output a second intermediate voltage signal, wherein the second intermediate voltage signal follows the input voltage signal; and a second voltage monitoring unit, configured to determine the first intermediate voltage signal. The system determines whether the second intermediate voltage signal is greater than a third preset value. If so, it outputs a second control signal. If not, it determines whether the first or second intermediate voltage signal is less than or equal to a third preset value and greater than or equal to a fourth preset value. If so, it maintains the current control signal. The second surge suppression unit receives the second control signal and receives the first or second intermediate voltage signal at a second preset speed according to the second control signal. It determines whether the first or second intermediate voltage signal is greater than or equal to a fifth preset value. If so, it outputs a first voltage signal, which is the voltage signal corresponding to the fifth preset value. If not, it outputs a second voltage signal, which follows the first or second intermediate voltage signal.

[0027] In a specific example, the anti-oscillation circuit system based on surge suppressor in the aircraft power supply processing module consists of a primary voltage monitoring unit, a secondary voltage monitoring unit, and two cascaded surge suppression units. The functional block diagram of the surge suppressor-based anti-oscillation circuit system is shown below. Figure 2 As shown.

[0028] This embodiment provides an anti-oscillation circuit system based on a surge suppressor, located in the aircraft power supply processing module circuit. The aircraft power supply processing module is situated between the aircraft power supply and the electrical equipment. The aircraft power supply output is processed by the aircraft power supply processing module before supplying power to the electrical equipment. The circuit system, incorporating a surge suppressor, prevents oscillations in the output voltage of the aircraft power supply processing module (i.e., the input voltage for power supply to the electrical equipment). The aircraft power supply processing module employs a two-stage cascaded surge suppression unit to suppress surge voltage in the aircraft power supply. By controlling the shutdown control input terminals of the two-stage surge suppressor chips, the power supply processing module circuit can turn its output on or off at different voltage thresholds. By combining the on / off times of the two-stage surge suppression units, a circuit system with a simple topology and flexible parameter configuration is achieved. This ensures that the power supply processing module output voltage is stable after voltage build-up when the current of the user system and the resistance of the power supply cable match the aircraft power output. When the current of the user system and the resistance of the power supply cable do not match the aircraft power output, the power supply processing module has no output. This avoids repeated fluctuations and oscillations in the output state of the aircraft power supply processing module (power supply input to the equipment), which could lead to malfunctions or even damage to the equipment.

[0029] In one possible implementation, determining whether the input voltage signal is greater than or equal to a first preset value includes: if not, outputting a third control signal so that the first surge suppression unit stops outputting the first intermediate voltage signal or the second intermediate voltage signal in response to the third control signal at a third preset speed.

[0030] This embodiment achieves controllable soft shutdown of the front-end power supply by outputting a third control signal when the input voltage is lower than a first preset value, and causing the first surge suppression unit to stop outputting at a third preset speed. On the one hand, when the input voltage is severely insufficient, the front-end power supply path can be reliably cut off, avoiding abnormal operation or damage of the subsequent circuit under low voltage conditions. On the other hand, by setting the shutdown speed, a sudden drop in output voltage is avoided, reducing the current impact on the circuit at the moment of shutdown, while leaving response time for the subsequent state judgment, preventing malfunctions caused by transient voltage drops.

[0031] In one possible implementation, determining whether the first intermediate voltage signal or the second intermediate voltage signal is less than or equal to a third preset value and greater than or equal to a fourth preset value includes: if not, outputting a fourth control signal so that the second surge suppression unit stops outputting the first voltage signal or the second voltage signal in response to the fourth control signal at a fourth preset speed.

[0032] This embodiment outputs a fourth control signal when the intermediate voltage is lower than the fourth preset value, and causes the second surge suppression unit to stop outputting at the fourth preset speed, thereby achieving reliable shutdown and slow-down control of the final power supply output. In conjunction with the hysteresis interval formed by the third and fourth preset values, it ensures that the output will only be restarted when the voltage truly recovers to the upper limit threshold, fundamentally eliminating the oscillating cycle of voltage drop when turned on, shutdown when dropped, and recovery when turned off.

[0033] In one possible implementation, the absolute value of the third preset value is different from the absolute value of the fourth preset value.

[0034] This embodiment constructs an asymmetric hysteresis voltage window by setting the third preset value (upper limit threshold) and the fourth preset value to different absolute values. Combined with the first preset value: when turned on, the voltage must reach a higher upper limit threshold to ensure sufficient power supply before connecting the downstream load; when turned off, the output is only cut off when the voltage drops to a lower lower limit threshold, allowing for a certain degree of voltage drop after power-on and load application without triggering shutdown. The buffer band formed between the thresholds ensures that the output state remains unchanged when the voltage fluctuates within this range, fundamentally eliminating the root cause of oscillation caused by the single threshold switch repeatedly flipping near the critical point. This is the core design of the entire anti-oscillation scheme.

[0035] In one possible implementation, the first voltage monitoring unit includes: a first transistor V1, a second transistor V2, a third transistor V3, a first capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a first chip N1; the second terminal of the first transistor is connected to the first terminal of the first capacitor, the first terminal of the first resistor, the first terminal of the third resistor, and the first terminal of the fourth resistor; the second terminal of the first capacitor is connected to the second terminal of the second resistor, the third terminal of the first chip, and the second terminal of the third transistor; the second terminal of the first resistor is connected to the first terminal of the second resistor and the second terminal of the first chip; the second terminal of the third resistor is connected to the first terminal of the first chip and the first terminal of the fifth resistor; the second terminal of the fourth resistor is connected to the first terminal of the second transistor; the second terminal of the fifth resistor is connected to the second terminal of the second transistor; the third terminal of the second transistor is connected to the first terminal of the third transistor and the first terminal of the sixth resistor; the first terminal of the first transistor receives a positive input signal of the input voltage signal; the second terminal of the first capacitor receives a negative input signal of the input voltage signal; and the second terminal of the sixth resistor outputs a first control signal.

[0036] In a specific example, the schematic diagram of the first-level voltage monitoring unit circuit is as follows: Figure 3 As shown, the adjustable precision parallel regulator chip N1 monitors the input voltage of the carrier power supply module. The input voltage is divided by resistors R1 and R2 to set the first-stage undervoltage shutdown threshold VTH1. When the input voltage of the carrier power supply module is not lower than VTH1, the cathode of chip N1 is in the ON state, making the #SHDN_1 signal high; when the input voltage of the carrier power supply module is lower than VTH1, the cathode of chip N1 is in the OFF state, making the #SHDN_1 signal low. The #SHDN_1 signal controls the first-stage surge suppression unit and other circuits requiring pre-control.

[0037] This embodiment implements a first voltage monitoring unit through a specific circuit consisting of a first transistor, a second transistor, a third transistor, a first capacitor, first to sixth resistors, and a first chip. It employs a voltage divider detection architecture combining transistors and precision chips, enabling precise setting of the first preset value (undervoltage shutdown threshold). The circuit is composed entirely of general-purpose discrete components and conventional chips, resulting in a simple structure, low cost, and high reliability, making it suitable for applications with stringent reliability requirements, such as aerospace. The undervoltage threshold can be flexibly modified by adjusting the resistance values ​​of the voltage divider resistors, adapting to different models and power supply specifications, demonstrating strong versatility and configurability. The transistor switch output method provides strong driving capabilities for the first and third control signals, allowing direct driving of the shutdown pin of the subsequent surge suppression chip without the need for additional drive circuitry.

[0038] In one possible implementation, the first surge suppression unit includes: a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a fourth transistor V5, and a second chip N2; the first terminal of the second capacitor is connected to the first terminal of the fourth transistor and the first terminal of the second chip; the first terminal of the third capacitor is connected to the second terminal of the second chip and the second terminal of the seventh resistor; the first terminal of the fourth capacitor is connected to the seventh terminal of the second chip; the first terminal of the fifth capacitor is connected to the fifth terminal of the second chip; the first terminal of the ninth resistor is connected to the second terminal of the eighth resistor and the fourth terminal of the second chip; the first terminal of the seventh resistor is connected to the second terminal of the fourth transistor; the first terminal of the eighth resistor is connected to the third terminal of the fourth transistor and the third terminal of the second chip; the second terminal of the second capacitor is grounded along with the second terminals of the third capacitor, the fourth capacitor, the second chip, the fifth capacitor, and the ninth resistor; the first terminal of the fourth capacitor receives a first control signal; and the first terminal of the eighth resistor outputs a first intermediate voltage signal or a second intermediate voltage signal.

[0039] In a specific example, the first terminal of the second chip N2 is VCC, the second terminal is GATE, the third terminal is OUT, the fourth terminal is FB, the fifth terminal is TMR, the sixth terminal is GND, and the seventh terminal is... .

[0040] In a specific example, the schematic diagram of the first-level surge suppression unit circuit is as follows: Figure 4 As shown, the surge suppressor chip N2 controls the linear power MOSFET V5 to achieve a first-stage voltage reduction of the surge voltage. The voltage clamping value of the first-stage surge suppressor unit's output voltage is set by the voltage divider function of resistors R8 and R9. The output or shutdown of the first-stage surge suppressor unit is controlled by the shutdown control input terminal of chip N2 via the #SHDN_1 signal. The on / off time of the first-stage surge suppressor unit is controlled by the external capacitor connected to chip N2. When the #SHDN_1 signal is high, the first-stage surge suppressor unit outputs, and the intermediate voltage signal VCC1 is built up; when the #SHDN_1 signal is low, the first-stage surge suppressor unit is shut down, and there is no output. After the first-stage surge suppressor unit circuit starts, if the output voltage of the first-stage surge suppressor unit does not reach the clamping value, the output voltage of the first-stage surge suppressor unit follows the input voltage of the first-stage surge suppressor unit.

[0041] This embodiment implements the first surge suppression unit through a specific circuit consisting of the second to fifth capacitors, the seventh to ninth resistors, the fourth transistor, and the second chip. It employs an architecture where a dedicated surge suppression chip drives a linear power MOSFET, automatically clamping the output to a safe voltage when the input surge voltage exceeds a second preset value, achieving first-level overvoltage protection and protecting downstream circuits. Under normal operating conditions, the output voltage follows the input voltage, with a small on-state voltage drop and high power supply efficiency, without affecting normal power quality. The on / off speed can be flexibly configured via an external capacitor (the fourth capacitor), enabling soft start and slow turn-off, effectively suppressing the inrush current and preventing the input voltage from being pulled down during closing. The clamping value is set by voltage division using the eighth and ninth resistors, allowing for convenient parameter adjustment and flexible configuration of the output voltage upper limit according to different downstream load requirements.

[0042] In one possible implementation, the second voltage monitoring unit includes: a sixth capacitor C6, a seventh capacitor C7, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and a third chip N3; the first terminal of the sixth capacitor is connected to the first terminal of the tenth resistor and the first terminal of the third chip; the first terminal of the eleventh resistor is connected to the second terminal of the tenth resistor and the fifth terminal of the third chip; the first terminal of the seventh capacitor is connected to the first terminal of the twelfth resistor and the second terminal of the third chip; the first terminal of the thirteenth resistor is connected to the second terminal of the twelfth resistor and the third terminal of the third chip; the second terminal of the sixth capacitor, the second terminal of the eleventh resistor, the fourth terminal of the third chip, the second terminal of the thirteenth resistor, and the second terminal of the seventh capacitor are grounded; the first terminal of the sixth capacitor receives a first intermediate voltage signal or a second intermediate voltage signal.

[0043] In a specific example, the secondary voltage monitoring unit consists of a linear voltage regulator circuit and a hysteresis comparator circuit. A schematic diagram of the linear voltage regulator circuit is shown below. Figure 5 As shown, the VCC2 voltage output from the wide input range (3V~55V) linear regulator chip N3 is used to power the operational amplifier chip N5 in the hysteresis comparator unit. The VCC2 voltage value is set by a voltage divider formed by resistors R12 and R13.

[0044] In a specific example, the first terminal of the third chip N3 is IN, the second terminal is OUT, the third terminal is ADJ, the fourth terminal is GND, and the fifth terminal is EN.

[0045] This embodiment uses a linear voltage regulator circuit consisting of the sixth capacitor, the seventh capacitor, the tenth to thirteenth resistors, and the third chip as the power supply for the second voltage monitoring unit. This provides a stable DC operating voltage for the subsequent hysteresis comparator circuit, ensuring that its threshold judgment is not affected by fluctuations in the front-end intermediate voltage VCC1. The wide input range linear regulator maintains output stability even with large variations in VCC1, adapting to the conditions of large fluctuations in aircraft power supply voltage. Combined with external filter capacitors, the output voltage ripple is small, providing a clean power supply for the comparator circuit and preventing operational amplifier mis-flipping due to power supply noise, further improving the reliability of anti-oscillation. The regulated output value is set using voltage divider resistors, allowing for flexible configuration.

[0046] In one possible implementation, the second voltage monitoring unit further includes: a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a fourth chip N4, and a fifth chip N5; the second terminal of the fourteenth resistor is connected to the first terminal of the fifteenth resistor and the first terminal of the nineteenth resistor; the first terminal of the sixteenth resistor is connected to the second terminal of the fifth chip; the second terminal of the sixteenth resistor is connected to the first terminal of the fourth chip, the first terminal of the seventeenth resistor, and the first terminal of the fifth chip. Connect the following: the second terminal of the seventeenth resistor is connected to the second terminal of the fourth chip and the first terminal of the eighteenth resistor; the second terminal of the nineteenth resistor is connected to the fifth terminal of the fifth chip and the first terminal of the twentieth resistor; the second terminal of the twentieth resistor is connected to the third terminal of the fifth chip and the first terminal of the twenty-first resistor; the second terminal of the fifteenth resistor, the third terminal of the fourth chip, the second terminal of the eighteenth resistor, and the fourth terminal of the fifth chip are grounded; the first terminal of the fourteenth resistor receives the first intermediate voltage signal or the second intermediate voltage signal; the second terminal of the twenty-first resistor outputs the second control signal; the first terminal of the seventh capacitor is connected to the first terminal of the sixteenth resistor.

[0047] In a specific example, the schematic diagram of the hysteresis comparator circuit is as follows: Figure 6 As shown, the voltage at the VIN- terminal of operational amplifier chip N5 is set as a reference voltage using adjustable precision parallel regulator chip N4 and resistors R17 and R18. The voltage obtained by dividing VCC1 using resistors R14 and R15 is then used to construct two asymmetric threshold voltages through a positive feedback network formed by chip N5, resistors R19 and R20, resulting in two asymmetric threshold voltages VTH2 corresponding to VCC1. + VTH2 - The calculation formula is as follows: VTH2 + =(VIN - (R) 20 +R 19) / R 20 ) (1+R) 14 / R 15 ) VTH2 - =(VIN - (R) 20 -R 19 ) / R 20 ) (1+R) 14 / R 15 ) In the formula, VTH2 + The third preset value, VTH2 - VIN is the fourth preset value. - R is the input voltage at the first terminal of the fourth chip N4; 20 Let R20 be the resistance value of the twentieth resistor. 19 R is the resistance value of the nineteenth resistor R19. 14 R is the resistance value of the fourteenth resistor R14. 15 This is the resistance value of the fifteenth resistor, R15.

[0048] Furthermore, when the VCC1 voltage is higher than the upper limit threshold VTH2 + When the #SHDN_2 signal is high, and the VCC1 voltage is lower than the lower threshold VTH2... - The #SHDN_2 signal is low. When the VCC1 voltage is at the upper threshold VTH2... + and lower limit threshold VTH2 - When fluctuations occur, the #SHDN_2 signal remains unchanged. The #SHDN_2 signal controls the secondary surge suppression unit, VTH2. + VTH2 serves as the turn-on voltage threshold for the back-end output stage. - As the secondary undervoltage shutdown voltage threshold.

[0049] This embodiment implements the core detection function of the second voltage monitoring unit through a hysteresis comparator circuit composed of resistors fourteen to twenty-first, the fourth chip, and the fifth chip. It employs a classic hysteresis comparator architecture using an operational amplifier and a positive feedback resistor network, which can stably construct asymmetric upper threshold and lower threshold. The circuit is mature and reliable. A high-precision fixed reference voltage is provided to the operational amplifier through a reference generation branch (an adjustable precision parallel regulator combined with a reference voltage divider resistor), ensuring the accuracy of the two threshold settings. By adjusting the resistance ratio of the positive feedback resistor network and the input voltage divider branch, VTH2 can be flexibly calculated and configured. + and VTH2 -The specific values ​​and parameter design are intuitive and easy to debug, and can be adapted to application scenarios with different power levels and cable impedances; the op-amp output is directly used as the second control signal, with strong driving capability, and can directly control the subsequent surge suppression chip without the need for an additional driver stage, making the circuit simple.

[0050] In one possible implementation, the second surge suppression unit includes: an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a sixth chip N6, and a fifth transistor V6; the first terminal of the eighth capacitor is connected to the first terminal of the sixth chip and the first terminal of the fifth transistor; the first terminal of the ninth capacitor is connected to the second terminal of the sixth chip and the second terminal of the twenty-second resistor; the first terminal of the tenth capacitor is connected to the seventh terminal of the sixth chip; the first terminal of the eleventh capacitor is connected to the fifth terminal of the sixth chip; and the twenty-fourth resistor... The first terminal is connected to the fourth terminal of the sixth chip and the second terminal of the twenty-third resistor; the first terminal of the twenty-second resistor is connected to the second terminal of the fifth transistor; the first terminal of the twenty-third resistor is connected to the third terminal of the fifth transistor and the third terminal of the sixth chip; the second terminal of the eighth capacitor is grounded to the second terminals of the ninth capacitor, the tenth capacitor, the sixth chip, the eleventh capacitor, and the twenty-fourth resistor; the first terminal of the eighth capacitor receives a first intermediate voltage signal or a second intermediate voltage signal; the first terminal of the tenth capacitor receives a second control signal; the first terminal of the twenty-third resistor outputs a first voltage signal or a second voltage signal.

[0051] In a specific example, the first terminal of the sixth chip N6 is VCC, the second terminal is GATE, the third terminal is OUT, the fourth terminal is FB, the fifth terminal is TMR, the sixth terminal is GND, and the seventh terminal is... .

[0052] In a specific example, the schematic diagram of the two-stage surge suppression unit circuit is as follows: Figure 7 As shown, a two-stage voltage reduction of the surge voltage is achieved by controlling the linear power MOSFET V6 through the surge suppressor chip N6. The output voltage clamping value of the second-stage surge suppression unit is set by the voltage divider through resistors R23 and R24. The output or shutdown of the second-stage surge suppression unit is controlled by the shutdown control input terminal of the chip N6 via the #SHDN_2 signal. The on / off time of the second-stage surge suppression unit is controlled by the external capacitor of the chip N6. When the #SHDN_2 signal is high, the second-stage surge suppression unit outputs, and the output stage builds up voltage; when the #SHDN_2 signal is low, the second-stage surge suppression unit is turned off, and there is no output. After the second-stage surge suppression unit circuit is started, if the output voltage of the second-stage surge suppression unit does not reach the clamping value, the output voltage of the second-stage surge suppression unit follows the input voltage of the second-stage surge suppression unit.

[0053] In a specific example, by reasonably configuring the resistance and capacitance values ​​in the circuit system to set the turn-on and turn-off voltage thresholds and turn-on and turn-off times of circuits such as the surge suppression unit in the aircraft power supply processing module, the output voltage of the aircraft power supply processing module is stably built up after the current on the electrical system and the resistance of the power supply cable are matched with the aircraft power output. When the current on the electrical system and the resistance of the power supply cable are not matched with the aircraft power output, the aircraft power supply processing module has no output.

[0054] In a specific example, the functional circuit formed by combining components such as resistors, capacitors, diodes, transistors, operational amplifiers, linear regulators, and adjustable precision parallel regulators with surge suppressor chips has a simple circuit architecture and control logic, and flexible parameter configuration. This circuit system simplifies the specifications and quantity of components, thereby reducing the complexity of the product and achieving low-cost and high-reliability design from the source.

[0055] This embodiment implements a second surge suppression unit through a specific circuit consisting of capacitors eight to eleven, resistors twenty-two to twenty-four, a sixth chip, and a fifth transistor. This forms a two-stage series surge protection with the first surge suppression unit, performing secondary voltage reduction clamping on the input surge voltage, resulting in a more stable output voltage and stronger protection capability, providing more reliable overvoltage protection for downstream equipment. Controlled by a second control signal with hysteresis characteristics, and with its configurable soft-start speed, it can slowly build up voltage and limit inrush current when a large downstream load is connected, preventing the voltage of the preceding stage from being pulled down and triggering false shutdown upon power-up. This, combined with the hysteresis threshold design, achieves anti-oscillation. Under normal operating conditions, the output voltage follows the input voltage, resulting in low conduction loss. In case of overvoltage, it automatically clamps to a fifth preset value to protect the equipment. All components are general-purpose, and the circuit structure of the second-stage surge unit is symmetrical to that of the first-stage surge unit, resulting in high design reusability, convenient maintenance, and controllable cost, making it suitable for engineering-scale mass applications.

[0056] Another embodiment of the present invention provides a method for designing an anti-oscillation circuit based on a surge suppressor. The method includes: using a first voltage monitoring unit to receive an input voltage signal, determining whether the input voltage signal is greater than or equal to a first preset value; if so, outputting a first control signal; using a first surge suppression unit to receive the first control signal, receiving the input voltage signal at a first preset speed according to the first control signal, determining whether the input voltage signal is greater than or equal to a second preset value; if so, outputting a first intermediate voltage signal, the first intermediate voltage signal being the voltage signal corresponding to the second preset value; if not, outputting a second intermediate voltage signal, the second intermediate voltage signal following the input voltage signal; using a second voltage monitoring unit to determine whether the first intermediate voltage signal or... If the second intermediate voltage signal is greater than the third preset value, then the second control signal is output; otherwise, it is determined whether the first intermediate voltage signal or the second intermediate voltage signal is less than or equal to the third preset value and greater than or equal to the fourth preset value. If so, the current control signal is maintained. Using the second surge suppression unit, the second control signal is received, and the first intermediate voltage signal or the second intermediate voltage signal is received at the second preset speed according to the second control signal. It is determined whether the first intermediate voltage signal or the second intermediate voltage signal is greater than or equal to the fifth preset value. If so, the first voltage signal is output, and the first voltage signal is the voltage signal corresponding to the fifth preset value. If not, the second voltage signal is output, and the second voltage signal follows the first intermediate voltage signal or the second intermediate voltage signal.

[0057] This embodiment provides a design method for an anti-oscillation circuit based on a surge suppressor, applied to an aircraft power supply processing module circuit. The aircraft power supply processing module is located between the aircraft power supply and the electrical equipment. The aircraft power supply output is processed by the aircraft power supply processing module before supplying power to the electrical equipment. A circuit system is designed to prevent oscillations in the output voltage of the aircraft power supply processing module (i.e., the input voltage for power supply to the electrical equipment) by incorporating a surge suppressor. The aircraft power supply processing module employs a two-stage cascaded surge suppression unit to suppress surge voltage in the aircraft power supply. By controlling the shutdown control input terminals of the two-stage surge suppressor chips, the power supply processing module circuit can turn its output on or off at different voltage thresholds. By combining the on / off times of the two-stage surge suppression units, a circuit system with a simple topology and flexible parameter configuration is achieved. This ensures that the power supply processing module output voltage is stable after voltage build-up when the current of the user system and the resistance of the power supply cable match the aircraft power output. When the current of the user system and the resistance of the power supply cable do not match the aircraft power output, the power supply processing module has no output. This avoids repeated fluctuations and oscillations in the output state of the aircraft power supply processing module (power supply input to the equipment), which could lead to malfunctions or even damage to the equipment.

[0058] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0059] It should also be noted that in the description of this invention, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0060] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. An anti-oscillation circuit system based on a surge suppressor, characterized in that, The system includes: The first voltage monitoring unit is used to receive the input voltage signal, determine whether the input voltage signal is greater than or equal to a first preset value, and if so, output a first control signal. The first surge suppression unit is used to receive a first control signal, receive an input voltage signal at a first preset speed according to the first control signal, determine whether the input voltage signal is greater than or equal to a second preset value, if yes, output a first intermediate voltage signal, the first intermediate voltage signal being the voltage signal corresponding to the second preset value; if no, output a second intermediate voltage signal, the second intermediate voltage signal following the input voltage signal. The second voltage monitoring unit is used to determine whether the first intermediate voltage signal or the second intermediate voltage signal is greater than the third preset value. If so, it outputs the second control signal. If not, it determines whether the first intermediate voltage signal or the second intermediate voltage signal is less than or equal to the third preset value and greater than or equal to the fourth preset value. If so, it maintains the current control signal. The second surge suppression unit is used to receive a second control signal, receive a first intermediate voltage signal or a second intermediate voltage signal at a second preset speed according to the second control signal, and determine whether the first intermediate voltage signal or the second intermediate voltage signal is greater than or equal to a fifth preset value. If yes, it outputs a first voltage signal, which is the voltage signal corresponding to the fifth preset value. If no, it outputs a second voltage signal, which follows the first intermediate voltage signal or the second intermediate voltage signal.

2. The anti-oscillation circuit system according to claim 1, characterized in that, The step of determining whether the input voltage signal is greater than or equal to a first preset value includes: If not, a third control signal is output so that the first surge suppression unit stops outputting the first intermediate voltage signal or the second intermediate voltage signal in response to the third control signal at a third preset speed.

3. The anti-oscillation circuit system according to claim 1, characterized in that, The step of determining whether the first intermediate voltage signal or the second intermediate voltage signal is less than or equal to a third preset value and greater than or equal to a fourth preset value includes: If not, a fourth control signal is output so that the second surge suppression unit stops outputting the first voltage signal or the second voltage signal in response to the fourth control signal at a fourth preset speed.

4. The anti-oscillation circuit system according to claim 1, characterized in that, The absolute value of the third preset value is different from the absolute value of the fourth preset value.

5. The anti-oscillation circuit system according to claim 1, characterized in that, The first voltage monitoring unit includes: a first transistor, a second transistor, a third transistor, a first capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a first chip; The second terminal of the first transistor is connected to the first terminal of the first capacitor, the first terminal of the first resistor, the first terminal of the third resistor, and the first terminal of the fourth resistor. The second terminal of the first capacitor is connected to the second terminal of the second resistor, the third terminal of the first chip, and the second terminal of the third transistor. The second end of the first resistor is connected to the first end of the second resistor and the second end of the first chip; The second end of the third resistor is connected to the first end of the first chip and the first end of the fifth resistor; The second terminal of the fourth resistor is connected to the first terminal of the second transistor; The second terminal of the fifth resistor is connected to the second terminal of the second transistor; The third terminal of the second transistor is connected to the first terminal of the third transistor and the first terminal of the sixth resistor; The first terminal of the first transistor receives the positive input signal of the input voltage signal; The second terminal of the first capacitor receives the negative input signal of the input voltage signal; The second terminal of the sixth resistor outputs the first control signal.

6. The anti-oscillation circuit system according to claim 1, characterized in that, The first surge suppression unit includes: a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a seventh resistor, an eighth resistor, a ninth resistor, a fourth transistor, and a second chip; The first terminal of the second capacitor is connected to the first terminal of the fourth transistor and the first terminal of the second chip; The first terminal of the third capacitor is connected to the second terminal of the second chip and the second terminal of the seventh resistor; The first terminal of the fourth capacitor is connected to the seventh terminal of the second chip; The first terminal of the fifth capacitor is connected to the fifth terminal of the second chip; The first terminal of the ninth resistor is connected to the second terminal of the eighth resistor and the fourth terminal of the second chip; The first terminal of the seventh resistor is connected to the second terminal of the fourth transistor; The first terminal of the eighth resistor is connected to the third terminal of the fourth transistor and the third terminal of the second chip; The second terminal of the second capacitor, the second terminal of the third capacitor, the second terminal of the fourth capacitor, the sixth terminal of the second chip, the second terminal of the fifth capacitor, and the second terminal of the ninth resistor are grounded; The first terminal of the fourth capacitor receives the first control signal; The first terminal of the eighth resistor outputs either a first intermediate voltage signal or a second intermediate voltage signal.

7. The anti-oscillation circuit system according to claim 1, characterized in that, The second voltage monitoring unit includes: a sixth capacitor, a seventh capacitor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a third chip; The first terminal of the sixth capacitor is connected to the first terminal of the tenth resistor and the first terminal of the third chip; The first terminal of the eleventh resistor is connected to the second terminal of the tenth resistor and the fifth terminal of the third chip; The first terminal of the seventh capacitor is connected to the first terminal of the twelfth resistor and the second terminal of the third chip; The first terminal of the thirteenth resistor is connected to the second terminal of the twelfth resistor and the third terminal of the third chip; The second terminal of the sixth capacitor, the second terminal of the eleventh resistor, the fourth terminal of the third chip, the second terminal of the thirteenth resistor, and the second terminal of the seventh capacitor are grounded; The first terminal of the sixth capacitor receives either the first intermediate voltage signal or the second intermediate voltage signal.

8. The anti-oscillation circuit system according to claim 7, characterized in that, The second voltage monitoring unit also includes: a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a fourth chip, and a fifth chip; The second terminal of the fourteenth resistor is connected to the first terminal of the fifteenth resistor and the first terminal of the nineteenth resistor; The first terminal of the sixteenth resistor is connected to the second terminal of the fifth chip; The second terminal of the sixteenth resistor is connected to the first terminal of the fourth chip, the first terminal of the seventeenth resistor, and the first terminal of the fifth chip; The second terminal of the seventeenth resistor is connected to the second terminal of the fourth chip and the first terminal of the eighteenth resistor; The second terminal of the nineteenth resistor is connected to the fifth terminal of the fifth chip and the first terminal of the twentieth resistor; The second terminal of the twentieth resistor is connected to the third terminal of the fifth chip and the first terminal of the twenty-first resistor; The second terminal of the fifteenth resistor, the third terminal of the fourth chip, the second terminal of the eighteenth resistor, and the fourth terminal of the fifth chip are grounded; The first terminal of the fourteenth resistor receives either the first intermediate voltage signal or the second intermediate voltage signal. The second control signal is output from the second terminal of the twenty-first resistor; The first terminal of the seventh capacitor is connected to the first terminal of the sixteenth resistor.

9. The anti-oscillation circuit system according to claim 1, characterized in that, The second surge suppression unit includes: an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a sixth chip, and a fifth transistor; The first terminal of the eighth capacitor is connected to the first terminal of the sixth chip and the first terminal of the fifth transistor; The first terminal of the ninth capacitor is connected to the second terminal of the sixth chip and the second terminal of the twenty-second resistor; The first terminal of the tenth capacitor is connected to the seventh terminal of the sixth chip; The first terminal of the eleventh capacitor is connected to the fifth terminal of the sixth chip; The first terminal of the twenty-fourth resistor is connected to the fourth terminal of the sixth chip and the second terminal of the twenty-third resistor; The first terminal of the twenty-second resistor is connected to the second terminal of the fifth transistor; The first terminal of the twenty-third resistor is connected to the third terminal of the fifth transistor and the third terminal of the sixth chip; The second terminal of the eighth capacitor, the second terminal of the ninth capacitor, the second terminal of the tenth capacitor, the sixth terminal of the sixth chip, the second terminal of the eleventh capacitor, and the second terminal of the twenty-fourth resistor are grounded. The first terminal of the eighth capacitor receives either the first intermediate voltage signal or the second intermediate voltage signal. The first terminal of the tenth capacitor receives the second control signal; The first terminal of the twenty-third resistor outputs either a first voltage signal or a second voltage signal.

10. A method for designing an anti-oscillation circuit based on a surge suppressor, characterized in that, The method includes: The first voltage monitoring unit receives the input voltage signal and determines whether the input voltage signal is greater than or equal to a first preset value. If so, the first control signal is output. Using a first surge suppression unit, a first control signal is received, and an input voltage signal is received at a first preset speed according to the first control signal. It is determined whether the input voltage signal is greater than or equal to a second preset value. If so, a first intermediate voltage signal is output, which is the voltage signal corresponding to the second preset value. If not, a second intermediate voltage signal is output, which follows the input voltage signal. Using the second voltage monitoring unit, determine whether the first intermediate voltage signal or the second intermediate voltage signal is greater than the third preset value. If yes, output the second control signal. If no, determine whether the first intermediate voltage signal or the second intermediate voltage signal is less than or equal to the third preset value and greater than or equal to the fourth preset value. If yes, maintain the current control signal. Using a second surge suppression unit, a second control signal is received, and a first intermediate voltage signal or a second intermediate voltage signal is received at a second preset speed according to the second control signal. It is determined whether the first intermediate voltage signal or the second intermediate voltage signal is greater than or equal to a fifth preset value. If so, a first voltage signal is output, which is the voltage signal corresponding to the fifth preset value. If not, a second voltage signal is output, which follows the first intermediate voltage signal or the second intermediate voltage signal.

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