A heterogeneous device hybrid energy storage SOP AC / DC decoupling collaborative control method, system, device and storage medium

Abstract

The application discloses a heterogeneous device hybrid energy storage SOP AC / DC decoupling collaborative control method, system, equipment and storage medium, relates to the technical field of power electronic conversion and distribution network flexible interconnection, and the method comprises the steps of establishing a midpoint physical connection; obtaining a current reference by superimposing voltage outer loop feedforward; obtaining a total duty cycle by superimposing a reference lower limit of a current inner loop; obtaining a midpoint error by sequentially enabling the upper and lower capacitor differences; obtaining a fine-tuning duty cycle by resonance regulation; obtaining upper and lower bridge arm duty cycles by cross-decoupling the total duty cycle and the fine-tuning duty cycle; and generating a pulse to drive a switching tube. The application can radically cure low-frequency oscillation of the midpoint potential, has small dynamic voltage drop and fast recovery, eliminates DC low-frequency ripple, reduces device stress and cost, balances heat distribution, is beneficial to high-power density integration, and has anti-saturation soft-start capability.

Description

Technical Field

[0001] This invention relates to the field of power electronic conversion and flexible interconnection technology of distribution networks, and in particular to a method, system, device and storage medium for AC / DC decoupling and coordinated control of a heterogeneous device hybrid energy storage SOP. Background Technology

[0002] With the high proportion of distributed power sources and unbalanced loads integrated into low-voltage distribution networks, the problem of three-phase load imbalance in distribution areas is becoming increasingly prominent, posing severe challenges to the traditional distribution network architecture in terms of power flow regulation and voltage support. Smart soft switches (SOPs) with energy storage interfaces are considered key equipment for improving the flexible interconnection level of distribution networks due to their combined bidirectional power regulation and flexible energy storage integration capabilities. However, in practical engineering applications, under extreme unbalanced load conditions, the huge 50Hz zero-sequence current generated on the AC side will directly flow into the midpoint of the DC bus split capacitor through the neutral line, causing severe low-frequency oscillations in the DC midpoint potential. Simultaneously, this condition will also superimpose a 100Hz second-harmonic pulsating power on the DC bus, seriously threatening the stable operation of the converter. How to simultaneously suppress midpoint potential drift and DC ripple from the perspectives of topology and control strategies, while reducing device voltage stress and switching losses, has become a core challenge restricting the development of high reliability and high power density for energy storage-type SOPs.

[0003] Existing energy storage SOPs mostly employ a back-to-back dual-ended converter structure, with the DC side typically equipped with a traditional two-level or interleaved parallel Buck-Boost converter as the energy storage interface. While this type of solution can maintain operation under conventional symmetrical loads, its topology only connects to the positive and negative terminals of the DC bus, lacking a physical electrical interface with the DC midpoint. This makes it impossible to actively regulate the zero-sequence charge injected into the midpoint, rendering it ineffective against midpoint potential oscillations and easily leading to abnormal converter shutdowns due to excessive midpoint offset. At the control level, existing strategies mostly employ a classic dual-closed-loop architecture with a single voltage outer loop and a current inner loop. Its bandwidth is limited, making it difficult to effectively smooth out low-frequency pulsating power while stabilizing the total DC voltage, easily leading to integral saturation and closed-loop oscillations, resulting in insufficient dynamic response performance. Furthermore, in traditional two-level topologies, the switching transistors must withstand the full 800V voltage stress, necessitating the use of expensive 1200V high-voltage SiC devices. This not only results in high hardware costs but also significant high-frequency switching losses, severely limiting the system's power density and engineering economics. Summary of the Invention

[0004] In view of the above-mentioned problems, the present invention provides a method, system, device and storage medium for AC / DC decoupling and coordinated control of heterogeneous device hybrid energy storage SOP.

[0005] Therefore, the technical problem solved by this invention is to provide an energy storage SOP topology and its control method that can achieve synergistic breakthroughs in active midpoint potential suppression, DC low-frequency ripple suppression, device voltage stress reduction, and switching loss optimization.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides a method for AC / DC decoupling and coordinated control of a hybrid energy storage SOP with heterogeneous devices, comprising: Establish a physical connection channel at the midpoint of the shared capacitor on both AC and DC sides; The total DC bus voltage is collected and the voltage outer loop control is performed. The current inner loop reference value is generated by superimposing the feedforward compensation. The battery current is collected and current inner loop control is performed. After superimposing the steady-state reference duty cycle, the amplitude is limited to generate the global total duty cycle. The voltages of the upper and lower capacitors are collected and the difference is calculated. After timing enable processing, a midpoint error signal is generated. Multi-band resonance adjustment and amplitude limiting are performed on the midpoint error signal to generate a fine-tuning duty cycle; The global total duty cycle and the fine-tuned duty cycle are cross-decoupled and allocated to obtain the final duty cycle of the upper and lower bridge arms; Drive pulses are generated based on the final duty cycle of the upper and lower bridge arms to control the on / off state of each switching transistor.

[0007] As a preferred scheme for a hybrid energy storage SOP with heterogeneous devices, the AC / DC decoupling and coordinated control method is as follows: The establishment of a physical connection channel at the midpoint of the AC / DC side shared capacitor includes: A DC bus shared by AC and DC sides is provided. The DC bus is composed of an upper support capacitor and a lower support capacitor connected in series. The connection point of the two support capacitors is led out as the DC physical midpoint. A double-ended converter is set on the AC side. The double-ended converter consists of two sets of converter units connected back to back. Each set of converter units includes a three-phase power bridge arm and a fourth bridge arm. The neutral point of the fourth bridge arm is connected to the neutral line of the AC system via a neutral inductor. Each phase power bridge arm is composed of an upper outer switch, an upper inner switch, a lower inner switch, and a lower outer switch connected in series between the DC positive bus and the DC negative bus. An upper clamping tube is provided to connect the DC physical midpoint to the common connection point of the upper outer switch and the upper inner switch, and a lower clamping tube is provided to connect the DC physical midpoint to the common connection point of the lower inner switch and the lower outer switch. The AC-side load neutral line is directly physically connected to the DC physical neutral point to form a physical return path for zero-sequence current. A DC-side three-level buck-boost energy storage converter is provided. The DC-side three-level buck-boost energy storage converter consists of a battery, a voltage divider inductor, and upper and lower half-bridges. The upper half-bridge consists of an upper outer switch and an upper inner switch, and the lower half-bridge consists of a lower inner switch and a lower outer switch. The upper inner switch and the lower inner switch, which are responsible for high-frequency switching, are wide-bandgap semiconductor devices, while the upper outer switch and the lower outer switch, which are responsible for power frequency freewheeling or clamping, are silicon-based semiconductor devices.

[0008] As a preferred scheme for a hybrid energy storage SOP with heterogeneous devices, the AC / DC decoupling and coordinated control method is as follows: The process of acquiring the total DC bus voltage and performing outer-loop voltage control, then superimposing feedforward compensation to generate an inner-loop current reference value, includes: The total DC bus voltage is collected and compared with a given reference value. The deviation obtained from the comparison is sent to the voltage outer loop proportional-integral controller for adjustment to obtain the voltage outer loop control quantity. Detect power surge commands from the AC-side load and calculate the feedforward compensation current based on the power surge commands; The voltage outer loop control quantity is superimposed with the feedforward compensation current, and the resulting composite signal is used as the reference command for the battery current inner loop.

[0009] As a preferred scheme for a hybrid energy storage SOP with heterogeneous devices, the AC / DC decoupling and coordinated control method is as follows: The process of acquiring battery current and performing inner-loop current control, superimposing the steady-state reference duty cycle, and then limiting the amplitude to generate the global total duty cycle includes: The actual output current of the battery is collected, and the actual output current of the battery is compared with the current inner loop reference command. The deviation obtained from the comparison is sent to the current inner loop proportional-integral controller for adjustment to obtain the current inner loop control quantity. A constant physical steady-state reference duty cycle is directly superimposed at the output of the current inner loop proportional-integral controller; The composite signal after superimposing the steady-state reference duty cycle is sent to the limiter for limiting processing, and the signal output after limiting processing is used as the global total duty cycle. The global total duty cycle serves as a common-mode reference signal for the upper and lower half-bridges to jointly maintain the total DC bus voltage. The steady-state reference duty cycle is a constant duty cycle component preset based on the system's rated operating point.

[0010] As a preferred scheme for a hybrid energy storage SOP with heterogeneous devices, the AC / DC decoupling and coordinated control method is as follows: The process of acquiring and subtracting the voltages of the upper and lower capacitors, and then generating a midpoint error signal after timing enable processing, includes: The voltages of the upper and lower support capacitors on the DC side are collected separately, and the midpoint potential deviation signal is obtained by subtracting the voltages of the upper and lower support capacitors on the DC side. Acquire the timing enable signal characterizing the transient process of system power-on, and multiply the midpoint potential deviation signal with the timing enable signal; After the system is powered on and the DC bus voltage is in the nonlinear establishment phase, the timing enable signal is in the first state, forcibly shielding the midpoint potential deviation signal. After the system completes the bus voltage build-up and enters the steady-state stage, the timing enable signal switches to the second state, allowing the midpoint potential deviation signal to pass through, thus obtaining the enabled midpoint error signal.

[0011] As a preferred scheme for a hybrid energy storage SOP with heterogeneous devices, the AC / DC decoupling and coordinated control method is as follows: The process of multi-band resonance modulation and amplitude limiting of the midpoint error signal to generate a fine-tuned duty cycle includes: The enabled midpoint error signal is sent to the equalizing proportional-integral control branch, the fundamental frequency quasi-proportional resonant control branch and the characteristic harmonic quasi-proportional resonant control branch that are connected in parallel. Each quasi-proportional resonant control branch provides gain at its respective resonant frequency, thereby suppressing the error components at the corresponding frequency. After summing the outputs of each branch, the amplitude is limited to generate a fine-tuned duty cycle.

[0012] As a preferred scheme for a hybrid energy storage SOP with heterogeneous devices, the AC / DC decoupling and coordinated control method is as follows: The step of generating drive pulses based on the final duty cycle of the upper and lower bridge arms to control the on / off state of each switching transistor includes: The final duty cycle of the upper half-bridge is sent to the upper half-bridge pulse width modulation generator to generate the first set of drive pulses. The positive pulse in the first set of drive pulses drives the main switch of the upper half-bridge, and the negative pulse in the first set of drive pulses drives the auxiliary switch of the upper half-bridge. The final duty cycle of the lower half-bridge is sent to the lower half-bridge pulse width modulation generator to generate a second set of drive pulses. The positive pulse in the second set of drive pulses drives the main switch of the lower half-bridge, and the negative pulse in the second set of drive pulses drives the auxiliary switch of the lower half-bridge. When the midpoint potential shifts in the positive direction, the duty cycle is fine-tuned to a positive value. The final duty cycle of the upper half-bridge decreases, causing the output duty cycle of the upper bridge arm to decrease. The final duty cycle of the lower half-bridge increases, causing the output duty cycle of the lower bridge arm to increase, thus transferring the excess charge accumulated at the midpoint to the lower half-bridge.

[0013] Secondly, this invention provides a heterogeneous device hybrid energy storage SOP AC / DC decoupling cooperative control system, comprising: The physical connection establishment module is used to establish a physical connection channel at the midpoint of the AC / DC side shared capacitor; The voltage outer loop feedforward control module is used to collect the total voltage of the DC bus and perform voltage outer loop control, and generate the current inner loop reference value after superimposing the feedforward compensation. The current inner loop duty cycle generation module is used to collect the battery current and perform current inner loop control, superimpose the steady-state reference duty cycle and limit it to generate the global total duty cycle. The timing enable error extraction module is used to collect the voltage of the upper and lower capacitors and calculate the difference. After timing enable processing, a midpoint error signal is generated. The multi-band resonance adjustment module is used to perform multi-band resonance adjustment and amplitude limiting on the midpoint error signal, and generate a fine-tuning duty cycle. The cross-decoupling allocation module is used to cross-decouple and allocate the global total duty cycle and the fine-tuning duty cycle to obtain the final duty cycle of the upper and lower bridge arms. The drive pulse generation module is used to generate drive pulses based on the final duty cycle of the upper and lower bridge arms to control the on / off state of each switching transistor.

[0014] Thirdly, the present invention provides a computer device, comprising: Memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the heterogeneous device hybrid energy storage SOP AC / DC decoupling cooperative control method are implemented.

[0015] Fourthly, the present invention provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of a heterogeneous device hybrid energy storage SOP AC / DC decoupling cooperative control method.

[0016] The beneficial effects of this invention are as follows: This invention effectively solves the problem of uncontrolled midpoint potential divergence caused by zero-sequence current backflow in energy storage SOPs under extreme unbalanced loads, enabling the system to maintain stable operation even under harsh conditions such as single-phase heavy loads, avoiding frequent shutdowns due to excessive midpoint offset in traditional solutions. Through the decoupling control of the midpoint physical channel established by the three-level buck-boost topology and the asymmetric duty cycle, the system can actively suppress low-frequency oscillations of the midpoint potential to a very small fluctuation range, significantly improving the equipment's adaptability to complex load environments. This invention eliminates the impact of pulsating power generated by unbalanced loads on the DC bus, resulting in minimal DC total voltage drop and rapid recovery during large load step changes, ensuring power supply quality for sensitive loads. The three-level structure significantly reduces the voltage stress on the switching transistors, allowing the use of lower voltage-level power devices, significantly reducing the number and cost of high-voltage devices, and improving engineering economics. The hybrid configuration of SiC / Si heterogeneous devices concentrates high-frequency losses on the inner switching transistors, while the outer devices only handle power frequency conduction. This effectively balances the heat distribution of the bridge arms, reduces the size of the heat sink and filter inductor, and meets the engineering requirements of mobile SOP equipment for high power density and lightweight design. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is an overall flowchart of a heterogeneous device hybrid energy storage SOP AC / DC decoupling and collaborative control method provided by the present invention.

[0019] Figure 2 This is a hardware topology diagram of a dual-terminal flexible interconnect system integrating 3L-Buck-Boost, which is a heterogeneous device hybrid energy storage SOP AC / DC decoupling collaborative control method provided by the present invention.

[0020] Figure 3 This is a block diagram of the DC-side energy storage converter ripple elimination control method of the AC / DC decoupling collaborative control method of heterogeneous device hybrid energy storage SOP provided by the present invention.

[0021] Figure 4 This is a block diagram of the midpoint potential balance control of the DC-side energy storage converter in a heterogeneous device hybrid energy storage SOP AC / DC decoupling and collaborative control method provided by the present invention. Detailed Implementation

[0022] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0023] Example 1, referring to Figure 1 This is the first embodiment of the present invention, which provides a heterogeneous device hybrid energy storage SOP AC / DC decoupling cooperative control method, including: S1: Establish a physical connection channel at the midpoint of the shared capacitor on both AC and DC sides; S2: Collect the total DC bus voltage and perform voltage outer loop control, and generate the current inner loop reference value after superimposing the feedforward compensation; S3: Collect battery current and perform inner loop control, then limit the current after superimposing the steady-state reference duty cycle to generate the global total duty cycle; S4: Collect the voltage of the upper and lower capacitors and calculate the difference. After timing enable processing, generate the midpoint error signal. S5: Perform multi-band resonance adjustment and amplitude limiting on the midpoint error signal to generate a fine-tuning duty cycle; S6: Cross-decouple the global total duty cycle and the fine-tuning duty cycle to obtain the final duty cycle of the upper and lower bridge arms; S7: Generates drive pulses based on the final duty cycle of the upper and lower bridge arms to control the on / off state of each switching transistor.

[0024] It should be noted that, through steps S1-S7, this invention achieves highly robust self-sustaining operation of the AC / DC two-stage system under extreme unbalanced conditions. By establishing a physical connection channel at the midpoint of the shared capacitor on both the AC and DC sides, a path for active regulation of zero-sequence charge is fundamentally provided. The global total duty cycle is responsible for maintaining the stability of the total DC bus voltage, while the fine-tuning duty cycle is responsible for adjusting the voltage balance of the upper and lower capacitors. The two are cross-decoupled to achieve independent control of common-mode voltage regulation and differential-mode voltage leveling without interference. The timing enable processing forcibly shields the midpoint error signal during the nonlinear transient period of system startup voltage build-up, and enables the resonant regulation link after the bus voltage is stably established, completely eliminating the system divergence problem caused by integral saturation. The entire control strategy upgrades the DC side from a single energy storage interface to a core hub with both total voltage self-sustaining and active midpoint stabilization capabilities, freeing the AC-side dual-terminal converter from the DC voltage regulation task and giving it full-bandwidth active / reactive power independent scheduling capabilities, significantly improving the power flow regulation freedom and engineering reliability of the flexible interconnected system.

[0025] Example 2, refer to Figures 1-4As an embodiment of the present invention, based on the previous embodiment, a heterogeneous device hybrid energy storage SOP AC / DC decoupling cooperative control method is provided, comprising: In this embodiment, establishing the physical connection channel at the midpoint of the AC / DC side common capacitor in step S1 includes: The hybrid device energy storage intelligent soft-switching system with integrated three-level buck-boost converter provided in this embodiment includes a dual-ended converter on the AC side and a three-level buck-boost energy storage converter on the DC side.

[0026] The AC and DC sides share a common DC bus. The DC bus is composed of supporting capacitors C1 and C2 connected in series. The connection point of the two capacitors is led out to the DC physical midpoint O.

[0027] The AC side consists of two symmetrical converter units back to back, sharing a DC bus. Each converter includes three-phase power arms (a, b, and c) and a fourth arm. The neutral point output of the fourth arm is connected to the neutral line of the AC system via a neutral inductor to actively cancel the unbalanced zero-sequence current generated at the load end.

[0028] Each phase bridge arm consists of six power switching transistors Q1 to Q6. Q1, Q2, Q3, and Q4 are connected in series between the positive and negative DC buses. The collector of the outer upper transistor Q1 is connected to the positive DC bus, and the emitter is connected to the drain of the inner upper transistor Q2. The source of the inner upper transistor Q2 is connected to the AC output terminal of this phase. The drain of the inner lower transistor Q3 is connected to the AC output terminal, and the source is connected to the collector of the outer lower transistor Q4. The emitter of the outer lower transistor Q4 is connected to the negative DC bus. The collector of the upper clamping transistor Q5 is connected to the DC midpoint O, and the emitter is connected to the common connection point of Q1 and Q2. The collector of the lower clamping transistor Q6 is connected to the common connection point of Q3 and Q4, and the emitter is connected to the DC midpoint O.

[0029] The neutral line of the unbalanced load connected to the AC-side double-ended converter is directly connected to the DC-side physical neutral point O, thus opening the physical return path for the AC-side zero-sequence current. Figure 2 As shown.

[0030] The DC-side three-level buck-boost energy storage converter consists of a battery, a voltage divider inductor, and two half-bridges. The upper half-bridge includes switching transistors Q1 and Q2, and the lower half-bridge includes switching transistors Q3 and Q4. The main transistors Q2 and Q3, which are responsible for the main high-frequency switching operations, are silicon carbide MOSFETs, while Q1 and Q4, which are responsible for the power frequency freewheeling or clamping functions, are silicon IGBTs.

[0031] In this embodiment, the step S2 above, which involves acquiring the total DC bus voltage and performing outer-loop voltage control, and then generating an inner-loop current reference value by superimposing feedforward compensation, includes: Real-time acquisition of DC bus total voltage V dcThe difference between this value and the 800V reference setpoint is then fed into the voltage outer loop proportional-integral controller.

[0032] The feedforward compensation current I is calculated from the power surge command detected by the AC-side load. ff_ref The output of the voltage outer loop proportional-integral controller is added to the feedforward compensation current to generate the reference command I for the battery current inner loop. ref .

[0033] In this embodiment, the process of acquiring battery current and performing inner-loop current control in step S3, followed by limiting the steady-state reference duty cycle to generate the global total duty cycle includes: Collect the actual output current I of the battery L1 Compare it with the current inner loop reference command I ref The difference is then fed into the inner loop proportional-integral controller.

[0034] To avoid integral divergence during startup transients and eliminate algebraic loop dead loops, a constant physical steady-state reference duty cycle is directly superimposed on the output of the current inner-loop proportional-integral controller. The superimposed signal is then sent to a limiter. In this embodiment, the preferred limiting range is 0.1 to 0.9. The signal output after limiting is defined as the global total duty cycle D. total , refer to Figure 3 It serves as a common-mode reference for maintaining a total voltage of 800 volts between the upper and lower half-bridges.

[0035] In this embodiment, the step S4 above, which involves acquiring the voltage difference between the upper and lower capacitors and generating a midpoint error signal after timing enable processing, includes: Real-time acquisition of DC side capacitor voltage V C1 With lower capacitor voltage V C2 The midpoint potential deviation signal is obtained by subtracting the two, and the deviation signal is introduced into one end of the multiplier. The other end of the multiplier is connected to the step enable module.

[0036] The nonlinear transient time of system power-on is set to 0.25 seconds. Before 0.25 seconds, the step enable module output is 0, forcibly shielding the midpoint voltage error signal. After 0.25 seconds, the bus voltage has been established stably, the step enable module output jumps to 1, the error signal is enabled and released, and the midpoint error signal is obtained after enabling.

[0037] In this embodiment, step S5 above, which involves multi-band resonance adjustment and amplitude limiting of the midpoint error signal to generate a fine-tuned duty cycle, includes: The enabled midpoint error signal is sent to the equalizing proportional-integral controller, the 50 Hz quasi-proportional resonant controller, and the 150 Hz quasi-proportional resonant controller that are connected in parallel.

[0038] Among them, the 50 Hz and 150 Hz quasi-proportional resonant controllers provide extremely high gain at their respective resonant frequencies.

[0039] The outputs of the three controllers are summed and then limited to generate a fine-tuned duty cycle ΔD for suppressing zero-sequence reverse current, as referenced. Figure 4 .

[0040] In this embodiment, the global total duty cycle and the fine-tuned duty cycle are cross-decoupled and allocated in step S6 above to obtain the final duty cycle of the upper and lower bridge arms, including: The global duty cycle D total The fine-tuned duty cycle ΔD is fed into the subtractor to generate the final transmission duty cycle D of the upper half-bridge. up =D total -ΔD; simultaneously, the global total duty cycle D total The fine-tuned duty cycle ΔD is fed into the adder to generate the final transmission duty cycle D of the lower half-bridge. down =D total +ΔD.

[0041] This enables independent control where the global total duty cycle is responsible for maintaining the total bus voltage, and the fine-tuning duty cycle is responsible for adjusting the voltage balance of the upper and lower capacitors.

[0042] In this embodiment, step S7 above, which generates drive pulses based on the final duty cycles of the upper and lower bridge arms to control the on / off state of each switch, includes: The final wave emission duty cycle D of the upper half-bridge up The pulse width modulation generator is fed into the upper half-bridge, and the generated positive pulse directly drives the upper half-bridge main switch Q2. The pulse is then inverted by logic NOT and drives the upper switch Q1. The final wave emission duty cycle D of the lower half-bridge down The pulse width modulation generator sends the positive pulse to the lower half-bridge, which directly drives the main switch Q3 of the lower half-bridge. After being inverted by logic NOT, the pulse drives the freewheeling diode Q4, ensuring normal boost charging of the lower half-bridge and avoiding short-circuit positive feedback caused by polarity reversal.

[0043] Taking the example of a single-phase heavy load on the AC side causing a 50 Hz zero-sequence current to inject charge into the midpoint and resulting in a sudden rise in the voltage of the upper capacitor, the system is in the steady-state equilibrium stoking stage at this time, and the error is positive. The quasi-proportional resonance algorithm calculates the positive fine-tuning duty cycle ΔD.

[0044] It should be noted that, through the above cross-decoupling logic, the final duty cycle D of the upper half-bridge is... up This reduces the charging of the upper capacitor C1, ultimately decreasing the duty cycle D of the lower half-bridge. down This increases the charging of the lower capacitor C2, and the system actively transfers the excess charge accumulated at the midpoint O to the lower half-bridge, controlling the midpoint potential fluctuation within a very small range within milliseconds.

[0045] Example 3: The above is a schematic scheme of an AC / DC decoupling collaborative control method for a heterogeneous device hybrid energy storage SOP according to this embodiment. It should be noted that the technical solution of an AC / DC decoupling collaborative control system for a heterogeneous device hybrid energy storage SOP belongs to the same concept as the above-described AC / DC decoupling collaborative control method for a heterogeneous device hybrid energy storage SOP. Details not described in detail in the technical solution of the AC / DC decoupling collaborative control system for a heterogeneous device hybrid energy storage SOP in this embodiment can be found in the description of the above-described AC / DC decoupling collaborative control method for a heterogeneous device hybrid energy storage SOP.

[0046] This embodiment also provides a heterogeneous device hybrid energy storage SOP AC / DC decoupling cooperative control system, including: The physical connection establishment module is used to establish a physical connection channel at the midpoint of the AC / DC side shared capacitor; The voltage outer loop feedforward control module is used to collect the total voltage of the DC bus and perform voltage outer loop control, and generate the current inner loop reference value after superimposing the feedforward compensation. The current inner loop duty cycle generation module is used to collect the battery current and perform current inner loop control, superimpose the steady-state reference duty cycle and limit it to generate the global total duty cycle. The timing enable error extraction module is used to collect the voltage of the upper and lower capacitors and calculate the difference. After timing enable processing, a midpoint error signal is generated. The multi-band resonance adjustment module is used to perform multi-band resonance adjustment and amplitude limiting on the midpoint error signal, and generate a fine-tuning duty cycle. The cross-decoupling allocation module is used to cross-decouple and allocate the global total duty cycle and the fine-tuning duty cycle to obtain the final duty cycle of the upper and lower bridge arms. The drive pulse generation module is used to generate drive pulses based on the final duty cycle of the upper and lower bridge arms to control the on / off state of each switching transistor.

[0047] This embodiment also provides a computer device applicable to a heterogeneous device hybrid energy storage SOP AC / DC decoupling cooperative control method, including: The system includes a memory and a processor. The memory stores computer-executable instructions, and the processor executes these instructions to implement the AC / DC decoupling and coordinated control method for a heterogeneous device hybrid energy storage SOP proposed in the above embodiments.

[0048] This embodiment also provides a storage medium storing a computer program that, when executed by a processor, implements a heterogeneous device hybrid energy storage SOP AC / DC decoupling collaborative control method as proposed in the above embodiment.

[0049] The storage medium proposed in this embodiment belongs to the same inventive concept as the heterogeneous device hybrid energy storage SOP AC / DC decoupling collaborative control method proposed in the above embodiment. Technical details not described in detail in this embodiment can be found in the above embodiments, and this embodiment has the same beneficial effects as the above embodiments.

[0050] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for AC / DC decoupling and coordinated control of a heterogeneous device hybrid energy storage SOP, characterized in that, include: Establish a physical connection channel at the midpoint of the shared capacitor on both AC and DC sides; The total DC bus voltage is collected and the voltage outer loop control is performed. The current inner loop reference value is generated by superimposing the feedforward compensation. The battery current is collected and current inner loop control is performed. After superimposing the steady-state reference duty cycle, the amplitude is limited to generate the global total duty cycle. The voltages of the upper and lower capacitors are collected and the difference is calculated. After timing enable processing, a midpoint error signal is generated. Multi-band resonance adjustment and amplitude limiting are performed on the midpoint error signal to generate a fine-tuning duty cycle; The global total duty cycle and the fine-tuned duty cycle are cross-decoupled and allocated to obtain the final duty cycle of the upper and lower bridge arms; Drive pulses are generated based on the final duty cycle of the upper and lower bridge arms to control the on / off state of each switching transistor.

2. The method for AC / DC decoupling and coordinated control of a heterogeneous device hybrid energy storage SOP as described in claim 1, characterized in that, The establishment of a physical connection channel at the midpoint of the AC / DC side shared capacitor includes: A DC bus shared by AC and DC sides is provided. The DC bus is composed of an upper support capacitor and a lower support capacitor connected in series. The connection point of the two support capacitors is led out as the DC physical midpoint. A double-ended converter is set on the AC side. The double-ended converter consists of two sets of converter units connected back to back. Each set of converter units includes a three-phase power bridge arm and a fourth bridge arm. The neutral point of the fourth bridge arm is connected to the neutral line of the AC system via a neutral inductor. Each phase power bridge arm is composed of an upper outer switch, an upper inner switch, a lower inner switch, and a lower outer switch connected in series between the DC positive bus and the DC negative bus. An upper clamping tube is provided to connect the DC physical midpoint to the common connection point of the upper outer switch and the upper inner switch, and a lower clamping tube is provided to connect the DC physical midpoint to the common connection point of the lower inner switch and the lower outer switch. The AC-side load neutral line is directly physically connected to the DC physical neutral point to form a physical return path for zero-sequence current. A DC-side three-level buck-boost energy storage converter is provided. The DC-side three-level buck-boost energy storage converter consists of a battery, a voltage divider inductor, and upper and lower half-bridges. The upper half-bridge consists of an upper outer switch and an upper inner switch, and the lower half-bridge consists of a lower inner switch and a lower outer switch. The upper inner switch and the lower inner switch, which are responsible for high-frequency switching, are wide-bandgap semiconductor devices, while the upper outer switch and the lower outer switch, which are responsible for power frequency freewheeling or clamping, are silicon-based semiconductor devices.

3. The AC / DC decoupling and coordinated control method for a heterogeneous device hybrid energy storage SOP as described in claim 2, characterized in that, The process of acquiring the total DC bus voltage and performing outer-loop voltage control, then superimposing feedforward compensation to generate an inner-loop current reference value, includes: The total DC bus voltage is collected and compared with a given reference value. The deviation obtained from the comparison is sent to the voltage outer loop proportional-integral controller for adjustment to obtain the voltage outer loop control quantity. Detect power surge commands from the AC-side load and calculate the feedforward compensation current based on the power surge commands; The voltage outer loop control quantity is superimposed with the feedforward compensation current, and the resulting composite signal is used as the reference command for the battery current inner loop.

4. The AC / DC decoupling and coordinated control method for a heterogeneous device hybrid energy storage SOP as described in claim 3, characterized in that, The process of acquiring battery current and performing inner-loop current control, superimposing the steady-state reference duty cycle, and then limiting the amplitude to generate the global total duty cycle includes: The actual output current of the battery is collected, and the actual output current of the battery is compared with the current inner loop reference command. The deviation obtained from the comparison is sent to the current inner loop proportional-integral controller for adjustment to obtain the current inner loop control quantity. A constant physical steady-state reference duty cycle is directly superimposed at the output of the current inner loop proportional-integral controller; The composite signal after superimposing the steady-state reference duty cycle is sent to the limiter for limiting processing. The signal output after limiting processing is used as the global total duty cycle. The global total duty cycle serves as a common-mode reference signal for the upper and lower half-bridges to jointly maintain the total DC bus voltage. The steady-state reference duty cycle is a constant duty cycle component preset based on the system's rated operating point.

5. The AC / DC decoupling and coordinated control method for a heterogeneous device hybrid energy storage SOP as described in claim 4, characterized in that, The process of acquiring and subtracting the voltages of the upper and lower capacitors, and then generating a midpoint error signal after timing enable processing, includes: The voltages of the upper and lower support capacitors on the DC side are collected separately, and the midpoint potential deviation signal is obtained by subtracting the voltages of the upper and lower support capacitors on the DC side. Acquire the timing enable signal characterizing the transient process of system power-on, and multiply the midpoint potential deviation signal with the timing enable signal; After the system is powered on and the DC bus voltage is in the nonlinear establishment phase, the timing enable signal is in the first state, forcibly shielding the midpoint potential deviation signal. After the system completes the bus voltage build-up and enters the steady-state stage, the timing enable signal switches to the second state, allowing the midpoint potential deviation signal to pass through, thus obtaining the enabled midpoint error signal.

6. The AC / DC decoupling and coordinated control method for a heterogeneous device hybrid energy storage SOP as described in claim 5, characterized in that, The process of multi-band resonance modulation and amplitude limiting of the midpoint error signal to generate a fine-tuned duty cycle includes: The enabled midpoint error signal is sent to the equalizing proportional-integral control branch, the fundamental frequency quasi-proportional resonant control branch and the characteristic harmonic quasi-proportional resonant control branch that are connected in parallel. Each quasi-proportional resonant control branch provides gain at its respective resonant frequency, thereby suppressing the error components at the corresponding frequency. After summing the outputs of each branch, the amplitude is limited to generate a fine-tuned duty cycle.

7. The AC / DC decoupling and coordinated control method for a heterogeneous device hybrid energy storage SOP as described in claim 6, characterized in that, The step of generating drive pulses based on the final duty cycle of the upper and lower bridge arms to control the on / off state of each switching transistor includes: The final duty cycle of the upper half-bridge is sent to the upper half-bridge pulse width modulation generator to generate the first set of drive pulses. The positive pulse in the first set of drive pulses drives the main switch of the upper half-bridge, and the negative pulse in the first set of drive pulses drives the auxiliary switch of the upper half-bridge. The final duty cycle of the lower half-bridge is sent to the lower half-bridge pulse width modulation generator to generate a second set of drive pulses. The positive pulse in the second set of drive pulses drives the main switch of the lower half-bridge, and the negative pulse in the second set of drive pulses drives the auxiliary switch of the lower half-bridge. When the midpoint potential shifts in the positive direction, the duty cycle is fine-tuned to a positive value. The final duty cycle of the upper half-bridge decreases, causing the output duty cycle of the upper bridge arm to decrease. The final duty cycle of the lower half-bridge increases, causing the output duty cycle of the lower bridge arm to increase, thus transferring the excess charge accumulated at the midpoint to the lower half-bridge.

8. A heterogeneous device hybrid energy storage SOP AC / DC decoupled collaborative control system, using the method described in any one of claims 1-7, characterized in that, include: The physical connection establishment module is used to establish a physical connection channel at the midpoint of the AC / DC side shared capacitor; The voltage outer loop feedforward control module is used to collect the total voltage of the DC bus and perform voltage outer loop control, and generate the current inner loop reference value after superimposing the feedforward compensation. The current inner loop duty cycle generation module is used to collect the battery current and perform current inner loop control, superimpose the steady-state reference duty cycle and limit it to generate the global total duty cycle. The timing enable error extraction module is used to collect the voltage of the upper and lower capacitors and calculate the difference. After timing enable processing, a midpoint error signal is generated. The multi-band resonance adjustment module is used to perform multi-band resonance adjustment and amplitude limiting on the midpoint error signal, and generate a fine-tuning duty cycle. The cross-decoupling allocation module is used to cross-decouple and allocate the global total duty cycle and the fine-tuning duty cycle to obtain the final duty cycle of the upper and lower bridge arms. The drive pulse generation module is used to generate drive pulses based on the final duty cycle of the upper and lower bridge arms to control the on / off state of each switching transistor.

9. A computer device, characterized in that, include: Memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions, which, when executed by the processor, implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores computer-executable instructions that, when executed by a processor, implement the steps of the method according to any one of claims 1 to 7.

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