Bilateral DC fault ride-through method for non-isolated MMC converter

Abstract

The application provides a kind of double-side DC fault ride-through method of non-isolated MMDC converter, comprising: step 1: when detecting that the output voltage of low-voltage side is lower than 0.8 times of rated value and output current exceeds 1.2 times of normal output current, it is determined that low-voltage side has a fault; when detecting that the output voltage of high-voltage side is lower than 0.8 times of rated value and output current exceeds 1.2 times of normal output current, it is determined that high-voltage side has a fault; step 2: when detecting a fault, take two-stage current limiting measures of virtual damping and converter blocking to eliminate internal overcurrent risk; virtual damping control can be started in time, without waiting for fault detection; step 3: after blocking all switch signals, restore switch signals to generate fault criterion current, and judge the fault based on the active injection current of MMDC converter; step 4: if output voltage and current recover to preset value within preset time, it is considered that the fault is self-healing.

Description

Technical Field

[0001] This invention relates to the field of fault ride-through technology for DC-DC converters, and more specifically, to a dual-sided DC fault ride-through method for a non-isolated MMDC converter. Background Technology

[0002] High-voltage direct current (HVDC) transmission systems offer advantages such as fast control response and large transmission capacity, making them a significant strength in renewable energy transmission systems and considered the most effective technical solution. Renewable energy medium-voltage DC aggregation systems, utilizing high-voltage DC-DC converters, can achieve long-distance high-voltage transmission while enhancing system stability and efficiency, reducing costs, and meeting the centralized transmission needs of renewable energy.

[0003] As a "low-inertia" system, DC transmission systems face severe overcurrent and overvoltage threats when faults occur. The reliability of DC / DC converters is a decisive factor affecting the safe and stable operation of the renewable energy DC transmission system in which they operate. However, current theoretical research on complex faults in high-voltage DC-DC converters and their fault ride-through methods is still incomplete. These theoretical deficiencies and imperfect fault handling techniques mean that if a fault's impact exceeds expectations, it can trigger a chain reaction of failures, threatening the safety and stability of the transmission system.

[0004] The literature “A Hybrid Modular Multistage DC-DC Converter with DC Fault Ride-through Capability” includes a converter-blocking fault ride-through strategy based on the proposed topology. Its fault current suppression level depends on the sensitivity of the fault detection device and cannot actively control the fault current.

[0005] The literature "Two Fault Ride-Through Strategies for DAB Converters" includes a fault ride-through strategy based on converter lockout and a fault ride-through strategy based on auxiliary current-limiting inductors. The fault ride-through strategy based on converter lockout cannot actively control the fault current, and the level of fault current suppression depends on the sensitivity of the fault detection device. The fault ride-through strategy based on auxiliary current-limiting inductors adds extra auxiliary equipment, reducing system economy and increasing the probability of equipment failure. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the purpose of this invention is to provide a dual-sided DC fault ride-through method for non-isolated MMDC converters.

[0007] The dual-sided DC fault ride-through method for a non-isolated MMDC converter provided by the present invention includes the following steps:

[0008] Step 1, Fault Detection: When the converter is operating under rated conditions, the low-voltage side output voltage is V. dcL The output current is I dcLReliability coefficient K set Set to 1.2, when the low-voltage side output voltage is detected to be lower than 0.8 times the rated value and the output current exceeds 1.2 times the normal output current, a fault is determined to have occurred on the low-voltage side; when the high-voltage side output voltage is detected to be lower than 0.8 times the rated value and the output current exceeds 1.2 times the normal output current, a fault is determined to have occurred on the high-voltage side.

[0009] Step 2, Fault Current Limiting: When a fault is detected, current limiting measures are taken to eliminate the risk of internal overcurrent. Once a DC fault occurs, the virtual impedance current limiting measure is immediately activated. When the converter restarts, the virtual impedance control is cut off. When a DC fault is detected, the converter starts the blocking procedure and blocks the switch for a preset time.

[0010] Step 3, Fault Judgment Current: After blocking all switching signals, the switching signals are restored to generate a fault judgment current, and the fault is judged based on the active injection current of the MMDC converter.

[0011] Step 4, Fault Recovery: If the output voltage and current recover to the preset values ​​within the preset time, since the low-voltage side output current of the MMDC is I... dcL If the fault criterion current is set to 1.2 times the normal value, the fault is considered to be a self-healing fault, the DCCB will not operate, the switching signal will return to normal, and the circuit will be restored to power supply.

[0012] If the fault current continues to rise after the converter restarts, the fault is determined to still exist. At this time, the DC side of the MMDC immediately restarts the blocking procedure. After the fault deionization time, the MMDC is restarted again. If the DC voltage fails to recover successfully three times in a row, the fault is determined to be a permanent fault. The DC fault line is isolated by the DC circuit breakers at both ends of the fault line.

[0013] Based on the sampling time window requirements of the DC transmission protection system, the fault detection time is set to 2.5ms.

[0014] In a new energy DC power transmission system based on converter self-cleaning DC faults, the converter fault deionization time is set to 100ms; based on the coordination between MMDC and external DC line protection and the converter, the blocking time is set to 20ms-100ms according to different application scenarios.

[0015] The MMDC converter adopts a three-phase topology, which consists of three identical phase arms, each containing a series inductor L. arm Each phase bridge arm's output terminal is connected to the low-voltage side via a filter inductor L2. The upper bridge arm of the MMDC consists of a full-bridge submodule, and the lower bridge arm consists of a half-bridge submodule.

[0016] DC power is transmitted bidirectionally between DC links. If each bridge arm generates only one DC current, the energy stored in the submodule capacitor will be quickly depleted in one bridge arm and saturated in the other bridge arm of the same phase.

[0017] To alleviate the imbalance of the average capacitor voltage between the upper and lower bridge arm submodules, MMDC uses AC circulating current to achieve active AC power exchange between the upper and lower bridge arms and to offset the submodule capacitor voltage deviation caused by DC power.

[0018] The voltages of the upper and lower bridge arms are expressed as follows:

[0019]

[0020] Among them, v px,ac v px,dc V represents the AC and DC voltage components in the upper arm of the bridge. nx,ac v nx,dc This indicates the AC and DC voltage components in the lower bridge arm;

[0021] DC voltage components v of the upper and lower bridge arms px,dc and v nx,dc Represented as:

[0022]

[0023] Among them, V dcL This is the low-voltage side output voltage; V dcH This is the output voltage on the high-voltage side;

[0024] The DC current components of the upper and lower bridge arms are represented as follows:

[0025]

[0026] Where P is the output power of the converter, and P is positive when power flows from the high-voltage side to the low-voltage side;

[0027] According to the superposition principle, the currents of the upper and lower bridge arms under normal conditions are:

[0028]

[0029] Where, φ h and φ l I represents the phase angles of the AC components of the upper and lower bridge arm currents, respectively; h and I l These represent the amplitudes of the AC components of the upper and lower bridge arm currents, respectively; ω is the angular frequency, and t is the unit time.

[0030] To maintain power balance in the bridge arms, the AC component of the upper bridge arm must meet the following requirements:

[0031] P px,dc =-P px,ac

[0032] Right now:

[0033]

[0034] Among them, P px,dc and P px,ac These represent the DC active power and AC active power of the upper bridge arm, respectively.

[0035] The current limiting measures include two levels of current limiting: virtual damping control and MMDC converter interlocking control.

[0036] The principle of virtual damping control is to introduce a controllable voltage offset into the control loop of the MMDC converter to replace the actual impedance. When the MMDC converter system is in normal operation, the output current I across the DC voltage is... dc Since the current is constant DC, it flows entirely through the branch containing the reactance. The voltage drop across the additional virtual impedance is zero, meaning the output voltage ΔU of the virtual impedance element is zero. dc When the value is 0, the virtual impedance link has no effect; after a DC fault occurs, the DC current drops rapidly, generating a current offset, and the current limiting control is immediately activated.

[0037] The voltage offset is expressed as:

[0038] Δu=I dc L v s

[0039] Among them, L v The voltage inductance value is represented by s, and the complex frequency variable is represented by s.

[0040] This differential element is equivalent to:

[0041] G(s) = T D s

[0042] Where G(s) is the transfer function, T D Represents the differential time constant;

[0043] The virtual impedance value is corrected based on the actual situation:

[0044]

[0045] Where, k D It is the differential gain.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] This invention proposes a dual-sided DC fault ride-through strategy for a non-isolated MMDC converter, which can accurately identify temporary and permanent faults, enabling fault ride-through of temporary faults and clearing of permanent faults in the MMDC converter; it can actively control the peak value and decay time of the fault current in the bridge arm by adjusting the virtual impedance value according to different application scenarios; once a DC fault occurs, the current limiting measures can be activated immediately without waiting for fault detection. Attached Figure Description

[0048] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0049] Figure 1 For the application of DC-DC converters in new energy DC grids;

[0050] Figure 2 This is a traditional non-isolated DC-DC converter topology;

[0051] Figure 3 This is the current loop of a traditional non-isolated DC-DC converter;

[0052] Figure 4a and Figure 4b This is a block diagram of fault ride-through control for a traditional non-isolated DC-DC converter.

[0053] Figure 5a and Figure 5b This is the current flow path after the full-bridge submodule is locked out;

[0054] Figure 6 Fault ride-through flowchart for a traditional non-isolated DC-DC converter;

[0055] Figures 7a-7c Simulation of steady-state operation of a traditional non-isolated DC-DC converter;

[0056] Figures 8a-8c Simulation of high-voltage side fault ride-through strategy;

[0057] Figures 9a-9c Simulation of low-voltage side fault ride-through strategy. Detailed Implementation

[0058] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0059] Example

[0060] This invention addresses the limitations of existing converter fault ride-through strategies by proposing a dual-sided DC fault ride-through strategy for non-isolated MMDC converters based on a two-stage current-limiting control system using virtual impedance and converter blocking. This scheme has the ability to block dual-sided DC faults and effectively reduces the level of fault current in the converter arms.

[0061] This invention further optimizes and tunes the set virtual impedance value, enabling proactive limitation of fault current on both high and low voltage sides. Based on two-stage current limiting control, this invention introduces the fault ride-through timing and detailed operation of a non-isolated MMDC converter. The proposed fault ride-through strategy has advantages such as bidirectional control and instantaneous deployment. The proposed non-isolated MMDC converter fault ride-through strategy can achieve the following functions:

[0062] Fault interruption of MMDC converter with dual-sided DC fault;

[0063] It can actively control the peak value and decay time of fault current in bridge arm by adjusting the virtual impedance value according to different application scenarios;

[0064] In the event of a DC fault, current limiting measures can be activated immediately.

[0065] Figure 1 The diagram illustrates a typical application scenario of a modular multilevel DC-DC converter (MMDC) in a renewable energy transmission system. (The diagram is intended to...) Figure 1 The invention illustrates the principles of this operational scheme in the typical application scenarios shown, and verifies its effectiveness through simulation examples. This invention aims to solve the following problems:

[0066] The design incorporates a two-stage current limiting control system for the non-isolated MMDC converter. Under high-voltage and low-voltage DC faults, the MMDC converter can actively limit the current by adjusting the virtual impedance value to control the peak value and decay time of the fault current, thereby preventing converter damage.

[0067] The design of a fault ride-through strategy for a non-isolated MMDC converter in conjunction with a DCCB enables fault ride-through of temporary faults and clearing of permanent faults. This fault ride-through strategy effectively limits overcurrent in the MMDC converter arms and prevents the non-faulty DC grid from supplying DC short-circuit current to the faulty DC grid.

[0068] The technical solution claimed in this invention is aimed at non-isolated MMDC converters, and designs an active current limiting control and fault ride-through strategy for non-isolated MMDC converters with DC short-circuit fault clearing capability. In the following text, ... Figure 2 The traditional non-isolated MMDC converter topology is shown, and its specific technical implementation scheme is explained.

[0069] Working principle of traditional non-isolated MMDC converter

[0070] Figure 2 In the middle, V dcH V is the voltage on the high-voltage side. dcL This is the voltage on the low-voltage side. This topology consists of three identical phase bridge arms, each containing a series inductor L. arm The output terminal of each phase bridge arm is connected to the low-voltage side via a filter inductor L2. To provide sufficient negative voltage for DC faults on both the high-voltage and low-voltage sides, the upper bridge arm of the MMDC consists of a full-bridge submodule (FBSM), and the lower bridge arm consists of a half-bridge submodule (HBSM).

[0071] Power transfer between MMDC DC links can cause an imbalance in the average voltage of the upper and lower bridge arm submodule capacitors. DC power can be transferred bidirectionally between DC links. If each bridge arm generates only one DC current, the energy stored in the submodule capacitors will be rapidly depleted in one bridge arm and saturated in the other bridge arm of the same phase. Therefore, even if the submodule capacitor voltages within the same bridge arm remain balanced, the average voltage of the upper and lower bridge arm submodule capacitors will deviate from their nominal values.

[0072] To alleviate the imbalance in the average capacitor voltage of the upper and lower bridge arm submodules, MMDC utilizes AC circulating current to achieve active AC power exchange between the upper and lower bridge arms, and to offset the submodule capacitor voltage deviation caused by DC power. Figure 2 The traditional non-isolated DC-DC converter topology shown has the following internal AC / DC current circulation under normal operating conditions: Figure 3 As shown.

[0073] Among them, I dcH and I dcL This represents the current on the high and low voltage sides of the MMDC. In normal operation of the MMDC, the upper arm contains both DC and AC voltage components. V px,ac V px,dc (x∈{a,b,c}) represents the AC and DC voltage components in the upper bridge arm (denoted by the subscript "p"), V nx,ac V nx,dc (x∈{a,b,c}) represents the AC and DC voltage components in the lower arm (denoted by the subscript "n").

[0074] The voltages of the upper and lower bridge arms can be expressed as:

[0075]

[0076] Among them, the DC voltage components V of the upper and lower bridge arms px,dc and V nx,dc It can be represented as:

[0077]

[0078] The DC current components of the upper and lower bridge arms can then be expressed as:

[0079]

[0080] Where P is the converter output power, and P is considered positive when power flows from the high-voltage side to the low-voltage side. According to the superposition principle, the upper and lower bridge arm currents under normal conditions can be obtained as follows:

[0081]

[0082] Where φ h and φ l These represent the phase angles of the AC components of the upper and lower bridge arm currents, respectively. h and I l These represent the amplitudes of the AC components of the upper and lower bridge arm currents, respectively.

[0083] To maintain power balance in the bridge arms, the AC component of the upper bridge arm must satisfy the following equation:

[0084] P px,dc =-P px,ac (5)

[0085] Right now:

[0086]

[0087] Where P px,dc and P px,ac These represent the DC active power and AC active power of the upper bridge arm, respectively.

[0088] Two-stage current limiting control for non-isolated MMDC converters

[0089] Current limiting control 1, virtual impedance control: Theoretically, fault current can be reduced by increasing the inductance value in the equivalent circuit. However, in actual circuits, increasing impedance will affect the steady-state characteristics of the MMDC and increase the cost of the converter station itself. Therefore, it is considered to introduce a controllable voltage offset in the control loop of the MMDC to replace the actual impedance.

[0090] Adding a virtual impedance to the DC side has the practical effect of adding a voltage offset to the DC voltage component, and the control strategy is shown in Figure 4.

[0091] As shown in the control strategy diagram, when the MMDC converter system is in normal operation, the output current I across the DC voltage is... dcSince the current is constant DC, it flows entirely through the branch containing the reactance. The voltage drop across the additional virtual impedance is zero, meaning the output voltage ΔU of the virtual impedance element is zero. dc When the value is 0, the virtual impedance circuit has no effect. After a DC fault occurs, the DC current drops rapidly, generating a current offset, and the current limiting control can be activated immediately.

[0092] The voltage offset can be expressed as:

[0093] Δu=I dc L v s (7)

[0094] This differential element can be equivalent to:

[0095] G(s) = T D s (8)

[0096] The virtual impedance value is corrected based on the actual situation:

[0097]

[0098] The essence of the virtual impedance current limiting scheme is to bypass the capacitors of the submodules in the discharge phase during a fault by means of control, thereby limiting the discharge energy in the fault circuit at its source and reducing the DC short-circuit current. The value of the virtual impedance is related to the level of the fault current that needs to be controlled. According to the fault current limiting requirements of different systems, the virtual impedance value can be adjusted to meet the system's specified fault current peak value and decay time.

[0099] Current limiting control 2, interlocking control: On each bridge arm of the MMDC, the upper bridge arm is composed of stacked full-bridge submodules (FBSMs), and the lower bridge arm is composed of half-bridge submodules (HBSMs). FBSMs have DC-side fault clearing capability and, compared to HBSMs, have an additional negative level output function, making them more flexible in control.

[0100] As shown in Figure 5, when the full-bridge submodule is locked, all switches are in the off state. Regardless of the current direction of the submodule, the capacitors after the submodule is locked are in a charging state. The submodule provides a reverse electromotive force by increasing the capacitor voltage, thereby clearing the DC fault current. MMDCs configured with FBSM can achieve DC fault isolation and self-cleaning through FBSM lockout.

[0101] Fault ride-through process for non-isolated MMDC converters

[0102] The above analysis presents fault current limiting measures for MMDC (Multi-Mode DC) systems. The implementation of DC system fault ride-through strategies depends on the cooperation between DCCB (Digital Current Block) and MMDC. This invention proposes a fault ride-through (FRT) method based on MMDC. The FRT strategy includes the following four steps:

[0103] It detects short-circuit faults, eliminates overcurrent, provides fault criterion current to the faulty branch, and restores the fault.

[0104] This invention proposes a fault ride-through (FRT) method for MMDC (Multi-Mode DC Controller), taking a low-voltage side DC fault as an example: When a fault is detected, the MMDC first blocks the switching signal to eliminate internal overcurrent, then provides a fault criterion current to the faulty load branch. Finally, the faulty branch is disconnected by a circuit breaker to restore power supply. Its fault ride-through flowchart is as follows: Figure 6 As shown.

[0105] Step 1, Fault Detection: When the converter is operating under rated conditions, the low-voltage side output voltage is equal to V. dcL The output current is I dcL Considering a certain margin, the reliability factor K set The value is set to 1.2. Therefore, when the output voltage is detected to be lower than 0.8 times the rated value and the output current exceeds 1.2 times the normal output current, it can be determined that a fault has occurred on the low-voltage side.

[0106] To ensure sufficient sensitivity, the DC fault threshold can be set relatively low. As long as the fault state can be distinguished from the normal operating state, there is no need to locate the fault. According to the sampling time window requirements commonly set for DC transmission protection, the fault detection time is set to 2.5ms.

[0107] Step 2, Fault Current Limiting: Due to the unpredictable and random nature of faults, certain current limiting measures need to be taken to eliminate potential internal overcurrent risks when a fault is detected. Once a DC fault occurs, the virtual impedance current limiting measure is immediately activated. To avoid affecting the subsequent restart of the converter, the virtual impedance control is disconnected at this time. When a DC fault is detected, the converter initiates a blocking procedure and blocks the switch for a certain period of time.

[0108] In new energy DC transmission systems based on converter self-cleaning DC faults, the converter fault deionization time is typically set to 100ms. To facilitate rapid control and circuit recovery, and considering the coordination between the MMDC and external DC line protection and the converter, the blocking time can be set to 20ms-100ms depending on the application scenario.

[0109] Step 3, Fault Criterion Current: After blocking all switching signals, the switching signals must be restored to generate a fault criterion current. Fault judgment is based on the active injection current of the MMDC converter.

[0110] Step 4, Fault Recovery: If the output voltage recovers within a certain time and the current recovers to a certain value, since the low-voltage side output current of the MMDC is I... dcLIf the fault criterion current is set to 1.2 times the normal value, then the fault is considered a self-healing fault, which is possible in a distribution network. In this case, the DCCB does not operate, the switching signal returns to normal, and the circuit resumes power supply.

[0111] If the fault current continues to rise after the converter restarts, the fault is determined to persist. In this case, the DC side of the MMDC immediately restarts the blocking procedure, and after the fault deionization time, the MMDC is restarted again. If the DC voltage fails to recover after three consecutive attempts, the fault is determined to be permanent, and the DC faulty line is isolated using the DC circuit breakers at both ends of the faulty line.

[0112] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. To verify the technical solution proposed in this invention, a system model was established based on the PSCAD / EMTDC simulation environment.

[0113] Application scenario: 200-400kV DC transmission system

[0114] To verify the effectiveness of the fault ride-through strategy of MMDC under DC grid-side faults, an MMDC simulation system was built, employing a unipolar structure such as... Figure 1 The control method used is shown in Figure 4.

[0115] The MMDC in this simulation model adopts a three-phase topology, in which each phase circuit contains upper and lower bridge arms, and each bridge arm contains 200 sub-modules. The upper bridge arm adopts a full-bridge sub-module topology, and the lower bridge arm adopts a half-bridge sub-module topology. Detailed simulation parameters are shown in Table 1.

[0116] Table 1 MMDC Converter Parameters

[0117] System parameters Value <![CDATA[low-voltage side port voltage value V dcL > 200kV <![CDATA[High-side port voltage value V dcH > 400kV <![CDATA[System rated power P ref > 200MW <![CDATA[Number N of sub-modules on the upper bridge arm p > 200 <![CDATA[Number N of lower bridge arm submodules n > 200 <![CDATA[Upper arm submodule capacitance value C p > 1800μF <![CDATA[Lower arm submodule capacitance value C n > 3000μF <![CDATA[Filter inductor L2]]> 40mH <![CDATA[Arm inductor L arm > 70mH <![CDATA[Bridge arm resistor R arm > 1.2Ω Operating frequency f 150Hz

[0118] Simulation results

[0119] High-voltage side short-circuit fault: To more intuitively demonstrate the development of MMDC high-voltage side short-circuit faults and verify the correctness of the fault ride-through strategy proposed in the theoretical analysis, this invention uses the control method described above to simulate and verify MMDC high-voltage side short-circuit faults. The specific parameters of the simulation model are shown in Table 1, and a short-circuit fault is artificially constructed on the high-voltage DC grid side, with the fault time being 1 second.

[0120] Before the short circuit fault occurred, the MMDC was operating stably with a rated transmission power of 200MW (high voltage side voltage of 400kV and low voltage side voltage of 200kV). At 1 second, the short circuit fault occurred, the voltage of the high voltage side DC port dropped rapidly, and the current of the DC ports on both sides rose rapidly.

[0121] In Figure 7, a short-circuit fault occurs at 1 second. The current rises immediately after the fault, and the time to complete fault detection and IGBT start-up blocking strategy is approximately 2 ms. During these 2 ms, the fault current is in the virtual impedance current-limiting phase. After 2 ms, the converter blocking phase starts, and the fault current drops to 0 within 2 ms. After the fault, the high-voltage side voltage drops rapidly to near 0, while the low-voltage side voltage remains unaffected due to the fault isolation effect of the full-bridge submodule.

[0122] During a high-voltage side short circuit, the voltage across the upper bridge arm after locking is approximately -200kV, while the voltage across the lower bridge arm after locking is 200kV. The current readings from the upper and lower bridge arms indicate that the valve on the fault side is blocked during the fault, and the current through the converter is quickly brought back to normal.

[0123] The complete fault ride-through process is shown in Figure 7. After approximately 0.3 seconds, the MMDC returned to normal operation. During the fault ride-through, the peak arm current was approximately 2kA, which is still within the safe range, verifying the effectiveness of the proposed fault ride-through strategy.

[0124] Low-voltage side short-circuit fault: Similar to the high-voltage side short-circuit fault, a short-circuit fault is artificially created on the low-voltage DC grid side, and the fault time is 1 second.

[0125] The simulation results of the MMDC DC grid-side fault are shown in Figures 8 and 9. Before the short-circuit fault occurred, the MMDC was operating stably with a rated transmission power of 200MW (high voltage side voltage of 400kV and low voltage side voltage of 200kV). At 1 second, the short-circuit fault occurred, the low voltage side DC port voltage dropped rapidly, and the DC port current on both sides rose rapidly.

[0126] In Figure 8, a short-circuit fault occurs at 1 second. The current rises immediately after the fault, and the time to complete fault detection and IGBT start-up blocking strategy is approximately 2 ms. During these 2 ms, the fault current is in the virtual impedance current-limiting phase. After 2 ms, the converter blocking phase starts, and the fault current drops to 0 within 20 ms. After the fault, the low-voltage side voltage drops to near 0, but due to the fault isolation effect of the full-bridge submodule, the high-voltage side voltage is unaffected.

[0127] After a short circuit on the low-voltage side is blocked, the voltage across the upper bridge arm is approximately 400kV, while the voltage across the lower bridge arm is 0kV. The current in the upper and lower bridge arms indicates that the valve on the fault side was blocked during the fault, and the current through the converter was quickly brought back to normal.

[0128] The complete fault ride-through process is shown in Figure 8. After approximately 0.3 seconds, the MMDC returned to normal operation. During the fault ride-through, the peak arm current was approximately 3.5kA, which is still within the safe range, verifying the effectiveness of the proposed fault ride-through strategy.

[0129] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0130] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A method for dual-sided DC fault ride-through of a non-isolated MMDC converter, characterized in that, The two-stage current limiting strategy, employing virtual damping and converter blocking, includes the following steps: Step 1, Fault Detection: When the converter is operating under rated conditions, the low-voltage side output voltage is V. dcL The output current is I dcL Reliability coefficient K set Set to 1.2, when the low-voltage side output voltage is detected to be lower than 0.8 times the rated value and the output current exceeds 1.2 times the normal output current, a fault is determined to have occurred on the low-voltage side; when the high-voltage side output voltage is detected to be lower than 0.8 times the rated value and the output current exceeds 1.2 times the normal output current, a fault is determined to have occurred on the high-voltage side. Step 2, Fault Current Limiting: When a fault is detected, current limiting measures are taken to eliminate the risk of internal overcurrent. Once a DC fault occurs, the virtual impedance current limiting measure is immediately activated. When the converter restarts, the virtual impedance control is cut off. When a DC fault is detected, the converter starts the blocking procedure and blocks the switch for a preset time. Step 3, Fault Judgment Current: After blocking all switching signals, the switching signals are restored to generate a fault judgment current, and the fault is judged based on the active injection current of the MMDC converter. Step 4, Fault Recovery: If the output voltage and current recover to the preset values ​​within the preset time, since the low-voltage side output current of the MMDC is I... dcL If the fault criterion current is set to 1.2 times the normal value, the fault is considered to be a self-healing fault, the DCCB will not operate, the switching signal will return to normal, and the circuit will be restored to power supply. If the fault current continues to rise after the converter restarts, the fault is determined to still exist. At this time, the DC side of the MMDC immediately restarts the blocking procedure. After the fault deionization time, the MMDC is restarted again. If the DC voltage fails to recover successfully three times in a row, the fault is determined to be a permanent fault. The DC fault line is isolated by the DC circuit breakers at both ends of the fault line.

2. The dual-sided DC fault ride-through method for a non-isolated MMDC converter according to claim 1, characterized in that, Based on the sampling time window requirements of the DC transmission protection system, the fault detection time is set to 2.5ms.

3. The dual-sided DC fault ride-through method for a non-isolated MMDC converter according to claim 1, characterized in that, In a new energy DC power transmission system based on converter self-cleaning DC faults, the converter fault deionization time is set to 100ms; based on the coordination between MMDC and external DC line protection and the converter, the blocking time is set to 20ms-100ms according to different application scenarios.

4. The dual-sided DC fault ride-through method for a non-isolated MMDC converter according to claim 1, characterized in that, The MMDC converter adopts a three-phase topology, which consists of three identical phase arms, each containing a series inductor L. arm Each phase bridge arm's output terminal is connected to the low-voltage side via a filter inductor L2. The upper bridge arm of the MMDC consists of a full-bridge submodule, and the lower bridge arm consists of a half-bridge submodule. DC power is transmitted bidirectionally between DC links. If each bridge arm generates only one DC current, the energy stored in the submodule capacitor will be quickly depleted in one bridge arm and saturated in the other bridge arm of the same phase. To alleviate the imbalance of the average capacitor voltage between the upper and lower bridge arm submodules, MMDC uses AC circulating current to achieve active AC power exchange between the upper and lower bridge arms and to offset the submodule capacitor voltage deviation caused by DC power. The voltages of the upper and lower bridge arms are expressed as follows: Among them, v px,ac v px,dc V represents the AC and DC voltage components in the upper arm of the bridge. nx,ac v nx,dc This indicates the AC and DC voltage components in the lower bridge arm; DC voltage components v of the upper and lower bridge arms px,dc and v nx,dc Represented as: Among them, V dcL This is the low-voltage side output voltage; V dcH This is the output voltage on the high-voltage side; The DC current components of the upper and lower bridge arms are represented as follows: Where P is the output power of the converter, and P is positive when power flows from the high-voltage side to the low-voltage side; According to the superposition principle, the currents of the upper and lower bridge arms under normal conditions are: Where, φ h and φ l I represents the phase angles of the AC components of the upper and lower bridge arm currents, respectively; h and I l These represent the amplitudes of the AC components of the upper and lower bridge arm currents, respectively; ω is the angular frequency, and t is the unit time. To maintain power balance in the bridge arms, the AC component of the upper bridge arm must meet the following requirements: P px,dc =-P px,ac Right now: Among them, P px,dc and P px,ac These represent the DC active power and AC active power of the upper bridge arm, respectively.

5. The dual-sided DC fault ride-through method for a non-isolated MMDC converter according to claim 4, characterized in that, The current limiting measures include a two-stage current limiting strategy: virtual damping control and MMDC converter lockout control. The principle of virtual damping control is to introduce a controllable voltage offset into the control loop of the MMDC converter to replace the actual impedance. When the MMDC converter system is in normal operation, the output current I across the DC voltage is... dc Since the current is constant DC, it flows entirely through the branch containing the reactance. The voltage drop across the additional virtual impedance is zero, meaning the output voltage ΔU of the virtual impedance element is zero. dc When the value is 0, the virtual impedance link has no effect; after a DC fault occurs, the DC current drops rapidly, generating a current offset, and the current limiting control is immediately activated. The voltage offset is expressed as: Δu=I dc L v s Among them, L v The voltage inductance value is represented by s, and the complex frequency variable is represented by s. This differential element is equivalent to: G(s)=T D s Where G(s) is the transfer function, T D Represents the differential time constant; The virtual impedance value is corrected based on the actual situation: Where, k D It is the differential gain.

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