A pre-synchronization control method and system for a multi-inverter parallel system

Abstract

The application discloses a kind of pre-synchronization control method and system of multi-inverter parallel system, including phase pre-synchronization using the discrete step adjustment strategy based on grid cycle trigger, phase step can be adaptively adjusted, step increase and decrease are carried out by comparing phase index deviation, and the double-counting determination mechanism of lock-in count and lock-out count is introduced;Voltage pre-synchronization uses the multi-stage adaptive step adjustment strategy based on target voltage dead zone, output voltage is kept stable after entering dead zone, and voltage synchronization is determined by continuous counting;At the same time, phase voltage cross-check mechanism is set, one pre-synchronization condition fails, and the other side count is cleared, to avoid false synchronization;State interaction and coordinated control between main controller and each module are realized through CAN bus.The application does not need complex parameter setting, has the advantages of simple realization, strong anti-interference ability, no oscillation, high reliability, etc., and can be widely applied to modular UPS, microgrid inverter, energy storage converter and other parallel systems.

Description

Technical Field

[0001] This invention relates to the field of power electronic control technology, and in particular to a pre-synchronization control method and system for a multi-inverter parallel system. Background Technology

[0002] With the rapid development of distributed generation, microgrids, and uninterruptible power supply (UPS) systems, parallel operation of multiple inverters has become the mainstream technical solution for achieving high-capacity, high-reliability power supply. In parallel systems, before each inverter module is put into parallel operation, its output voltage amplitude, frequency, and phase must be completely consistent with the common bus or main unit. Otherwise, a huge inrush current will be generated at the moment of parallel connection, which may seriously damage power devices, trigger system protection, or even burn out equipment. Therefore, phase pre-synchronization and voltage pre-synchronization are key technologies for achieving safe and smooth parallel operation of multiple inverters.

[0003] Existing technology 1: Phase synchronization method based on phase-locked loop (PLL). Traditional PLLs detect the zero-crossing point of the grid voltage or instantaneous phase error and use a proportional-integral (PI) regulator to achieve phase tracking. Under good grid conditions and low harmonic content, this method has a certain synchronization accuracy and response speed. However, this method has the following prominent problems: (1) It is sensitive to grid harmonics and noise, and is prone to phase oscillation and lockout jitter; (2) The tuning of PI parameters depends on the system model, and the engineering debugging is complicated, making it difficult to balance dynamic response speed and steady-state accuracy; (3) When the grid frequency fluctuates, the dynamic tracking performance deteriorates, and phase loss is prone to occur; (4) It requires complex trigonometric function calculations, which places high demands on the computing power of the controller.

[0004] Existing technology 2: Phase synchronization method based on zero-crossing detection. Some technical solutions use grid voltage zero-crossing detection to trigger the synchronization signal, and adjust the inverter output phase by detecting the voltage zero-crossing point. This type of method has the following shortcomings: (1) There are often large harmonic interference and noise near the zero-crossing point, which can easily cause false triggering; (2) Synchronization adjustment can only be performed once in one cycle, and the adjustment speed is slow; (3) There is a lack of a continuous phase-locked state determination mechanism, and it is impossible to accurately determine whether synchronization is completed.

[0005] Existing technology 3: Voltage synchronization method based on PI regulation In terms of voltage pre-synchronization, existing technologies usually use PI controllers to perform closed-loop regulation of the output voltage amplitude, set the target voltage as a fixed reference value, and use the single entry into the error band range as the criterion for synchronization completion. This type of scheme has the following shortcomings: (1) The parameter design of the PI controller depends on the output impedance characteristics of the system. In the case of multiple modules in parallel and inconsistent line impedances, the parameter tuning is complicated and has poor adaptability; (2) Only the instantaneous voltage value entering the target range is used as the criterion, lacking the judgment of continuous stability. It is easy to cause misjudgment in the case of voltage sampling fluctuation or load disturbance; (3) There is no dead zone design in the voltage regulation process, which is easy to generate small oscillations near the target value, affecting the stability of the system; (4) In the multi-module parallel system, there is no unified voltage coordination mechanism, making it difficult to ensure the consistency of the output voltage amplitude of each module.

[0006] Existing Technology 4: Communication-Based Parallel Synchronization Methods. Some technical solutions utilize communication methods such as CAN bus to achieve inverter parallel synchronization. However, existing communication synchronization methods mostly focus on carrier synchronization or simple start-stop control, lacking a unified solution for discrete adjustment, state determination, and multi-module coordination during phase and voltage pre-synchronization. Specifically, existing methods do not disclose the combined technical features of "discrete phase index triggering + step-by-step index increment / decrement adjustment + lock-in / unlock dual-count locking determination," nor do they disclose the combined technical features of "step-by-step adjustment based on target voltage dead zone + continuous counting determination."

[0007] In summary, the existing technologies still have the following technical defects in the parallel pre-synchronization control of multiple inverters that need to be addressed: (1) Phase synchronization relies on continuous phase-locked loops or zero-crossing detection, and the convergence speed is limited by the fixed step size. The parameter tuning is complex, the anti-disturbance capability is weak, and the lock-in state judgment is unreliable. (2) Voltage synchronization adopts continuous PI control, which is prone to oscillation. The fixed step size is difficult to balance the convergence speed and steady-state accuracy. The single judgment criterion is unreliable and is easily affected by sampling noise. Phase and voltage synchronization are independent of each other, and a disturbance in one side can easily cause the other side to be falsely ready. (3) The phase and voltage pre-synchronization process lacks a unified discrete triggering and step adjustment mechanism, and the synchronization state management is imperfect. (4) There is a lack of communication-based collaborative pre-synchronization control between multiple modules, making it difficult to ensure that all modules are put into parallel operation after synchronization is completed. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention provides a pre-synchronization control method and system for a multi-inverter parallel system. Phase pre-synchronization employs an off-step adjustment strategy triggered by the grid cycle, which adaptively adjusts the phase step size by comparing phase index deviations. A dual-counting determination mechanism of lock-in and unlock counts is introduced to achieve rapid phase approximation and reliable locking. Voltage pre-synchronization uses a multi-level adaptive step adjustment strategy based on the target voltage dead zone. The output voltage remains stable after entering the dead zone, and voltage synchronization is determined by continuous counting. Simultaneously, a phase voltage cross-verification mechanism is set up; if one pre-synchronization condition fails, the count of the other is reset to zero, avoiding false synchronization.

[0009] The objective of this invention is achieved in one respect as follows: a pre-synchronization control method for a multi-inverter parallel system, comprising:

[0010] Phase pre-synchronization: The power grid phase is discretized into multiple phase index points. Phase adjustment is triggered at a preset fixed phase index point in each power grid cycle. Discrete step adjustment is performed based on the deviation between the current phase index and the reference phase index. The phase lock status is determined based on a dual counting mechanism of lock-in counter and unlock counter.

[0011] Voltage pre-synchronization: Set a target voltage dead zone, adjust in steps according to the deviation between the inverter output voltage and the target voltage dead zone, and determine the voltage synchronization status based on a continuous counting mechanism;

[0012] Phase-voltage cross-check: During the counting and judgment process of phase pre-synchronization and voltage pre-synchronization, the status of each other is monitored. If the other party fails to meet the synchronization condition during the counting accumulation period, the counter of the other party is cleared.

[0013] Multi-module collaborative operation: Each inverter module reports its synchronization status to the main controller via the CAN bus. After the main controller confirms that all online modules have completed phase and voltage synchronization, it issues a unified grid connection and closing command.

[0014] Furthermore, the phase pre-synchronization specifically includes:

[0015] Based on the power grid cycle, the power grid phase is discretized into N phase index points within each power grid cycle, where N is a positive integer greater than 100; a phase adjustment is triggered once at a preset fixed phase index point in each power grid cycle.

[0016] Obtain the phase deviation between the current inverter's phase index value and the reference phase index value;

[0017] When the phase deviation value is greater than 0, the current phase index value is decreased by a preset step size and the phase accumulator output is decreased simultaneously. When the phase deviation value is less than 0, the current phase index value is increased by a preset step size and the phase accumulator output is increased simultaneously. When the phase deviation value is equal to 0, the phase remains unchanged.

[0018] Set a phase lock-in counter and a phase unlock counter. When the absolute value of the phase deviation is less than or equal to the preset tolerance threshold for M consecutive power grid cycles, the phase lock flag is set. When the absolute value of the phase deviation is greater than the preset tolerance threshold for K consecutive power grid cycles, the phase lock flag is reset, where M≥3 and K≥3.

[0019] Furthermore, the phase pre-synchronization process employs a phase adaptive step size adjustment strategy, dividing the adjustment step size into multiple levels based on the absolute value of the phase deviation; when the absolute value of the phase deviation is greater than the first deviation threshold, a large adjustment step size is used to quickly converge the phase deviation; when the absolute value of the phase deviation decreases to between the tolerance threshold and the first deviation threshold, a medium step size is used; when the absolute value of the phase deviation is less than or equal to the tolerance threshold, a minimum step size is used; the minimum step size is 1 phase index point.

[0020] Furthermore, the voltage pre-synchronization specifically includes:

[0021] Collect the output voltage amplitude V of the inverter out Obtain the target voltage value V target Set the target voltage dead zone [V] target -ΔV dead V target +ΔV dead ], where the target voltage dead zone half-width ΔV dead >0;

[0022] When the output voltage amplitude V out When the voltage is below the lower limit of the target voltage dead zone, gradually increase the output voltage setpoint; when the output voltage amplitude V... out When the voltage exceeds the upper limit of the target voltage dead zone, gradually reduce the output voltage setpoint.

[0023] When the output voltage amplitude is within the target voltage dead zone for L consecutive sampling cycles, the voltage pre-synchronization is determined to be completed and the voltage synchronization flag is set, where L≥1000;

[0024] Furthermore, the voltage pre-synchronization process employs multi-level adaptive voltage step size adjustment; based on the absolute value of the voltage deviation and the target voltage dead zone half-width ΔV... dead The voltage adjustment step size is divided into at least three levels based on the multiple relationship; the larger the voltage deviation, the larger the selected voltage step size; the closer to the target voltage dead zone, the smaller the selected voltage step size; voltage adjustment is stopped after entering the target voltage dead zone.

[0025] Furthermore, the phase voltage cross-check specifically includes: continuously monitoring the phase lock flag during the process of voltage stabilization counter continuously accumulating and counting to determine voltage synchronization; if the phase lock flag is reset before the voltage stabilization counter reaches the voltage stabilization determination threshold, the voltage stabilization counter is cleared and voltage pre-synchronization counting is restarted; if the output voltage amplitude is detected to continuously deviate from the target voltage dead zone during the phase lock counter accumulation process, the phase lock counter is cleared and phase pre-synchronization is re-executed.

[0026] Furthermore, the multi-module collaboration and parallel operation specifically includes: each inverter module sending the phase lock flag and voltage synchronization flag to the main controller via the CAN bus; the main controller collecting the synchronization flags of all online modules; and when it is confirmed that all online modules have completed synchronization, issuing a unified grid connection command to put each inverter module into parallel operation and stopping the execution of the phase pre-synchronization process and voltage pre-synchronization process.

[0027] Another aspect of the objective of this invention is achieved as follows: a pre-synchronization control system for a multi-inverter parallel system, comprising at least two inverter modules, a main controller, and a CAN bus communication network;

[0028] The main controller collects the synchronization status of each module and issues a unified grid connection and closing command after all online modules have completed synchronization.

[0029] The CAN bus communication network is used to connect the main controller and each inverter module;

[0030] The inverter module includes a three-phase inverter bridge, an LC filter circuit, a voltage and current sampling circuit, and a slave controller; the slave controller is used to perform phase pre-synchronization process, voltage pre-synchronization process, phase-voltage cross-verification, and multi-module coordination and parallel operation.

[0031] Furthermore, the slave controller uses a TI TMS320F280025 DSP, and the master controller uses a TI TMS320F280039 DSP.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) The control architecture is simplified and the computing power requirement is greatly reduced: The present invention adopts a discrete step-by-step adjustment mechanism to replace the traditional proportional-integral (PI) continuous closed-loop control, which eliminates the need to build a phase-locked loop (PLL), perform complex coordinate transformations and trigonometric function calculations, and tune multiple sets of PI parameters. The slave controllers of each inverter module only need to achieve phase and voltage pre-synchronization through index comparison, integer addition and subtraction, and counter operations, which significantly reduces the algorithm complexity and processor computing power requirement, and can run efficiently on a low-cost embedded digital signal processor (DSP), shortening the engineering debugging cycle.

[0033] (2) The phase synchronization anti-interference capability is strong and the lock determination reliability is high. The present invention adopts a phase indexing mechanism based on the discrete power grid cycle and triggers the adjustment at a fixed phase indexing point that avoids the noise sensitive area of ​​the zero crossing point, which fundamentally eliminates the defects of zero crossing detection being susceptible to harmonic interference and noise false triggering. At the same time, by introducing a dual-counter hysteresis determination mechanism of lock-in counter and unlock counter, the phase lock flag is set or reset only when the phase deviation is stably within the tolerance range for multiple consecutive power grid cycles or continuously exceeds the tolerance range. This effectively filters out the phase jitter caused by power grid harmonics, sampling noise and instantaneous disturbances, and avoids the false lock or frequent unlock problems caused by single sampling misjudgment in the prior art.

[0034] (3) Balancing dynamic convergence speed and steady-state synchronization accuracy: In phase pre-synchronization, the present invention adopts an adaptive step size adjustment strategy, which automatically switches between large, medium and small adjustment step sizes according to the magnitude of the absolute value of the phase deviation. When the deviation is large, a large step size is used to quickly approach the reference phase, and when the deviation is close to the tolerance threshold, the minimum step size is switched to fine adjustment, thus achieving a balance between fast convergence and high accuracy. In voltage pre-synchronization, a multi-level adaptive voltage step size adjustment is adopted. The larger the voltage deviation, the larger the adjustment step size, and the smaller the step size is as close as possible to the target voltage dead zone. While ensuring fast voltage convergence, the contradiction between convergence speed and steady-state accuracy in fixed step size adjustment is avoided.

[0035] (4) Voltage synchronization without oscillation, steady-state determination is disturbance-resistant: The present invention introduces a target voltage dead zone in voltage pre-synchronization. When the inverter output voltage enters the dead zone range, the voltage setpoint regulation is stopped, which completely eliminates the high-frequency steady-state oscillation generated near the target voltage by the traditional PI controller in pursuit of zero error regulation. At the same time, a voltage stability determination mechanism based on long-term continuous counting is adopted. Voltage synchronization is determined to be completed only when the output voltage is stable in the dead zone for multiple consecutive sampling cycles. This effectively overcomes the shortcomings of the prior art, which uses a single entry into the error band as the synchronization criterion and is easily affected by sampling fluctuations and load disturbances. It significantly improves the anti-interference and reliability of voltage synchronization determination.

[0036] (5) Effectively eliminates false synchronization of single indicators and prevents parallel gate surge: This invention innovatively introduces a phase-voltage cross-verification mechanism, which monitors the phase lock status in real time during the voltage stability counter accumulation count and the voltage deviation status in real time during the phase lock counter accumulation count. Once an abnormal disturbance of another indicator is detected during the counting judgment stage of any indicator, the accumulation counter of this side is immediately cleared and the corresponding pre-synchronization process is re-executed. This mechanism fundamentally solves the problem of false synchronization readiness caused by the independent phase synchronization and voltage synchronization and lack of collaborative verification in the prior art, which results in "one indicator being temporarily qualified while the other indicator is actually unstable". It effectively avoids the risk of parallel gate surge current and power device damage caused by false synchronization.

[0037] (6) Good consistency of multi-module coordination and no circulating current in parallel operation: This invention constructs a status interaction network between the main controller and each inverter module through a CAN bus. Each module reports its local phase lock flag and voltage synchronization flag to the main controller in real time. The main controller only issues a grid-connected closing command after confirming that all online modules have completed phase and voltage pre-synchronization simultaneously. This coordination mechanism ensures the consistency of each inverter module in terms of synchronization completion and operation sequence, avoiding the closing sequence differences and parallel circulating current impacts caused by independent judgment and separate reporting by each module in the prior art.

[0038] (7) Excellent anomaly handling and strong self-healing capability: The present invention sets up a multi-level anomaly detection and protection mechanism covering communication timeout, voltage over-limit, phase loss and module failure. When any anomaly occurs during the pre-synchronization process, the corresponding synchronization flag and counter are automatically reset, grid connection is prohibited, and the pre-synchronization process is automatically restarted after the anomaly is eliminated. It can be restored to the standby synchronization state without manual intervention, which significantly improves the operational reliability and maintainability of the parallel system under harsh working conditions.

[0039] (8) Strong engineering applicability, topology and power level independence: The pre-synchronization control method of the present invention does not depend on specific inverter topology, power level or line impedance parameters, and does not require complex retuning of control parameters for different numbers of parallel modules or grid conditions. It can be widely applied to modular uninterruptible power supplies (UPS), microgrid inverters, energy storage converters and other multi-machine parallel operation scenarios, and has good versatility and scalability. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0041] Figure 1 This is a schematic flowchart of the phase pre-synchronization control method of the present invention.

[0042] Figure 2 This is a schematic flowchart of the voltage pre-synchronization control method of the present invention.

[0043] Figure 3 This is a waveform diagram of the phase pre-synchronization experiment in an embodiment of the present invention.

[0044] Figure 4 This is an overall architecture diagram of the multi-inverter parallel pre-synchronization system of the present invention.

[0045] Figure 5 This is a schematic diagram of the phase index generation and triggering timing of the present invention.

[0046] Figure 6 This is a schematic diagram of the CAN bus communication protocol frame format of the present invention.

[0047] Figure 7 This is a flowchart illustrating the multi-module synchronous state coordination and parallel operation process of the present invention.

[0048] Figure 8 This is a flowchart of the phase-voltage cross-verification logic of the present invention.

[0049] Symbol name:

[0050]

[0051]

[0052]

[0053] Detailed Implementation

[0054] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] The method of this invention employs a phase pre-synchronization strategy based on the discrete phase index of the power grid cycle and a step-type voltage pre-synchronization strategy based on the target voltage dead zone; and adds phase-voltage cross-verification; in a multi-inverter parallel system, each module sequentially executes the following control steps before being put into parallel operation:

[0056] Step 1) System Initialization and Status Self-Check: After power-on, the system initializes the control parameters, counters, and communication interfaces of each inverter module. The status detection unit monitors the operating status, fault signals, and communication connection status of each module in real time. When a module is detected to be in standby or fault state, the phase synchronization flag, voltage synchronization flag, and related counters are reset, and entry into the pre-synchronization process is prohibited; when all modules to be connected in parallel are detected to be in normal standby state and without faults, the pre-synchronization control process is enabled.

[0057] Step 2) Phase Index Discretization: The slave controller of each inverter module generates a sinusoidal phase index using a fixed-frequency timer interrupt. Let the grid frequency be f. ac The timer interrupt frequency is f int Then the number of phase index points in each power grid cycle is N = f int / f ac The phase accumulator accumulates a fixed step size in each interrupt cycle, and wraps back to 0 when the accumulated value exceeds 2π. The phase index value Index = floor (phase accumulator output / (2π) × N), and its value ranges from 0 to N-1.

[0058] Step 3) Phase pre-synchronization discrete triggering: Within each grid cycle, when the inverter's phase index value reaches a preset fixed trigger value, the phase synchronization triggering unit generates a synchronization enable signal, setting the synchronization enable flag Syn_En_Flag. This triggering mechanism ensures that phase correction is performed only at fixed discrete phase points, avoiding system oscillations caused by continuous adjustment, and also avoiding harmonic interference regions near zero crossings.

[0059] Step 4) Phase Deviation Calculation: When the synchronization enable flag is valid, the phase deviation calculation unit obtains the current inverter's phase index value Index_cur and the reference phase index value Index_ref (usually the host phase or common bus phase) from the communication network. Considering index wrap-around, the phase deviation ΔP is calculated; the sign of ΔP indicates whether the current phase is leading (positive) or lagging (negative) relative to the reference phase, and |ΔP| indicates the magnitude of the phase difference (in index points).

[0060] Step 5) Phase Correction Based on Steps: Adaptive phase step size adjustment is adopted. The phase step adjustment unit executes an adjustment strategy based on the phase deviation ΔP: Multiple step sizes are divided according to the absolute value of the phase deviation; when the absolute value of the phase deviation is greater than the first deviation threshold, a large adjustment step size is used to quickly reduce the phase deviation; when the phase deviation is between the tolerance threshold T and the first deviation threshold, a medium step size is used; when the absolute value of the phase deviation is ≤ the tolerance threshold T, the minimum step size is used (preferably 1 index point). When ΔP>0 (phase leading), the phase index is decreased by the selected step size, and the phase accumulator is decreased simultaneously; when ΔP<0 (phase lagging), the phase index is increased by the selected step size, and the phase accumulator is increased simultaneously; when ΔP=0, it remains unchanged.

[0061] Step 6) Phase Tolerance Determination and Dual Counter Update: The phase tolerance determination unit compares the deviation between the corrected phase index and the reference phase index with a preset tolerance threshold T. Two counters are set: Phase Lock Counter Count_Lock: records the number of grid cycles in which the phase deviation is continuously within the tolerance range; Phase Unlock Counter Count_Unlock: records the number of grid cycles in which the phase deviation is continuously outside the tolerance range. When |ΔP| ≤ T, the phase is determined to have entered the synchronization tolerance range: Count_Unlock is cleared, Count_Lock is incremented, and the counter is limited to its upper limit; when |ΔP| > T, the phase is determined to have deviated from the tolerance range: Count_Lock is cleared, Count_Unlock is incremented, and the counter is limited to its upper limit. At the end of each grid cycle, the synchronization enable flag Syn_En_Flag is reset to avoid repeated triggering of phase adjustment within the same cycle.

[0062] Step 7) Phase Locking Status Determination Locking Condition: When Count_Lock continuously reaches the preset locking threshold M, the phase is determined to be in a locked state, and the phase synchronization completion flag Phase_Locked = 1 is set; Unlocking Condition: When Count_Unlock continuously reaches the preset unlocking threshold K, the phase is determined to be unlocked, and the phase synchronization completion flag Phase_Locked = 0 is reset.

[0063] Step 8) Voltage Sampling and Validity Judgment: The voltage sampling unit collects the output voltage amplitude V of each inverter module at a fixed period. out If the module is fault-free and in operation, it enters voltage pre-synchronization; if there is an abnormality, the voltage synchronization flag and voltage stabilization counter are reset, and voltage regulation is prohibited.

[0064] Step 9) Stepped adjustment based on the target voltage dead zone; using a multi-level adaptive voltage step size, the voltage stepping adjustment unit will adjust the output voltage amplitude V outCompare with the target voltage range; target range [Vt] arget -ΔV dead V target +ΔV dead Based on voltage deviation and dead zone half-width ΔV dead The voltage step size should be divided into at least three ranges; the larger the voltage deviation, the larger the step size; the closer to the dead zone, the smaller the step size; when V out < V target -ΔV dead Increase the voltage setpoint by the selected step size and reset the voltage stabilization counter Count_VolStable; when V out > V target +ΔV dead : Decrease the voltage setpoint by the selected step size and reset the voltage stability counter Count_VolStable; When the voltage falls into the dead zone: Keep the voltage setpoint unchanged and the voltage stability counter starts to accumulate.

[0065] Step 10) Voltage synchronization status determination: if the output voltage is within the dead zone, Count_VolStable increments; if it deviates from the dead zone, the counter is cleared; when Count_VolStable reaches the threshold L, the voltage synchronization flag Vol_Synced=1 is set.

[0066] Step 11) Phase-voltage cross-verification: The cross-verification unit continuously performs two monitoring tasks in parallel: ① If the phase lock flag Phase_Locked changes from set to reset while the voltage stability counter Count_VolStable has not yet reached the threshold L, then Count_VolStable is directly cleared and the voltage pre-synchronization count is restarted; ② If the output voltage continuously deviates from the target voltage dead zone during the accumulation of the phase lock count Count_Lock, then Count_Lock is cleared and the phase pre-synchronization count is restarted.

[0067] Step 12) Multi-module collaboration and parallel connection: When an inverter module simultaneously satisfies phase locking (Phase_Locked = 1) and voltage synchronization completion (Vol_Synced = 1), the module broadcasts its synchronization completion status to the main controller via the CAN bus. The main controller collects the synchronization status of all modules to be connected in parallel; after confirming that all online modules have completed pre-synchronization, it issues a unified grid connection closing command, closes the grid connection switch, and engages in parallel connection; after parallel connection, the pre-synchronization algorithm is disabled, and the droop / constant voltage and constant frequency normal control mode is switched. If communication interruption, voltage exceeding limit, or module failure occurs during the pre-synchronization process, the module reports the fault; the main controller prohibits closing, and the module re-enters the pre-synchronization process after the fault is cleared.

[0068] Step 13) Anomaly Handling and Recovery Mechanism: The system is equipped with a comprehensive anomaly handling mechanism, including communication anomaly detection, voltage over-limit protection, phase loss protection, and automatic restart of the pre-synchronization process after anomaly is resolved.

[0069] This invention provides a specific embodiment: System overall architecture:

[0070] like Figure 4 As shown, this embodiment uses a parallel system of four 30 kW three-phase T-type three-level inverters as an example. The system includes inverter modules PSU1~PSUn (n≥2), a main controller, a CAN bus communication network, and a common load.

[0071] Each inverter module includes a three-phase inverter bridge, an LC filter circuit, a voltage and current sampling circuit, and a slave controller (using a TI TMS320F280025 DSP). The master controller (using a TI TMS320F280039 DSP) connects to each slave controller via a CAN bus (CAN2.0B, 500 kbps baud rate) to coordinate the pre-synchronization process and parallel connection control of each module. The output of each module is connected to the AC bus (400 V / 50 Hz) to supply power to the common load.

[0072] After the system powers on, each inverter module enters standby mode. The main controller broadcasts a pre-synchronization command to all slave controllers via the CAN bus. Each slave controller independently performs phase pre-synchronization, voltage pre-synchronization, and phase-voltage cross-checking locally. Once the local phase lock flag (Phase_Locked) and voltage synchronization flag (Vol_Synced) are both set, the slave controller reports the synchronization status to the main controller via the CAN bus. The main controller polls the status of each module every 20 ms. Only after confirming that all online modules have completed synchronization does it issue a grid-connection closing command, closing the grid-connection switch to initiate parallel operation.

[0073] Phase index discretization and fixed-point triggering: such as Figure 5 As shown, this embodiment uses a fixed-frequency timer interrupt to generate a sinusoidal wave phase index. Let the power grid frequency f be... ac = 50 Hz, timer interrupt frequency f int = 16 kHz, then the number of phase index points N in each power grid cycle is N = f int / f ac= 320. The phase accumulator accumulates a fixed step size of 2π / N in each interrupt cycle, and wraps back to 0 when the accumulated value exceeds 2π. The phase index value SinValue_Index = floor(phase accumulator output / (2π) × N), with a value range of 0 to 319. Each index point corresponds to 1.125° electrical angle, and a total of 320 phase index points are contained in one power grid cycle (20ms).

[0074] Within each grid cycle, when the inverter's phase index value reaches a preset fixed trigger value of 10 (corresponding to approximately 11.25°, avoiding the zero-crossing noise sensitive area near index 0), the phase synchronization trigger unit generates a synchronization enable signal, setting the synchronization enable flag Syn_En_Flag = 1. This triggering mechanism ensures that phase correction is performed only at fixed discrete phase points, avoiding system oscillations caused by continuous adjustment, and also avoiding harmonic interference areas near the zero-crossing point. Syn_En_Flag is reset at the end of each grid cycle to prevent repeated triggering within the same cycle.

[0075] Phase pre-synchronization control methods: such as Figure 1 As shown, the phase pre-synchronization control method includes the following steps:

[0076] When the synchronization enable flag Syn_En_Flag is valid, the phase deviation calculation unit obtains the current inverter's phase index value SinValue_Index (denoted as Index_cur) and the reference phase index value CounterofSyn (denoted as Index_ref, usually the host phase or common bus phase) from the communication network. Considering index wrap-around, the phase deviation ΔP is calculated; the sign of ΔP indicates whether the current phase is leading (positive) or lagging (negative) relative to the reference phase, and |ΔP| indicates the magnitude of the phase difference (in index points).

[0077] The phase step adjustment unit executes an adjustment strategy based on the phase deviation ΔP. This embodiment employs a phase adaptive step size adjustment strategy: dividing the adjustment into three levels based on the absolute value of the phase deviation. Let the tolerance threshold T = 3 index points, and the first deviation threshold be 8 index points.

[0078]

[0079] When ΔP > 0 (phase leading), decrease the phase index by the selected step size, and simultaneously decrease the phase accumulator; when ΔP < 0 (phase lagging), increase the phase index by the selected step size, and simultaneously increase the phase accumulator; when ΔP = 0, it remains unchanged.

[0080] The phase tolerance determination unit compares the deviation between the corrected phase index and the reference phase index with the tolerance threshold T. Two counters are set: a phase lock-in counter (Count_Lock) records the number of grid cycles in which the phase deviation is continuously within the tolerance range; and a phase unlock counter (Count_Unlock) records the number of grid cycles in which the phase deviation is continuously outside the tolerance range.

[0081] When |ΔP| ≤ T, the phase is determined to be within the synchronization tolerance range: Count_Unlock is cleared to zero, Count_Lock is incremented, and the counter is limited to the upper limit. When |ΔP| > T, the phase is determined to be outside the tolerance range: Count_Lock is cleared to zero, Count_Unlock is incremented, and the counter is limited to the upper limit.

[0082] Locking condition: When Count_Lock continuously reaches the preset locking threshold M = 3, the phase is determined to be in a locked state, and the phase synchronization completion flag Phase_Locked = 1 is set.

[0083] Unlock condition: When Count_Unlock continuously reaches the preset unlock threshold K = 3, the phase is determined to be unlocked, and the phase synchronization completion flag Phase_Locked = 0 is reset.

[0084] Voltage pre-synchronization control methods: such as Figure 2 As shown, the voltage pre-synchronization control method includes the following steps:

[0085] The voltage sampling unit acquires the inverter output voltage amplitude V with a grid cycle (20 ms). out When the module is fault-free and in operation, it enters voltage pre-synchronization; if there is an abnormality, the voltage synchronization flag Vol_Synced and the voltage stability counter Count_VolStable are reset, and voltage regulation is disabled.

[0086] The voltage stepping adjustment unit will output voltage amplitude V out With the target voltage range [V target − ΔV dead V target + ΔV dead Comparison. In this embodiment, the target voltage value V target = 326 V, dead zone half-width ΔV dead = 0.1V, meaning the dead zone range is 325.9 V ~ 326.1 V.

[0087] This embodiment employs multi-level adaptive voltage step size adjustment, based on the absolute value of the voltage deviation and the dead zone half-width ΔV. deadThe voltage step size is divided into three levels based on the multiple relationship:

[0088]

[0089] When V out < V target - ΔV dead When the voltage is increased by the selected step size, the voltage stabilizer counter Count_VolStable is reset; when V out > V target + ΔV dead When the voltage is in the dead zone, the voltage setpoint is reduced by the selected step size, and Count_VolStable is reset; when the voltage falls into the dead zone, the voltage setpoint remains unchanged, and Count_VolStable starts to accumulate.

[0090] Voltage synchronization status determination: When the output voltage is within the dead zone, Count_VolStable increments; when it deviates from the dead zone, the counter is reset to zero. When Count_VolStable reaches the threshold L = 1500 (corresponding to 30s), the voltage synchronization flag Vol_Synced = 1 is set.

[0091] Meanwhile, the system continuously performs voltage over-limit detection: if V out If the voltage exceeds the allowable range (e.g., 324 V ~ 328 V), fault protection will be triggered, Vol_Synced will be reset, and grid connection will be prohibited.

[0092] Phase-voltage cross-checking mechanism: such as Figure 8 As shown, the cross-validation unit continuously executes two monitoring functions in parallel:

[0093] Condition 1: If the phase lock flag Phase_Locked changes from set to reset while the voltage stability counter Count_VolStable has not yet reached the threshold L, then Count_VolStable is cleared directly and the voltage pre-synchronization count is restarted.

[0094] Condition 2: During the accumulation process of the phase lock counter Count_Lock, if the detected output voltage amplitude V out Continuous deviation from the target voltage dead zone [V target - ΔV dead V target + ΔV dead If ], then Count_Lock is cleared and the phase pre-synchronization count is re-accumulated.

[0095] Verification passed: Both Phase_Locked and Vol_Synced flags remain valid and stable, allowing grid connection and closing.

[0096] Verification failed: If any trigger condition is activated, the corresponding pre-synchronization process will be re-executed.

[0097] This cross-validation mechanism fundamentally solves the problem of false synchronization and readiness caused by a single indicator being temporarily qualified while another indicator is disturbed.

[0098] CAN bus communication protocol and multi-module collaborative deployment: As shown in Figure 6, this embodiment adopts the CAN 2.0B extended frame format. The 29-bit identifier is allocated as follows: Bits 28-26 are reserved bits (fixed to 001); bits 25-18 are the source address (sender address, 1 for master, 16-19 for slave); bits 17-10 are the destination address (receiver address, 255 for broadcast address); bit 9 is the PTP flag (0 for broadcast, 1 for point-to-point); bits 8-0 are the protocol number (fixed to 0x69).

[0099] The 8-byte data field is defined as follows: Byte 0 is errType (error type); Byte 1 is msgType + err (bit 7 is the err flag, bits 6~0 are the message type); Bytes 2~3 are valueType (parameter ID, 16 bits); Bytes 4~7 are data (parameter value, little endian).

[0100] The main message types include: 0x01 (query parameters, master → slave), 0x03 (set parameters / broadcast), 0x05 (slave reports power data), 0x06 (slave reports voltage data), 0x10 (phase synchronization trigger), and 0x20 (voltage synchronization trigger).

[0101] like Figure 7 As shown, the main controller performs multi-module synchronization status coordination every 20 ms in its main loop. The main controller polls the operating status of each module, counting the number of online modules (online_cnt) and the number of synchronization-ready modules (sync_ready_cnt) (i.e., the number of modules with Phase_Locked = 1 and Vol_Synced = 1). If online_cnt > 0 and sync_ready_cnt == online_cnt, a unified grid connection closing command is broadcast via the CAN bus, closing the grid connection switch, and all modules are put into parallel operation.

[0102] If communication interruption, voltage over-limit, or module failure occurs during the pre-synchronization process, the module reports the fault, and the main control prohibits closing the circuit breaker; after the fault is cleared, the module re-enters the pre-synchronization process.

[0103] Experimental verification: such as Figure 3 The figure shows the experimental waveforms obtained using the phase pre-synchronization method of this invention. CH1 is the master phase index waveform (reference phase), CH2 is the slave phase index waveform (tracking phase), CH3 is the phase deviation waveform (ΔP), and CH4 is the phase lock flag waveform (Phase_Locked). The horizontal axis represents the time axis (20 ms / division, corresponding to one power grid cycle), and the vertical axis represents the waveform amplitude of each channel (phase index value / lock flag status).

[0104] At the initial stage of the experiment, the slave phase lagged behind the master phase by approximately 30°. At time t1 (synchronization trigger point, index value = 10, avoiding zero crossings), the slave controller initiated adaptive step size adjustment. Due to the large initial deviation, the system initially used a large step size (4 index points) for rapid convergence; as the deviation decreased, it gradually switched to a medium step size (2 index points) and then a minimum step size (1 index point). After approximately 3 grid cycles (60 ms) of step adjustment, at time t_lock, the slave phase gradually approached and finally locked to the master phase, and the phase lock flag Phase_Locked was set. After locking, the phase deviation was less than ±1 index point (corresponding to approximately ±1.125°). The entire adjustment process was smooth, with no overshoot oscillations.

[0105] In the voltage pre-synchronization experiment, the output voltage enters the target voltage dead zone (325.9 V ~ 326.1 V) after approximately 2 seconds of step adjustment, and the voltage stability counter Count_VolStable begins to accumulate; after approximately 30 seconds, it reaches the threshold of 1500, and the voltage synchronization flag Vol_Synced is set. After the output voltage enters the dead zone, the system no longer performs voltage setpoint adjustment, effectively avoiding steady-state oscillations common in traditional PI control.

[0106] Under harsh operating conditions (grid containing 15% harmonic interference and sampling noise), the present invention combines adaptive step size, dual counter locking judgment and phase-voltage cross-verification, and no false synchronization ready phenomenon occurs. All modules are synchronously connected in parallel under a unified closing command, and the closing inrush current is effectively suppressed.

[0107] This invention provides a pre-synchronization control method and system for a multi-inverter parallel system. The method includes phase pre-synchronization employing an offline stepped adjustment strategy triggered by the grid cycle, which adaptively adjusts the phase step size by comparing phase index deviations and introducing a dual-counting determination mechanism of lock-in and unlock-out counting. Voltage pre-synchronization employs a multi-level adaptive stepped adjustment strategy based on the target voltage dead zone, ensuring the output voltage remains stable after entering the dead zone and determining voltage synchronization completion through continuous counting. A phase voltage cross-verification mechanism is also included; if one pre-synchronization condition fails, the count of the other is reset to zero, preventing false synchronization. Status interaction and coordinated control between the main controller and each module are achieved via a CAN bus. This invention requires no complex parameter tuning and has advantages such as simple implementation, strong anti-interference capability, no oscillation, and high reliability. It can be widely applied to parallel systems such as modular UPS, microgrid inverters, and energy storage converters.

[0108] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A pre-synchronization control method for a multi-inverter parallel system, characterized in that, include: Phase pre-synchronization: The power grid phase is discretized into multiple phase index points. Phase adjustment is triggered at a preset fixed phase index point in each power grid cycle. Discrete step adjustment is performed based on the deviation between the current phase index and the reference phase index. The phase lock status is determined based on the dual counting mechanism of the lock-in counter and the unlock counter. Voltage pre-synchronization: Set a target voltage dead zone, adjust in steps according to the deviation between the inverter output voltage and the target voltage dead zone, and determine the voltage synchronization status based on a continuous counting mechanism; Phase-voltage cross-check: During the counting and judgment process of phase pre-synchronization and voltage pre-synchronization, the status of each other is monitored. If the other party fails to meet the synchronization condition during the counting accumulation period, the counter of the other party is cleared. Multi-module collaborative operation: Each inverter module reports its synchronization status to the main controller via the CAN bus. After the main controller confirms that all online modules have completed phase and voltage synchronization, it issues a unified grid connection and closing command.

2. The pre-synchronization control method for a multi-inverter parallel system according to claim 1, characterized in that, The phase pre-synchronization specifically includes: Based on the power grid cycle, the power grid phase is discretized into N phase index points within each power grid cycle, where N is a positive integer greater than 100; a phase adjustment is triggered once at a preset fixed phase index point in each power grid cycle. Obtain the phase deviation between the current inverter's phase index value and the reference phase index value; When the phase deviation value is greater than 0, the current phase index value is decreased by a preset step size and the phase accumulator output is decreased simultaneously. When the phase deviation value is less than 0, the current phase index value is increased by a preset step size and the phase accumulator output is increased simultaneously. When the phase deviation value is equal to 0, the phase remains unchanged. Set a phase lock-in counter and a phase unlock counter. When the absolute value of the phase deviation is less than or equal to the preset tolerance threshold for M consecutive power grid cycles, the phase lock flag is set. When the absolute value of the phase deviation is greater than the preset tolerance threshold for K consecutive power grid cycles, the phase lock flag is reset, where M≥3 and K≥3.

3. The pre-synchronization control method for a multi-inverter parallel system according to claim 2, characterized in that, The phase pre-synchronization process employs a phase adaptive step size adjustment strategy, which divides the adjustment step size into multiple levels based on the absolute value of the phase deviation. When the absolute value of the phase deviation is greater than the first deviation threshold, a large adjustment step size is used to quickly converge the phase deviation. When the absolute value of the phase deviation decreases to between the tolerance threshold and the first deviation threshold, a medium step size is used. When the absolute value of the phase deviation is less than or equal to the tolerance threshold, a minimum step size is used. The minimum step size is one phase index point.

4. The pre-synchronization control method for a multi-inverter parallel system according to claim 1, characterized in that, The voltage pre-synchronization specifically includes: Collect the output voltage amplitude V of the inverter out Obtain the target voltage value V target Set the target voltage dead zone [V] target -ΔV dead V target +ΔV dead ], where the target voltage dead zone half-width ΔV dead >0; When the output voltage amplitude V out When the voltage is below the lower limit of the target voltage dead zone, gradually increase the output voltage setpoint; when the output voltage amplitude V... out When the voltage exceeds the upper limit of the target voltage dead zone, gradually reduce the output voltage setpoint. When the output voltage amplitude is within the target voltage dead zone for L consecutive sampling cycles, the voltage pre-synchronization is determined to be complete and the voltage synchronization flag is set, where L≥1000.

5. The pre-synchronization control method for a multi-inverter parallel system according to claim 4, characterized in that, The voltage pre-synchronization process employs multi-level adaptive voltage step size adjustment; based on the absolute value of the voltage deviation and the target voltage dead zone half-width ΔV... dead The voltage adjustment step size is divided into at least three levels based on the multiple relationship; the larger the voltage deviation, the larger the selected voltage step size; the closer to the target voltage dead zone, the smaller the selected voltage step size; voltage adjustment is stopped after entering the target voltage dead zone.

6. The pre-synchronization control method for a multi-inverter parallel system according to claim 1, characterized in that, The phase voltage cross-check specifically includes: continuously monitoring the phase lock flag during the process of voltage stabilization counter continuously accumulating and counting to determine voltage synchronization; if the phase lock flag is reset before the voltage stabilization counter reaches the voltage stabilization determination threshold, the voltage stabilization counter is cleared and the voltage pre-synchronization counting is restarted; if the output voltage amplitude is detected to continuously deviate from the target voltage dead zone during the phase lock counter accumulation process, the phase lock counter is cleared and the phase pre-synchronization is re-executed.

7. The pre-synchronization control method for a multi-inverter parallel system according to claim 1, characterized in that, The multi-module collaboration and parallel operation specifically includes: each inverter module sending the phase lock flag and voltage synchronization flag to the main controller via the CAN bus; the main controller collecting the synchronization flags of all online modules; and when it is confirmed that all online modules have completed synchronization, issuing a unified grid connection command to put each inverter module into parallel operation and stopping the phase pre-synchronization process and voltage pre-synchronization process.

8. A pre-synchronization control system for a multi-inverter parallel system, characterized in that, It includes at least two inverter modules, a main controller, and a CAN bus communication network; The main controller collects the synchronization status of each module and issues a unified grid connection and closing command after all online modules have completed synchronization. The CAN bus communication network is used to connect the main controller and each inverter module; The inverter module includes a three-phase inverter bridge, an LC filter circuit, a voltage and current sampling circuit, and a slave controller; the slave controller is used to perform phase pre-synchronization process, voltage pre-synchronization process, phase-voltage cross-verification, and multi-module coordination and parallel operation.

9. A pre-synchronization control system for a multi-inverter parallel system according to claim 8, characterized in that, The slave controller uses a TI TMS320F280025 DSP, and the master controller uses a TI TMS320F280039 DSP.

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