Voltage monitoring common-mode failure suppression circuit, method, and power management chip

Abstract

The voltage monitoring common cause failure inhibition circuit, the method and the power management chip provided by the embodiments of the present disclosure comprise: a first power supply domain configured to supply power to each main function load circuit and a voltage monitoring module in a chip; a second power supply domain configured to supply power to a band gap reference voltage generation module and a power supply monitoring module; the band gap reference voltage generation module is configured to generate a monitoring reference voltage; the voltage monitoring module is configured to generate a first monitoring signal according to the monitoring reference voltage and the output voltage of the output channel corresponding to each main function load circuit, wherein the first monitoring signal represents the relationship between the voltage signal of each main function load circuit in the chip and the monitoring reference voltage; the power supply monitoring module is configured to generate a second monitoring signal according to the monitoring reference voltage and the first power supply domain voltage. On the one hand, the circuit common cause failure is avoided, and on the other hand, the overall area of the circuit is reduced.

Description

Technical Field

[0001] This invention relates to the field of power management chip technology and related technical fields, specifically to a voltage monitoring common cause failure suppression circuit, method, and power management chip. Background Technology

[0002] In automotive-grade highly integrated chips, voltage monitoring circuits are used to monitor the undervoltage (UV) and overvoltage (OV) states of multiple power rails in real time, which is a critical prerequisite for the system to enter a safe state. According to ISO 26262-11:2018, "common power supply" and "common reference source" are explicitly defined as dependency failure initiators (DFIs). Once the main power supply fails, if the monitoring circuit is dependent on the main power supply, all monitoring channels will fail synchronously, causing the system to be unable to detect the fault and trigger a safety response, constituting a typical common cause failure (CCF).

[0003] To address the risk of common-cause failure, existing technologies mainly adopt a fully independent power supply scheme for the entire module, that is, to configure an independent second power domain (VCC2) for the entire voltage monitoring module (including multiplexers, multiplexers MUX, and digital logic circuits). Although this scheme can achieve complete physical decoupling between the monitoring circuit and the main power supply, it has the following drawbacks: (1) The independent power supply needs to provide hundreds of microamps of current to support the multiplexers and digital logic; (2) The low dropout linear regulator (LDO) that implements this current level on-chip needs to occupy a large chip area; (3) If there is no external VCC2 pin, the design cost and complexity of the on-chip high-current LDO are extremely high, and the transient response requirements are stringent. Summary of the Invention

[0004] In view of this, the embodiments described herein provide a voltage monitoring common cause failure suppression circuit, method, and power management chip that, on the one hand, avoids common cause failures in the circuit, and on the other hand, reduces the overall circuit area.

[0005] In a first aspect, according to the present disclosure, a voltage monitoring common-cause failure suppression circuit with independent power supply for the main power monitoring channel is provided, comprising: The first power domain is configured to supply power to the various main functional load circuits and voltage monitoring modules in the chip. The second power domain is configured to supply power to the bandgap reference voltage generation module and the power monitoring module. The bandgap reference voltage generation module is configured to generate a monitoring reference voltage; The voltage monitoring module is configured to generate a first monitoring signal based on the monitoring reference voltage and the output voltage of the output channel corresponding to each main functional load circuit, wherein the first monitoring signal characterizes the relationship between the output voltage of the output channel corresponding to each main functional load circuit in the chip and the monitoring reference voltage. The power monitoring module is configured to generate a second monitoring signal based on the monitoring reference voltage and the first power domain voltage.

[0006] In some embodiments of this disclosure, the first power domain and the second power domain are isolated in physical layout and power network.

[0007] In some embodiments of this disclosure, the load current of the second power domain is in the microampere range, and the load current of the first power domain is in the milliampere range.

[0008] In some embodiments of this disclosure, a fault response module; The fault response module is configured to generate a reset signal or a shutdown control signal based on the first monitoring signal and / or the second monitoring signal.

[0009] In some embodiments of this disclosure, the power monitoring module includes a first comparator, the non-inverting input of the first comparator receiving the monitoring reference voltage, the inverting input of the first comparator connected to the voltage sampling terminal of the output channel corresponding to each main functional load circuit, the power supply terminal of the first comparator connected to the output terminal of the second power domain, and the output terminal of the first comparator outputting a second monitoring signal, wherein the voltage sampling terminal is connected to the output terminal of the first power domain through a voltage divider network.

[0010] In some embodiments of this disclosure, the voltage monitoring module includes N second comparators. The non-inverting inputs of the N second comparators respectively receive the monitoring reference voltage. The inverting inputs of the N comparators are respectively connected to the voltage sampling terminals of the output channels corresponding to each main functional load circuit. The power supply terminals of the N second comparators are respectively connected to the output terminals of the first power domain. The output terminals of the N second comparators respectively output a first monitoring signal. The voltage sampling terminals are connected to the output terminals of the first power domain through a voltage divider network. The voltage sampling terminals corresponding to different main functional load circuits are different.

[0011] In some embodiments of this disclosure, a self-testing module is also included; The self-test module is configured to detect the power monitoring module during the power-on phase of the voltage monitoring common cause failure suppression circuit.

[0012] In some embodiments of this disclosure, the self-test module includes a test stimulus generation unit and a test response determination unit; The test stimulus generation unit is configured to generate a first test reference voltage lower than the monitoring reference voltage to the non-inverting input of the first comparator in a first test mode, and to generate a second test reference voltage higher than the monitoring reference voltage to the non-inverting input of the first comparator in a second test mode. The test response determination unit is configured to read the third monitoring signal output by the first comparator in the first test mode or the second test mode, and determine whether the power monitoring module is working properly based on the third monitoring signal.

[0013] Secondly, according to the present disclosure, a voltage monitoring common cause failure suppression method with independent power supply for the main power monitoring channel is provided, which is applied to the voltage monitoring common cause failure suppression circuit described in any one of the first aspects.

[0014] Thirdly, according to the present disclosure, a power management chip is provided, including the voltage monitoring common cause failure suppression circuit described in any of the first aspects.

[0015] The voltage monitoring common-cause failure suppression circuit with independent power supply for the main power monitoring channel provided in this embodiment firstly includes a first power domain and a second power domain. The first power domain voltage generated by the first power domain supplies power to the main functional load circuit and the voltage monitoring module of the chip, while the second power domain voltage generated by the second power domain supplies power to the bandgap reference voltage generation module and the power monitoring module. This allows the bandgap reference voltage generation module and the power monitoring module to be placed in the second power domain, while the high-power main functional load circuit (such as multiplexers, digital logic, etc.) and the voltage monitoring module are kept in the first power domain. Since the power consumption of the bandgap reference voltage generation module and the power monitoring module is extremely low (typically a few microamps), the current requirement of the second power domain drops sharply from hundreds of microamps in traditional solutions to the microamp level, and the corresponding LDO area can be reduced to less than one-tenth of that in traditional solutions. Furthermore, in the voltage monitoring common-cause failure suppression circuit provided in this embodiment, the power monitoring module and the bandgap reference voltage generation module are powered by the second power domain voltage generated by the second power domain. When the first power domain voltage generated by the first power domain fails, the bandgap reference voltage generation module still outputs the correct monitoring reference voltage, and the power monitoring module still normally compares the monitoring reference voltage and the first power domain voltage. When the power monitoring module detects that the first power domain voltage has dropped below the monitoring reference voltage, it triggers the voltage monitoring common-cause failure suppression circuit to reset or shut down through the fault response module, causing the voltage monitoring common-cause failure suppression circuit to enter a safe state. Since the voltage monitoring common-cause failure suppression circuit has entered a safe state, there is no undetected dangerous failure in the voltage monitoring module, and therefore it does not constitute a common-cause failure in the functional safety sense.

[0016] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein: Figure 1 This is a schematic diagram of a voltage monitoring common cause failure suppression circuit with independent power supply for the main power monitoring channel provided in this embodiment of the disclosure; Figure 2 This is a partial structural schematic diagram of a voltage monitoring common cause failure suppression circuit with independent power supply for the main power monitoring channel provided in this embodiment.

[0018] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0020] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0021] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] In this article, the terms "or" or "or" are merely a way of describing the relationship between related objects, indicating that there can be three kinds of relationships. For example, A or B can mean that only A exists, both A and B exist, or only B exists.

[0023] Furthermore, in all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0024] In the description of this application, unless otherwise stated, "multiple" means two or more (including two), and similarly, "multiple groups" means two or more (including two groups).

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0026] Based on the problems existing in the prior art, this disclosure provides a voltage monitoring common-cause failure suppression circuit with independent power supply for the main power monitoring channel. Figure 1 This is a schematic diagram of a voltage monitoring common cause failure suppression circuit with independent power supply for the main power monitoring channel provided in this embodiment of the disclosure, as shown below. Figure 1 As shown, the voltage monitoring common-cause failure suppression circuit with independent power supply for the main power monitoring channel includes: a first power domain 10, configured to supply power to each main functional load circuit (not shown) and voltage monitoring module 40 in the chip; a second power domain 20, configured to supply power to bandgap reference voltage generation module 30 and power monitoring module 50; the bandgap reference voltage generation module 30, configured to generate a monitoring reference voltage BG; the voltage monitoring module 40, configured to generate a first monitoring signal based on the monitoring reference voltage BG and the output voltage of the output channel corresponding to each main functional load circuit, wherein the first monitoring signal characterizes the relationship between the output voltage of the output channel corresponding to each main functional load circuit in the chip and the monitoring reference voltage; and the power monitoring module 50, configured to generate a second monitoring signal based on the monitoring reference voltage BG and the first power domain voltage VCC1.

[0027] Specifically, when the chip is in normal operating condition, the first power domain 10 generates a first power domain voltage VCC1, and the second power domain 20 generates a second power domain voltage VCC2. The first power domain voltage VCC1 provides normal operating voltage (e.g., 3.3V or 5V) for each main functional load circuit of the chip (not shown in the figure). The bandgap reference voltage generation module 30, powered by the second power domain voltage VCC2, continuously outputs a high-precision monitoring reference voltage (e.g., 1.2V). The power monitoring module 50 is powered by the second power domain voltage VCC2, and its non-inverting input receives the monitoring reference voltage BG. Its inverting input receives the sampled voltage Vfb after the first power domain voltage VCC1 is divided. The power monitoring module compares the two (monitoring reference voltage and sampled voltage) and outputs the corresponding second monitoring signal (i.e., logic level) to the fault response module 60.

[0028] When the voltage of the first power domain 10 drops due to some fault (such as an external short circuit, failure of the internal low-dropout regulator (LDO), etc.), the sampling voltage of the first power domain voltage VCC1 will drop accordingly. When the first power domain voltage VCC1 drops below the preset monitoring reference voltage BG, the sampling voltage Vfb of the first power domain voltage VCC1 is less than the monitoring reference voltage VCC1, and the output of the power monitoring module 50 flips (that is, changes from high level to low level). After receiving the flip signal, the fault response module 60 immediately generates a reset signal RST or a shutdown control signal to switch the voltage monitoring common cause failure suppression circuit to a safe state.

[0029] Throughout the process, since the bandgap reference voltage generation module 30 and the power monitoring module 50 are powered by the second power domain 20, which is physically isolated from the first power domain 10, their output monitoring reference voltage BG is not affected by the drop in the first power domain voltage VCC1 and remains stable. Therefore, the power monitoring module 50 can make a correct comparison decision during the failure of the first power domain voltage VCC1, ensuring that the fault is reliably detected and reported.

[0030] It should be noted that in the above embodiments, the first power domain 10 is provided by the first power supply circuit (e.g., the first LDO), and the second power domain 20 is provided by the second power supply circuit (e.g., the second LDO) independent of the first power supply circuit. The output terminal of the first power supply circuit constitutes the first power domain, and the output terminal of the second power supply circuit constitutes the second power domain.

[0031] The voltage monitoring common-cause failure suppression circuit with independent power supply for the main power monitoring channel provided in this embodiment firstly includes a first power domain and a second power domain. The first power domain voltage generated by the first power domain supplies power to the main functional load circuit and the voltage monitoring module of the chip, while the second power domain voltage generated by the second power domain supplies power to the bandgap reference voltage generation module and the power monitoring module. This allows the bandgap reference voltage generation module and the power monitoring module to be placed in the second power domain, while the high-power main functional load circuit (such as multiplexers, digital logic, etc.) and the voltage monitoring module are kept in the first power domain. Since the power consumption of the bandgap reference voltage generation module and the power monitoring module is extremely low (typically a few microamps), the current requirement of the second power domain drops sharply from hundreds of microamps in traditional solutions to the microamp level, and the corresponding LDO area can be reduced to less than one-tenth of that in traditional solutions. Furthermore, in the voltage monitoring common-cause failure suppression circuit provided in this embodiment, the power monitoring module and the bandgap reference voltage generation module are powered by the second power domain voltage generated by the second power domain. When the first power domain voltage generated by the first power domain fails, the bandgap reference voltage generation module still outputs the correct monitoring reference voltage, and the power monitoring module still normally compares the monitoring reference voltage and the first power domain voltage. When the power monitoring module detects that the first power domain voltage has dropped below the monitoring reference voltage, it triggers the voltage monitoring common-cause failure suppression circuit to reset or shut down through the fault response module, causing the voltage monitoring common-cause failure suppression circuit to enter a safe state. Since the voltage monitoring common-cause failure suppression circuit has entered a safe state, there is no undetected dangerous failure in the voltage monitoring module, and therefore it does not constitute a common-cause failure in the functional safety sense.

[0032] Based on the above embodiments, see below. Figure 1 The voltage monitoring common cause failure suppression circuit with independent power supply for the main power monitoring channel also includes a fault response module 60; the fault response module 60 is configured to generate a reset signal or a shutdown control signal based on the first monitoring signal and / or the second monitoring signal.

[0033] When the power monitoring module 50 compares the two (monitoring reference voltage and sampling voltage) and outputs the corresponding second monitoring signal (i.e., logic level) to the fault response module 60, the fault response module 60 generates a reset signal or a shutdown control signal when the second monitoring signal is low. The reset signal or shutdown control signal triggers the voltage monitoring common cause failure suppression circuit to reset or the power supply to be turned off.

[0034] Furthermore, if the second monitoring signal received by the fault response module 60 is high, it indicates that the first power domain voltage VCC1 generated by the first power domain can provide normal operating voltage for each main functional load circuit of the chip.

[0035] During the period when the second monitoring signal is at a high level, the fault response module 60 determines the amount and direction of voltage signal drift acting on each main functional load circuit based on the first monitoring signal generated by the received voltage monitoring module.

[0036] Based on the above embodiments, continue to combine Figure 1 The power monitoring module 50 includes a first comparator. The non-inverting input of the first comparator receives a monitoring reference voltage. The inverting input of the first comparator is connected to a voltage sampling terminal. The power supply terminal of the first comparator is connected to the output terminal of a second power domain. The output terminal of the first comparator outputs a second monitoring signal. The voltage sampling terminal is connected to the output terminal of the first power domain through a voltage divider network.

[0037] Combination Figure 1 The power supply comparator includes a first comparator. The non-inverting input of the first comparator receives the monitoring reference voltage, and the inverting input is connected to the voltage sampling terminal. The voltage sampling terminal is connected to the output of the first power domain through a voltage divider network. The power supply terminal of the first comparator is connected to the output of the second power domain. The first comparator compares the sampled voltage of the voltage sampling terminal (there is a certain proportional relationship between the sampled voltage of the voltage sampling terminal and the output voltage of the first power domain, that is, the output voltage of the first power domain can be deduced from the sampled voltage of the voltage sampling terminal) with the monitoring reference voltage. When the voltage of the first power domain generated by the first power domain fails, the bandgap reference voltage generation module still outputs the correct monitoring reference voltage, and the power supply monitoring module still compares the monitoring reference voltage and the voltage of the first power domain normally. When the power supply monitoring module detects that the voltage of the first power domain has dropped below the monitoring reference voltage, it triggers the voltage monitoring common cause failure suppression circuit to reset or shut down through the fault response module, so that the voltage monitoring common cause failure suppression circuit enters a safe state.

[0038] It should be noted that the first power domain is a raw, unprocessed high voltage (e.g., typically 3.3V, 5V, or 1.8V), which directly supplies the main functional load circuitry (usually a high-power circuit) inside the chip. The monitoring reference voltage generated by the bandgap reference voltage generation module is typically around 1.2V. Therefore, the first comparator of the power monitoring module cannot directly compare 3.3V and 1.2V. A voltage divider network (e.g., two resistors R1 and R2) must be used to divide the output voltage of the first power domain to obtain the sampling voltage. For example, 3.3V is divided into 1.2V, and the resulting sampled voltage is compared with the monitoring reference voltage.

[0039] In addition, the first power domain, acting as an "energy source," is connected to the power supply terminal of the first comparator. Its function is to supply power to the first comparator so that the transistors inside the comparator can function normally.

[0040] Based on the above embodiments, continue to combine Figure 1 The voltage monitoring module includes N second comparators. The non-inverting input terminals of the N second comparators receive the monitoring reference voltage, and the inverting input terminals of the N comparators receive the output voltage of the output channel corresponding to each main functional load circuit. The power supply terminals of the N second comparators are connected to the output terminals of the first power domain, and the output terminals of the N second comparators output the first monitoring signal.

[0041] Combination Figure 1 The voltage comparator includes N second comparators. The non-inverting inputs of the N second comparators receive the monitoring reference voltage, and the inverting inputs of the N second comparators receive the output voltage of the output channel corresponding to each main functional load circuit. The power supply terminals of the N second comparators are connected to the output terminal of the first power domain. By comparing the sampled voltage of the voltage sampling terminal (there is a certain proportional relationship between the sampled voltage of the voltage sampling terminal and the output voltage of the first power domain, that is, the output voltage of the first power domain can be deduced from the sampled voltage of the voltage sampling terminal) with the monitoring reference voltage, it is determined whether the voltage signals of each main functional load circuit in the generated chip meet the requirements.

[0042] Specifically, if the first monitoring signal output by the first second comparator is low, based on the correspondence between each second comparator and each main functional load circuit, it can be determined that the voltage signal provided by the first power domain to the first main functional load circuit in the chip has a certain drift. At this time, the amount and direction of the drift of the voltage signal provided by the first power domain to the first main functional load circuit in the chip can be determined based on the monitoring reference voltage signal of the first second comparator and the output voltage of the output channel corresponding to the first main functional load circuit.

[0043] Based on the above embodiments, Figure 2 This is a partial structural schematic diagram of a voltage monitoring common cause failure suppression circuit with independent power supply for the main power monitoring channel provided in this embodiment of the disclosure, as shown below. Figure 2 As shown, the voltage monitoring common-cause failure suppression circuit with independent power supply for the main power monitoring channel also includes a self-test module 60; the self-test module 60 is configured to test the power monitoring module during the power-on phase of the voltage monitoring common-cause failure suppression circuit. Specifically, the self-test module 60 includes a test stimulus generation unit and a test response determination unit; the test stimulus generation unit is configured to generate a first test reference voltage lower than the monitoring reference voltage to the non-inverting input terminal of the first comparator in a first test mode, and to generate a second test reference voltage higher than the monitoring reference voltage to the non-inverting input terminal of the first comparator in a second test mode; the test response determination unit is configured to read the third monitoring signal output by the first comparator in the first test mode or the second test mode, and determine whether the power monitoring module is working properly based on the third monitoring signal.

[0044] Specifically, Power-On Self-Test (BIST). When the voltage monitoring common-cause failure suppression circuit is powered on, the second power domain is established before (or simultaneously with) the first power domain. Before the first power domain supplies power to the main functional load circuits in the chip, the self-test logic of the self-test module runs once. The specific process is as follows: (1) Test whether the output voltage of the bandgap reference voltage generation module is within the accuracy range (e.g., 1.2V ±0.5%). (2) Inject high test voltage and low test voltage in sequence to verify whether the first comparator of the power monitoring module responds normally under the upper and lower limit thresholds.

[0045] Only after passing the self-test is the first power domain allowed to supply power to the various main functional load circuits in the chip.

[0046] In a specific implementation, when the voltage monitoring common cause failure suppression circuit is in the self-test phase, the self-test enable signal BIST_EN is high, the self-test module is enabled, and the self-test module generates a first test reference voltage lower than the monitoring reference voltage to the non-inverting input of the first comparator in the first test mode, and generates a second test reference voltage higher than the monitoring reference voltage to the non-inverting input of the first comparator in the second test mode. At this time, the test response determination unit reads the third monitoring signal output by the first comparator in the first test mode or the second test mode, and verifies whether the first comparator of the power monitoring module responds normally under the upper and lower limit thresholds according to the third monitoring signal. When the voltage monitoring common cause failure suppression circuit completes the self-test, the self-test enable signal BIST_EN is low, the self-test module is not enabled, the self-test module outputs the sampling voltage Vfb to the first comparator, and the power monitoring module compares the two (monitoring reference voltage and sampling voltage) and outputs the corresponding second monitoring signal (i.e., logic level) to the fault response module 60.

[0047] It should be noted that, Figure 2The schematic diagram of the self-test module is shown as an example. In a specific implementation, the self-test module includes specific circuitry for generating a first test reference voltage lower than the monitoring reference voltage and a second test reference voltage higher than the monitoring reference voltage. This disclosure does not provide a specific description of this circuitry.

[0048] In the above embodiments, the self-test module is powered by the second power domain and is physically isolated from the voltage monitoring module. When the voltage monitoring common-cause failure suppression circuit is powered on, the functional integrity of the power monitoring module is verified by inputting a preset monitoring reference voltage to the second comparator.

[0049] In a specific implementation, the first power domain and the second power domain are isolated in terms of physical layout and power network.

[0050] Specifically, the physical isolation of the first and second power domains means that during the chip's physical design phase, the voltage monitoring module powered by the first power domain and the bandgap reference voltage generation module and power monitoring module powered by the second power domain are completely separated spatially. Specifically, the voltage monitoring module powered by the first power domain and the bandgap reference voltage generation module and power monitoring module powered by the second power domain are clearly placed in different physical areas of the chip layout, ensuring sufficient physical spacing between them to reduce crosstalk and coupling noise generated through substrates, metal interconnects, etc. Furthermore, the power and ground lines corresponding to the voltage monitoring module, bandgap reference voltage generation module, and power monitoring module are independently routed, without interweaving or sharing, preventing noise from being conducted through the power network.

[0051] The isolation between the first and second power domains on the power network emphasizes the independence of circuit connections, ensuring that the two power domains do not affect each other in terms of electrical characteristics. Specifically, the two power domains are powered by different power supply circuits; the first power domain is powered by a first power supply circuit, and the second power domain is powered by a second power supply circuit. From the power supply circuit to the load, each power domain has its own complete power delivery network (PDN), including power lines, ground lines, and decoupling capacitors. Furthermore, special designs at the interface can prevent backflow from one power domain to the other in the event of a voltage anomaly in the first power domain.

[0052] By isolating the first and second power domains in physical layout and power network, it is ensured that when voltage fluctuations, noise, or even failures occur in the first power domain, they will not affect the bandgap reference voltage generation module and power monitoring module powered by the independent second power domain through physical space or electrical connection. The bandgap reference voltage generation module and power monitoring module can still work normally, thereby detecting faults in a timely manner and triggering system reset, bringing the entire system into a safe state and effectively avoiding common-cause failures.

[0053] In a specific implementation, the load current of the second power domain is in the microampere range, and the load current of the first power domain is in the milliampere range.

[0054] In this design, the first power domain is responsible for powering all the main functional circuits of the chip and the voltage monitoring module (the number of voltage monitoring modules is the same as the number of main functional load circuits in the chip). Therefore, the first power domain needs to provide load currents as high as milliamps or even amperes. The second power domain only needs to power the comparators of the bandgap reference voltage generation module and the power monitoring module, with a total current requirement of only microamps.

[0055] Because the second power domain has an extremely light load, its power supply circuit (LDO) area can be made very small (reduced to less than one-tenth of the conventional solution), which is the key to achieving "significantly reduced chip area" in the embodiments of this disclosure.

[0056] It should be noted that in the above embodiments, the second power domain can be generated from a backup power source that is physically isolated from the first power domain through the second power supply circuit, or energy can be stored and maintained through a very small external capacitor, without the need for additional high-current power supply pins, which is especially suitable for highly integrated PMIC / MCU / SoC.

[0057] Based on the above embodiments, this disclosure also provides a voltage monitoring common cause failure suppression method with independent power supply for the main power monitoring channel. This method is applied to the voltage monitoring common cause failure suppression circuit described in any of the above embodiments and has the beneficial effects of any of the above embodiments. This disclosure does not specifically limit this method.

[0058] Based on the above embodiments, this disclosure also provides a power management chip, including the voltage monitoring common cause failure suppression circuit described in any of the above embodiments, which has the beneficial effects of any of the above embodiments. This disclosure does not specifically limit the chip in this regard.

[0059] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0060] In the various embodiments of this application, the functional units or modules can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0061] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0062] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0063] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0064] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A voltage monitoring common-cause failure suppression circuit with independent power supply for the main power monitoring channel, characterized in that, include: The first power domain is configured to supply power to the various main functional load circuits and voltage monitoring modules in the chip. The second power domain is configured to supply power to the bandgap reference voltage generation module and the power monitoring module. The bandgap reference voltage generation module is configured to generate a monitoring reference voltage; The voltage monitoring module is configured to generate a first monitoring signal based on the monitoring reference voltage and the output voltage of the output channel corresponding to each main functional load circuit, wherein the first monitoring signal indicates whether the output voltage of the output channel corresponding to each main functional load circuit in the chip is under-voltage or over-voltage. The power monitoring module is configured to generate a second monitoring signal based on the monitoring reference voltage and the first power domain voltage.

2. The circuit according to claim 1, characterized in that, The first power domain and the second power domain are isolated in terms of physical layout and power network.

3. The circuit according to claim 1, characterized in that, The load current of the second power domain is in the microampere range, while the load current of the first power domain is in the milliampere range.

4. The circuit according to claim 1, characterized in that, It also includes a fault response module; The fault response module is configured to generate a reset signal or a shutdown control signal based on the first monitoring signal and / or the second monitoring signal.

5. The circuit according to claim 1, characterized in that, The power monitoring module includes a first comparator. The non-inverting input of the first comparator receives the monitoring reference voltage. The inverting input of the first comparator is connected to a voltage sampling terminal. The power supply terminal of the first comparator is connected to the output terminal of the second power domain. The output terminal of the first comparator outputs a second monitoring signal. The voltage sampling terminal is connected to the output terminal of the first power domain through a voltage divider network.

6. The circuit according to claim 1, characterized in that, The voltage monitoring module includes N second comparators. The non-inverting input terminals of the N second comparators respectively receive the monitoring reference voltage, and the inverting input terminals of the N comparators respectively receive the output voltage of the output channel corresponding to each main functional load circuit. The power supply terminals of the N second comparators are respectively connected to the output terminals of the first power domain, and the output terminals of the N second comparators respectively output the first monitoring signal.

7. The circuit according to claim 5, characterized in that, The system also includes a self-testing module; The self-test module is configured to detect the power monitoring module during the power-on phase of the voltage monitoring common cause failure suppression circuit.

8. The circuit according to claim 7, characterized in that, The self-test module includes a test stimulus generation unit and a test response determination unit; The test stimulus generation unit is configured to generate a first test reference voltage lower than the monitoring reference voltage to the non-inverting input of the first comparator in a first test mode, and to generate a second test reference voltage higher than the monitoring reference voltage to the non-inverting input of the first comparator in a second test mode. The test response determination unit is configured to read the third monitoring signal output by the first comparator in the first test mode or the second test mode, and determine whether the power monitoring module is working properly based on the third monitoring signal.

9. A method for suppressing common-cause failure of voltage monitoring with independent power supply for the main power monitoring channel, applied to the voltage monitoring common-cause failure suppression circuit according to any one of claims 1-8.

10. A power management chip, characterized in that, Includes the voltage monitoring common cause failure suppression circuit as described in any one of claims 1-8.

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