Multi-path power combining control circuit and multi-path power combining control method

Abstract

The application discloses a multi-path power supply combining control circuit and a multi-path power supply combining control method, and belongs to the technical field of power supply. The multi-path power supply combining control circuit detects the voltage of the input end of N paths of power supplies through a control module, and initiatively selects one path of power supplies to be turned on to a combining output end based on a detection result, so that the determined and stable combining output according to a preset strategy (such as a fixed priority) is realized. The application fundamentally avoids the unnecessary switching problem caused by the slight fluctuation of the input voltage in the traditional ORING scheme, and significantly improves the stability and reliability of the power supply system. Meanwhile, the circuit architecture is clear, N detection and control channels which are independent of each other are arranged, so that the application can flexibly support two paths and more than two paths of power supply inputs, has good scalability and universality, and overcomes the limitation that the existing scheme usually only supports fixed two paths and is difficult to expand.

Description

Technical Field

[0001] This application relates to the field of power supply technology, and in particular to a multi-source power supply combining control circuit and a multi-source power supply combining control method. Background Technology

[0002] In optical communication systems, to ensure continuous and uninterrupted operation of equipment, it is typically required that the powered equipment support multiple power sources, i.e., a primary and backup power supply scheme. Currently, there are two main technical approaches in this field: one is the commonly used "ORING" combining scheme, which allows multiple inputs to be connected in parallel and powered by the input with the highest instantaneous voltage. However, this scheme has inherent defects. When the operating power supply voltage experiences a slight fluctuation within the normal range, and another input voltage is slightly higher, it will trigger an unnecessary switching of the power supply branch. This process may cause output disturbances, affecting the stability and reliability of the power supply, and it is impossible to determine the primary and backup power, causing unnecessary trouble for network construction. The second is the existing dedicated primary and backup power combining control circuit. Although this type of scheme can avoid voltage-sensitive switching, it is usually highly integrated and not scalable. It often only supports two fixed inputs and the switching threshold voltage is fixed, lacking flexibility and versatility, and is difficult to adapt to application scenarios with variable input numbers or diverse voltage specifications. Summary of the Invention

[0003] To address the technical problems of existing ORING combining schemes, such as unnecessary switching caused by minor voltage fluctuations and the high integration and lack of scalability of existing main and backup circuits, a multi-power combining control circuit and method are provided, which aim to achieve stable combining based on determined priorities and can be flexibly expanded to support multiple power inputs.

[0004] This application provides a multi-source power supply combining control circuit, including:

[0005] There are N power input terminals, where N is an integer greater than or equal to 2;

[0006] N switching circuits, the first end of each switching circuit is connected to a power input terminal, and the second end of each switching circuit is connected to a combined output terminal.

[0007] The control module includes N detection terminals and N logic control terminals. Each detection terminal corresponds to a power input terminal and is connected to the corresponding power input terminal. Each logic control terminal corresponds to a switching circuit and is connected to the control input terminal of the corresponding switching circuit. The control module is used to detect the voltage of the N power input terminals and, based on the detection results, turn on the switching circuit corresponding to one power supply so that the combined output terminal outputs the voltage of the corresponding power supply.

[0008] Optionally, the control module includes:

[0009] There are N detection circuits, and the input terminal of each detection circuit is used as a detection terminal to detect the voltage of the corresponding power input terminal and output a detection signal.

[0010] N cascaded logic units, each of which corresponds to a detection circuit and a switching circuit;

[0011] Each cascaded logic unit includes a first input terminal, a second input terminal, and an output terminal;

[0012] The first input terminal of the cascaded logic unit is connected to the output terminal of the corresponding detection circuit to receive the detection signal;

[0013] The output terminal of the cascaded logic unit serves as a logic control terminal and is connected to the control input terminal of the corresponding switching circuit.

[0014] The second input terminal of the first-stage cascaded logic unit is the same as the first input terminal;

[0015] The second input terminal of the Mth cascaded logic unit is connected to the output terminal of the (M-1)th cascaded logic unit to receive the interlock signal from the previous stage, where M is an integer greater than 1 and less than or equal to N;

[0016] The cascaded logic unit is configured such that when its first input receives a detection signal indicating that the power supply is normal, and its second input receives an interlock signal indicating that the preceding stage is allowed to conduct, its output outputs a conduction signal for conducting the corresponding switching circuit. The conduction signal also serves as an interlock signal to prevent the subsequent cascaded logic unit from conducting.

[0017] Optionally, the detection circuit includes:

[0018] The first resistor R1, one end of which serves as the input terminal of the detection circuit;

[0019] The second resistor R2 has one end connected to the other end of the first resistor R1;

[0020] The third resistor R3 has one end connected to the other end of the second resistor R2, and the other end of the third resistor R3 is connected to the power supply ground.

[0021] The fourth resistor R4 has one end connected to one end of the third resistor R3, and the other end connected to the power supply ground.

[0022] The fifth resistor R5, one end of which is connected to one end of the fourth resistor R4;

[0023] The sixth resistor R6 is connected at one end to the other end of the fifth resistor R5, and serves as the output terminal of the detection circuit.

[0024] The first capacitor C1 has one end connected to one end of the fifth resistor R5, and the other end of the first capacitor C1 is connected to the power supply ground.

[0025] The comparator has its output connected to one end of the sixth resistor R6, its non-inverting input connected to one end of the first capacitor C1, and its negative power supply terminal connected to ground.

[0026] The seventh resistor R7 has one end connected to the reference voltage terminal of the comparator and the other end connected to the inverting input terminal of the comparator.

[0027] The eighth resistor R8 has one end connected to the inverting input of the comparator and the other end connected to the power supply ground.

[0028] The second capacitor C2 has one end connected to the positive power supply terminal of the comparator and the other end connected to the power supply ground.

[0029] The ninth resistor R9 has one end connected to one end of the second capacitor C2, and the other end connected to the power supply terminal of the device.

[0030] Optionally, the first-level cascaded logic unit includes:

[0031] The tenth resistor R10, one end of which is connected to the corresponding power input terminal;

[0032] Eleventh resistor R11, one end of which is connected to the other end of tenth resistor R10;

[0033] The twelfth resistor R12 has one end connected to the other end of the eleventh resistor R11, and the other end of the twelfth resistor R12 is connected to the power supply ground.

[0034] The thirteenth resistor R13 has one end connected to one end of the twelfth resistor R12, and the other end connected to the power supply ground.

[0035] The first diode D1 has its anode connected to the power supply ground and its cathode connected to one end of the thirteenth resistor R13.

[0036] The first AND gate has its first input terminal connected to the negative terminal of the first diode D1, and its negative power supply terminal connected to the power ground.

[0037] The fourteenth resistor R14, one end of which is connected to the output of the corresponding detection circuit as the first input of the first cascaded logic unit, and the other end of which is connected to the second input of the first AND gate.

[0038] The sixteenth resistor R16, one end of which is connected to the device power supply terminal, and the other end of which is connected to the positive power supply terminal of the first AND gate;

[0039] The fourth capacitor C4 has one end connected to the other end of the sixteenth resistor R16, and the other end of the fourth capacitor C4 is connected to the power supply ground.

[0040] The seventeenth resistor R17, one end of which is connected to the output terminal of the first AND gate;

[0041] The eighteenth resistor R18, one end of which is connected to the other end of the seventeenth resistor R17 to serve as the output terminal of the first-stage cascaded logic unit, and the other end of the eighteenth resistor R18 is connected to the power supply ground.

[0042] Optionally, the first-stage cascaded logic unit further includes:

[0043] The third capacitor C3 has one end connected to the second input terminal of the first AND gate, and the other end connected to the power supply ground.

[0044] The fifteenth resistor R15 has one end connected to the second input terminal of the first AND gate, and the other end connected to the power supply ground.

[0045] Optionally, the Mth cascaded logic unit includes:

[0046] The NOT gate has its input terminal serving as the second input terminal of the Mth cascaded logic unit and connected to the output terminal of the (M-1)th cascaded logic unit; the negative power supply terminal of the NOT gate is connected to the power ground.

[0047] The nineteenth resistor R19 has its first end connected to the corresponding power input terminal, and its other end connected to the positive power supply terminal of the NOT gate.

[0048] The fifth capacitor C5 has one end connected to the positive power supply terminal of the NOT gate, and the other end connected to the power supply ground.

[0049] The twentieth resistor R20, one end of which is connected to the output terminal of the NOT gate;

[0050] The second AND gate, the first input of the second AND gate serves as the first input of the Mth cascaded logic unit and is connected to the output of the corresponding detection circuit; the second input of the second AND gate is connected to the other end of the twentieth resistor R20, and the negative power supply terminal of the second AND gate is connected to the power supply ground;

[0051] The 22nd resistor R22, one end of which is connected to the output of the second AND gate;

[0052] The twenty-third resistor R23 has one end connected to the other end of the twenty-second resistor R22 as the output terminal of the Mth cascaded logic unit, and the other end of the twenty-third resistor R23 is connected to the power supply ground.

[0053] The 24th resistor R24 ​​has one end connected to the device power supply terminal and the other end connected to the positive power supply terminal of the second AND gate.

[0054] The seventh capacitor C7 has one end connected to the other end of the twenty-fourth resistor R24, and the other end of the seventh capacitor C7 is connected to the power supply ground.

[0055] Optionally, the Mth cascaded logic unit further includes:

[0056] The 21st resistor R21 has one end connected to the second input terminal of the second AND gate, and the other end connected to the power supply ground.

[0057] The sixth capacitor C6 has one end connected to one end of the twenty-first resistor R21, and the other end connected to the power supply ground.

[0058] Optionally, the switching circuit employs a field-effect transistor.

[0059] Optionally, the control module may be an MCU, CPLD, or FPGA.

[0060] This application provides a multi-source power supply combining control method, applied to the multi-source power supply combining control circuit as described above, including:

[0061] Detect the voltage of the power supply at N power input terminals;

[0062] Based on the preset priority order, determine whether there is a valid power source with the highest priority;

[0063] If so, the switch circuit corresponding to the highest priority power supply is turned on, and all other switch circuits are turned off.

[0064] The beneficial effects of the above technical solution are as follows:

[0065] In this technical solution, the multi-power supply combining control circuit provided in this application detects the voltage at the N power supply input terminals through a control module, and actively selects to conduct one of the power supplies to the combined output terminal based on the detection results, thereby achieving deterministic and stable combined output according to a preset strategy (such as fixed priority). This application fundamentally avoids the unnecessary switching problem caused by small fluctuations in input voltage in traditional "ORING" solutions, significantly improving the stability and reliability of the power supply system. At the same time, its circuit architecture is clear. By setting up N independent detection and control paths, this application can flexibly support two or more power supply inputs, possessing good scalability and versatility, overcoming the limitations of existing solutions that typically only support two fixed power supplies and are difficult to expand. Attached Figure Description

[0066] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0067] Figure 1 For the existing SQ24900 chip's combining control circuit;

[0068] Figure 2 For the existing TPS2121 chip's combining control circuit;

[0069] Figure 3 This is a block diagram of one embodiment of the multi-power supply combining control circuit described in this application;

[0070] Figure 4 This is a schematic diagram of the internal modules of the control module described in this application;

[0071] Figure 5 This is a circuit diagram of one embodiment of the detection circuit described in this application;

[0072] Figure 6 This is a circuit diagram of one embodiment of the first-stage cascaded logic unit of this application;

[0073] Figure 7 This is a circuit diagram of one embodiment of the M-th cascaded logic unit described in this application;

[0074] Figure 8This is a waveform diagram of power switching;

[0075] Figure 9 This is a flowchart of one embodiment of the multi-source power supply combining control method described in this application. Detailed Implementation

[0076] The advantages of this application are further illustrated below with reference to the accompanying drawings and specific embodiments.

[0077] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0078] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0079] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0080] In the description of this application, it should be understood that the numerical labels before the steps do not indicate the order of the steps, but are only used to facilitate the description of this application and to distinguish each step, and therefore should not be construed as a limitation of this application.

[0081] Currently, in the field of implementing multi-source power combining (or "OR" logic), there are two main types of technical solutions: one is based on TPS2456A, SQ24900 (see TPS2456A, SQ24900, etc.). Figure 1The "voltage competition" combiner controller based on an ideal diode, represented by A1 in the example, drives an external MOSFET to simulate an ideal diode, forming an "OR" logic so that the path with the highest instantaneous voltage supplies power to the load. While this scheme can reduce losses and strive for smooth switching, its power supply path selection depends entirely on the instantaneous comparison of the input voltage, thus having an inherent defect of causing unnecessary and oscillating switching due to normal and minor voltage fluctuations; another type is represented by TPS2121 (see...). Figure 2 Combiner controllers with fixed priority control, such as A1, ensure power supply selection according to preset priorities, avoiding oscillation problems caused by voltage contention. However, these solutions are typically highly integrated dedicated chips with fixed key parameters such as the number of input channels, priority, voltage, and power level. They cannot be flexibly adjusted or expanded according to application requirements, thus limiting their applicability in scenarios requiring adaptation to multiple or different power supplies. In summary, current mainstream technologies fail to balance "power supply selection stability" and "system configuration flexibility."

[0082] Based on the above-mentioned problems, this application provides a multi-power supply combining control circuit that achieves stable combining based on determined priority and can be flexibly expanded to support multiple power supply inputs (see [reference]). Figure 3 It includes: N power input terminals 2, N switching circuits 3 and control module 1.

[0083] There are N power input terminals 2, where N is an integer greater than or equal to 2;

[0084] N switching circuits 3, the first end of each switching circuit 3 is connected to a power input terminal 2, and the second end of each switching circuit 3 is connected to a combined output terminal 4.

[0085] The control module 1 includes N detection terminals and N logic control terminals. Each detection terminal corresponds to a power input terminal 2 and is connected to the corresponding power input terminal 2. Each logic control terminal corresponds to a switching circuit 3 and is connected to the control input terminal of the corresponding switching circuit 3. The control module 1 is used to detect the voltage of the N power input terminals 2 and, according to the detection result, conduct the switching circuit 3 corresponding to one power supply so that the combined output terminal 4 outputs the voltage of the corresponding power supply.

[0086] In this embodiment, the multi-power supply combining control circuit detects the voltage of the N power supply input terminals 2 through the control module 1, and actively selects to conduct one of the power supplies to the combining output terminal 4 based on the detection results, thereby achieving deterministic and stable combining output according to a preset strategy (such as fixed priority). This application fundamentally avoids the unnecessary switching problem caused by small fluctuations in input voltage in the traditional "ORING" scheme, significantly improving the stability and reliability of the power supply system. At the same time, its circuit architecture is clear. By setting up N independent detection and control paths, this application can flexibly support two or more power supply inputs, has good scalability and versatility, and overcomes the limitations of existing solutions that usually only support two fixed power supplies and are difficult to expand.

[0087] In a preferred embodiment, see Figure 4 The control module 1 shown may include:

[0088] N detection circuits, each of which has an input terminal as a detection terminal, used to detect the voltage of the corresponding power input terminal 2 and output a detection signal;

[0089] N cascaded logic units, each of which corresponds to a detection circuit and a switching circuit 3;

[0090] Each cascaded logic unit includes a first input terminal, a second input terminal, and an output terminal;

[0091] The first input terminal of the cascaded logic unit is connected to the output terminal of the corresponding detection circuit to receive the detection signal;

[0092] The output terminal of the cascaded logic unit serves as a logic control terminal and is connected to the control input terminal of the corresponding switching circuit 3.

[0093] The second input terminal of the first-stage cascaded logic unit is the same as the first input terminal;

[0094] The second input terminal of the Mth cascaded logic unit is connected to the output terminal of the (M-1)th cascaded logic unit to receive the interlock signal from the previous stage, where M is an integer greater than 1 and less than or equal to N;

[0095] The cascaded logic unit is configured such that when its first input terminal receives a detection signal indicating that the power supply is normal, and its second input terminal receives an interlock signal indicating that the preceding stage is allowed to conduct, its output terminal outputs a conduction signal for conducting the corresponding switch circuit 3. The conduction signal also serves as an interlock signal to prevent the subsequent cascaded logic unit from conducting.

[0096] In this embodiment, the control module 1 is specifically composed of N independent detection circuits and N cascaded logic units. Each detection circuit monitors the voltage state of the corresponding power input terminal 2 in real time and outputs a detection signal. The cascaded logic unit adopts a hardware interlock architecture: its first input terminal receives the detection signal of its own path, and its output terminal is connected to the control terminal of the corresponding switch circuit 3 to determine its on / off state. For each stage except the first stage, its second input terminal is connected to the output terminal of the previous stage logic unit to receive the interlock signal of the previous stage. This logic unit is configured to only issue a valid signal to turn on the corresponding switch from its output terminal when its first input terminal confirms that the power supply of its own path is normal and its second input terminal receives the interlock signal that the previous stage allows conduction. This signal drives the switch of its own stage and also acts as a locking signal to prohibit the output of the next stage logic unit. The second input terminal of the first stage logic unit is fixedly configured to be in the allowed conduction state, thereby establishing its highest priority. This cascaded interlocking mechanism strictly guarantees from a hardware logic perspective that at any given time, only one power supply (i.e., the highest priority and effective power supply) is turned on to supply power to the combined output terminal 4, realizing stable combining based on determined priority, completely eliminating the oscillation switching problem caused by small voltage fluctuations, and the architecture is clear, and more power inputs can be flexibly supported by adding or removing the same units, with good scalability.

[0097] In a preferred embodiment, see Figure 5 The detection circuit shown may include:

[0098] The first resistor R1, one end of which serves as the input terminal of the detection circuit;

[0099] The second resistor R2 has one end connected to the other end of the first resistor R1;

[0100] The third resistor R3 has one end connected to the other end of the second resistor R2, and the other end of the third resistor R3 is connected to the power supply ground.

[0101] The fourth resistor R4 has one end connected to one end of the third resistor R3, and the other end connected to the power supply ground.

[0102] The fifth resistor R5, one end of which is connected to one end of the fourth resistor R4;

[0103] The sixth resistor R6 is connected at one end to the other end of the fifth resistor R5, and serves as the output terminal of the detection circuit.

[0104] The first capacitor C1 has one end connected to one end of the fifth resistor R5, and the other end of the first capacitor C1 is connected to the power supply ground.

[0105] Comparator U1, the output terminal of comparator U1 is connected to one end of the sixth resistor R6, the non-inverting input terminal of comparator U1 is connected to one end of the first capacitor C1, and the negative power supply terminal of comparator U1 is connected to the power supply ground.

[0106] The seventh resistor R7 has one end connected to the reference voltage terminal of the comparator U1 and the other end connected to the inverting input terminal of the comparator U1.

[0107] The eighth resistor R8 has one end connected to the inverting input of the comparator U1, and the other end connected to the power supply ground.

[0108] The second capacitor C2 has one end connected to the positive power supply terminal of the comparator U1, and the other end connected to the power supply ground.

[0109] The ninth resistor R9 has one end connected to one end of the second capacitor C2, and the other end connected to the power supply terminal of the device.

[0110] In this embodiment, the detection circuit samples the input power supply voltage through a voltage divider network consisting of the first resistor R1 to the fourth resistor R4, and filters it using the first capacitor C1 to obtain a stable and interference-resistant sampled voltage. This sampled voltage is sent to the non-inverting input of comparator U1 and compared with a stable threshold voltage provided by a reference voltage source (introduced through resistor R7). When the input power supply voltage is normal, causing the sampled voltage to be higher than the threshold, comparator U1 outputs a high-level valid detection signal; otherwise, it outputs a low-level signal. This circuit structure provides accurate and fast voltage state judgment, and its output signal is clear and unambiguous, providing a reliable and interference-resistant input reference for subsequent priority logic decisions. Simultaneously, the decoupling power supply provided to comparator U1 through the ninth resistor R9 and the second capacitor C2 further ensures its operational stability under power fluctuation environments, ensuring the detection reliability of the entire combining control system from the source.

[0111] In a preferred embodiment, see Figure 6 The first-level cascaded logic unit shown may include:

[0112] The tenth resistor R10, one end of which is connected to the corresponding power input terminal 2;

[0113] Eleventh resistor R11, one end of which is connected to the other end of tenth resistor R10;

[0114] The twelfth resistor R12 has one end connected to the other end of the eleventh resistor R11, and the other end of the twelfth resistor R12 is connected to the power supply ground.

[0115] The thirteenth resistor R13 has one end connected to one end of the twelfth resistor R12, and the other end connected to the power supply ground.

[0116] The first diode D1 has its anode connected to the power supply ground and its cathode connected to one end of the thirteenth resistor R13.

[0117] The first AND gate U2 has its first input terminal connected to the negative terminal of the first diode D1, and its negative power supply terminal connected to the power ground.

[0118] The fourteenth resistor R14, one end of which is connected to the output of the corresponding detection circuit as the first input of the first cascaded logic unit, and the other end of which is connected to the second input of the first AND gate U2.

[0119] The sixteenth resistor R16, one end of which is connected to the power supply terminal of the device, and the other end of which is connected to the positive power supply terminal of the first AND gate U2;

[0120] The fourth capacitor C4 has one end connected to the other end of the sixteenth resistor R16, and the other end of the fourth capacitor C4 is connected to the power supply ground.

[0121] The seventeenth resistor R17, one end of which is connected to the output terminal of the first AND gate U2;

[0122] The eighteenth resistor R18, one end of which is connected to the other end of the seventeenth resistor R17 to serve as the output terminal of the first-stage cascaded logic unit, and the other end of the eighteenth resistor R18 is connected to the power supply ground.

[0123] In this embodiment, the first-stage cascaded logic unit generates a stable high level at the first input of its first AND gate U2 through a voltage divider network consisting of resistors R10 to R13 (tenth to thirteenth) and diode D1. This hardware implements the highest priority logic condition of "always receiving the enable signal." When the corresponding detection circuit outputs a valid signal indicating normal power supply and sends it to the second input of the AND gate via resistor R14 (fourteenth), both input conditions of the AND gate are simultaneously satisfied, and its output becomes valid. This valid signal, after passing through resistors R17 and R18 (seventeenth and eighteenth), serves as a control signal to drive the current-stage switching circuit 3 and as an interlock signal to the next stage. This specific circuit reliably and deterministically establishes the highest priority of the first power supply by combining a simple analog voltage divider with digital logic, ensuring a clear starting point for the priority sequence after system power-on or reset. Simultaneously, the use of resistors and capacitors also plays a role in signal conditioning and decoupling, enhancing the unit's anti-interference capability and operational stability in complex power supply environments.

[0124] In a preferred embodiment, the first-stage cascaded logic unit further includes:

[0125] The third capacitor C3 has one end connected to the second input terminal of the first AND gate U2, and the other end connected to the power supply ground.

[0126] The fifteenth resistor R15 has one end connected to the second input terminal of the first AND gate U2, and the other end connected to the power supply ground.

[0127] In this embodiment, a fifteenth resistor R15 and a third capacitor C3 are added to the first-stage cascaded logic unit. The fifteenth resistor R15 is connected between the second input terminal of the first AND gate U2 and the power supply ground, forming a clear pull-down loop. This ensures that the input terminal remains stable at a low level when there is no external detection signal input, effectively preventing logic malfunctions that may be caused by the input terminal being floating. The capacitor C3 is connected in parallel between the second input terminal and ground, forming an RC low-pass filter network together with the resistor R14. This network can effectively filter out high-frequency noise and glitches introduced from the detection circuit transmission line or coupled from the environment. This RC network significantly improves the purity and stability of the signal at the second input terminal, making the cascaded logic unit's decision on valid detection signals more reliable and accurate. This further enhances the anti-interference capability and robustness of the entire priority control circuit in complex electromagnetic environments.

[0128] In a preferred embodiment, see Figure 7 As shown, the Mth cascaded logic unit may include:

[0129] NOT gate U3, the input terminal of which serves as the second input terminal of the Mth cascaded logic unit and is connected to the output terminal of the (M-1)th cascaded logic unit; the negative power supply terminal of NOT gate U3 is connected to the power supply ground;

[0130] The nineteenth resistor R19, the first end of the nineteenth resistor R19 is connected to the corresponding power input terminal 2, and the other end of the nineteenth resistor R19 is connected to the positive power supply terminal of the NOT gate U3.

[0131] The fifth capacitor C5 has one end connected to the positive power supply terminal of the NOT gate U3, and the other end connected to the power supply ground.

[0132] The twentieth resistor R20, one end of which is connected to the output terminal of the NOT gate U3;

[0133] The second AND gate U4 has its first input terminal serving as the first input terminal of the Mth cascaded logic unit and connected to the output terminal of the corresponding detection circuit; the second input terminal of the second AND gate U4 is connected to the other end of the twentieth resistor R20, and the negative power supply terminal of the second AND gate U4 is connected to the power supply ground.

[0134] The twenty-second resistor R22, one end of which is connected to the output terminal of the second AND gate U4;

[0135] The twenty-third resistor R23 has one end connected to the other end of the twenty-second resistor R22 as the output terminal of the Mth cascaded logic unit, and the other end of the twenty-third resistor R23 is connected to the power supply ground.

[0136] The 24th resistor R24 ​​has one end connected to the device power supply terminal and the other end connected to the positive power supply terminal of the second AND gate U4.

[0137] The seventh capacitor C7 has one end connected to the other end of the twenty-fourth resistor R24, and the other end of the seventh capacitor C7 is connected to the power supply ground.

[0138] In this embodiment, the Mth cascaded logic unit incorporates a NOT gate U3 to form the core interlocking logic. The input of NOT gate U3 is connected to the output of the preceding unit to receive its interlocking signal. When the preceding unit is turned on, its high-level interlocking signal is inverted by NOT gate U3 to become low and sent to the second input of the second AND gate U4 of this stage, thereby logically forcibly shutting off the AND gate output of this stage, achieving hardware interlocking. NOT gate U3 outputs a high level only when the preceding unit is turned off (outputs a low level), providing the possibility for the subsequent stage to turn on. The second AND gate U4 of this unit comprehensively judges the normal power detection signal of this stage (first input) and the "enable conduction" interlocking state from the preceding stage (second input after NOT gate U3). Only when both conditions are met simultaneously does its output generate a valid control signal. This circuit structure, with its simple and reliable hardware logic, strictly ensures the sequential and exclusive nature of power-on. Meanwhile, the logic devices are provided with stable power supply through the nineteenth resistor R19, the twenty-fourth resistor R24, the fifth capacitor C5, and the seventh capacitor C7, and the driving capability and anti-interference ability of the output signal are adjusted through the twenty-second resistor R22 and the twenty-third resistor R23, thereby achieving stable and conflict-free priority switching control under complex working conditions.

[0139] In a preferred embodiment, the Mth cascaded logic unit further includes:

[0140] The twenty-first resistor R21 has one end connected to the second input terminal of the second AND gate U4, and the other end connected to the power supply ground.

[0141] The sixth capacitor C6 has one end connected to one end of the twenty-first resistor R21, and the other end connected to the power supply ground.

[0142] In this embodiment, the M-th cascaded logic unit further includes a 21st resistor R21 and a 6th capacitor C6. The 21st resistor R21 is connected between the second input terminal of the second AND gate U4 and the power supply ground, forming a defined pull-down loop. This ensures that the input terminal is reliably clamped to a low level when there is no effective drive from the interlock signal path from the preceding stage, preventing uncertainty in the logic state due to floating or disturbed signal lines. The 6th capacitor C6 is connected in parallel between the second input terminal and ground, forming a low-pass filter network together with the equivalent impedance of the signal path. This network effectively attenuates high-frequency noise, ringing, and glitches transmitted from the output terminal of the NOT gate U3 or spatially coupled to this critical logic node, thereby significantly smoothing signal edges and improving the accuracy and anti-interference capability of logic decisions. The introduction of this RC combination further strengthens the signal integrity of the cascaded interlock link from a hardware perspective, ensuring that the priority logic can still work reliably and stably in an electrical noise environment, and enhancing the robustness of the entire combining control circuit in complex application scenarios.

[0143] As an example, and not a limitation, a multi-power supply combining control circuit includes two power input terminals (main power supply and backup power supply) and two switching circuits. The control module can prioritize ensuring that the higher-priority main power supply powers the load. Referring to Table 1, this manifests as follows: when only the main power supply exists, its corresponding switching circuit is controlled to conduct; when only the backup power supply exists, its corresponding switching circuit is switched on; and when both the main power supply and backup power supply exist simultaneously, the control system will consistently select the main power supply to conduct and forcibly shut down the backup power supply, placing it in a disconnected state. This achieves the behavioral logic of "main power supply priority, backup power supply only activated when main power supply fails."

[0144] Table 1

[0145]

[0146] See Figure 8 As shown: the horizontal axis represents time, and the vertical axis represents voltage. The yellow waveform represents the backup power supply voltage, the purple waveform represents the primary power supply voltage, and the blue waveform represents the combined voltage. Compared with existing technologies, this scheme demonstrates significant advantages during primary / backup power supply switching: the switching process is smooth and seamless, with no significant voltage oscillations, and has minimal impact on the combined voltage, effectively improving the stability and reliability of the power supply system.

[0147] In a preferred embodiment, the switching circuit 3 may employ a field-effect transistor.

[0148] In this embodiment, the switching circuit 3 uses a field-effect transistor (FET) to control the on / off state of the power path. Due to its inherent low on-resistance, the FET can significantly reduce the voltage drop and power consumption from the power input terminal 2 to the combined output terminal 4 when on, thereby significantly improving the energy conversion efficiency of the entire combined circuit. Its voltage-driven control method is directly and efficiently compatible with the output signals of the aforementioned cascaded logic units, eliminating the need for complex drive circuits and simplifying the system configuration. Simultaneously, the FET possesses extremely fast switching response speed, ensuring that priority switching commands are executed quickly, achieving rapid and smooth switching between power supply branches, effectively avoiding the risk of voltage drops or interruptions during switching. Furthermore, its mature manufacturing process and wide range of models provide a highly reliable and low-cost flexible solution for applications with different voltage and current levels.

[0149] In a preferred embodiment, the control module 1 can be implemented using a microcontroller unit (MCU), a complex programmable logic device (CPLD), or a field-programmable gate array (FPGA). By programming the detection and cascading interlocking logic using code or a hardware description language and integrating it within a single programmable device, this embodiment significantly improves the flexibility and integration of control. Users can flexibly define or adjust the priority order, voltage detection threshold, and judgment logic of each power supply by modifying the program code according to actual needs, without modifying the external hardware circuitry. This software-defined implementation allows the same hardware platform to quickly adapt to application scenarios with different numbers of input channels (N) and different voltage specifications, significantly enhancing the versatility and scalability of the solution. Simultaneously, the high integration reduces the number of external components, which is beneficial for improving system reliability, reducing overall cost, and facilitating subsequent functional upgrades and maintenance.

[0150] The multi-power supply combining control circuit of this embodiment can meet the application requirements of multi-backup power supply systems. By optimizing the control waveform of the switching process through hardware circuitry, the problems of current backflow and switching oscillation that may occur during path switching are effectively reduced. Through hardware circuitry composed of discrete logic devices, a clear power supply gating priority is established and executed. This infrastructure has good scalability, and its protection scope not only covers the two-input combining embodiment described, but also extends to specific implementations of four-input, five-input, and even more-input combining based on the same principle. The priority combining control function of control module 1 can be implemented independently through hardware logic circuitry, or it can be fully implemented using programmable devices such as microcontrollers (MCUs), systems-on-chips (SoCs), or digital signal processors (DSPs), or it can be implemented by combining hardware logic and programmable devices.

[0151] See Figure 9 As shown, this application provides a multi-source power supply combining control method, applied in the above-mentioned multi-source power supply combining control circuit, including:

[0152] S1. Detect the voltage of the power supply at N power input terminals 2;

[0153] S2. Determine whether there is a valid power source with the highest priority according to the preset priority order;

[0154] S3. If so, control the switching circuit 3 corresponding to the highest priority power supply to be turned on, and control the turning off of all other switching circuits 3.

[0155] In this embodiment, the multi-power supply combining control method first detects the voltage state of each power supply input terminal 2, and then makes a logical decision based on a preset and determined priority order. The core of this method is that its decision logic does not rely on instantaneous comparisons of input voltage levels, but strictly follows a pre-set priority order. Only when the highest priority power supply is detected as valid will the corresponding switch be turned on and all other switches be turned off. This process solidifies the principle of "selecting the highest priority" at the algorithm level, ensuring the determinism and stability of power supply selection, fundamentally eliminating oscillation switching caused by normal voltage fluctuations, and significantly improving the reliability of the power supply system. Simultaneously, the preset priority order can be flexibly defined and adjusted according to actual primary and backup requirements, making the method applicable to diverse power supply configuration scenarios and possessing good logical scalability. This provides a clear, reliable, and programmable control process for achieving highly reliable multi-power supply combining management.

[0156] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A multi-source power supply combining control circuit, characterized in that, include: There are N power input terminals, where N is an integer greater than or equal to 2; N switching circuits, the first end of each switching circuit is connected to a power input terminal, and the second end of each switching circuit is connected to a combined output terminal. The control module includes N detection terminals and N logic control terminals. Each detection terminal corresponds to a power input terminal and is connected to the corresponding power input terminal. Each logic control terminal corresponds to a switching circuit and is connected to the control input terminal of the corresponding switching circuit. The control module is used to detect the voltage of the N power input terminals and, based on the detection results, turn on the switching circuit corresponding to one power supply so that the combined output terminal outputs the voltage of the corresponding power supply.

2. The multi-source power supply combining control circuit according to claim 1, characterized in that, The control module includes: There are N detection circuits, and the input terminal of each detection circuit is used as a detection terminal to detect the voltage of the corresponding power input terminal and output a detection signal. N cascaded logic units, each of which corresponds to a detection circuit and a switching circuit; Each cascaded logic unit includes a first input terminal, a second input terminal, and an output terminal; The first input terminal of the cascaded logic unit is connected to the output terminal of the corresponding detection circuit to receive the detection signal; The output terminal of the cascaded logic unit serves as a logic control terminal and is connected to the control input terminal of the corresponding switching circuit. The second input terminal of the first-level cascaded logic unit is the same as the first input terminal; the second input terminal of the M-th level cascaded logic unit is connected to the output terminal of the (M-1)-th level cascaded logic unit to receive the interlock signal from the previous level, where M is an integer greater than 1 and less than or equal to N; The cascaded logic unit is configured such that when its first input receives a detection signal indicating that the power supply is normal, and its second input receives an interlock signal indicating that the preceding stage is allowed to conduct, its output outputs a conduction signal for conducting the corresponding switching circuit. The conduction signal also serves as an interlock signal to prevent the subsequent cascaded logic unit from conducting.

3. The multi-power supply combining control circuit according to claim 2, characterized in that, The detection circuit includes: The first resistor R1, one end of which serves as the input terminal of the detection circuit; The second resistor R2 has one end connected to the other end of the first resistor R1; The third resistor R3 has one end connected to the other end of the second resistor R2, and the other end of the third resistor R3 is connected to the power supply ground. The fourth resistor R4 has one end connected to one end of the third resistor R3, and the other end connected to the power supply ground. The fifth resistor R5, one end of which is connected to one end of the fourth resistor R4; The sixth resistor R6 is connected at one end to the other end of the fifth resistor R5, and serves as the output terminal of the detection circuit. The first capacitor C1 has one end connected to one end of the fifth resistor R5, and the other end of the first capacitor C1 is connected to the power supply ground. The comparator has its output terminal connected to one end of the sixth resistor R6, its non-inverting input terminal connected to one end of the first capacitor C1, and its negative power supply terminal connected to power ground. The seventh resistor R7 has one end connected to the reference voltage terminal of the comparator and the other end connected to the inverting input terminal of the comparator. The eighth resistor R8 has one end connected to the inverting input of the comparator and the other end connected to the power supply ground. The second capacitor C2 has one end connected to the positive power supply terminal of the comparator and the other end connected to the power supply ground. The ninth resistor R9 has one end connected to one end of the second capacitor C2, and the other end connected to the power supply terminal of the device.

4. The multi-source power supply combining control circuit according to claim 2, characterized in that, The first-stage cascaded logic unit includes: The tenth resistor R10, one end of which is connected to the corresponding power input terminal; Eleventh resistor R11, one end of which is connected to the other end of tenth resistor R10; The twelfth resistor R12 has one end connected to the other end of the eleventh resistor R11, and the other end of the twelfth resistor R12 is connected to the power supply ground. The thirteenth resistor R13 has one end connected to one end of the twelfth resistor R12, and the other end connected to the power supply ground. The first diode has its anode connected to the power supply ground and its cathode connected to one end of the thirteenth resistor R13. The first AND gate has its first input terminal connected to the negative terminal of the first diode, and its negative power supply terminal connected to the power ground. The fourteenth resistor R14, one end of which is connected to the output of the corresponding detection circuit as the first input of the first cascaded logic unit, and the other end of which is connected to the second input of the first AND gate. The sixteenth resistor R16, one end of which is connected to the device power supply terminal, and the other end of which is connected to the positive power supply terminal of the first AND gate; The fourth capacitor C4 has one end connected to the other end of the sixteenth resistor R16, and the other end of the fourth capacitor C4 is connected to the power supply ground. The seventeenth resistor R17, one end of which is connected to the output terminal of the first AND gate; The eighteenth resistor R18, one end of which is connected to the other end of the seventeenth resistor R17 to serve as the output terminal of the first-stage cascaded logic unit, and the other end of the eighteenth resistor R18 is connected to the power supply ground.

5. The multi-source power supply combining control circuit according to claim 4, characterized in that, The first-stage cascaded logic unit also includes: The third capacitor C3 has one end connected to the second input terminal of the first AND gate, and the other end connected to the power supply ground. The fifteenth resistor R15 has one end connected to the second input terminal of the first AND gate, and the other end connected to the power supply ground.

6. The multi-source power supply combining control circuit according to claim 2, characterized in that, The Mth cascaded logic unit includes: The NOT gate has its input terminal serving as the second input terminal of the Mth cascaded logic unit and connected to the output terminal of the (M-1)th cascaded logic unit; the negative power supply terminal of the NOT gate is connected to the power ground. The nineteenth resistor R19 has its first end connected to the corresponding power input terminal, and its other end connected to the positive power supply terminal of the NOT gate. The fifth capacitor C5 has one end connected to the positive power supply terminal of the NOT gate, and the other end connected to the power supply ground. The twentieth resistor R20, one end of which is connected to the output terminal of the NOT gate; The second AND gate, the first input of the second AND gate serves as the first input of the Mth cascaded logic unit and is connected to the output of the corresponding detection circuit; the second input of the second AND gate is connected to the other end of the twentieth resistor R20, and the negative power supply terminal of the second AND gate is connected to the power supply ground; The 22nd resistor R22, one end of which is connected to the output of the second AND gate; The twenty-third resistor R23 has one end connected to the other end of the twenty-second resistor R22 as the output terminal of the Mth cascaded logic unit, and the other end of the twenty-third resistor R23 is connected to the power supply ground. The 24th resistor R24 ​​has one end connected to the device power supply terminal and the other end connected to the positive power supply terminal of the second AND gate. The seventh capacitor C7 has one end connected to the other end of the twenty-fourth resistor R24, and the other end of the seventh capacitor C7 is connected to the power supply ground.

7. The multi-source power supply combining control circuit according to claim 6, characterized in that, The Mth cascaded logic unit further includes: The 21st resistor R21 has one end connected to the second input terminal of the second AND gate, and the other end connected to the power supply ground. The sixth capacitor C6 has one end connected to one end of the twenty-first resistor R21, and the other end connected to the power supply ground.

8. The multi-source power supply combining control circuit according to claim 1, characterized in that, The switching circuit uses a field-effect transistor.

9. The multi-source power supply combining control circuit according to claim 1, characterized in that, The control module uses an MCU, CPLD, or FPGA.

10. A method for controlling the combination of multiple power supplies, applied in the multi-power supply combination control circuit as described in any one of claims 1-9, characterized in that, include: Detect the voltage of the power supply at N power input terminals; Based on the preset priority order, determine whether there is a valid power source with the highest priority; If so, the switch circuit corresponding to the highest priority power supply is turned on, and all other switch circuits are turned off.

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